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1/*
2 * Copyright (C) 2009 Nokia Corporation
3 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
4 *
5 * Some code and ideas taken from drivers/video/omap/ driver
6 * by Imre Deak.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#define DSS_SUBSYS_NAME "DPI"
22
23#include <linux/kernel.h>
24#include <linux/delay.h>
25#include <linux/export.h>
26#include <linux/err.h>
27#include <linux/errno.h>
28#include <linux/platform_device.h>
29#include <linux/regulator/consumer.h>
30#include <linux/string.h>
31#include <linux/of.h>
32#include <linux/clk.h>
33#include <linux/sys_soc.h>
34
35#include "omapdss.h"
36#include "dss.h"
37
38struct dpi_data {
39 struct platform_device *pdev;
40 enum dss_model dss_model;
41 struct dss_device *dss;
42
43 struct regulator *vdds_dsi_reg;
44 enum dss_clk_source clk_src;
45 struct dss_pll *pll;
46
47 struct mutex lock;
48
49 struct videomode vm;
50 struct dss_lcd_mgr_config mgr_config;
51 int data_lines;
52
53 struct omap_dss_device output;
54};
55
56static struct dpi_data *dpi_get_data_from_dssdev(struct omap_dss_device *dssdev)
57{
58 return container_of(dssdev, struct dpi_data, output);
59}
60
61static enum dss_clk_source dpi_get_clk_src_dra7xx(struct dpi_data *dpi,
62 enum omap_channel channel)
63{
64 /*
65 * Possible clock sources:
66 * LCD1: FCK/PLL1_1/HDMI_PLL
67 * LCD2: FCK/PLL1_3/HDMI_PLL (DRA74x: PLL2_3)
68 * LCD3: FCK/PLL1_3/HDMI_PLL (DRA74x: PLL2_1)
69 */
70
71 switch (channel) {
72 case OMAP_DSS_CHANNEL_LCD:
73 {
74 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL1_1))
75 return DSS_CLK_SRC_PLL1_1;
76 break;
77 }
78 case OMAP_DSS_CHANNEL_LCD2:
79 {
80 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL1_3))
81 return DSS_CLK_SRC_PLL1_3;
82 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL2_3))
83 return DSS_CLK_SRC_PLL2_3;
84 break;
85 }
86 case OMAP_DSS_CHANNEL_LCD3:
87 {
88 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL2_1))
89 return DSS_CLK_SRC_PLL2_1;
90 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL1_3))
91 return DSS_CLK_SRC_PLL1_3;
92 break;
93 }
94 default:
95 break;
96 }
97
98 return DSS_CLK_SRC_FCK;
99}
100
101static enum dss_clk_source dpi_get_clk_src(struct dpi_data *dpi)
102{
103 enum omap_channel channel = dpi->output.dispc_channel;
104
105 /*
106 * XXX we can't currently use DSI PLL for DPI with OMAP3, as the DSI PLL
107 * would also be used for DISPC fclk. Meaning, when the DPI output is
108 * disabled, DISPC clock will be disabled, and TV out will stop.
109 */
110 switch (dpi->dss_model) {
111 case DSS_MODEL_OMAP2:
112 case DSS_MODEL_OMAP3:
113 return DSS_CLK_SRC_FCK;
114
115 case DSS_MODEL_OMAP4:
116 switch (channel) {
117 case OMAP_DSS_CHANNEL_LCD:
118 return DSS_CLK_SRC_PLL1_1;
119 case OMAP_DSS_CHANNEL_LCD2:
120 return DSS_CLK_SRC_PLL2_1;
121 default:
122 return DSS_CLK_SRC_FCK;
123 }
124
125 case DSS_MODEL_OMAP5:
126 switch (channel) {
127 case OMAP_DSS_CHANNEL_LCD:
128 return DSS_CLK_SRC_PLL1_1;
129 case OMAP_DSS_CHANNEL_LCD3:
130 return DSS_CLK_SRC_PLL2_1;
131 case OMAP_DSS_CHANNEL_LCD2:
132 default:
133 return DSS_CLK_SRC_FCK;
134 }
135
136 case DSS_MODEL_DRA7:
137 return dpi_get_clk_src_dra7xx(dpi, channel);
138
139 default:
140 return DSS_CLK_SRC_FCK;
141 }
142}
143
144struct dpi_clk_calc_ctx {
145 struct dpi_data *dpi;
146 unsigned int clkout_idx;
147
148 /* inputs */
149
150 unsigned long pck_min, pck_max;
151
152 /* outputs */
153
154 struct dss_pll_clock_info pll_cinfo;
155 unsigned long fck;
156 struct dispc_clock_info dispc_cinfo;
157};
158
159static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
160 unsigned long pck, void *data)
161{
162 struct dpi_clk_calc_ctx *ctx = data;
163
164 /*
165 * Odd dividers give us uneven duty cycle, causing problem when level
166 * shifted. So skip all odd dividers when the pixel clock is on the
167 * higher side.
168 */
169 if (ctx->pck_min >= 100000000) {
170 if (lckd > 1 && lckd % 2 != 0)
171 return false;
172
173 if (pckd > 1 && pckd % 2 != 0)
174 return false;
175 }
176
177 ctx->dispc_cinfo.lck_div = lckd;
178 ctx->dispc_cinfo.pck_div = pckd;
179 ctx->dispc_cinfo.lck = lck;
180 ctx->dispc_cinfo.pck = pck;
181
182 return true;
183}
184
185
186static bool dpi_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
187 void *data)
188{
189 struct dpi_clk_calc_ctx *ctx = data;
190
191 ctx->pll_cinfo.mX[ctx->clkout_idx] = m_dispc;
192 ctx->pll_cinfo.clkout[ctx->clkout_idx] = dispc;
193
194 return dispc_div_calc(ctx->dpi->dss->dispc, dispc,
195 ctx->pck_min, ctx->pck_max,
196 dpi_calc_dispc_cb, ctx);
197}
198
199
200static bool dpi_calc_pll_cb(int n, int m, unsigned long fint,
201 unsigned long clkdco,
202 void *data)
203{
204 struct dpi_clk_calc_ctx *ctx = data;
205
206 ctx->pll_cinfo.n = n;
207 ctx->pll_cinfo.m = m;
208 ctx->pll_cinfo.fint = fint;
209 ctx->pll_cinfo.clkdco = clkdco;
210
211 return dss_pll_hsdiv_calc_a(ctx->dpi->pll, clkdco,
212 ctx->pck_min, dss_get_max_fck_rate(ctx->dpi->dss),
213 dpi_calc_hsdiv_cb, ctx);
214}
215
216static bool dpi_calc_dss_cb(unsigned long fck, void *data)
217{
218 struct dpi_clk_calc_ctx *ctx = data;
219
220 ctx->fck = fck;
221
222 return dispc_div_calc(ctx->dpi->dss->dispc, fck,
223 ctx->pck_min, ctx->pck_max,
224 dpi_calc_dispc_cb, ctx);
225}
226
227static bool dpi_pll_clk_calc(struct dpi_data *dpi, unsigned long pck,
228 struct dpi_clk_calc_ctx *ctx)
229{
230 unsigned long clkin;
231
232 memset(ctx, 0, sizeof(*ctx));
233 ctx->dpi = dpi;
234 ctx->clkout_idx = dss_pll_get_clkout_idx_for_src(dpi->clk_src);
235
236 clkin = clk_get_rate(dpi->pll->clkin);
237
238 if (dpi->pll->hw->type == DSS_PLL_TYPE_A) {
239 unsigned long pll_min, pll_max;
240
241 ctx->pck_min = pck - 1000;
242 ctx->pck_max = pck + 1000;
243
244 pll_min = 0;
245 pll_max = 0;
246
247 return dss_pll_calc_a(ctx->dpi->pll, clkin,
248 pll_min, pll_max,
249 dpi_calc_pll_cb, ctx);
250 } else { /* DSS_PLL_TYPE_B */
251 dss_pll_calc_b(dpi->pll, clkin, pck, &ctx->pll_cinfo);
252
253 ctx->dispc_cinfo.lck_div = 1;
254 ctx->dispc_cinfo.pck_div = 1;
255 ctx->dispc_cinfo.lck = ctx->pll_cinfo.clkout[0];
256 ctx->dispc_cinfo.pck = ctx->dispc_cinfo.lck;
257
258 return true;
259 }
260}
261
262static bool dpi_dss_clk_calc(struct dpi_data *dpi, unsigned long pck,
263 struct dpi_clk_calc_ctx *ctx)
264{
265 int i;
266
267 /*
268 * DSS fck gives us very few possibilities, so finding a good pixel
269 * clock may not be possible. We try multiple times to find the clock,
270 * each time widening the pixel clock range we look for, up to
271 * +/- ~15MHz.
272 */
273
274 for (i = 0; i < 25; ++i) {
275 bool ok;
276
277 memset(ctx, 0, sizeof(*ctx));
278 ctx->dpi = dpi;
279 if (pck > 1000 * i * i * i)
280 ctx->pck_min = max(pck - 1000 * i * i * i, 0lu);
281 else
282 ctx->pck_min = 0;
283 ctx->pck_max = pck + 1000 * i * i * i;
284
285 ok = dss_div_calc(dpi->dss, pck, ctx->pck_min,
286 dpi_calc_dss_cb, ctx);
287 if (ok)
288 return ok;
289 }
290
291 return false;
292}
293
294
295
296static int dpi_set_pll_clk(struct dpi_data *dpi, enum omap_channel channel,
297 unsigned long pck_req, unsigned long *fck, int *lck_div,
298 int *pck_div)
299{
300 struct dpi_clk_calc_ctx ctx;
301 int r;
302 bool ok;
303
304 ok = dpi_pll_clk_calc(dpi, pck_req, &ctx);
305 if (!ok)
306 return -EINVAL;
307
308 r = dss_pll_set_config(dpi->pll, &ctx.pll_cinfo);
309 if (r)
310 return r;
311
312 dss_select_lcd_clk_source(dpi->dss, channel, dpi->clk_src);
313
314 dpi->mgr_config.clock_info = ctx.dispc_cinfo;
315
316 *fck = ctx.pll_cinfo.clkout[ctx.clkout_idx];
317 *lck_div = ctx.dispc_cinfo.lck_div;
318 *pck_div = ctx.dispc_cinfo.pck_div;
319
320 return 0;
321}
322
323static int dpi_set_dispc_clk(struct dpi_data *dpi, unsigned long pck_req,
324 unsigned long *fck, int *lck_div, int *pck_div)
325{
326 struct dpi_clk_calc_ctx ctx;
327 int r;
328 bool ok;
329
330 ok = dpi_dss_clk_calc(dpi, pck_req, &ctx);
331 if (!ok)
332 return -EINVAL;
333
334 r = dss_set_fck_rate(dpi->dss, ctx.fck);
335 if (r)
336 return r;
337
338 dpi->mgr_config.clock_info = ctx.dispc_cinfo;
339
340 *fck = ctx.fck;
341 *lck_div = ctx.dispc_cinfo.lck_div;
342 *pck_div = ctx.dispc_cinfo.pck_div;
343
344 return 0;
345}
346
347static int dpi_set_mode(struct dpi_data *dpi)
348{
349 struct videomode *vm = &dpi->vm;
350 int lck_div = 0, pck_div = 0;
351 unsigned long fck = 0;
352 unsigned long pck;
353 int r = 0;
354
355 if (dpi->pll)
356 r = dpi_set_pll_clk(dpi, dpi->output.dispc_channel,
357 vm->pixelclock, &fck, &lck_div, &pck_div);
358 else
359 r = dpi_set_dispc_clk(dpi, vm->pixelclock, &fck,
360 &lck_div, &pck_div);
361 if (r)
362 return r;
363
364 pck = fck / lck_div / pck_div;
365
366 if (pck != vm->pixelclock) {
367 DSSWARN("Could not find exact pixel clock. Requested %lu Hz, got %lu Hz\n",
368 vm->pixelclock, pck);
369
370 vm->pixelclock = pck;
371 }
372
373 dss_mgr_set_timings(&dpi->output, vm);
374
375 return 0;
376}
377
378static void dpi_config_lcd_manager(struct dpi_data *dpi)
379{
380 dpi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
381
382 dpi->mgr_config.stallmode = false;
383 dpi->mgr_config.fifohandcheck = false;
384
385 dpi->mgr_config.video_port_width = dpi->data_lines;
386
387 dpi->mgr_config.lcden_sig_polarity = 0;
388
389 dss_mgr_set_lcd_config(&dpi->output, &dpi->mgr_config);
390}
391
392static int dpi_display_enable(struct omap_dss_device *dssdev)
393{
394 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
395 struct omap_dss_device *out = &dpi->output;
396 int r;
397
398 mutex_lock(&dpi->lock);
399
400 if (!out->dispc_channel_connected) {
401 DSSERR("failed to enable display: no output/manager\n");
402 r = -ENODEV;
403 goto err_no_out_mgr;
404 }
405
406 if (dpi->vdds_dsi_reg) {
407 r = regulator_enable(dpi->vdds_dsi_reg);
408 if (r)
409 goto err_reg_enable;
410 }
411
412 r = dispc_runtime_get(dpi->dss->dispc);
413 if (r)
414 goto err_get_dispc;
415
416 r = dss_dpi_select_source(dpi->dss, out->port_num, out->dispc_channel);
417 if (r)
418 goto err_src_sel;
419
420 if (dpi->pll) {
421 r = dss_pll_enable(dpi->pll);
422 if (r)
423 goto err_pll_init;
424 }
425
426 r = dpi_set_mode(dpi);
427 if (r)
428 goto err_set_mode;
429
430 dpi_config_lcd_manager(dpi);
431
432 mdelay(2);
433
434 r = dss_mgr_enable(&dpi->output);
435 if (r)
436 goto err_mgr_enable;
437
438 mutex_unlock(&dpi->lock);
439
440 return 0;
441
442err_mgr_enable:
443err_set_mode:
444 if (dpi->pll)
445 dss_pll_disable(dpi->pll);
446err_pll_init:
447err_src_sel:
448 dispc_runtime_put(dpi->dss->dispc);
449err_get_dispc:
450 if (dpi->vdds_dsi_reg)
451 regulator_disable(dpi->vdds_dsi_reg);
452err_reg_enable:
453err_no_out_mgr:
454 mutex_unlock(&dpi->lock);
455 return r;
456}
457
458static void dpi_display_disable(struct omap_dss_device *dssdev)
459{
460 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
461
462 mutex_lock(&dpi->lock);
463
464 dss_mgr_disable(&dpi->output);
465
466 if (dpi->pll) {
467 dss_select_lcd_clk_source(dpi->dss, dpi->output.dispc_channel,
468 DSS_CLK_SRC_FCK);
469 dss_pll_disable(dpi->pll);
470 }
471
472 dispc_runtime_put(dpi->dss->dispc);
473
474 if (dpi->vdds_dsi_reg)
475 regulator_disable(dpi->vdds_dsi_reg);
476
477 mutex_unlock(&dpi->lock);
478}
479
480static void dpi_set_timings(struct omap_dss_device *dssdev,
481 struct videomode *vm)
482{
483 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
484
485 DSSDBG("dpi_set_timings\n");
486
487 mutex_lock(&dpi->lock);
488
489 dpi->vm = *vm;
490
491 mutex_unlock(&dpi->lock);
492}
493
494static void dpi_get_timings(struct omap_dss_device *dssdev,
495 struct videomode *vm)
496{
497 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
498
499 mutex_lock(&dpi->lock);
500
501 *vm = dpi->vm;
502
503 mutex_unlock(&dpi->lock);
504}
505
506static int dpi_check_timings(struct omap_dss_device *dssdev,
507 struct videomode *vm)
508{
509 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
510 enum omap_channel channel = dpi->output.dispc_channel;
511 int lck_div, pck_div;
512 unsigned long fck;
513 unsigned long pck;
514 struct dpi_clk_calc_ctx ctx;
515 bool ok;
516
517 if (vm->hactive % 8 != 0)
518 return -EINVAL;
519
520 if (!dispc_mgr_timings_ok(dpi->dss->dispc, channel, vm))
521 return -EINVAL;
522
523 if (vm->pixelclock == 0)
524 return -EINVAL;
525
526 if (dpi->pll) {
527 ok = dpi_pll_clk_calc(dpi, vm->pixelclock, &ctx);
528 if (!ok)
529 return -EINVAL;
530
531 fck = ctx.pll_cinfo.clkout[ctx.clkout_idx];
532 } else {
533 ok = dpi_dss_clk_calc(dpi, vm->pixelclock, &ctx);
534 if (!ok)
535 return -EINVAL;
536
537 fck = ctx.fck;
538 }
539
540 lck_div = ctx.dispc_cinfo.lck_div;
541 pck_div = ctx.dispc_cinfo.pck_div;
542
543 pck = fck / lck_div / pck_div;
544
545 vm->pixelclock = pck;
546
547 return 0;
548}
549
550static int dpi_verify_pll(struct dss_pll *pll)
551{
552 int r;
553
554 /* do initial setup with the PLL to see if it is operational */
555
556 r = dss_pll_enable(pll);
557 if (r)
558 return r;
559
560 dss_pll_disable(pll);
561
562 return 0;
563}
564
565static const struct soc_device_attribute dpi_soc_devices[] = {
566 { .machine = "OMAP3[456]*" },
567 { .machine = "[AD]M37*" },
568 { /* sentinel */ }
569};
570
571static int dpi_init_regulator(struct dpi_data *dpi)
572{
573 struct regulator *vdds_dsi;
574
575 /*
576 * The DPI uses the DSI VDDS on OMAP34xx, OMAP35xx, OMAP36xx, AM37xx and
577 * DM37xx only.
578 */
579 if (!soc_device_match(dpi_soc_devices))
580 return 0;
581
582 if (dpi->vdds_dsi_reg)
583 return 0;
584
585 vdds_dsi = devm_regulator_get(&dpi->pdev->dev, "vdds_dsi");
586 if (IS_ERR(vdds_dsi)) {
587 if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER)
588 DSSERR("can't get VDDS_DSI regulator\n");
589 return PTR_ERR(vdds_dsi);
590 }
591
592 dpi->vdds_dsi_reg = vdds_dsi;
593
594 return 0;
595}
596
597static void dpi_init_pll(struct dpi_data *dpi)
598{
599 struct dss_pll *pll;
600
601 if (dpi->pll)
602 return;
603
604 dpi->clk_src = dpi_get_clk_src(dpi);
605
606 pll = dss_pll_find_by_src(dpi->dss, dpi->clk_src);
607 if (!pll)
608 return;
609
610 if (dpi_verify_pll(pll)) {
611 DSSWARN("PLL not operational\n");
612 return;
613 }
614
615 dpi->pll = pll;
616}
617
618/*
619 * Return a hardcoded channel for the DPI output. This should work for
620 * current use cases, but this can be later expanded to either resolve
621 * the channel in some more dynamic manner, or get the channel as a user
622 * parameter.
623 */
624static enum omap_channel dpi_get_channel(struct dpi_data *dpi, int port_num)
625{
626 switch (dpi->dss_model) {
627 case DSS_MODEL_OMAP2:
628 case DSS_MODEL_OMAP3:
629 return OMAP_DSS_CHANNEL_LCD;
630
631 case DSS_MODEL_DRA7:
632 switch (port_num) {
633 case 2:
634 return OMAP_DSS_CHANNEL_LCD3;
635 case 1:
636 return OMAP_DSS_CHANNEL_LCD2;
637 case 0:
638 default:
639 return OMAP_DSS_CHANNEL_LCD;
640 }
641
642 case DSS_MODEL_OMAP4:
643 return OMAP_DSS_CHANNEL_LCD2;
644
645 case DSS_MODEL_OMAP5:
646 return OMAP_DSS_CHANNEL_LCD3;
647
648 default:
649 DSSWARN("unsupported DSS version\n");
650 return OMAP_DSS_CHANNEL_LCD;
651 }
652}
653
654static int dpi_connect(struct omap_dss_device *dssdev,
655 struct omap_dss_device *dst)
656{
657 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
658 int r;
659
660 r = dpi_init_regulator(dpi);
661 if (r)
662 return r;
663
664 dpi_init_pll(dpi);
665
666 r = dss_mgr_connect(&dpi->output, dssdev);
667 if (r)
668 return r;
669
670 r = omapdss_output_set_device(dssdev, dst);
671 if (r) {
672 DSSERR("failed to connect output to new device: %s\n",
673 dst->name);
674 dss_mgr_disconnect(&dpi->output, dssdev);
675 return r;
676 }
677
678 return 0;
679}
680
681static void dpi_disconnect(struct omap_dss_device *dssdev,
682 struct omap_dss_device *dst)
683{
684 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
685
686 WARN_ON(dst != dssdev->dst);
687
688 if (dst != dssdev->dst)
689 return;
690
691 omapdss_output_unset_device(dssdev);
692
693 dss_mgr_disconnect(&dpi->output, dssdev);
694}
695
696static const struct omapdss_dpi_ops dpi_ops = {
697 .connect = dpi_connect,
698 .disconnect = dpi_disconnect,
699
700 .enable = dpi_display_enable,
701 .disable = dpi_display_disable,
702
703 .check_timings = dpi_check_timings,
704 .set_timings = dpi_set_timings,
705 .get_timings = dpi_get_timings,
706};
707
708static void dpi_init_output_port(struct dpi_data *dpi, struct device_node *port)
709{
710 struct omap_dss_device *out = &dpi->output;
711 int r;
712 u32 port_num;
713
714 r = of_property_read_u32(port, "reg", &port_num);
715 if (r)
716 port_num = 0;
717
718 switch (port_num) {
719 case 2:
720 out->name = "dpi.2";
721 break;
722 case 1:
723 out->name = "dpi.1";
724 break;
725 case 0:
726 default:
727 out->name = "dpi.0";
728 break;
729 }
730
731 out->dev = &dpi->pdev->dev;
732 out->id = OMAP_DSS_OUTPUT_DPI;
733 out->output_type = OMAP_DISPLAY_TYPE_DPI;
734 out->dispc_channel = dpi_get_channel(dpi, port_num);
735 out->port_num = port_num;
736 out->ops.dpi = &dpi_ops;
737 out->owner = THIS_MODULE;
738
739 omapdss_register_output(out);
740}
741
742static void dpi_uninit_output_port(struct device_node *port)
743{
744 struct dpi_data *dpi = port->data;
745 struct omap_dss_device *out = &dpi->output;
746
747 omapdss_unregister_output(out);
748}
749
750int dpi_init_port(struct dss_device *dss, struct platform_device *pdev,
751 struct device_node *port, enum dss_model dss_model)
752{
753 struct dpi_data *dpi;
754 struct device_node *ep;
755 u32 datalines;
756 int r;
757
758 dpi = devm_kzalloc(&pdev->dev, sizeof(*dpi), GFP_KERNEL);
759 if (!dpi)
760 return -ENOMEM;
761
762 ep = of_get_next_child(port, NULL);
763 if (!ep)
764 return 0;
765
766 r = of_property_read_u32(ep, "data-lines", &datalines);
767 if (r) {
768 DSSERR("failed to parse datalines\n");
769 goto err_datalines;
770 }
771
772 dpi->data_lines = datalines;
773
774 of_node_put(ep);
775
776 dpi->pdev = pdev;
777 dpi->dss_model = dss_model;
778 dpi->dss = dss;
779 port->data = dpi;
780
781 mutex_init(&dpi->lock);
782
783 dpi_init_output_port(dpi, port);
784
785 return 0;
786
787err_datalines:
788 of_node_put(ep);
789
790 return r;
791}
792
793void dpi_uninit_port(struct device_node *port)
794{
795 struct dpi_data *dpi = port->data;
796
797 if (!dpi)
798 return;
799
800 dpi_uninit_output_port(port);
801}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2009 Nokia Corporation
4 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
5 *
6 * Some code and ideas taken from drivers/video/omap/ driver
7 * by Imre Deak.
8 */
9
10#define DSS_SUBSYS_NAME "DPI"
11
12#include <linux/clk.h>
13#include <linux/delay.h>
14#include <linux/err.h>
15#include <linux/errno.h>
16#include <linux/export.h>
17#include <linux/kernel.h>
18#include <linux/of.h>
19#include <linux/platform_device.h>
20#include <linux/regulator/consumer.h>
21#include <linux/string.h>
22#include <linux/sys_soc.h>
23
24#include <drm/drm_bridge.h>
25
26#include "dss.h"
27#include "omapdss.h"
28
29struct dpi_data {
30 struct platform_device *pdev;
31 enum dss_model dss_model;
32 struct dss_device *dss;
33 unsigned int id;
34
35 struct regulator *vdds_dsi_reg;
36 enum dss_clk_source clk_src;
37 struct dss_pll *pll;
38
39 struct dss_lcd_mgr_config mgr_config;
40 unsigned long pixelclock;
41 int data_lines;
42
43 struct omap_dss_device output;
44 struct drm_bridge bridge;
45};
46
47#define drm_bridge_to_dpi(bridge) container_of(bridge, struct dpi_data, bridge)
48
49/* -----------------------------------------------------------------------------
50 * Clock Handling and PLL
51 */
52
53static enum dss_clk_source dpi_get_clk_src_dra7xx(struct dpi_data *dpi,
54 enum omap_channel channel)
55{
56 /*
57 * Possible clock sources:
58 * LCD1: FCK/PLL1_1/HDMI_PLL
59 * LCD2: FCK/PLL1_3/HDMI_PLL (DRA74x: PLL2_3)
60 * LCD3: FCK/PLL1_3/HDMI_PLL (DRA74x: PLL2_1)
61 */
62
63 switch (channel) {
64 case OMAP_DSS_CHANNEL_LCD:
65 {
66 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL1_1))
67 return DSS_CLK_SRC_PLL1_1;
68 break;
69 }
70 case OMAP_DSS_CHANNEL_LCD2:
71 {
72 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL1_3))
73 return DSS_CLK_SRC_PLL1_3;
74 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL2_3))
75 return DSS_CLK_SRC_PLL2_3;
76 break;
77 }
78 case OMAP_DSS_CHANNEL_LCD3:
79 {
80 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL2_1))
81 return DSS_CLK_SRC_PLL2_1;
82 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL1_3))
83 return DSS_CLK_SRC_PLL1_3;
84 break;
85 }
86 default:
87 break;
88 }
89
90 return DSS_CLK_SRC_FCK;
91}
92
93static enum dss_clk_source dpi_get_clk_src(struct dpi_data *dpi)
94{
95 enum omap_channel channel = dpi->output.dispc_channel;
96
97 /*
98 * XXX we can't currently use DSI PLL for DPI with OMAP3, as the DSI PLL
99 * would also be used for DISPC fclk. Meaning, when the DPI output is
100 * disabled, DISPC clock will be disabled, and TV out will stop.
101 */
102 switch (dpi->dss_model) {
103 case DSS_MODEL_OMAP2:
104 case DSS_MODEL_OMAP3:
105 return DSS_CLK_SRC_FCK;
106
107 case DSS_MODEL_OMAP4:
108 switch (channel) {
109 case OMAP_DSS_CHANNEL_LCD:
110 return DSS_CLK_SRC_PLL1_1;
111 case OMAP_DSS_CHANNEL_LCD2:
112 return DSS_CLK_SRC_PLL2_1;
113 default:
114 return DSS_CLK_SRC_FCK;
115 }
116
117 case DSS_MODEL_OMAP5:
118 switch (channel) {
119 case OMAP_DSS_CHANNEL_LCD:
120 return DSS_CLK_SRC_PLL1_1;
121 case OMAP_DSS_CHANNEL_LCD3:
122 return DSS_CLK_SRC_PLL2_1;
123 case OMAP_DSS_CHANNEL_LCD2:
124 default:
125 return DSS_CLK_SRC_FCK;
126 }
127
128 case DSS_MODEL_DRA7:
129 return dpi_get_clk_src_dra7xx(dpi, channel);
130
131 default:
132 return DSS_CLK_SRC_FCK;
133 }
134}
135
136struct dpi_clk_calc_ctx {
137 struct dpi_data *dpi;
138 unsigned int clkout_idx;
139
140 /* inputs */
141
142 unsigned long pck_min, pck_max;
143
144 /* outputs */
145
146 struct dss_pll_clock_info pll_cinfo;
147 unsigned long fck;
148 struct dispc_clock_info dispc_cinfo;
149};
150
151static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
152 unsigned long pck, void *data)
153{
154 struct dpi_clk_calc_ctx *ctx = data;
155
156 /*
157 * Odd dividers give us uneven duty cycle, causing problem when level
158 * shifted. So skip all odd dividers when the pixel clock is on the
159 * higher side.
160 */
161 if (ctx->pck_min >= 100000000) {
162 if (lckd > 1 && lckd % 2 != 0)
163 return false;
164
165 if (pckd > 1 && pckd % 2 != 0)
166 return false;
167 }
168
169 ctx->dispc_cinfo.lck_div = lckd;
170 ctx->dispc_cinfo.pck_div = pckd;
171 ctx->dispc_cinfo.lck = lck;
172 ctx->dispc_cinfo.pck = pck;
173
174 return true;
175}
176
177
178static bool dpi_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
179 void *data)
180{
181 struct dpi_clk_calc_ctx *ctx = data;
182
183 ctx->pll_cinfo.mX[ctx->clkout_idx] = m_dispc;
184 ctx->pll_cinfo.clkout[ctx->clkout_idx] = dispc;
185
186 return dispc_div_calc(ctx->dpi->dss->dispc, dispc,
187 ctx->pck_min, ctx->pck_max,
188 dpi_calc_dispc_cb, ctx);
189}
190
191
192static bool dpi_calc_pll_cb(int n, int m, unsigned long fint,
193 unsigned long clkdco,
194 void *data)
195{
196 struct dpi_clk_calc_ctx *ctx = data;
197
198 ctx->pll_cinfo.n = n;
199 ctx->pll_cinfo.m = m;
200 ctx->pll_cinfo.fint = fint;
201 ctx->pll_cinfo.clkdco = clkdco;
202
203 return dss_pll_hsdiv_calc_a(ctx->dpi->pll, clkdco,
204 ctx->pck_min, dss_get_max_fck_rate(ctx->dpi->dss),
205 dpi_calc_hsdiv_cb, ctx);
206}
207
208static bool dpi_calc_dss_cb(unsigned long fck, void *data)
209{
210 struct dpi_clk_calc_ctx *ctx = data;
211
212 ctx->fck = fck;
213
214 return dispc_div_calc(ctx->dpi->dss->dispc, fck,
215 ctx->pck_min, ctx->pck_max,
216 dpi_calc_dispc_cb, ctx);
217}
218
219static bool dpi_pll_clk_calc(struct dpi_data *dpi, unsigned long pck,
220 struct dpi_clk_calc_ctx *ctx)
221{
222 unsigned long clkin;
223
224 memset(ctx, 0, sizeof(*ctx));
225 ctx->dpi = dpi;
226 ctx->clkout_idx = dss_pll_get_clkout_idx_for_src(dpi->clk_src);
227
228 clkin = clk_get_rate(dpi->pll->clkin);
229
230 if (dpi->pll->hw->type == DSS_PLL_TYPE_A) {
231 unsigned long pll_min, pll_max;
232
233 ctx->pck_min = pck - 1000;
234 ctx->pck_max = pck + 1000;
235
236 pll_min = 0;
237 pll_max = 0;
238
239 return dss_pll_calc_a(ctx->dpi->pll, clkin,
240 pll_min, pll_max,
241 dpi_calc_pll_cb, ctx);
242 } else { /* DSS_PLL_TYPE_B */
243 dss_pll_calc_b(dpi->pll, clkin, pck, &ctx->pll_cinfo);
244
245 ctx->dispc_cinfo.lck_div = 1;
246 ctx->dispc_cinfo.pck_div = 1;
247 ctx->dispc_cinfo.lck = ctx->pll_cinfo.clkout[0];
248 ctx->dispc_cinfo.pck = ctx->dispc_cinfo.lck;
249
250 return true;
251 }
252}
253
254static bool dpi_dss_clk_calc(struct dpi_data *dpi, unsigned long pck,
255 struct dpi_clk_calc_ctx *ctx)
256{
257 int i;
258
259 /*
260 * DSS fck gives us very few possibilities, so finding a good pixel
261 * clock may not be possible. We try multiple times to find the clock,
262 * each time widening the pixel clock range we look for, up to
263 * +/- ~15MHz.
264 */
265
266 for (i = 0; i < 25; ++i) {
267 bool ok;
268
269 memset(ctx, 0, sizeof(*ctx));
270 ctx->dpi = dpi;
271 if (pck > 1000 * i * i * i)
272 ctx->pck_min = max(pck - 1000 * i * i * i, 0lu);
273 else
274 ctx->pck_min = 0;
275 ctx->pck_max = pck + 1000 * i * i * i;
276
277 ok = dss_div_calc(dpi->dss, pck, ctx->pck_min,
278 dpi_calc_dss_cb, ctx);
279 if (ok)
280 return ok;
281 }
282
283 return false;
284}
285
286
287
288static int dpi_set_pll_clk(struct dpi_data *dpi, unsigned long pck_req)
289{
290 struct dpi_clk_calc_ctx ctx;
291 int r;
292 bool ok;
293
294 ok = dpi_pll_clk_calc(dpi, pck_req, &ctx);
295 if (!ok)
296 return -EINVAL;
297
298 r = dss_pll_set_config(dpi->pll, &ctx.pll_cinfo);
299 if (r)
300 return r;
301
302 dss_select_lcd_clk_source(dpi->dss, dpi->output.dispc_channel,
303 dpi->clk_src);
304
305 dpi->mgr_config.clock_info = ctx.dispc_cinfo;
306
307 return 0;
308}
309
310static int dpi_set_dispc_clk(struct dpi_data *dpi, unsigned long pck_req)
311{
312 struct dpi_clk_calc_ctx ctx;
313 int r;
314 bool ok;
315
316 ok = dpi_dss_clk_calc(dpi, pck_req, &ctx);
317 if (!ok)
318 return -EINVAL;
319
320 r = dss_set_fck_rate(dpi->dss, ctx.fck);
321 if (r)
322 return r;
323
324 dpi->mgr_config.clock_info = ctx.dispc_cinfo;
325
326 return 0;
327}
328
329static int dpi_set_mode(struct dpi_data *dpi)
330{
331 int r;
332
333 if (dpi->pll)
334 r = dpi_set_pll_clk(dpi, dpi->pixelclock);
335 else
336 r = dpi_set_dispc_clk(dpi, dpi->pixelclock);
337
338 return r;
339}
340
341static void dpi_config_lcd_manager(struct dpi_data *dpi)
342{
343 dpi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
344
345 dpi->mgr_config.stallmode = false;
346 dpi->mgr_config.fifohandcheck = false;
347
348 dpi->mgr_config.video_port_width = dpi->data_lines;
349
350 dpi->mgr_config.lcden_sig_polarity = 0;
351
352 dss_mgr_set_lcd_config(&dpi->output, &dpi->mgr_config);
353}
354
355static int dpi_clock_update(struct dpi_data *dpi, unsigned long *clock)
356{
357 int lck_div, pck_div;
358 unsigned long fck;
359 struct dpi_clk_calc_ctx ctx;
360
361 if (dpi->pll) {
362 if (!dpi_pll_clk_calc(dpi, *clock, &ctx))
363 return -EINVAL;
364
365 fck = ctx.pll_cinfo.clkout[ctx.clkout_idx];
366 } else {
367 if (!dpi_dss_clk_calc(dpi, *clock, &ctx))
368 return -EINVAL;
369
370 fck = ctx.fck;
371 }
372
373 lck_div = ctx.dispc_cinfo.lck_div;
374 pck_div = ctx.dispc_cinfo.pck_div;
375
376 *clock = fck / lck_div / pck_div;
377
378 return 0;
379}
380
381static int dpi_verify_pll(struct dss_pll *pll)
382{
383 int r;
384
385 /* do initial setup with the PLL to see if it is operational */
386
387 r = dss_pll_enable(pll);
388 if (r)
389 return r;
390
391 dss_pll_disable(pll);
392
393 return 0;
394}
395
396static void dpi_init_pll(struct dpi_data *dpi)
397{
398 struct dss_pll *pll;
399
400 if (dpi->pll)
401 return;
402
403 dpi->clk_src = dpi_get_clk_src(dpi);
404
405 pll = dss_pll_find_by_src(dpi->dss, dpi->clk_src);
406 if (!pll)
407 return;
408
409 if (dpi_verify_pll(pll)) {
410 DSSWARN("PLL not operational\n");
411 return;
412 }
413
414 dpi->pll = pll;
415}
416
417/* -----------------------------------------------------------------------------
418 * DRM Bridge Operations
419 */
420
421static int dpi_bridge_attach(struct drm_bridge *bridge,
422 enum drm_bridge_attach_flags flags)
423{
424 struct dpi_data *dpi = drm_bridge_to_dpi(bridge);
425
426 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
427 return -EINVAL;
428
429 dpi_init_pll(dpi);
430
431 return drm_bridge_attach(bridge->encoder, dpi->output.next_bridge,
432 bridge, flags);
433}
434
435static enum drm_mode_status
436dpi_bridge_mode_valid(struct drm_bridge *bridge,
437 const struct drm_display_info *info,
438 const struct drm_display_mode *mode)
439{
440 struct dpi_data *dpi = drm_bridge_to_dpi(bridge);
441 unsigned long clock = mode->clock * 1000;
442 int ret;
443
444 if (mode->hdisplay % 8 != 0)
445 return MODE_BAD_WIDTH;
446
447 if (mode->clock == 0)
448 return MODE_NOCLOCK;
449
450 ret = dpi_clock_update(dpi, &clock);
451 if (ret < 0)
452 return MODE_CLOCK_RANGE;
453
454 return MODE_OK;
455}
456
457static bool dpi_bridge_mode_fixup(struct drm_bridge *bridge,
458 const struct drm_display_mode *mode,
459 struct drm_display_mode *adjusted_mode)
460{
461 struct dpi_data *dpi = drm_bridge_to_dpi(bridge);
462 unsigned long clock = mode->clock * 1000;
463 int ret;
464
465 ret = dpi_clock_update(dpi, &clock);
466 if (ret < 0)
467 return false;
468
469 adjusted_mode->clock = clock / 1000;
470
471 return true;
472}
473
474static void dpi_bridge_mode_set(struct drm_bridge *bridge,
475 const struct drm_display_mode *mode,
476 const struct drm_display_mode *adjusted_mode)
477{
478 struct dpi_data *dpi = drm_bridge_to_dpi(bridge);
479
480 dpi->pixelclock = adjusted_mode->clock * 1000;
481}
482
483static void dpi_bridge_enable(struct drm_bridge *bridge)
484{
485 struct dpi_data *dpi = drm_bridge_to_dpi(bridge);
486 int r;
487
488 if (dpi->vdds_dsi_reg) {
489 r = regulator_enable(dpi->vdds_dsi_reg);
490 if (r)
491 return;
492 }
493
494 r = dispc_runtime_get(dpi->dss->dispc);
495 if (r)
496 goto err_get_dispc;
497
498 r = dss_dpi_select_source(dpi->dss, dpi->id, dpi->output.dispc_channel);
499 if (r)
500 goto err_src_sel;
501
502 if (dpi->pll) {
503 r = dss_pll_enable(dpi->pll);
504 if (r)
505 goto err_pll_init;
506 }
507
508 r = dpi_set_mode(dpi);
509 if (r)
510 goto err_set_mode;
511
512 dpi_config_lcd_manager(dpi);
513
514 mdelay(2);
515
516 r = dss_mgr_enable(&dpi->output);
517 if (r)
518 goto err_mgr_enable;
519
520 return;
521
522err_mgr_enable:
523err_set_mode:
524 if (dpi->pll)
525 dss_pll_disable(dpi->pll);
526err_pll_init:
527err_src_sel:
528 dispc_runtime_put(dpi->dss->dispc);
529err_get_dispc:
530 if (dpi->vdds_dsi_reg)
531 regulator_disable(dpi->vdds_dsi_reg);
532}
533
534static void dpi_bridge_disable(struct drm_bridge *bridge)
535{
536 struct dpi_data *dpi = drm_bridge_to_dpi(bridge);
537
538 dss_mgr_disable(&dpi->output);
539
540 if (dpi->pll) {
541 dss_select_lcd_clk_source(dpi->dss, dpi->output.dispc_channel,
542 DSS_CLK_SRC_FCK);
543 dss_pll_disable(dpi->pll);
544 }
545
546 dispc_runtime_put(dpi->dss->dispc);
547
548 if (dpi->vdds_dsi_reg)
549 regulator_disable(dpi->vdds_dsi_reg);
550}
551
552static const struct drm_bridge_funcs dpi_bridge_funcs = {
553 .attach = dpi_bridge_attach,
554 .mode_valid = dpi_bridge_mode_valid,
555 .mode_fixup = dpi_bridge_mode_fixup,
556 .mode_set = dpi_bridge_mode_set,
557 .enable = dpi_bridge_enable,
558 .disable = dpi_bridge_disable,
559};
560
561static void dpi_bridge_init(struct dpi_data *dpi)
562{
563 dpi->bridge.funcs = &dpi_bridge_funcs;
564 dpi->bridge.of_node = dpi->pdev->dev.of_node;
565 dpi->bridge.type = DRM_MODE_CONNECTOR_DPI;
566
567 drm_bridge_add(&dpi->bridge);
568}
569
570static void dpi_bridge_cleanup(struct dpi_data *dpi)
571{
572 drm_bridge_remove(&dpi->bridge);
573}
574
575/* -----------------------------------------------------------------------------
576 * Initialisation and Cleanup
577 */
578
579/*
580 * Return a hardcoded channel for the DPI output. This should work for
581 * current use cases, but this can be later expanded to either resolve
582 * the channel in some more dynamic manner, or get the channel as a user
583 * parameter.
584 */
585static enum omap_channel dpi_get_channel(struct dpi_data *dpi)
586{
587 switch (dpi->dss_model) {
588 case DSS_MODEL_OMAP2:
589 case DSS_MODEL_OMAP3:
590 return OMAP_DSS_CHANNEL_LCD;
591
592 case DSS_MODEL_DRA7:
593 switch (dpi->id) {
594 case 2:
595 return OMAP_DSS_CHANNEL_LCD3;
596 case 1:
597 return OMAP_DSS_CHANNEL_LCD2;
598 case 0:
599 default:
600 return OMAP_DSS_CHANNEL_LCD;
601 }
602
603 case DSS_MODEL_OMAP4:
604 return OMAP_DSS_CHANNEL_LCD2;
605
606 case DSS_MODEL_OMAP5:
607 return OMAP_DSS_CHANNEL_LCD3;
608
609 default:
610 DSSWARN("unsupported DSS version\n");
611 return OMAP_DSS_CHANNEL_LCD;
612 }
613}
614
615static int dpi_init_output_port(struct dpi_data *dpi, struct device_node *port)
616{
617 struct omap_dss_device *out = &dpi->output;
618 u32 port_num = 0;
619 int r;
620
621 dpi_bridge_init(dpi);
622
623 of_property_read_u32(port, "reg", &port_num);
624 dpi->id = port_num <= 2 ? port_num : 0;
625
626 switch (port_num) {
627 case 2:
628 out->name = "dpi.2";
629 break;
630 case 1:
631 out->name = "dpi.1";
632 break;
633 case 0:
634 default:
635 out->name = "dpi.0";
636 break;
637 }
638
639 out->dev = &dpi->pdev->dev;
640 out->id = OMAP_DSS_OUTPUT_DPI;
641 out->type = OMAP_DISPLAY_TYPE_DPI;
642 out->dispc_channel = dpi_get_channel(dpi);
643 out->of_port = port_num;
644
645 r = omapdss_device_init_output(out, &dpi->bridge);
646 if (r < 0) {
647 dpi_bridge_cleanup(dpi);
648 return r;
649 }
650
651 omapdss_device_register(out);
652
653 return 0;
654}
655
656static void dpi_uninit_output_port(struct device_node *port)
657{
658 struct dpi_data *dpi = port->data;
659 struct omap_dss_device *out = &dpi->output;
660
661 omapdss_device_unregister(out);
662 omapdss_device_cleanup_output(out);
663
664 dpi_bridge_cleanup(dpi);
665}
666
667/* -----------------------------------------------------------------------------
668 * Initialisation and Cleanup
669 */
670
671static const struct soc_device_attribute dpi_soc_devices[] = {
672 { .machine = "OMAP3[456]*" },
673 { .machine = "[AD]M37*" },
674 { /* sentinel */ }
675};
676
677static int dpi_init_regulator(struct dpi_data *dpi)
678{
679 struct regulator *vdds_dsi;
680
681 /*
682 * The DPI uses the DSI VDDS on OMAP34xx, OMAP35xx, OMAP36xx, AM37xx and
683 * DM37xx only.
684 */
685 if (!soc_device_match(dpi_soc_devices))
686 return 0;
687
688 vdds_dsi = devm_regulator_get(&dpi->pdev->dev, "vdds_dsi");
689 if (IS_ERR(vdds_dsi)) {
690 if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER)
691 DSSERR("can't get VDDS_DSI regulator\n");
692 return PTR_ERR(vdds_dsi);
693 }
694
695 dpi->vdds_dsi_reg = vdds_dsi;
696
697 return 0;
698}
699
700int dpi_init_port(struct dss_device *dss, struct platform_device *pdev,
701 struct device_node *port, enum dss_model dss_model)
702{
703 struct dpi_data *dpi;
704 struct device_node *ep;
705 u32 datalines;
706 int r;
707
708 dpi = devm_kzalloc(&pdev->dev, sizeof(*dpi), GFP_KERNEL);
709 if (!dpi)
710 return -ENOMEM;
711
712 ep = of_get_next_child(port, NULL);
713 if (!ep)
714 return 0;
715
716 r = of_property_read_u32(ep, "data-lines", &datalines);
717 of_node_put(ep);
718 if (r) {
719 DSSERR("failed to parse datalines\n");
720 return r;
721 }
722
723 dpi->data_lines = datalines;
724
725 dpi->pdev = pdev;
726 dpi->dss_model = dss_model;
727 dpi->dss = dss;
728 port->data = dpi;
729
730 r = dpi_init_regulator(dpi);
731 if (r)
732 return r;
733
734 return dpi_init_output_port(dpi, port);
735}
736
737void dpi_uninit_port(struct device_node *port)
738{
739 struct dpi_data *dpi = port->data;
740
741 if (!dpi)
742 return;
743
744 dpi_uninit_output_port(port);
745}