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1/*
2 * tc358767 eDP bridge driver
3 *
4 * Copyright (C) 2016 CogentEmbedded Inc
5 * Author: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
6 *
7 * Copyright (C) 2016 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
8 *
9 * Copyright (C) 2016 Zodiac Inflight Innovations
10 *
11 * Initially based on: drivers/gpu/drm/i2c/tda998x_drv.c
12 *
13 * Copyright (C) 2012 Texas Instruments
14 * Author: Rob Clark <robdclark@gmail.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 */
26
27#include <linux/clk.h>
28#include <linux/device.h>
29#include <linux/gpio/consumer.h>
30#include <linux/i2c.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/regmap.h>
34#include <linux/slab.h>
35
36#include <drm/drm_atomic_helper.h>
37#include <drm/drm_crtc_helper.h>
38#include <drm/drm_dp_helper.h>
39#include <drm/drm_edid.h>
40#include <drm/drm_of.h>
41#include <drm/drm_panel.h>
42
43/* Registers */
44
45/* Display Parallel Interface */
46#define DPIPXLFMT 0x0440
47#define VS_POL_ACTIVE_LOW (1 << 10)
48#define HS_POL_ACTIVE_LOW (1 << 9)
49#define DE_POL_ACTIVE_HIGH (0 << 8)
50#define SUB_CFG_TYPE_CONFIG1 (0 << 2) /* LSB aligned */
51#define SUB_CFG_TYPE_CONFIG2 (1 << 2) /* Loosely Packed */
52#define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */
53#define DPI_BPP_RGB888 (0 << 0)
54#define DPI_BPP_RGB666 (1 << 0)
55#define DPI_BPP_RGB565 (2 << 0)
56
57/* Video Path */
58#define VPCTRL0 0x0450
59#define OPXLFMT_RGB666 (0 << 8)
60#define OPXLFMT_RGB888 (1 << 8)
61#define FRMSYNC_DISABLED (0 << 4) /* Video Timing Gen Disabled */
62#define FRMSYNC_ENABLED (1 << 4) /* Video Timing Gen Enabled */
63#define MSF_DISABLED (0 << 0) /* Magic Square FRC disabled */
64#define MSF_ENABLED (1 << 0) /* Magic Square FRC enabled */
65#define HTIM01 0x0454
66#define HTIM02 0x0458
67#define VTIM01 0x045c
68#define VTIM02 0x0460
69#define VFUEN0 0x0464
70#define VFUEN BIT(0) /* Video Frame Timing Upload */
71
72/* System */
73#define TC_IDREG 0x0500
74#define SYSCTRL 0x0510
75#define DP0_AUDSRC_NO_INPUT (0 << 3)
76#define DP0_AUDSRC_I2S_RX (1 << 3)
77#define DP0_VIDSRC_NO_INPUT (0 << 0)
78#define DP0_VIDSRC_DSI_RX (1 << 0)
79#define DP0_VIDSRC_DPI_RX (2 << 0)
80#define DP0_VIDSRC_COLOR_BAR (3 << 0)
81
82/* Control */
83#define DP0CTL 0x0600
84#define VID_MN_GEN BIT(6) /* Auto-generate M/N values */
85#define EF_EN BIT(5) /* Enable Enhanced Framing */
86#define VID_EN BIT(1) /* Video transmission enable */
87#define DP_EN BIT(0) /* Enable DPTX function */
88
89/* Clocks */
90#define DP0_VIDMNGEN0 0x0610
91#define DP0_VIDMNGEN1 0x0614
92#define DP0_VMNGENSTATUS 0x0618
93
94/* Main Channel */
95#define DP0_SECSAMPLE 0x0640
96#define DP0_VIDSYNCDELAY 0x0644
97#define DP0_TOTALVAL 0x0648
98#define DP0_STARTVAL 0x064c
99#define DP0_ACTIVEVAL 0x0650
100#define DP0_SYNCVAL 0x0654
101#define DP0_MISC 0x0658
102#define TU_SIZE_RECOMMENDED (63) /* LSCLK cycles per TU */
103#define BPC_6 (0 << 5)
104#define BPC_8 (1 << 5)
105
106/* AUX channel */
107#define DP0_AUXCFG0 0x0660
108#define DP0_AUXCFG1 0x0664
109#define AUX_RX_FILTER_EN BIT(16)
110
111#define DP0_AUXADDR 0x0668
112#define DP0_AUXWDATA(i) (0x066c + (i) * 4)
113#define DP0_AUXRDATA(i) (0x067c + (i) * 4)
114#define DP0_AUXSTATUS 0x068c
115#define AUX_STATUS_MASK 0xf0
116#define AUX_STATUS_SHIFT 4
117#define AUX_TIMEOUT BIT(1)
118#define AUX_BUSY BIT(0)
119#define DP0_AUXI2CADR 0x0698
120
121/* Link Training */
122#define DP0_SRCCTRL 0x06a0
123#define DP0_SRCCTRL_SCRMBLDIS BIT(13)
124#define DP0_SRCCTRL_EN810B BIT(12)
125#define DP0_SRCCTRL_NOTP (0 << 8)
126#define DP0_SRCCTRL_TP1 (1 << 8)
127#define DP0_SRCCTRL_TP2 (2 << 8)
128#define DP0_SRCCTRL_LANESKEW BIT(7)
129#define DP0_SRCCTRL_SSCG BIT(3)
130#define DP0_SRCCTRL_LANES_1 (0 << 2)
131#define DP0_SRCCTRL_LANES_2 (1 << 2)
132#define DP0_SRCCTRL_BW27 (1 << 1)
133#define DP0_SRCCTRL_BW162 (0 << 1)
134#define DP0_SRCCTRL_AUTOCORRECT BIT(0)
135#define DP0_LTSTAT 0x06d0
136#define LT_LOOPDONE BIT(13)
137#define LT_STATUS_MASK (0x1f << 8)
138#define LT_CHANNEL1_EQ_BITS (DP_CHANNEL_EQ_BITS << 4)
139#define LT_INTERLANE_ALIGN_DONE BIT(3)
140#define LT_CHANNEL0_EQ_BITS (DP_CHANNEL_EQ_BITS)
141#define DP0_SNKLTCHGREQ 0x06d4
142#define DP0_LTLOOPCTRL 0x06d8
143#define DP0_SNKLTCTRL 0x06e4
144
145/* PHY */
146#define DP_PHY_CTRL 0x0800
147#define DP_PHY_RST BIT(28) /* DP PHY Global Soft Reset */
148#define BGREN BIT(25) /* AUX PHY BGR Enable */
149#define PWR_SW_EN BIT(24) /* PHY Power Switch Enable */
150#define PHY_M1_RST BIT(12) /* Reset PHY1 Main Channel */
151#define PHY_RDY BIT(16) /* PHY Main Channels Ready */
152#define PHY_M0_RST BIT(8) /* Reset PHY0 Main Channel */
153#define PHY_A0_EN BIT(1) /* PHY Aux Channel0 Enable */
154#define PHY_M0_EN BIT(0) /* PHY Main Channel0 Enable */
155
156/* PLL */
157#define DP0_PLLCTRL 0x0900
158#define DP1_PLLCTRL 0x0904 /* not defined in DS */
159#define PXL_PLLCTRL 0x0908
160#define PLLUPDATE BIT(2)
161#define PLLBYP BIT(1)
162#define PLLEN BIT(0)
163#define PXL_PLLPARAM 0x0914
164#define IN_SEL_REFCLK (0 << 14)
165#define SYS_PLLPARAM 0x0918
166#define REF_FREQ_38M4 (0 << 8) /* 38.4 MHz */
167#define REF_FREQ_19M2 (1 << 8) /* 19.2 MHz */
168#define REF_FREQ_26M (2 << 8) /* 26 MHz */
169#define REF_FREQ_13M (3 << 8) /* 13 MHz */
170#define SYSCLK_SEL_LSCLK (0 << 4)
171#define LSCLK_DIV_1 (0 << 0)
172#define LSCLK_DIV_2 (1 << 0)
173
174/* Test & Debug */
175#define TSTCTL 0x0a00
176#define PLL_DBG 0x0a04
177
178static bool tc_test_pattern;
179module_param_named(test, tc_test_pattern, bool, 0644);
180
181struct tc_edp_link {
182 struct drm_dp_link base;
183 u8 assr;
184 int scrambler_dis;
185 int spread;
186 int coding8b10b;
187 u8 swing;
188 u8 preemp;
189};
190
191struct tc_data {
192 struct device *dev;
193 struct regmap *regmap;
194 struct drm_dp_aux aux;
195
196 struct drm_bridge bridge;
197 struct drm_connector connector;
198 struct drm_panel *panel;
199
200 /* link settings */
201 struct tc_edp_link link;
202
203 /* display edid */
204 struct edid *edid;
205 /* current mode */
206 struct drm_display_mode *mode;
207
208 u32 rev;
209 u8 assr;
210
211 struct gpio_desc *sd_gpio;
212 struct gpio_desc *reset_gpio;
213 struct clk *refclk;
214};
215
216static inline struct tc_data *aux_to_tc(struct drm_dp_aux *a)
217{
218 return container_of(a, struct tc_data, aux);
219}
220
221static inline struct tc_data *bridge_to_tc(struct drm_bridge *b)
222{
223 return container_of(b, struct tc_data, bridge);
224}
225
226static inline struct tc_data *connector_to_tc(struct drm_connector *c)
227{
228 return container_of(c, struct tc_data, connector);
229}
230
231/* Simple macros to avoid repeated error checks */
232#define tc_write(reg, var) \
233 do { \
234 ret = regmap_write(tc->regmap, reg, var); \
235 if (ret) \
236 goto err; \
237 } while (0)
238#define tc_read(reg, var) \
239 do { \
240 ret = regmap_read(tc->regmap, reg, var); \
241 if (ret) \
242 goto err; \
243 } while (0)
244
245static inline int tc_poll_timeout(struct regmap *map, unsigned int addr,
246 unsigned int cond_mask,
247 unsigned int cond_value,
248 unsigned long sleep_us, u64 timeout_us)
249{
250 ktime_t timeout = ktime_add_us(ktime_get(), timeout_us);
251 unsigned int val;
252 int ret;
253
254 for (;;) {
255 ret = regmap_read(map, addr, &val);
256 if (ret)
257 break;
258 if ((val & cond_mask) == cond_value)
259 break;
260 if (timeout_us && ktime_compare(ktime_get(), timeout) > 0) {
261 ret = regmap_read(map, addr, &val);
262 break;
263 }
264 if (sleep_us)
265 usleep_range((sleep_us >> 2) + 1, sleep_us);
266 }
267 return ret ?: (((val & cond_mask) == cond_value) ? 0 : -ETIMEDOUT);
268}
269
270static int tc_aux_wait_busy(struct tc_data *tc, unsigned int timeout_ms)
271{
272 return tc_poll_timeout(tc->regmap, DP0_AUXSTATUS, AUX_BUSY, 0,
273 1000, 1000 * timeout_ms);
274}
275
276static int tc_aux_get_status(struct tc_data *tc, u8 *reply)
277{
278 int ret;
279 u32 value;
280
281 ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &value);
282 if (ret < 0)
283 return ret;
284 if (value & AUX_BUSY) {
285 if (value & AUX_TIMEOUT) {
286 dev_err(tc->dev, "i2c access timeout!\n");
287 return -ETIMEDOUT;
288 }
289 return -EBUSY;
290 }
291
292 *reply = (value & AUX_STATUS_MASK) >> AUX_STATUS_SHIFT;
293 return 0;
294}
295
296static ssize_t tc_aux_transfer(struct drm_dp_aux *aux,
297 struct drm_dp_aux_msg *msg)
298{
299 struct tc_data *tc = aux_to_tc(aux);
300 size_t size = min_t(size_t, 8, msg->size);
301 u8 request = msg->request & ~DP_AUX_I2C_MOT;
302 u8 *buf = msg->buffer;
303 u32 tmp = 0;
304 int i = 0;
305 int ret;
306
307 if (size == 0)
308 return 0;
309
310 ret = tc_aux_wait_busy(tc, 100);
311 if (ret)
312 goto err;
313
314 if (request == DP_AUX_I2C_WRITE || request == DP_AUX_NATIVE_WRITE) {
315 /* Store data */
316 while (i < size) {
317 if (request == DP_AUX_NATIVE_WRITE)
318 tmp = tmp | (buf[i] << (8 * (i & 0x3)));
319 else
320 tmp = (tmp << 8) | buf[i];
321 i++;
322 if (((i % 4) == 0) || (i == size)) {
323 tc_write(DP0_AUXWDATA((i - 1) >> 2), tmp);
324 tmp = 0;
325 }
326 }
327 } else if (request != DP_AUX_I2C_READ &&
328 request != DP_AUX_NATIVE_READ) {
329 return -EINVAL;
330 }
331
332 /* Store address */
333 tc_write(DP0_AUXADDR, msg->address);
334 /* Start transfer */
335 tc_write(DP0_AUXCFG0, ((size - 1) << 8) | request);
336
337 ret = tc_aux_wait_busy(tc, 100);
338 if (ret)
339 goto err;
340
341 ret = tc_aux_get_status(tc, &msg->reply);
342 if (ret)
343 goto err;
344
345 if (request == DP_AUX_I2C_READ || request == DP_AUX_NATIVE_READ) {
346 /* Read data */
347 while (i < size) {
348 if ((i % 4) == 0)
349 tc_read(DP0_AUXRDATA(i >> 2), &tmp);
350 buf[i] = tmp & 0xff;
351 tmp = tmp >> 8;
352 i++;
353 }
354 }
355
356 return size;
357err:
358 return ret;
359}
360
361static const char * const training_pattern1_errors[] = {
362 "No errors",
363 "Aux write error",
364 "Aux read error",
365 "Max voltage reached error",
366 "Loop counter expired error",
367 "res", "res", "res"
368};
369
370static const char * const training_pattern2_errors[] = {
371 "No errors",
372 "Aux write error",
373 "Aux read error",
374 "Clock recovery failed error",
375 "Loop counter expired error",
376 "res", "res", "res"
377};
378
379static u32 tc_srcctrl(struct tc_data *tc)
380{
381 /*
382 * No training pattern, skew lane 1 data by two LSCLK cycles with
383 * respect to lane 0 data, AutoCorrect Mode = 0
384 */
385 u32 reg = DP0_SRCCTRL_NOTP | DP0_SRCCTRL_LANESKEW;
386
387 if (tc->link.scrambler_dis)
388 reg |= DP0_SRCCTRL_SCRMBLDIS; /* Scrambler Disabled */
389 if (tc->link.coding8b10b)
390 /* Enable 8/10B Encoder (TxData[19:16] not used) */
391 reg |= DP0_SRCCTRL_EN810B;
392 if (tc->link.spread)
393 reg |= DP0_SRCCTRL_SSCG; /* Spread Spectrum Enable */
394 if (tc->link.base.num_lanes == 2)
395 reg |= DP0_SRCCTRL_LANES_2; /* Two Main Channel Lanes */
396 if (tc->link.base.rate != 162000)
397 reg |= DP0_SRCCTRL_BW27; /* 2.7 Gbps link */
398 return reg;
399}
400
401static void tc_wait_pll_lock(struct tc_data *tc)
402{
403 /* Wait for PLL to lock: up to 2.09 ms, depending on refclk */
404 usleep_range(3000, 6000);
405}
406
407static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
408{
409 int ret;
410 int i_pre, best_pre = 1;
411 int i_post, best_post = 1;
412 int div, best_div = 1;
413 int mul, best_mul = 1;
414 int delta, best_delta;
415 int ext_div[] = {1, 2, 3, 5, 7};
416 int best_pixelclock = 0;
417 int vco_hi = 0;
418
419 dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock,
420 refclk);
421 best_delta = pixelclock;
422 /* Loop over all possible ext_divs, skipping invalid configurations */
423 for (i_pre = 0; i_pre < ARRAY_SIZE(ext_div); i_pre++) {
424 /*
425 * refclk / ext_pre_div should be in the 1 to 200 MHz range.
426 * We don't allow any refclk > 200 MHz, only check lower bounds.
427 */
428 if (refclk / ext_div[i_pre] < 1000000)
429 continue;
430 for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) {
431 for (div = 1; div <= 16; div++) {
432 u32 clk;
433 u64 tmp;
434
435 tmp = pixelclock * ext_div[i_pre] *
436 ext_div[i_post] * div;
437 do_div(tmp, refclk);
438 mul = tmp;
439
440 /* Check limits */
441 if ((mul < 1) || (mul > 128))
442 continue;
443
444 clk = (refclk / ext_div[i_pre] / div) * mul;
445 /*
446 * refclk * mul / (ext_pre_div * pre_div)
447 * should be in the 150 to 650 MHz range
448 */
449 if ((clk > 650000000) || (clk < 150000000))
450 continue;
451
452 clk = clk / ext_div[i_post];
453 delta = clk - pixelclock;
454
455 if (abs(delta) < abs(best_delta)) {
456 best_pre = i_pre;
457 best_post = i_post;
458 best_div = div;
459 best_mul = mul;
460 best_delta = delta;
461 best_pixelclock = clk;
462 }
463 }
464 }
465 }
466 if (best_pixelclock == 0) {
467 dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n",
468 pixelclock);
469 return -EINVAL;
470 }
471
472 dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock,
473 best_delta);
474 dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk,
475 ext_div[best_pre], best_div, best_mul, ext_div[best_post]);
476
477 /* if VCO >= 300 MHz */
478 if (refclk / ext_div[best_pre] / best_div * best_mul >= 300000000)
479 vco_hi = 1;
480 /* see DS */
481 if (best_div == 16)
482 best_div = 0;
483 if (best_mul == 128)
484 best_mul = 0;
485
486 /* Power up PLL and switch to bypass */
487 tc_write(PXL_PLLCTRL, PLLBYP | PLLEN);
488
489 tc_write(PXL_PLLPARAM,
490 (vco_hi << 24) | /* For PLL VCO >= 300 MHz = 1 */
491 (ext_div[best_pre] << 20) | /* External Pre-divider */
492 (ext_div[best_post] << 16) | /* External Post-divider */
493 IN_SEL_REFCLK | /* Use RefClk as PLL input */
494 (best_div << 8) | /* Divider for PLL RefClk */
495 (best_mul << 0)); /* Multiplier for PLL */
496
497 /* Force PLL parameter update and disable bypass */
498 tc_write(PXL_PLLCTRL, PLLUPDATE | PLLEN);
499
500 tc_wait_pll_lock(tc);
501
502 return 0;
503err:
504 return ret;
505}
506
507static int tc_pxl_pll_dis(struct tc_data *tc)
508{
509 /* Enable PLL bypass, power down PLL */
510 return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP);
511}
512
513static int tc_stream_clock_calc(struct tc_data *tc)
514{
515 int ret;
516 /*
517 * If the Stream clock and Link Symbol clock are
518 * asynchronous with each other, the value of M changes over
519 * time. This way of generating link clock and stream
520 * clock is called Asynchronous Clock mode. The value M
521 * must change while the value N stays constant. The
522 * value of N in this Asynchronous Clock mode must be set
523 * to 2^15 or 32,768.
524 *
525 * LSCLK = 1/10 of high speed link clock
526 *
527 * f_STRMCLK = M/N * f_LSCLK
528 * M/N = f_STRMCLK / f_LSCLK
529 *
530 */
531 tc_write(DP0_VIDMNGEN1, 32768);
532
533 return 0;
534err:
535 return ret;
536}
537
538static int tc_aux_link_setup(struct tc_data *tc)
539{
540 unsigned long rate;
541 u32 value;
542 int ret;
543
544 rate = clk_get_rate(tc->refclk);
545 switch (rate) {
546 case 38400000:
547 value = REF_FREQ_38M4;
548 break;
549 case 26000000:
550 value = REF_FREQ_26M;
551 break;
552 case 19200000:
553 value = REF_FREQ_19M2;
554 break;
555 case 13000000:
556 value = REF_FREQ_13M;
557 break;
558 default:
559 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate);
560 return -EINVAL;
561 }
562
563 /* Setup DP-PHY / PLL */
564 value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
565 tc_write(SYS_PLLPARAM, value);
566
567 tc_write(DP_PHY_CTRL, BGREN | PWR_SW_EN | BIT(2) | PHY_A0_EN);
568
569 /*
570 * Initially PLLs are in bypass. Force PLL parameter update,
571 * disable PLL bypass, enable PLL
572 */
573 tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN);
574 tc_wait_pll_lock(tc);
575
576 tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN);
577 tc_wait_pll_lock(tc);
578
579 ret = tc_poll_timeout(tc->regmap, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1,
580 1000);
581 if (ret == -ETIMEDOUT) {
582 dev_err(tc->dev, "Timeout waiting for PHY to become ready");
583 return ret;
584 } else if (ret)
585 goto err;
586
587 /* Setup AUX link */
588 tc_write(DP0_AUXCFG1, AUX_RX_FILTER_EN |
589 (0x06 << 8) | /* Aux Bit Period Calculator Threshold */
590 (0x3f << 0)); /* Aux Response Timeout Timer */
591
592 return 0;
593err:
594 dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret);
595 return ret;
596}
597
598static int tc_get_display_props(struct tc_data *tc)
599{
600 int ret;
601 /* temp buffer */
602 u8 tmp[8];
603
604 /* Read DP Rx Link Capability */
605 ret = drm_dp_link_probe(&tc->aux, &tc->link.base);
606 if (ret < 0)
607 goto err_dpcd_read;
608 if (tc->link.base.rate != 162000 && tc->link.base.rate != 270000) {
609 dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n");
610 tc->link.base.rate = 270000;
611 }
612
613 if (tc->link.base.num_lanes > 2) {
614 dev_dbg(tc->dev, "Falling to 2 lanes\n");
615 tc->link.base.num_lanes = 2;
616 }
617
618 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, tmp);
619 if (ret < 0)
620 goto err_dpcd_read;
621 tc->link.spread = tmp[0] & BIT(0); /* 0.5% down spread */
622
623 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, tmp);
624 if (ret < 0)
625 goto err_dpcd_read;
626 tc->link.coding8b10b = tmp[0] & BIT(0);
627 tc->link.scrambler_dis = 0;
628 /* read assr */
629 ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, tmp);
630 if (ret < 0)
631 goto err_dpcd_read;
632 tc->link.assr = tmp[0] & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
633
634 dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n",
635 tc->link.base.revision >> 4, tc->link.base.revision & 0x0f,
636 (tc->link.base.rate == 162000) ? "1.62Gbps" : "2.7Gbps",
637 tc->link.base.num_lanes,
638 (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) ?
639 "enhanced" : "non-enhanced");
640 dev_dbg(tc->dev, "ANSI 8B/10B: %d\n", tc->link.coding8b10b);
641 dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n",
642 tc->link.assr, tc->assr);
643
644 return 0;
645
646err_dpcd_read:
647 dev_err(tc->dev, "failed to read DPCD: %d\n", ret);
648 return ret;
649}
650
651static int tc_set_video_mode(struct tc_data *tc, struct drm_display_mode *mode)
652{
653 int ret;
654 int vid_sync_dly;
655 int max_tu_symbol;
656
657 int left_margin = mode->htotal - mode->hsync_end;
658 int right_margin = mode->hsync_start - mode->hdisplay;
659 int hsync_len = mode->hsync_end - mode->hsync_start;
660 int upper_margin = mode->vtotal - mode->vsync_end;
661 int lower_margin = mode->vsync_start - mode->vdisplay;
662 int vsync_len = mode->vsync_end - mode->vsync_start;
663
664 /*
665 * Recommended maximum number of symbols transferred in a transfer unit:
666 * DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size,
667 * (output active video bandwidth in bytes))
668 * Must be less than tu_size.
669 */
670 max_tu_symbol = TU_SIZE_RECOMMENDED - 1;
671
672 dev_dbg(tc->dev, "set mode %dx%d\n",
673 mode->hdisplay, mode->vdisplay);
674 dev_dbg(tc->dev, "H margin %d,%d sync %d\n",
675 left_margin, right_margin, hsync_len);
676 dev_dbg(tc->dev, "V margin %d,%d sync %d\n",
677 upper_margin, lower_margin, vsync_len);
678 dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal);
679
680
681 /*
682 * LCD Ctl Frame Size
683 * datasheet is not clear of vsdelay in case of DPI
684 * assume we do not need any delay when DPI is a source of
685 * sync signals
686 */
687 tc_write(VPCTRL0, (0 << 20) /* VSDELAY */ |
688 OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED);
689 tc_write(HTIM01, (ALIGN(left_margin, 2) << 16) | /* H back porch */
690 (ALIGN(hsync_len, 2) << 0)); /* Hsync */
691 tc_write(HTIM02, (ALIGN(right_margin, 2) << 16) | /* H front porch */
692 (ALIGN(mode->hdisplay, 2) << 0)); /* width */
693 tc_write(VTIM01, (upper_margin << 16) | /* V back porch */
694 (vsync_len << 0)); /* Vsync */
695 tc_write(VTIM02, (lower_margin << 16) | /* V front porch */
696 (mode->vdisplay << 0)); /* height */
697 tc_write(VFUEN0, VFUEN); /* update settings */
698
699 /* Test pattern settings */
700 tc_write(TSTCTL,
701 (120 << 24) | /* Red Color component value */
702 (20 << 16) | /* Green Color component value */
703 (99 << 8) | /* Blue Color component value */
704 (1 << 4) | /* Enable I2C Filter */
705 (2 << 0) | /* Color bar Mode */
706 0);
707
708 /* DP Main Stream Attributes */
709 vid_sync_dly = hsync_len + left_margin + mode->hdisplay;
710 tc_write(DP0_VIDSYNCDELAY,
711 (max_tu_symbol << 16) | /* thresh_dly */
712 (vid_sync_dly << 0));
713
714 tc_write(DP0_TOTALVAL, (mode->vtotal << 16) | (mode->htotal));
715
716 tc_write(DP0_STARTVAL,
717 ((upper_margin + vsync_len) << 16) |
718 ((left_margin + hsync_len) << 0));
719
720 tc_write(DP0_ACTIVEVAL, (mode->vdisplay << 16) | (mode->hdisplay));
721
722 tc_write(DP0_SYNCVAL, (vsync_len << 16) | (hsync_len << 0));
723
724 tc_write(DPIPXLFMT, VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW |
725 DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 | DPI_BPP_RGB888);
726
727 tc_write(DP0_MISC, (max_tu_symbol << 23) | (TU_SIZE_RECOMMENDED << 16) |
728 BPC_8);
729
730 return 0;
731err:
732 return ret;
733}
734
735static int tc_link_training(struct tc_data *tc, int pattern)
736{
737 const char * const *errors;
738 u32 srcctrl = tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
739 DP0_SRCCTRL_AUTOCORRECT;
740 int timeout;
741 int retry;
742 u32 value;
743 int ret;
744
745 if (pattern == DP_TRAINING_PATTERN_1) {
746 srcctrl |= DP0_SRCCTRL_TP1;
747 errors = training_pattern1_errors;
748 } else {
749 srcctrl |= DP0_SRCCTRL_TP2;
750 errors = training_pattern2_errors;
751 }
752
753 /* Set DPCD 0x102 for Training Part 1 or 2 */
754 tc_write(DP0_SNKLTCTRL, DP_LINK_SCRAMBLING_DISABLE | pattern);
755
756 tc_write(DP0_LTLOOPCTRL,
757 (0x0f << 28) | /* Defer Iteration Count */
758 (0x0f << 24) | /* Loop Iteration Count */
759 (0x0d << 0)); /* Loop Timer Delay */
760
761 retry = 5;
762 do {
763 /* Set DP0 Training Pattern */
764 tc_write(DP0_SRCCTRL, srcctrl);
765
766 /* Enable DP0 to start Link Training */
767 tc_write(DP0CTL, DP_EN);
768
769 /* wait */
770 timeout = 1000;
771 do {
772 tc_read(DP0_LTSTAT, &value);
773 udelay(1);
774 } while ((!(value & LT_LOOPDONE)) && (--timeout));
775 if (timeout == 0) {
776 dev_err(tc->dev, "Link training timeout!\n");
777 } else {
778 int pattern = (value >> 11) & 0x3;
779 int error = (value >> 8) & 0x7;
780
781 dev_dbg(tc->dev,
782 "Link training phase %d done after %d uS: %s\n",
783 pattern, 1000 - timeout, errors[error]);
784 if (pattern == DP_TRAINING_PATTERN_1 && error == 0)
785 break;
786 if (pattern == DP_TRAINING_PATTERN_2) {
787 value &= LT_CHANNEL1_EQ_BITS |
788 LT_INTERLANE_ALIGN_DONE |
789 LT_CHANNEL0_EQ_BITS;
790 /* in case of two lanes */
791 if ((tc->link.base.num_lanes == 2) &&
792 (value == (LT_CHANNEL1_EQ_BITS |
793 LT_INTERLANE_ALIGN_DONE |
794 LT_CHANNEL0_EQ_BITS)))
795 break;
796 /* in case of one line */
797 if ((tc->link.base.num_lanes == 1) &&
798 (value == (LT_INTERLANE_ALIGN_DONE |
799 LT_CHANNEL0_EQ_BITS)))
800 break;
801 }
802 }
803 /* restart */
804 tc_write(DP0CTL, 0);
805 usleep_range(10, 20);
806 } while (--retry);
807 if (retry == 0) {
808 dev_err(tc->dev, "Failed to finish training phase %d\n",
809 pattern);
810 }
811
812 return 0;
813err:
814 return ret;
815}
816
817static int tc_main_link_setup(struct tc_data *tc)
818{
819 struct drm_dp_aux *aux = &tc->aux;
820 struct device *dev = tc->dev;
821 unsigned int rate;
822 u32 dp_phy_ctrl;
823 int timeout;
824 u32 value;
825 int ret;
826 u8 tmp[8];
827
828 /* display mode should be set at this point */
829 if (!tc->mode)
830 return -EINVAL;
831
832 /* from excel file - DP0_SrcCtrl */
833 tc_write(DP0_SRCCTRL, DP0_SRCCTRL_SCRMBLDIS | DP0_SRCCTRL_EN810B |
834 DP0_SRCCTRL_LANESKEW | DP0_SRCCTRL_LANES_2 |
835 DP0_SRCCTRL_BW27 | DP0_SRCCTRL_AUTOCORRECT);
836 /* from excel file - DP1_SrcCtrl */
837 tc_write(0x07a0, 0x00003083);
838
839 rate = clk_get_rate(tc->refclk);
840 switch (rate) {
841 case 38400000:
842 value = REF_FREQ_38M4;
843 break;
844 case 26000000:
845 value = REF_FREQ_26M;
846 break;
847 case 19200000:
848 value = REF_FREQ_19M2;
849 break;
850 case 13000000:
851 value = REF_FREQ_13M;
852 break;
853 default:
854 return -EINVAL;
855 }
856 value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
857 tc_write(SYS_PLLPARAM, value);
858 /* Setup Main Link */
859 dp_phy_ctrl = BGREN | PWR_SW_EN | BIT(2) | PHY_A0_EN | PHY_M0_EN;
860 tc_write(DP_PHY_CTRL, dp_phy_ctrl);
861 msleep(100);
862
863 /* PLL setup */
864 tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN);
865 tc_wait_pll_lock(tc);
866
867 tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN);
868 tc_wait_pll_lock(tc);
869
870 /* PXL PLL setup */
871 if (tc_test_pattern) {
872 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk),
873 1000 * tc->mode->clock);
874 if (ret)
875 goto err;
876 }
877
878 /* Reset/Enable Main Links */
879 dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST;
880 tc_write(DP_PHY_CTRL, dp_phy_ctrl);
881 usleep_range(100, 200);
882 dp_phy_ctrl &= ~(DP_PHY_RST | PHY_M1_RST | PHY_M0_RST);
883 tc_write(DP_PHY_CTRL, dp_phy_ctrl);
884
885 timeout = 1000;
886 do {
887 tc_read(DP_PHY_CTRL, &value);
888 udelay(1);
889 } while ((!(value & PHY_RDY)) && (--timeout));
890
891 if (timeout == 0) {
892 dev_err(dev, "timeout waiting for phy become ready");
893 return -ETIMEDOUT;
894 }
895
896 /* Set misc: 8 bits per color */
897 ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8);
898 if (ret)
899 goto err;
900
901 /*
902 * ASSR mode
903 * on TC358767 side ASSR configured through strap pin
904 * seems there is no way to change this setting from SW
905 *
906 * check is tc configured for same mode
907 */
908 if (tc->assr != tc->link.assr) {
909 dev_dbg(dev, "Trying to set display to ASSR: %d\n",
910 tc->assr);
911 /* try to set ASSR on display side */
912 tmp[0] = tc->assr;
913 ret = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, tmp[0]);
914 if (ret < 0)
915 goto err_dpcd_read;
916 /* read back */
917 ret = drm_dp_dpcd_readb(aux, DP_EDP_CONFIGURATION_SET, tmp);
918 if (ret < 0)
919 goto err_dpcd_read;
920
921 if (tmp[0] != tc->assr) {
922 dev_dbg(dev, "Failed to switch display ASSR to %d, falling back to unscrambled mode\n",
923 tc->assr);
924 /* trying with disabled scrambler */
925 tc->link.scrambler_dis = 1;
926 }
927 }
928
929 /* Setup Link & DPRx Config for Training */
930 ret = drm_dp_link_configure(aux, &tc->link.base);
931 if (ret < 0)
932 goto err_dpcd_write;
933
934 /* DOWNSPREAD_CTRL */
935 tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00;
936 /* MAIN_LINK_CHANNEL_CODING_SET */
937 tmp[1] = tc->link.coding8b10b ? DP_SET_ANSI_8B10B : 0x00;
938 ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, tmp, 2);
939 if (ret < 0)
940 goto err_dpcd_write;
941
942 ret = tc_link_training(tc, DP_TRAINING_PATTERN_1);
943 if (ret)
944 goto err;
945
946 ret = tc_link_training(tc, DP_TRAINING_PATTERN_2);
947 if (ret)
948 goto err;
949
950 /* Clear DPCD 0x102 */
951 /* Note: Can Not use DP0_SNKLTCTRL (0x06E4) short cut */
952 tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00;
953 ret = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, tmp[0]);
954 if (ret < 0)
955 goto err_dpcd_write;
956
957 /* Clear Training Pattern, set AutoCorrect Mode = 1 */
958 tc_write(DP0_SRCCTRL, tc_srcctrl(tc) | DP0_SRCCTRL_AUTOCORRECT);
959
960 /* Wait */
961 timeout = 100;
962 do {
963 udelay(1);
964 /* Read DPCD 0x202-0x207 */
965 ret = drm_dp_dpcd_read_link_status(aux, tmp + 2);
966 if (ret < 0)
967 goto err_dpcd_read;
968 } while ((--timeout) &&
969 !(drm_dp_channel_eq_ok(tmp + 2, tc->link.base.num_lanes)));
970
971 if (timeout == 0) {
972 /* Read DPCD 0x200-0x201 */
973 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT, tmp, 2);
974 if (ret < 0)
975 goto err_dpcd_read;
976 dev_err(dev, "channel(s) EQ not ok\n");
977 dev_info(dev, "0x0200 SINK_COUNT: 0x%02x\n", tmp[0]);
978 dev_info(dev, "0x0201 DEVICE_SERVICE_IRQ_VECTOR: 0x%02x\n",
979 tmp[1]);
980 dev_info(dev, "0x0202 LANE0_1_STATUS: 0x%02x\n", tmp[2]);
981 dev_info(dev, "0x0204 LANE_ALIGN_STATUS_UPDATED: 0x%02x\n",
982 tmp[4]);
983 dev_info(dev, "0x0205 SINK_STATUS: 0x%02x\n", tmp[5]);
984 dev_info(dev, "0x0206 ADJUST_REQUEST_LANE0_1: 0x%02x\n",
985 tmp[6]);
986
987 return -EAGAIN;
988 }
989
990 ret = tc_set_video_mode(tc, tc->mode);
991 if (ret)
992 goto err;
993
994 /* Set M/N */
995 ret = tc_stream_clock_calc(tc);
996 if (ret)
997 goto err;
998
999 return 0;
1000err_dpcd_read:
1001 dev_err(tc->dev, "Failed to read DPCD: %d\n", ret);
1002 return ret;
1003err_dpcd_write:
1004 dev_err(tc->dev, "Failed to write DPCD: %d\n", ret);
1005err:
1006 return ret;
1007}
1008
1009static int tc_main_link_stream(struct tc_data *tc, int state)
1010{
1011 int ret;
1012 u32 value;
1013
1014 dev_dbg(tc->dev, "stream: %d\n", state);
1015
1016 if (state) {
1017 value = VID_MN_GEN | DP_EN;
1018 if (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
1019 value |= EF_EN;
1020 tc_write(DP0CTL, value);
1021 /*
1022 * VID_EN assertion should be delayed by at least N * LSCLK
1023 * cycles from the time VID_MN_GEN is enabled in order to
1024 * generate stable values for VID_M. LSCLK is 270 MHz or
1025 * 162 MHz, VID_N is set to 32768 in tc_stream_clock_calc(),
1026 * so a delay of at least 203 us should suffice.
1027 */
1028 usleep_range(500, 1000);
1029 value |= VID_EN;
1030 tc_write(DP0CTL, value);
1031 /* Set input interface */
1032 value = DP0_AUDSRC_NO_INPUT;
1033 if (tc_test_pattern)
1034 value |= DP0_VIDSRC_COLOR_BAR;
1035 else
1036 value |= DP0_VIDSRC_DPI_RX;
1037 tc_write(SYSCTRL, value);
1038 } else {
1039 tc_write(DP0CTL, 0);
1040 }
1041
1042 return 0;
1043err:
1044 return ret;
1045}
1046
1047static void tc_bridge_pre_enable(struct drm_bridge *bridge)
1048{
1049 struct tc_data *tc = bridge_to_tc(bridge);
1050
1051 drm_panel_prepare(tc->panel);
1052}
1053
1054static void tc_bridge_enable(struct drm_bridge *bridge)
1055{
1056 struct tc_data *tc = bridge_to_tc(bridge);
1057 int ret;
1058
1059 ret = tc_main_link_setup(tc);
1060 if (ret < 0) {
1061 dev_err(tc->dev, "main link setup error: %d\n", ret);
1062 return;
1063 }
1064
1065 ret = tc_main_link_stream(tc, 1);
1066 if (ret < 0) {
1067 dev_err(tc->dev, "main link stream start error: %d\n", ret);
1068 return;
1069 }
1070
1071 drm_panel_enable(tc->panel);
1072}
1073
1074static void tc_bridge_disable(struct drm_bridge *bridge)
1075{
1076 struct tc_data *tc = bridge_to_tc(bridge);
1077 int ret;
1078
1079 drm_panel_disable(tc->panel);
1080
1081 ret = tc_main_link_stream(tc, 0);
1082 if (ret < 0)
1083 dev_err(tc->dev, "main link stream stop error: %d\n", ret);
1084}
1085
1086static void tc_bridge_post_disable(struct drm_bridge *bridge)
1087{
1088 struct tc_data *tc = bridge_to_tc(bridge);
1089
1090 drm_panel_unprepare(tc->panel);
1091}
1092
1093static bool tc_bridge_mode_fixup(struct drm_bridge *bridge,
1094 const struct drm_display_mode *mode,
1095 struct drm_display_mode *adj)
1096{
1097 /* Fixup sync polarities, both hsync and vsync are active low */
1098 adj->flags = mode->flags;
1099 adj->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
1100 adj->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
1101
1102 return true;
1103}
1104
1105static int tc_connector_mode_valid(struct drm_connector *connector,
1106 struct drm_display_mode *mode)
1107{
1108 /* DPI interface clock limitation: upto 154 MHz */
1109 if (mode->clock > 154000)
1110 return MODE_CLOCK_HIGH;
1111
1112 return MODE_OK;
1113}
1114
1115static void tc_bridge_mode_set(struct drm_bridge *bridge,
1116 struct drm_display_mode *mode,
1117 struct drm_display_mode *adj)
1118{
1119 struct tc_data *tc = bridge_to_tc(bridge);
1120
1121 tc->mode = mode;
1122}
1123
1124static int tc_connector_get_modes(struct drm_connector *connector)
1125{
1126 struct tc_data *tc = connector_to_tc(connector);
1127 struct edid *edid;
1128 unsigned int count;
1129
1130 if (tc->panel && tc->panel->funcs && tc->panel->funcs->get_modes) {
1131 count = tc->panel->funcs->get_modes(tc->panel);
1132 if (count > 0)
1133 return count;
1134 }
1135
1136 edid = drm_get_edid(connector, &tc->aux.ddc);
1137
1138 kfree(tc->edid);
1139 tc->edid = edid;
1140 if (!edid)
1141 return 0;
1142
1143 drm_mode_connector_update_edid_property(connector, edid);
1144 count = drm_add_edid_modes(connector, edid);
1145
1146 return count;
1147}
1148
1149static void tc_connector_set_polling(struct tc_data *tc,
1150 struct drm_connector *connector)
1151{
1152 /* TODO: add support for HPD */
1153 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1154 DRM_CONNECTOR_POLL_DISCONNECT;
1155}
1156
1157static struct drm_encoder *
1158tc_connector_best_encoder(struct drm_connector *connector)
1159{
1160 struct tc_data *tc = connector_to_tc(connector);
1161
1162 return tc->bridge.encoder;
1163}
1164
1165static const struct drm_connector_helper_funcs tc_connector_helper_funcs = {
1166 .get_modes = tc_connector_get_modes,
1167 .mode_valid = tc_connector_mode_valid,
1168 .best_encoder = tc_connector_best_encoder,
1169};
1170
1171static const struct drm_connector_funcs tc_connector_funcs = {
1172 .fill_modes = drm_helper_probe_single_connector_modes,
1173 .destroy = drm_connector_cleanup,
1174 .reset = drm_atomic_helper_connector_reset,
1175 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1176 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1177};
1178
1179static int tc_bridge_attach(struct drm_bridge *bridge)
1180{
1181 u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1182 struct tc_data *tc = bridge_to_tc(bridge);
1183 struct drm_device *drm = bridge->dev;
1184 int ret;
1185
1186 /* Create eDP connector */
1187 drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs);
1188 ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs,
1189 DRM_MODE_CONNECTOR_eDP);
1190 if (ret)
1191 return ret;
1192
1193 if (tc->panel)
1194 drm_panel_attach(tc->panel, &tc->connector);
1195
1196 drm_display_info_set_bus_formats(&tc->connector.display_info,
1197 &bus_format, 1);
1198 drm_mode_connector_attach_encoder(&tc->connector, tc->bridge.encoder);
1199
1200 return 0;
1201}
1202
1203static const struct drm_bridge_funcs tc_bridge_funcs = {
1204 .attach = tc_bridge_attach,
1205 .mode_set = tc_bridge_mode_set,
1206 .pre_enable = tc_bridge_pre_enable,
1207 .enable = tc_bridge_enable,
1208 .disable = tc_bridge_disable,
1209 .post_disable = tc_bridge_post_disable,
1210 .mode_fixup = tc_bridge_mode_fixup,
1211};
1212
1213static bool tc_readable_reg(struct device *dev, unsigned int reg)
1214{
1215 return reg != SYSCTRL;
1216}
1217
1218static const struct regmap_range tc_volatile_ranges[] = {
1219 regmap_reg_range(DP0_AUXWDATA(0), DP0_AUXSTATUS),
1220 regmap_reg_range(DP0_LTSTAT, DP0_SNKLTCHGREQ),
1221 regmap_reg_range(DP_PHY_CTRL, DP_PHY_CTRL),
1222 regmap_reg_range(DP0_PLLCTRL, PXL_PLLCTRL),
1223 regmap_reg_range(VFUEN0, VFUEN0),
1224};
1225
1226static const struct regmap_access_table tc_volatile_table = {
1227 .yes_ranges = tc_volatile_ranges,
1228 .n_yes_ranges = ARRAY_SIZE(tc_volatile_ranges),
1229};
1230
1231static bool tc_writeable_reg(struct device *dev, unsigned int reg)
1232{
1233 return (reg != TC_IDREG) &&
1234 (reg != DP0_LTSTAT) &&
1235 (reg != DP0_SNKLTCHGREQ);
1236}
1237
1238static const struct regmap_config tc_regmap_config = {
1239 .name = "tc358767",
1240 .reg_bits = 16,
1241 .val_bits = 32,
1242 .reg_stride = 4,
1243 .max_register = PLL_DBG,
1244 .cache_type = REGCACHE_RBTREE,
1245 .readable_reg = tc_readable_reg,
1246 .volatile_table = &tc_volatile_table,
1247 .writeable_reg = tc_writeable_reg,
1248 .reg_format_endian = REGMAP_ENDIAN_BIG,
1249 .val_format_endian = REGMAP_ENDIAN_LITTLE,
1250};
1251
1252static int tc_probe(struct i2c_client *client, const struct i2c_device_id *id)
1253{
1254 struct device *dev = &client->dev;
1255 struct tc_data *tc;
1256 int ret;
1257
1258 tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL);
1259 if (!tc)
1260 return -ENOMEM;
1261
1262 tc->dev = dev;
1263
1264 /* port@2 is the output port */
1265 ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &tc->panel, NULL);
1266 if (ret && ret != -ENODEV)
1267 return ret;
1268
1269 /* Shut down GPIO is optional */
1270 tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH);
1271 if (IS_ERR(tc->sd_gpio))
1272 return PTR_ERR(tc->sd_gpio);
1273
1274 if (tc->sd_gpio) {
1275 gpiod_set_value_cansleep(tc->sd_gpio, 0);
1276 usleep_range(5000, 10000);
1277 }
1278
1279 /* Reset GPIO is optional */
1280 tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
1281 if (IS_ERR(tc->reset_gpio))
1282 return PTR_ERR(tc->reset_gpio);
1283
1284 if (tc->reset_gpio) {
1285 gpiod_set_value_cansleep(tc->reset_gpio, 1);
1286 usleep_range(5000, 10000);
1287 }
1288
1289 tc->refclk = devm_clk_get(dev, "ref");
1290 if (IS_ERR(tc->refclk)) {
1291 ret = PTR_ERR(tc->refclk);
1292 dev_err(dev, "Failed to get refclk: %d\n", ret);
1293 return ret;
1294 }
1295
1296 tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config);
1297 if (IS_ERR(tc->regmap)) {
1298 ret = PTR_ERR(tc->regmap);
1299 dev_err(dev, "Failed to initialize regmap: %d\n", ret);
1300 return ret;
1301 }
1302
1303 ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev);
1304 if (ret) {
1305 dev_err(tc->dev, "can not read device ID: %d\n", ret);
1306 return ret;
1307 }
1308
1309 if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) {
1310 dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev);
1311 return -EINVAL;
1312 }
1313
1314 tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */
1315
1316 ret = tc_aux_link_setup(tc);
1317 if (ret)
1318 return ret;
1319
1320 /* Register DP AUX channel */
1321 tc->aux.name = "TC358767 AUX i2c adapter";
1322 tc->aux.dev = tc->dev;
1323 tc->aux.transfer = tc_aux_transfer;
1324 ret = drm_dp_aux_register(&tc->aux);
1325 if (ret)
1326 return ret;
1327
1328 ret = tc_get_display_props(tc);
1329 if (ret)
1330 goto err_unregister_aux;
1331
1332 tc_connector_set_polling(tc, &tc->connector);
1333
1334 tc->bridge.funcs = &tc_bridge_funcs;
1335 tc->bridge.of_node = dev->of_node;
1336 drm_bridge_add(&tc->bridge);
1337
1338 i2c_set_clientdata(client, tc);
1339
1340 return 0;
1341err_unregister_aux:
1342 drm_dp_aux_unregister(&tc->aux);
1343 return ret;
1344}
1345
1346static int tc_remove(struct i2c_client *client)
1347{
1348 struct tc_data *tc = i2c_get_clientdata(client);
1349
1350 drm_bridge_remove(&tc->bridge);
1351 drm_dp_aux_unregister(&tc->aux);
1352
1353 tc_pxl_pll_dis(tc);
1354
1355 return 0;
1356}
1357
1358static const struct i2c_device_id tc358767_i2c_ids[] = {
1359 { "tc358767", 0 },
1360 { }
1361};
1362MODULE_DEVICE_TABLE(i2c, tc358767_i2c_ids);
1363
1364static const struct of_device_id tc358767_of_ids[] = {
1365 { .compatible = "toshiba,tc358767", },
1366 { }
1367};
1368MODULE_DEVICE_TABLE(of, tc358767_of_ids);
1369
1370static struct i2c_driver tc358767_driver = {
1371 .driver = {
1372 .name = "tc358767",
1373 .of_match_table = tc358767_of_ids,
1374 },
1375 .id_table = tc358767_i2c_ids,
1376 .probe = tc_probe,
1377 .remove = tc_remove,
1378};
1379module_i2c_driver(tc358767_driver);
1380
1381MODULE_AUTHOR("Andrey Gusakov <andrey.gusakov@cogentembedded.com>");
1382MODULE_DESCRIPTION("tc358767 eDP encoder driver");
1383MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * TC358767/TC358867/TC9595 DSI/DPI-to-DPI/(e)DP bridge driver
4 *
5 * The TC358767/TC358867/TC9595 can operate in multiple modes.
6 * All modes are supported -- DPI->(e)DP / DSI->DPI / DSI->(e)DP .
7 *
8 * Copyright (C) 2016 CogentEmbedded Inc
9 * Author: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
10 *
11 * Copyright (C) 2016 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
12 *
13 * Copyright (C) 2016 Zodiac Inflight Innovations
14 *
15 * Initially based on: drivers/gpu/drm/i2c/tda998x_drv.c
16 *
17 * Copyright (C) 2012 Texas Instruments
18 * Author: Rob Clark <robdclark@gmail.com>
19 */
20
21#include <linux/bitfield.h>
22#include <linux/clk.h>
23#include <linux/device.h>
24#include <linux/gpio/consumer.h>
25#include <linux/i2c.h>
26#include <linux/kernel.h>
27#include <linux/media-bus-format.h>
28#include <linux/module.h>
29#include <linux/regmap.h>
30#include <linux/slab.h>
31
32#include <drm/display/drm_dp_helper.h>
33#include <drm/drm_atomic_helper.h>
34#include <drm/drm_bridge.h>
35#include <drm/drm_edid.h>
36#include <drm/drm_mipi_dsi.h>
37#include <drm/drm_of.h>
38#include <drm/drm_panel.h>
39#include <drm/drm_print.h>
40#include <drm/drm_probe_helper.h>
41
42/* Registers */
43
44/* PPI layer registers */
45#define PPI_STARTPPI 0x0104 /* START control bit */
46#define PPI_LPTXTIMECNT 0x0114 /* LPTX timing signal */
47#define LPX_PERIOD 3
48#define PPI_LANEENABLE 0x0134
49#define PPI_TX_RX_TA 0x013c
50#define TTA_GET 0x40000
51#define TTA_SURE 6
52#define PPI_D0S_ATMR 0x0144
53#define PPI_D1S_ATMR 0x0148
54#define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */
55#define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */
56#define PPI_D2S_CLRSIPOCOUNT 0x016c /* Assertion timer for Lane 2 */
57#define PPI_D3S_CLRSIPOCOUNT 0x0170 /* Assertion timer for Lane 3 */
58#define PPI_START_FUNCTION BIT(0)
59
60/* DSI layer registers */
61#define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
62#define DSI_LANEENABLE 0x0210 /* Enables each lane */
63#define DSI_RX_START BIT(0)
64
65/* Lane enable PPI and DSI register bits */
66#define LANEENABLE_CLEN BIT(0)
67#define LANEENABLE_L0EN BIT(1)
68#define LANEENABLE_L1EN BIT(2)
69#define LANEENABLE_L2EN BIT(1)
70#define LANEENABLE_L3EN BIT(2)
71
72/* Display Parallel Input Interface */
73#define DPIPXLFMT 0x0440
74#define VS_POL_ACTIVE_LOW (1 << 10)
75#define HS_POL_ACTIVE_LOW (1 << 9)
76#define DE_POL_ACTIVE_HIGH (0 << 8)
77#define SUB_CFG_TYPE_CONFIG1 (0 << 2) /* LSB aligned */
78#define SUB_CFG_TYPE_CONFIG2 (1 << 2) /* Loosely Packed */
79#define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */
80#define DPI_BPP_RGB888 (0 << 0)
81#define DPI_BPP_RGB666 (1 << 0)
82#define DPI_BPP_RGB565 (2 << 0)
83
84/* Display Parallel Output Interface */
85#define POCTRL 0x0448
86#define POCTRL_S2P BIT(7)
87#define POCTRL_PCLK_POL BIT(3)
88#define POCTRL_VS_POL BIT(2)
89#define POCTRL_HS_POL BIT(1)
90#define POCTRL_DE_POL BIT(0)
91
92/* Video Path */
93#define VPCTRL0 0x0450
94#define VSDELAY GENMASK(31, 20)
95#define OPXLFMT_RGB666 (0 << 8)
96#define OPXLFMT_RGB888 (1 << 8)
97#define FRMSYNC_DISABLED (0 << 4) /* Video Timing Gen Disabled */
98#define FRMSYNC_ENABLED (1 << 4) /* Video Timing Gen Enabled */
99#define MSF_DISABLED (0 << 0) /* Magic Square FRC disabled */
100#define MSF_ENABLED (1 << 0) /* Magic Square FRC enabled */
101#define HTIM01 0x0454
102#define HPW GENMASK(8, 0)
103#define HBPR GENMASK(24, 16)
104#define HTIM02 0x0458
105#define HDISPR GENMASK(10, 0)
106#define HFPR GENMASK(24, 16)
107#define VTIM01 0x045c
108#define VSPR GENMASK(7, 0)
109#define VBPR GENMASK(23, 16)
110#define VTIM02 0x0460
111#define VFPR GENMASK(23, 16)
112#define VDISPR GENMASK(10, 0)
113#define VFUEN0 0x0464
114#define VFUEN BIT(0) /* Video Frame Timing Upload */
115
116/* System */
117#define TC_IDREG 0x0500
118#define SYSSTAT 0x0508
119#define SYSCTRL 0x0510
120#define DP0_AUDSRC_NO_INPUT (0 << 3)
121#define DP0_AUDSRC_I2S_RX (1 << 3)
122#define DP0_VIDSRC_NO_INPUT (0 << 0)
123#define DP0_VIDSRC_DSI_RX (1 << 0)
124#define DP0_VIDSRC_DPI_RX (2 << 0)
125#define DP0_VIDSRC_COLOR_BAR (3 << 0)
126#define SYSRSTENB 0x050c
127#define ENBI2C (1 << 0)
128#define ENBLCD0 (1 << 2)
129#define ENBBM (1 << 3)
130#define ENBDSIRX (1 << 4)
131#define ENBREG (1 << 5)
132#define ENBHDCP (1 << 8)
133#define GPIOM 0x0540
134#define GPIOC 0x0544
135#define GPIOO 0x0548
136#define GPIOI 0x054c
137#define INTCTL_G 0x0560
138#define INTSTS_G 0x0564
139
140#define INT_SYSERR BIT(16)
141#define INT_GPIO_H(x) (1 << (x == 0 ? 2 : 10))
142#define INT_GPIO_LC(x) (1 << (x == 0 ? 3 : 11))
143
144#define INT_GP0_LCNT 0x0584
145#define INT_GP1_LCNT 0x0588
146
147/* Control */
148#define DP0CTL 0x0600
149#define VID_MN_GEN BIT(6) /* Auto-generate M/N values */
150#define EF_EN BIT(5) /* Enable Enhanced Framing */
151#define VID_EN BIT(1) /* Video transmission enable */
152#define DP_EN BIT(0) /* Enable DPTX function */
153
154/* Clocks */
155#define DP0_VIDMNGEN0 0x0610
156#define DP0_VIDMNGEN1 0x0614
157#define DP0_VMNGENSTATUS 0x0618
158
159/* Main Channel */
160#define DP0_SECSAMPLE 0x0640
161#define DP0_VIDSYNCDELAY 0x0644
162#define VID_SYNC_DLY GENMASK(15, 0)
163#define THRESH_DLY GENMASK(31, 16)
164
165#define DP0_TOTALVAL 0x0648
166#define H_TOTAL GENMASK(15, 0)
167#define V_TOTAL GENMASK(31, 16)
168#define DP0_STARTVAL 0x064c
169#define H_START GENMASK(15, 0)
170#define V_START GENMASK(31, 16)
171#define DP0_ACTIVEVAL 0x0650
172#define H_ACT GENMASK(15, 0)
173#define V_ACT GENMASK(31, 16)
174
175#define DP0_SYNCVAL 0x0654
176#define VS_WIDTH GENMASK(30, 16)
177#define HS_WIDTH GENMASK(14, 0)
178#define SYNCVAL_HS_POL_ACTIVE_LOW (1 << 15)
179#define SYNCVAL_VS_POL_ACTIVE_LOW (1 << 31)
180#define DP0_MISC 0x0658
181#define TU_SIZE_RECOMMENDED (63) /* LSCLK cycles per TU */
182#define MAX_TU_SYMBOL GENMASK(28, 23)
183#define TU_SIZE GENMASK(21, 16)
184#define BPC_6 (0 << 5)
185#define BPC_8 (1 << 5)
186
187/* AUX channel */
188#define DP0_AUXCFG0 0x0660
189#define DP0_AUXCFG0_BSIZE GENMASK(11, 8)
190#define DP0_AUXCFG0_ADDR_ONLY BIT(4)
191#define DP0_AUXCFG1 0x0664
192#define AUX_RX_FILTER_EN BIT(16)
193
194#define DP0_AUXADDR 0x0668
195#define DP0_AUXWDATA(i) (0x066c + (i) * 4)
196#define DP0_AUXRDATA(i) (0x067c + (i) * 4)
197#define DP0_AUXSTATUS 0x068c
198#define AUX_BYTES GENMASK(15, 8)
199#define AUX_STATUS GENMASK(7, 4)
200#define AUX_TIMEOUT BIT(1)
201#define AUX_BUSY BIT(0)
202#define DP0_AUXI2CADR 0x0698
203
204/* Link Training */
205#define DP0_SRCCTRL 0x06a0
206#define DP0_SRCCTRL_SCRMBLDIS BIT(13)
207#define DP0_SRCCTRL_EN810B BIT(12)
208#define DP0_SRCCTRL_NOTP (0 << 8)
209#define DP0_SRCCTRL_TP1 (1 << 8)
210#define DP0_SRCCTRL_TP2 (2 << 8)
211#define DP0_SRCCTRL_LANESKEW BIT(7)
212#define DP0_SRCCTRL_SSCG BIT(3)
213#define DP0_SRCCTRL_LANES_1 (0 << 2)
214#define DP0_SRCCTRL_LANES_2 (1 << 2)
215#define DP0_SRCCTRL_BW27 (1 << 1)
216#define DP0_SRCCTRL_BW162 (0 << 1)
217#define DP0_SRCCTRL_AUTOCORRECT BIT(0)
218#define DP0_LTSTAT 0x06d0
219#define LT_LOOPDONE BIT(13)
220#define LT_STATUS_MASK (0x1f << 8)
221#define LT_CHANNEL1_EQ_BITS (DP_CHANNEL_EQ_BITS << 4)
222#define LT_INTERLANE_ALIGN_DONE BIT(3)
223#define LT_CHANNEL0_EQ_BITS (DP_CHANNEL_EQ_BITS)
224#define DP0_SNKLTCHGREQ 0x06d4
225#define DP0_LTLOOPCTRL 0x06d8
226#define DP0_SNKLTCTRL 0x06e4
227
228#define DP1_SRCCTRL 0x07a0
229
230/* PHY */
231#define DP_PHY_CTRL 0x0800
232#define DP_PHY_RST BIT(28) /* DP PHY Global Soft Reset */
233#define BGREN BIT(25) /* AUX PHY BGR Enable */
234#define PWR_SW_EN BIT(24) /* PHY Power Switch Enable */
235#define PHY_M1_RST BIT(12) /* Reset PHY1 Main Channel */
236#define PHY_RDY BIT(16) /* PHY Main Channels Ready */
237#define PHY_M0_RST BIT(8) /* Reset PHY0 Main Channel */
238#define PHY_2LANE BIT(2) /* PHY Enable 2 lanes */
239#define PHY_A0_EN BIT(1) /* PHY Aux Channel0 Enable */
240#define PHY_M0_EN BIT(0) /* PHY Main Channel0 Enable */
241
242/* PLL */
243#define DP0_PLLCTRL 0x0900
244#define DP1_PLLCTRL 0x0904 /* not defined in DS */
245#define PXL_PLLCTRL 0x0908
246#define PLLUPDATE BIT(2)
247#define PLLBYP BIT(1)
248#define PLLEN BIT(0)
249#define PXL_PLLPARAM 0x0914
250#define IN_SEL_REFCLK (0 << 14)
251#define SYS_PLLPARAM 0x0918
252#define REF_FREQ_38M4 (0 << 8) /* 38.4 MHz */
253#define REF_FREQ_19M2 (1 << 8) /* 19.2 MHz */
254#define REF_FREQ_26M (2 << 8) /* 26 MHz */
255#define REF_FREQ_13M (3 << 8) /* 13 MHz */
256#define SYSCLK_SEL_LSCLK (0 << 4)
257#define LSCLK_DIV_1 (0 << 0)
258#define LSCLK_DIV_2 (1 << 0)
259
260/* Test & Debug */
261#define TSTCTL 0x0a00
262#define COLOR_R GENMASK(31, 24)
263#define COLOR_G GENMASK(23, 16)
264#define COLOR_B GENMASK(15, 8)
265#define ENI2CFILTER BIT(4)
266#define COLOR_BAR_MODE GENMASK(1, 0)
267#define COLOR_BAR_MODE_BARS 2
268#define PLL_DBG 0x0a04
269
270static bool tc_test_pattern;
271module_param_named(test, tc_test_pattern, bool, 0644);
272
273struct tc_edp_link {
274 u8 dpcd[DP_RECEIVER_CAP_SIZE];
275 unsigned int rate;
276 u8 num_lanes;
277 u8 assr;
278 bool scrambler_dis;
279 bool spread;
280};
281
282struct tc_data {
283 struct device *dev;
284 struct regmap *regmap;
285 struct drm_dp_aux aux;
286
287 struct drm_bridge bridge;
288 struct drm_bridge *panel_bridge;
289 struct drm_connector connector;
290
291 struct mipi_dsi_device *dsi;
292
293 /* link settings */
294 struct tc_edp_link link;
295
296 /* current mode */
297 struct drm_display_mode mode;
298
299 u32 rev;
300 u8 assr;
301
302 struct gpio_desc *sd_gpio;
303 struct gpio_desc *reset_gpio;
304 struct clk *refclk;
305
306 /* do we have IRQ */
307 bool have_irq;
308
309 /* Input connector type, DSI and not DPI. */
310 bool input_connector_dsi;
311
312 /* HPD pin number (0 or 1) or -ENODEV */
313 int hpd_pin;
314};
315
316static inline struct tc_data *aux_to_tc(struct drm_dp_aux *a)
317{
318 return container_of(a, struct tc_data, aux);
319}
320
321static inline struct tc_data *bridge_to_tc(struct drm_bridge *b)
322{
323 return container_of(b, struct tc_data, bridge);
324}
325
326static inline struct tc_data *connector_to_tc(struct drm_connector *c)
327{
328 return container_of(c, struct tc_data, connector);
329}
330
331static inline int tc_poll_timeout(struct tc_data *tc, unsigned int addr,
332 unsigned int cond_mask,
333 unsigned int cond_value,
334 unsigned long sleep_us, u64 timeout_us)
335{
336 unsigned int val;
337
338 return regmap_read_poll_timeout(tc->regmap, addr, val,
339 (val & cond_mask) == cond_value,
340 sleep_us, timeout_us);
341}
342
343static int tc_aux_wait_busy(struct tc_data *tc)
344{
345 return tc_poll_timeout(tc, DP0_AUXSTATUS, AUX_BUSY, 0, 100, 100000);
346}
347
348static int tc_aux_write_data(struct tc_data *tc, const void *data,
349 size_t size)
350{
351 u32 auxwdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)] = { 0 };
352 int ret, count = ALIGN(size, sizeof(u32));
353
354 memcpy(auxwdata, data, size);
355
356 ret = regmap_raw_write(tc->regmap, DP0_AUXWDATA(0), auxwdata, count);
357 if (ret)
358 return ret;
359
360 return size;
361}
362
363static int tc_aux_read_data(struct tc_data *tc, void *data, size_t size)
364{
365 u32 auxrdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)];
366 int ret, count = ALIGN(size, sizeof(u32));
367
368 ret = regmap_raw_read(tc->regmap, DP0_AUXRDATA(0), auxrdata, count);
369 if (ret)
370 return ret;
371
372 memcpy(data, auxrdata, size);
373
374 return size;
375}
376
377static u32 tc_auxcfg0(struct drm_dp_aux_msg *msg, size_t size)
378{
379 u32 auxcfg0 = msg->request;
380
381 if (size)
382 auxcfg0 |= FIELD_PREP(DP0_AUXCFG0_BSIZE, size - 1);
383 else
384 auxcfg0 |= DP0_AUXCFG0_ADDR_ONLY;
385
386 return auxcfg0;
387}
388
389static ssize_t tc_aux_transfer(struct drm_dp_aux *aux,
390 struct drm_dp_aux_msg *msg)
391{
392 struct tc_data *tc = aux_to_tc(aux);
393 size_t size = min_t(size_t, DP_AUX_MAX_PAYLOAD_BYTES - 1, msg->size);
394 u8 request = msg->request & ~DP_AUX_I2C_MOT;
395 u32 auxstatus;
396 int ret;
397
398 ret = tc_aux_wait_busy(tc);
399 if (ret)
400 return ret;
401
402 switch (request) {
403 case DP_AUX_NATIVE_READ:
404 case DP_AUX_I2C_READ:
405 break;
406 case DP_AUX_NATIVE_WRITE:
407 case DP_AUX_I2C_WRITE:
408 if (size) {
409 ret = tc_aux_write_data(tc, msg->buffer, size);
410 if (ret < 0)
411 return ret;
412 }
413 break;
414 default:
415 return -EINVAL;
416 }
417
418 /* Store address */
419 ret = regmap_write(tc->regmap, DP0_AUXADDR, msg->address);
420 if (ret)
421 return ret;
422 /* Start transfer */
423 ret = regmap_write(tc->regmap, DP0_AUXCFG0, tc_auxcfg0(msg, size));
424 if (ret)
425 return ret;
426
427 ret = tc_aux_wait_busy(tc);
428 if (ret)
429 return ret;
430
431 ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &auxstatus);
432 if (ret)
433 return ret;
434
435 if (auxstatus & AUX_TIMEOUT)
436 return -ETIMEDOUT;
437 /*
438 * For some reason address-only DP_AUX_I2C_WRITE (MOT), still
439 * reports 1 byte transferred in its status. To deal we that
440 * we ignore aux_bytes field if we know that this was an
441 * address-only transfer
442 */
443 if (size)
444 size = FIELD_GET(AUX_BYTES, auxstatus);
445 msg->reply = FIELD_GET(AUX_STATUS, auxstatus);
446
447 switch (request) {
448 case DP_AUX_NATIVE_READ:
449 case DP_AUX_I2C_READ:
450 if (size)
451 return tc_aux_read_data(tc, msg->buffer, size);
452 break;
453 }
454
455 return size;
456}
457
458static const char * const training_pattern1_errors[] = {
459 "No errors",
460 "Aux write error",
461 "Aux read error",
462 "Max voltage reached error",
463 "Loop counter expired error",
464 "res", "res", "res"
465};
466
467static const char * const training_pattern2_errors[] = {
468 "No errors",
469 "Aux write error",
470 "Aux read error",
471 "Clock recovery failed error",
472 "Loop counter expired error",
473 "res", "res", "res"
474};
475
476static u32 tc_srcctrl(struct tc_data *tc)
477{
478 /*
479 * No training pattern, skew lane 1 data by two LSCLK cycles with
480 * respect to lane 0 data, AutoCorrect Mode = 0
481 */
482 u32 reg = DP0_SRCCTRL_NOTP | DP0_SRCCTRL_LANESKEW | DP0_SRCCTRL_EN810B;
483
484 if (tc->link.scrambler_dis)
485 reg |= DP0_SRCCTRL_SCRMBLDIS; /* Scrambler Disabled */
486 if (tc->link.spread)
487 reg |= DP0_SRCCTRL_SSCG; /* Spread Spectrum Enable */
488 if (tc->link.num_lanes == 2)
489 reg |= DP0_SRCCTRL_LANES_2; /* Two Main Channel Lanes */
490 if (tc->link.rate != 162000)
491 reg |= DP0_SRCCTRL_BW27; /* 2.7 Gbps link */
492 return reg;
493}
494
495static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl)
496{
497 int ret;
498
499 ret = regmap_write(tc->regmap, pllctrl, PLLUPDATE | PLLEN);
500 if (ret)
501 return ret;
502
503 /* Wait for PLL to lock: up to 7.5 ms, depending on refclk */
504 usleep_range(15000, 20000);
505
506 return 0;
507}
508
509static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
510{
511 int ret;
512 int i_pre, best_pre = 1;
513 int i_post, best_post = 1;
514 int div, best_div = 1;
515 int mul, best_mul = 1;
516 int delta, best_delta;
517 int ext_div[] = {1, 2, 3, 5, 7};
518 int clk_min, clk_max;
519 int best_pixelclock = 0;
520 int vco_hi = 0;
521 u32 pxl_pllparam;
522
523 /*
524 * refclk * mul / (ext_pre_div * pre_div) should be in range:
525 * - DPI ..... 0 to 100 MHz
526 * - (e)DP ... 150 to 650 MHz
527 */
528 if (tc->bridge.type == DRM_MODE_CONNECTOR_DPI) {
529 clk_min = 0;
530 clk_max = 100000000;
531 } else {
532 clk_min = 150000000;
533 clk_max = 650000000;
534 }
535
536 dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock,
537 refclk);
538 best_delta = pixelclock;
539 /* Loop over all possible ext_divs, skipping invalid configurations */
540 for (i_pre = 0; i_pre < ARRAY_SIZE(ext_div); i_pre++) {
541 /*
542 * refclk / ext_pre_div should be in the 1 to 200 MHz range.
543 * We don't allow any refclk > 200 MHz, only check lower bounds.
544 */
545 if (refclk / ext_div[i_pre] < 1000000)
546 continue;
547 for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) {
548 for (div = 1; div <= 16; div++) {
549 u32 clk;
550 u64 tmp;
551
552 tmp = pixelclock * ext_div[i_pre] *
553 ext_div[i_post] * div;
554 do_div(tmp, refclk);
555 mul = tmp;
556
557 /* Check limits */
558 if ((mul < 1) || (mul > 128))
559 continue;
560
561 clk = (refclk / ext_div[i_pre] / div) * mul;
562 if ((clk > clk_max) || (clk < clk_min))
563 continue;
564
565 clk = clk / ext_div[i_post];
566 delta = clk - pixelclock;
567
568 if (abs(delta) < abs(best_delta)) {
569 best_pre = i_pre;
570 best_post = i_post;
571 best_div = div;
572 best_mul = mul;
573 best_delta = delta;
574 best_pixelclock = clk;
575 }
576 }
577 }
578 }
579 if (best_pixelclock == 0) {
580 dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n",
581 pixelclock);
582 return -EINVAL;
583 }
584
585 dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock,
586 best_delta);
587 dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk,
588 ext_div[best_pre], best_div, best_mul, ext_div[best_post]);
589
590 /* if VCO >= 300 MHz */
591 if (refclk / ext_div[best_pre] / best_div * best_mul >= 300000000)
592 vco_hi = 1;
593 /* see DS */
594 if (best_div == 16)
595 best_div = 0;
596 if (best_mul == 128)
597 best_mul = 0;
598
599 /* Power up PLL and switch to bypass */
600 ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP | PLLEN);
601 if (ret)
602 return ret;
603
604 pxl_pllparam = vco_hi << 24; /* For PLL VCO >= 300 MHz = 1 */
605 pxl_pllparam |= ext_div[best_pre] << 20; /* External Pre-divider */
606 pxl_pllparam |= ext_div[best_post] << 16; /* External Post-divider */
607 pxl_pllparam |= IN_SEL_REFCLK; /* Use RefClk as PLL input */
608 pxl_pllparam |= best_div << 8; /* Divider for PLL RefClk */
609 pxl_pllparam |= best_mul; /* Multiplier for PLL */
610
611 ret = regmap_write(tc->regmap, PXL_PLLPARAM, pxl_pllparam);
612 if (ret)
613 return ret;
614
615 /* Force PLL parameter update and disable bypass */
616 return tc_pllupdate(tc, PXL_PLLCTRL);
617}
618
619static int tc_pxl_pll_dis(struct tc_data *tc)
620{
621 /* Enable PLL bypass, power down PLL */
622 return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP);
623}
624
625static int tc_stream_clock_calc(struct tc_data *tc)
626{
627 /*
628 * If the Stream clock and Link Symbol clock are
629 * asynchronous with each other, the value of M changes over
630 * time. This way of generating link clock and stream
631 * clock is called Asynchronous Clock mode. The value M
632 * must change while the value N stays constant. The
633 * value of N in this Asynchronous Clock mode must be set
634 * to 2^15 or 32,768.
635 *
636 * LSCLK = 1/10 of high speed link clock
637 *
638 * f_STRMCLK = M/N * f_LSCLK
639 * M/N = f_STRMCLK / f_LSCLK
640 *
641 */
642 return regmap_write(tc->regmap, DP0_VIDMNGEN1, 32768);
643}
644
645static int tc_set_syspllparam(struct tc_data *tc)
646{
647 unsigned long rate;
648 u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
649
650 rate = clk_get_rate(tc->refclk);
651 switch (rate) {
652 case 38400000:
653 pllparam |= REF_FREQ_38M4;
654 break;
655 case 26000000:
656 pllparam |= REF_FREQ_26M;
657 break;
658 case 19200000:
659 pllparam |= REF_FREQ_19M2;
660 break;
661 case 13000000:
662 pllparam |= REF_FREQ_13M;
663 break;
664 default:
665 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate);
666 return -EINVAL;
667 }
668
669 return regmap_write(tc->regmap, SYS_PLLPARAM, pllparam);
670}
671
672static int tc_aux_link_setup(struct tc_data *tc)
673{
674 int ret;
675 u32 dp0_auxcfg1;
676
677 /* Setup DP-PHY / PLL */
678 ret = tc_set_syspllparam(tc);
679 if (ret)
680 goto err;
681
682 ret = regmap_write(tc->regmap, DP_PHY_CTRL,
683 BGREN | PWR_SW_EN | PHY_A0_EN);
684 if (ret)
685 goto err;
686 /*
687 * Initially PLLs are in bypass. Force PLL parameter update,
688 * disable PLL bypass, enable PLL
689 */
690 ret = tc_pllupdate(tc, DP0_PLLCTRL);
691 if (ret)
692 goto err;
693
694 ret = tc_pllupdate(tc, DP1_PLLCTRL);
695 if (ret)
696 goto err;
697
698 ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 100, 100000);
699 if (ret == -ETIMEDOUT) {
700 dev_err(tc->dev, "Timeout waiting for PHY to become ready");
701 return ret;
702 } else if (ret) {
703 goto err;
704 }
705
706 /* Setup AUX link */
707 dp0_auxcfg1 = AUX_RX_FILTER_EN;
708 dp0_auxcfg1 |= 0x06 << 8; /* Aux Bit Period Calculator Threshold */
709 dp0_auxcfg1 |= 0x3f << 0; /* Aux Response Timeout Timer */
710
711 ret = regmap_write(tc->regmap, DP0_AUXCFG1, dp0_auxcfg1);
712 if (ret)
713 goto err;
714
715 /* Register DP AUX channel */
716 tc->aux.name = "TC358767 AUX i2c adapter";
717 tc->aux.dev = tc->dev;
718 tc->aux.transfer = tc_aux_transfer;
719 drm_dp_aux_init(&tc->aux);
720
721 return 0;
722err:
723 dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret);
724 return ret;
725}
726
727static int tc_get_display_props(struct tc_data *tc)
728{
729 u8 revision, num_lanes;
730 unsigned int rate;
731 int ret;
732 u8 reg;
733
734 /* Read DP Rx Link Capability */
735 ret = drm_dp_dpcd_read(&tc->aux, DP_DPCD_REV, tc->link.dpcd,
736 DP_RECEIVER_CAP_SIZE);
737 if (ret < 0)
738 goto err_dpcd_read;
739
740 revision = tc->link.dpcd[DP_DPCD_REV];
741 rate = drm_dp_max_link_rate(tc->link.dpcd);
742 num_lanes = drm_dp_max_lane_count(tc->link.dpcd);
743
744 if (rate != 162000 && rate != 270000) {
745 dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n");
746 rate = 270000;
747 }
748
749 tc->link.rate = rate;
750
751 if (num_lanes > 2) {
752 dev_dbg(tc->dev, "Falling to 2 lanes\n");
753 num_lanes = 2;
754 }
755
756 tc->link.num_lanes = num_lanes;
757
758 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, ®);
759 if (ret < 0)
760 goto err_dpcd_read;
761 tc->link.spread = reg & DP_MAX_DOWNSPREAD_0_5;
762
763 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, ®);
764 if (ret < 0)
765 goto err_dpcd_read;
766
767 tc->link.scrambler_dis = false;
768 /* read assr */
769 ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, ®);
770 if (ret < 0)
771 goto err_dpcd_read;
772 tc->link.assr = reg & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
773
774 dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n",
775 revision >> 4, revision & 0x0f,
776 (tc->link.rate == 162000) ? "1.62Gbps" : "2.7Gbps",
777 tc->link.num_lanes,
778 drm_dp_enhanced_frame_cap(tc->link.dpcd) ?
779 "enhanced" : "default");
780 dev_dbg(tc->dev, "Downspread: %s, scrambler: %s\n",
781 tc->link.spread ? "0.5%" : "0.0%",
782 tc->link.scrambler_dis ? "disabled" : "enabled");
783 dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n",
784 tc->link.assr, tc->assr);
785
786 return 0;
787
788err_dpcd_read:
789 dev_err(tc->dev, "failed to read DPCD: %d\n", ret);
790 return ret;
791}
792
793static int tc_set_common_video_mode(struct tc_data *tc,
794 const struct drm_display_mode *mode)
795{
796 int left_margin = mode->htotal - mode->hsync_end;
797 int right_margin = mode->hsync_start - mode->hdisplay;
798 int hsync_len = mode->hsync_end - mode->hsync_start;
799 int upper_margin = mode->vtotal - mode->vsync_end;
800 int lower_margin = mode->vsync_start - mode->vdisplay;
801 int vsync_len = mode->vsync_end - mode->vsync_start;
802 int ret;
803
804 dev_dbg(tc->dev, "set mode %dx%d\n",
805 mode->hdisplay, mode->vdisplay);
806 dev_dbg(tc->dev, "H margin %d,%d sync %d\n",
807 left_margin, right_margin, hsync_len);
808 dev_dbg(tc->dev, "V margin %d,%d sync %d\n",
809 upper_margin, lower_margin, vsync_len);
810 dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal);
811
812
813 /*
814 * LCD Ctl Frame Size
815 * datasheet is not clear of vsdelay in case of DPI
816 * assume we do not need any delay when DPI is a source of
817 * sync signals
818 */
819 ret = regmap_write(tc->regmap, VPCTRL0,
820 FIELD_PREP(VSDELAY, right_margin + 10) |
821 OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED);
822 if (ret)
823 return ret;
824
825 ret = regmap_write(tc->regmap, HTIM01,
826 FIELD_PREP(HBPR, ALIGN(left_margin, 2)) |
827 FIELD_PREP(HPW, ALIGN(hsync_len, 2)));
828 if (ret)
829 return ret;
830
831 ret = regmap_write(tc->regmap, HTIM02,
832 FIELD_PREP(HDISPR, ALIGN(mode->hdisplay, 2)) |
833 FIELD_PREP(HFPR, ALIGN(right_margin, 2)));
834 if (ret)
835 return ret;
836
837 ret = regmap_write(tc->regmap, VTIM01,
838 FIELD_PREP(VBPR, upper_margin) |
839 FIELD_PREP(VSPR, vsync_len));
840 if (ret)
841 return ret;
842
843 ret = regmap_write(tc->regmap, VTIM02,
844 FIELD_PREP(VFPR, lower_margin) |
845 FIELD_PREP(VDISPR, mode->vdisplay));
846 if (ret)
847 return ret;
848
849 ret = regmap_write(tc->regmap, VFUEN0, VFUEN); /* update settings */
850 if (ret)
851 return ret;
852
853 /* Test pattern settings */
854 ret = regmap_write(tc->regmap, TSTCTL,
855 FIELD_PREP(COLOR_R, 120) |
856 FIELD_PREP(COLOR_G, 20) |
857 FIELD_PREP(COLOR_B, 99) |
858 ENI2CFILTER |
859 FIELD_PREP(COLOR_BAR_MODE, COLOR_BAR_MODE_BARS));
860
861 return ret;
862}
863
864static int tc_set_dpi_video_mode(struct tc_data *tc,
865 const struct drm_display_mode *mode)
866{
867 u32 value = POCTRL_S2P;
868
869 if (tc->mode.flags & DRM_MODE_FLAG_NHSYNC)
870 value |= POCTRL_HS_POL;
871
872 if (tc->mode.flags & DRM_MODE_FLAG_NVSYNC)
873 value |= POCTRL_VS_POL;
874
875 return regmap_write(tc->regmap, POCTRL, value);
876}
877
878static int tc_set_edp_video_mode(struct tc_data *tc,
879 const struct drm_display_mode *mode)
880{
881 int ret;
882 int vid_sync_dly;
883 int max_tu_symbol;
884
885 int left_margin = mode->htotal - mode->hsync_end;
886 int hsync_len = mode->hsync_end - mode->hsync_start;
887 int upper_margin = mode->vtotal - mode->vsync_end;
888 int vsync_len = mode->vsync_end - mode->vsync_start;
889 u32 dp0_syncval;
890 u32 bits_per_pixel = 24;
891 u32 in_bw, out_bw;
892 u32 dpipxlfmt;
893
894 /*
895 * Recommended maximum number of symbols transferred in a transfer unit:
896 * DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size,
897 * (output active video bandwidth in bytes))
898 * Must be less than tu_size.
899 */
900
901 in_bw = mode->clock * bits_per_pixel / 8;
902 out_bw = tc->link.num_lanes * tc->link.rate;
903 max_tu_symbol = DIV_ROUND_UP(in_bw * TU_SIZE_RECOMMENDED, out_bw);
904
905 /* DP Main Stream Attributes */
906 vid_sync_dly = hsync_len + left_margin + mode->hdisplay;
907 ret = regmap_write(tc->regmap, DP0_VIDSYNCDELAY,
908 FIELD_PREP(THRESH_DLY, max_tu_symbol) |
909 FIELD_PREP(VID_SYNC_DLY, vid_sync_dly));
910
911 ret = regmap_write(tc->regmap, DP0_TOTALVAL,
912 FIELD_PREP(H_TOTAL, mode->htotal) |
913 FIELD_PREP(V_TOTAL, mode->vtotal));
914 if (ret)
915 return ret;
916
917 ret = regmap_write(tc->regmap, DP0_STARTVAL,
918 FIELD_PREP(H_START, left_margin + hsync_len) |
919 FIELD_PREP(V_START, upper_margin + vsync_len));
920 if (ret)
921 return ret;
922
923 ret = regmap_write(tc->regmap, DP0_ACTIVEVAL,
924 FIELD_PREP(V_ACT, mode->vdisplay) |
925 FIELD_PREP(H_ACT, mode->hdisplay));
926 if (ret)
927 return ret;
928
929 dp0_syncval = FIELD_PREP(VS_WIDTH, vsync_len) |
930 FIELD_PREP(HS_WIDTH, hsync_len);
931
932 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
933 dp0_syncval |= SYNCVAL_VS_POL_ACTIVE_LOW;
934
935 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
936 dp0_syncval |= SYNCVAL_HS_POL_ACTIVE_LOW;
937
938 ret = regmap_write(tc->regmap, DP0_SYNCVAL, dp0_syncval);
939 if (ret)
940 return ret;
941
942 dpipxlfmt = DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 | DPI_BPP_RGB888;
943
944 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
945 dpipxlfmt |= VS_POL_ACTIVE_LOW;
946
947 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
948 dpipxlfmt |= HS_POL_ACTIVE_LOW;
949
950 ret = regmap_write(tc->regmap, DPIPXLFMT, dpipxlfmt);
951 if (ret)
952 return ret;
953
954 ret = regmap_write(tc->regmap, DP0_MISC,
955 FIELD_PREP(MAX_TU_SYMBOL, max_tu_symbol) |
956 FIELD_PREP(TU_SIZE, TU_SIZE_RECOMMENDED) |
957 BPC_8);
958 return ret;
959}
960
961static int tc_wait_link_training(struct tc_data *tc)
962{
963 u32 value;
964 int ret;
965
966 ret = tc_poll_timeout(tc, DP0_LTSTAT, LT_LOOPDONE,
967 LT_LOOPDONE, 500, 100000);
968 if (ret) {
969 dev_err(tc->dev, "Link training timeout waiting for LT_LOOPDONE!\n");
970 return ret;
971 }
972
973 ret = regmap_read(tc->regmap, DP0_LTSTAT, &value);
974 if (ret)
975 return ret;
976
977 return (value >> 8) & 0x7;
978}
979
980static int tc_main_link_enable(struct tc_data *tc)
981{
982 struct drm_dp_aux *aux = &tc->aux;
983 struct device *dev = tc->dev;
984 u32 dp_phy_ctrl;
985 u32 value;
986 int ret;
987 u8 tmp[DP_LINK_STATUS_SIZE];
988
989 dev_dbg(tc->dev, "link enable\n");
990
991 ret = regmap_read(tc->regmap, DP0CTL, &value);
992 if (ret)
993 return ret;
994
995 if (WARN_ON(value & DP_EN)) {
996 ret = regmap_write(tc->regmap, DP0CTL, 0);
997 if (ret)
998 return ret;
999 }
1000
1001 ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc));
1002 if (ret)
1003 return ret;
1004 /* SSCG and BW27 on DP1 must be set to the same as on DP0 */
1005 ret = regmap_write(tc->regmap, DP1_SRCCTRL,
1006 (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) |
1007 ((tc->link.rate != 162000) ? DP0_SRCCTRL_BW27 : 0));
1008 if (ret)
1009 return ret;
1010
1011 ret = tc_set_syspllparam(tc);
1012 if (ret)
1013 return ret;
1014
1015 /* Setup Main Link */
1016 dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN;
1017 if (tc->link.num_lanes == 2)
1018 dp_phy_ctrl |= PHY_2LANE;
1019
1020 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
1021 if (ret)
1022 return ret;
1023
1024 /* PLL setup */
1025 ret = tc_pllupdate(tc, DP0_PLLCTRL);
1026 if (ret)
1027 return ret;
1028
1029 ret = tc_pllupdate(tc, DP1_PLLCTRL);
1030 if (ret)
1031 return ret;
1032
1033 /* Reset/Enable Main Links */
1034 dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST;
1035 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
1036 usleep_range(100, 200);
1037 dp_phy_ctrl &= ~(DP_PHY_RST | PHY_M1_RST | PHY_M0_RST);
1038 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
1039
1040 ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 500, 100000);
1041 if (ret) {
1042 dev_err(dev, "timeout waiting for phy become ready");
1043 return ret;
1044 }
1045
1046 /* Set misc: 8 bits per color */
1047 ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8);
1048 if (ret)
1049 return ret;
1050
1051 /*
1052 * ASSR mode
1053 * on TC358767 side ASSR configured through strap pin
1054 * seems there is no way to change this setting from SW
1055 *
1056 * check is tc configured for same mode
1057 */
1058 if (tc->assr != tc->link.assr) {
1059 dev_dbg(dev, "Trying to set display to ASSR: %d\n",
1060 tc->assr);
1061 /* try to set ASSR on display side */
1062 tmp[0] = tc->assr;
1063 ret = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, tmp[0]);
1064 if (ret < 0)
1065 goto err_dpcd_read;
1066 /* read back */
1067 ret = drm_dp_dpcd_readb(aux, DP_EDP_CONFIGURATION_SET, tmp);
1068 if (ret < 0)
1069 goto err_dpcd_read;
1070
1071 if (tmp[0] != tc->assr) {
1072 dev_dbg(dev, "Failed to switch display ASSR to %d, falling back to unscrambled mode\n",
1073 tc->assr);
1074 /* trying with disabled scrambler */
1075 tc->link.scrambler_dis = true;
1076 }
1077 }
1078
1079 /* Setup Link & DPRx Config for Training */
1080 tmp[0] = drm_dp_link_rate_to_bw_code(tc->link.rate);
1081 tmp[1] = tc->link.num_lanes;
1082
1083 if (drm_dp_enhanced_frame_cap(tc->link.dpcd))
1084 tmp[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
1085
1086 ret = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, tmp, 2);
1087 if (ret < 0)
1088 goto err_dpcd_write;
1089
1090 /* DOWNSPREAD_CTRL */
1091 tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00;
1092 /* MAIN_LINK_CHANNEL_CODING_SET */
1093 tmp[1] = DP_SET_ANSI_8B10B;
1094 ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, tmp, 2);
1095 if (ret < 0)
1096 goto err_dpcd_write;
1097
1098 /* Reset voltage-swing & pre-emphasis */
1099 tmp[0] = tmp[1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 |
1100 DP_TRAIN_PRE_EMPH_LEVEL_0;
1101 ret = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, tmp, 2);
1102 if (ret < 0)
1103 goto err_dpcd_write;
1104
1105 /* Clock-Recovery */
1106
1107 /* Set DPCD 0x102 for Training Pattern 1 */
1108 ret = regmap_write(tc->regmap, DP0_SNKLTCTRL,
1109 DP_LINK_SCRAMBLING_DISABLE |
1110 DP_TRAINING_PATTERN_1);
1111 if (ret)
1112 return ret;
1113
1114 ret = regmap_write(tc->regmap, DP0_LTLOOPCTRL,
1115 (15 << 28) | /* Defer Iteration Count */
1116 (15 << 24) | /* Loop Iteration Count */
1117 (0xd << 0)); /* Loop Timer Delay */
1118 if (ret)
1119 return ret;
1120
1121 ret = regmap_write(tc->regmap, DP0_SRCCTRL,
1122 tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
1123 DP0_SRCCTRL_AUTOCORRECT |
1124 DP0_SRCCTRL_TP1);
1125 if (ret)
1126 return ret;
1127
1128 /* Enable DP0 to start Link Training */
1129 ret = regmap_write(tc->regmap, DP0CTL,
1130 (drm_dp_enhanced_frame_cap(tc->link.dpcd) ?
1131 EF_EN : 0) | DP_EN);
1132 if (ret)
1133 return ret;
1134
1135 /* wait */
1136
1137 ret = tc_wait_link_training(tc);
1138 if (ret < 0)
1139 return ret;
1140
1141 if (ret) {
1142 dev_err(tc->dev, "Link training phase 1 failed: %s\n",
1143 training_pattern1_errors[ret]);
1144 return -ENODEV;
1145 }
1146
1147 /* Channel Equalization */
1148
1149 /* Set DPCD 0x102 for Training Pattern 2 */
1150 ret = regmap_write(tc->regmap, DP0_SNKLTCTRL,
1151 DP_LINK_SCRAMBLING_DISABLE |
1152 DP_TRAINING_PATTERN_2);
1153 if (ret)
1154 return ret;
1155
1156 ret = regmap_write(tc->regmap, DP0_SRCCTRL,
1157 tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
1158 DP0_SRCCTRL_AUTOCORRECT |
1159 DP0_SRCCTRL_TP2);
1160 if (ret)
1161 return ret;
1162
1163 /* wait */
1164 ret = tc_wait_link_training(tc);
1165 if (ret < 0)
1166 return ret;
1167
1168 if (ret) {
1169 dev_err(tc->dev, "Link training phase 2 failed: %s\n",
1170 training_pattern2_errors[ret]);
1171 return -ENODEV;
1172 }
1173
1174 /*
1175 * Toshiba's documentation suggests to first clear DPCD 0x102, then
1176 * clear the training pattern bit in DP0_SRCCTRL. Testing shows
1177 * that the link sometimes drops if those steps are done in that order,
1178 * but if the steps are done in reverse order, the link stays up.
1179 *
1180 * So we do the steps differently than documented here.
1181 */
1182
1183 /* Clear Training Pattern, set AutoCorrect Mode = 1 */
1184 ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc) |
1185 DP0_SRCCTRL_AUTOCORRECT);
1186 if (ret)
1187 return ret;
1188
1189 /* Clear DPCD 0x102 */
1190 /* Note: Can Not use DP0_SNKLTCTRL (0x06E4) short cut */
1191 tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00;
1192 ret = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, tmp[0]);
1193 if (ret < 0)
1194 goto err_dpcd_write;
1195
1196 /* Check link status */
1197 ret = drm_dp_dpcd_read_link_status(aux, tmp);
1198 if (ret < 0)
1199 goto err_dpcd_read;
1200
1201 ret = 0;
1202
1203 value = tmp[0] & DP_CHANNEL_EQ_BITS;
1204
1205 if (value != DP_CHANNEL_EQ_BITS) {
1206 dev_err(tc->dev, "Lane 0 failed: %x\n", value);
1207 ret = -ENODEV;
1208 }
1209
1210 if (tc->link.num_lanes == 2) {
1211 value = (tmp[0] >> 4) & DP_CHANNEL_EQ_BITS;
1212
1213 if (value != DP_CHANNEL_EQ_BITS) {
1214 dev_err(tc->dev, "Lane 1 failed: %x\n", value);
1215 ret = -ENODEV;
1216 }
1217
1218 if (!(tmp[2] & DP_INTERLANE_ALIGN_DONE)) {
1219 dev_err(tc->dev, "Interlane align failed\n");
1220 ret = -ENODEV;
1221 }
1222 }
1223
1224 if (ret) {
1225 dev_err(dev, "0x0202 LANE0_1_STATUS: 0x%02x\n", tmp[0]);
1226 dev_err(dev, "0x0203 LANE2_3_STATUS 0x%02x\n", tmp[1]);
1227 dev_err(dev, "0x0204 LANE_ALIGN_STATUS_UPDATED: 0x%02x\n", tmp[2]);
1228 dev_err(dev, "0x0205 SINK_STATUS: 0x%02x\n", tmp[3]);
1229 dev_err(dev, "0x0206 ADJUST_REQUEST_LANE0_1: 0x%02x\n", tmp[4]);
1230 dev_err(dev, "0x0207 ADJUST_REQUEST_LANE2_3: 0x%02x\n", tmp[5]);
1231 return ret;
1232 }
1233
1234 return 0;
1235err_dpcd_read:
1236 dev_err(tc->dev, "Failed to read DPCD: %d\n", ret);
1237 return ret;
1238err_dpcd_write:
1239 dev_err(tc->dev, "Failed to write DPCD: %d\n", ret);
1240 return ret;
1241}
1242
1243static int tc_main_link_disable(struct tc_data *tc)
1244{
1245 int ret;
1246
1247 dev_dbg(tc->dev, "link disable\n");
1248
1249 ret = regmap_write(tc->regmap, DP0_SRCCTRL, 0);
1250 if (ret)
1251 return ret;
1252
1253 ret = regmap_write(tc->regmap, DP0CTL, 0);
1254 if (ret)
1255 return ret;
1256
1257 return regmap_update_bits(tc->regmap, DP_PHY_CTRL,
1258 PHY_M0_RST | PHY_M1_RST | PHY_M0_EN,
1259 PHY_M0_RST | PHY_M1_RST);
1260}
1261
1262static int tc_dsi_rx_enable(struct tc_data *tc)
1263{
1264 u32 value;
1265 int ret;
1266
1267 regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 25);
1268 regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 25);
1269 regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 25);
1270 regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 25);
1271 regmap_write(tc->regmap, PPI_D0S_ATMR, 0);
1272 regmap_write(tc->regmap, PPI_D1S_ATMR, 0);
1273 regmap_write(tc->regmap, PPI_TX_RX_TA, TTA_GET | TTA_SURE);
1274 regmap_write(tc->regmap, PPI_LPTXTIMECNT, LPX_PERIOD);
1275
1276 value = ((LANEENABLE_L0EN << tc->dsi->lanes) - LANEENABLE_L0EN) |
1277 LANEENABLE_CLEN;
1278 regmap_write(tc->regmap, PPI_LANEENABLE, value);
1279 regmap_write(tc->regmap, DSI_LANEENABLE, value);
1280
1281 /* Set input interface */
1282 value = DP0_AUDSRC_NO_INPUT;
1283 if (tc_test_pattern)
1284 value |= DP0_VIDSRC_COLOR_BAR;
1285 else
1286 value |= DP0_VIDSRC_DSI_RX;
1287 ret = regmap_write(tc->regmap, SYSCTRL, value);
1288 if (ret)
1289 return ret;
1290
1291 usleep_range(120, 150);
1292
1293 regmap_write(tc->regmap, PPI_STARTPPI, PPI_START_FUNCTION);
1294 regmap_write(tc->regmap, DSI_STARTDSI, DSI_RX_START);
1295
1296 return 0;
1297}
1298
1299static int tc_dpi_rx_enable(struct tc_data *tc)
1300{
1301 u32 value;
1302
1303 /* Set input interface */
1304 value = DP0_AUDSRC_NO_INPUT;
1305 if (tc_test_pattern)
1306 value |= DP0_VIDSRC_COLOR_BAR;
1307 else
1308 value |= DP0_VIDSRC_DPI_RX;
1309 return regmap_write(tc->regmap, SYSCTRL, value);
1310}
1311
1312static int tc_dpi_stream_enable(struct tc_data *tc)
1313{
1314 int ret;
1315
1316 dev_dbg(tc->dev, "enable video stream\n");
1317
1318 /* Setup PLL */
1319 ret = tc_set_syspllparam(tc);
1320 if (ret)
1321 return ret;
1322
1323 /*
1324 * Initially PLLs are in bypass. Force PLL parameter update,
1325 * disable PLL bypass, enable PLL
1326 */
1327 ret = tc_pllupdate(tc, DP0_PLLCTRL);
1328 if (ret)
1329 return ret;
1330
1331 ret = tc_pllupdate(tc, DP1_PLLCTRL);
1332 if (ret)
1333 return ret;
1334
1335 /* Pixel PLL must always be enabled for DPI mode */
1336 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk),
1337 1000 * tc->mode.clock);
1338 if (ret)
1339 return ret;
1340
1341 ret = tc_set_common_video_mode(tc, &tc->mode);
1342 if (ret)
1343 return ret;
1344
1345 ret = tc_set_dpi_video_mode(tc, &tc->mode);
1346 if (ret)
1347 return ret;
1348
1349 return tc_dsi_rx_enable(tc);
1350}
1351
1352static int tc_dpi_stream_disable(struct tc_data *tc)
1353{
1354 dev_dbg(tc->dev, "disable video stream\n");
1355
1356 tc_pxl_pll_dis(tc);
1357
1358 return 0;
1359}
1360
1361static int tc_edp_stream_enable(struct tc_data *tc)
1362{
1363 int ret;
1364 u32 value;
1365
1366 dev_dbg(tc->dev, "enable video stream\n");
1367
1368 /*
1369 * Pixel PLL must be enabled for DSI input mode and test pattern.
1370 *
1371 * Per TC9595XBG datasheet Revision 0.1 2018-12-27 Figure 4.18
1372 * "Clock Mode Selection and Clock Sources", either Pixel PLL
1373 * or DPI_PCLK supplies StrmClk. DPI_PCLK is only available in
1374 * case valid Pixel Clock are supplied to the chip DPI input.
1375 * In case built-in test pattern is desired OR DSI input mode
1376 * is used, DPI_PCLK is not available and thus Pixel PLL must
1377 * be used instead.
1378 */
1379 if (tc->input_connector_dsi || tc_test_pattern) {
1380 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk),
1381 1000 * tc->mode.clock);
1382 if (ret)
1383 return ret;
1384 }
1385
1386 ret = tc_set_common_video_mode(tc, &tc->mode);
1387 if (ret)
1388 return ret;
1389
1390 ret = tc_set_edp_video_mode(tc, &tc->mode);
1391 if (ret)
1392 return ret;
1393
1394 /* Set M/N */
1395 ret = tc_stream_clock_calc(tc);
1396 if (ret)
1397 return ret;
1398
1399 value = VID_MN_GEN | DP_EN;
1400 if (drm_dp_enhanced_frame_cap(tc->link.dpcd))
1401 value |= EF_EN;
1402 ret = regmap_write(tc->regmap, DP0CTL, value);
1403 if (ret)
1404 return ret;
1405 /*
1406 * VID_EN assertion should be delayed by at least N * LSCLK
1407 * cycles from the time VID_MN_GEN is enabled in order to
1408 * generate stable values for VID_M. LSCLK is 270 MHz or
1409 * 162 MHz, VID_N is set to 32768 in tc_stream_clock_calc(),
1410 * so a delay of at least 203 us should suffice.
1411 */
1412 usleep_range(500, 1000);
1413 value |= VID_EN;
1414 ret = regmap_write(tc->regmap, DP0CTL, value);
1415 if (ret)
1416 return ret;
1417
1418 /* Set input interface */
1419 if (tc->input_connector_dsi)
1420 return tc_dsi_rx_enable(tc);
1421 else
1422 return tc_dpi_rx_enable(tc);
1423}
1424
1425static int tc_edp_stream_disable(struct tc_data *tc)
1426{
1427 int ret;
1428
1429 dev_dbg(tc->dev, "disable video stream\n");
1430
1431 ret = regmap_update_bits(tc->regmap, DP0CTL, VID_EN, 0);
1432 if (ret)
1433 return ret;
1434
1435 tc_pxl_pll_dis(tc);
1436
1437 return 0;
1438}
1439
1440static void
1441tc_dpi_bridge_atomic_enable(struct drm_bridge *bridge,
1442 struct drm_bridge_state *old_bridge_state)
1443
1444{
1445 struct tc_data *tc = bridge_to_tc(bridge);
1446 int ret;
1447
1448 ret = tc_dpi_stream_enable(tc);
1449 if (ret < 0) {
1450 dev_err(tc->dev, "main link stream start error: %d\n", ret);
1451 tc_main_link_disable(tc);
1452 return;
1453 }
1454}
1455
1456static void
1457tc_dpi_bridge_atomic_disable(struct drm_bridge *bridge,
1458 struct drm_bridge_state *old_bridge_state)
1459{
1460 struct tc_data *tc = bridge_to_tc(bridge);
1461 int ret;
1462
1463 ret = tc_dpi_stream_disable(tc);
1464 if (ret < 0)
1465 dev_err(tc->dev, "main link stream stop error: %d\n", ret);
1466}
1467
1468static void
1469tc_edp_bridge_atomic_enable(struct drm_bridge *bridge,
1470 struct drm_bridge_state *old_bridge_state)
1471{
1472 struct tc_data *tc = bridge_to_tc(bridge);
1473 int ret;
1474
1475 ret = tc_get_display_props(tc);
1476 if (ret < 0) {
1477 dev_err(tc->dev, "failed to read display props: %d\n", ret);
1478 return;
1479 }
1480
1481 ret = tc_main_link_enable(tc);
1482 if (ret < 0) {
1483 dev_err(tc->dev, "main link enable error: %d\n", ret);
1484 return;
1485 }
1486
1487 ret = tc_edp_stream_enable(tc);
1488 if (ret < 0) {
1489 dev_err(tc->dev, "main link stream start error: %d\n", ret);
1490 tc_main_link_disable(tc);
1491 return;
1492 }
1493}
1494
1495static void
1496tc_edp_bridge_atomic_disable(struct drm_bridge *bridge,
1497 struct drm_bridge_state *old_bridge_state)
1498{
1499 struct tc_data *tc = bridge_to_tc(bridge);
1500 int ret;
1501
1502 ret = tc_edp_stream_disable(tc);
1503 if (ret < 0)
1504 dev_err(tc->dev, "main link stream stop error: %d\n", ret);
1505
1506 ret = tc_main_link_disable(tc);
1507 if (ret < 0)
1508 dev_err(tc->dev, "main link disable error: %d\n", ret);
1509}
1510
1511static int tc_dpi_atomic_check(struct drm_bridge *bridge,
1512 struct drm_bridge_state *bridge_state,
1513 struct drm_crtc_state *crtc_state,
1514 struct drm_connector_state *conn_state)
1515{
1516 /* DSI->DPI interface clock limitation: upto 100 MHz */
1517 if (crtc_state->adjusted_mode.clock > 100000)
1518 return -EINVAL;
1519
1520 return 0;
1521}
1522
1523static int tc_edp_atomic_check(struct drm_bridge *bridge,
1524 struct drm_bridge_state *bridge_state,
1525 struct drm_crtc_state *crtc_state,
1526 struct drm_connector_state *conn_state)
1527{
1528 /* DPI->(e)DP interface clock limitation: upto 154 MHz */
1529 if (crtc_state->adjusted_mode.clock > 154000)
1530 return -EINVAL;
1531
1532 return 0;
1533}
1534
1535static enum drm_mode_status
1536tc_dpi_mode_valid(struct drm_bridge *bridge,
1537 const struct drm_display_info *info,
1538 const struct drm_display_mode *mode)
1539{
1540 /* DPI interface clock limitation: upto 100 MHz */
1541 if (mode->clock > 100000)
1542 return MODE_CLOCK_HIGH;
1543
1544 return MODE_OK;
1545}
1546
1547static enum drm_mode_status
1548tc_edp_mode_valid(struct drm_bridge *bridge,
1549 const struct drm_display_info *info,
1550 const struct drm_display_mode *mode)
1551{
1552 struct tc_data *tc = bridge_to_tc(bridge);
1553 u32 req, avail;
1554 u32 bits_per_pixel = 24;
1555
1556 /* DPI interface clock limitation: upto 154 MHz */
1557 if (mode->clock > 154000)
1558 return MODE_CLOCK_HIGH;
1559
1560 req = mode->clock * bits_per_pixel / 8;
1561 avail = tc->link.num_lanes * tc->link.rate;
1562
1563 if (req > avail)
1564 return MODE_BAD;
1565
1566 return MODE_OK;
1567}
1568
1569static void tc_bridge_mode_set(struct drm_bridge *bridge,
1570 const struct drm_display_mode *mode,
1571 const struct drm_display_mode *adj)
1572{
1573 struct tc_data *tc = bridge_to_tc(bridge);
1574
1575 drm_mode_copy(&tc->mode, mode);
1576}
1577
1578static struct edid *tc_get_edid(struct drm_bridge *bridge,
1579 struct drm_connector *connector)
1580{
1581 struct tc_data *tc = bridge_to_tc(bridge);
1582
1583 return drm_get_edid(connector, &tc->aux.ddc);
1584}
1585
1586static int tc_connector_get_modes(struct drm_connector *connector)
1587{
1588 struct tc_data *tc = connector_to_tc(connector);
1589 int num_modes;
1590 struct edid *edid;
1591 int ret;
1592
1593 ret = tc_get_display_props(tc);
1594 if (ret < 0) {
1595 dev_err(tc->dev, "failed to read display props: %d\n", ret);
1596 return 0;
1597 }
1598
1599 if (tc->panel_bridge) {
1600 num_modes = drm_bridge_get_modes(tc->panel_bridge, connector);
1601 if (num_modes > 0)
1602 return num_modes;
1603 }
1604
1605 edid = tc_get_edid(&tc->bridge, connector);
1606 num_modes = drm_add_edid_modes(connector, edid);
1607 kfree(edid);
1608
1609 return num_modes;
1610}
1611
1612static const struct drm_connector_helper_funcs tc_connector_helper_funcs = {
1613 .get_modes = tc_connector_get_modes,
1614};
1615
1616static enum drm_connector_status tc_bridge_detect(struct drm_bridge *bridge)
1617{
1618 struct tc_data *tc = bridge_to_tc(bridge);
1619 bool conn;
1620 u32 val;
1621 int ret;
1622
1623 ret = regmap_read(tc->regmap, GPIOI, &val);
1624 if (ret)
1625 return connector_status_unknown;
1626
1627 conn = val & BIT(tc->hpd_pin);
1628
1629 if (conn)
1630 return connector_status_connected;
1631 else
1632 return connector_status_disconnected;
1633}
1634
1635static enum drm_connector_status
1636tc_connector_detect(struct drm_connector *connector, bool force)
1637{
1638 struct tc_data *tc = connector_to_tc(connector);
1639
1640 if (tc->hpd_pin >= 0)
1641 return tc_bridge_detect(&tc->bridge);
1642
1643 if (tc->panel_bridge)
1644 return connector_status_connected;
1645 else
1646 return connector_status_unknown;
1647}
1648
1649static const struct drm_connector_funcs tc_connector_funcs = {
1650 .detect = tc_connector_detect,
1651 .fill_modes = drm_helper_probe_single_connector_modes,
1652 .destroy = drm_connector_cleanup,
1653 .reset = drm_atomic_helper_connector_reset,
1654 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1655 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1656};
1657
1658static int tc_dpi_bridge_attach(struct drm_bridge *bridge,
1659 enum drm_bridge_attach_flags flags)
1660{
1661 struct tc_data *tc = bridge_to_tc(bridge);
1662
1663 if (!tc->panel_bridge)
1664 return 0;
1665
1666 return drm_bridge_attach(tc->bridge.encoder, tc->panel_bridge,
1667 &tc->bridge, flags);
1668}
1669
1670static int tc_edp_bridge_attach(struct drm_bridge *bridge,
1671 enum drm_bridge_attach_flags flags)
1672{
1673 u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1674 struct tc_data *tc = bridge_to_tc(bridge);
1675 struct drm_device *drm = bridge->dev;
1676 int ret;
1677
1678 if (tc->panel_bridge) {
1679 /* If a connector is required then this driver shall create it */
1680 ret = drm_bridge_attach(tc->bridge.encoder, tc->panel_bridge,
1681 &tc->bridge, flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR);
1682 if (ret)
1683 return ret;
1684 }
1685
1686 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
1687 return 0;
1688
1689 tc->aux.drm_dev = drm;
1690 ret = drm_dp_aux_register(&tc->aux);
1691 if (ret < 0)
1692 return ret;
1693
1694 /* Create DP/eDP connector */
1695 drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs);
1696 ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs, tc->bridge.type);
1697 if (ret)
1698 goto aux_unregister;
1699
1700 /* Don't poll if don't have HPD connected */
1701 if (tc->hpd_pin >= 0) {
1702 if (tc->have_irq)
1703 tc->connector.polled = DRM_CONNECTOR_POLL_HPD;
1704 else
1705 tc->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
1706 DRM_CONNECTOR_POLL_DISCONNECT;
1707 }
1708
1709 drm_display_info_set_bus_formats(&tc->connector.display_info,
1710 &bus_format, 1);
1711 tc->connector.display_info.bus_flags =
1712 DRM_BUS_FLAG_DE_HIGH |
1713 DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE |
1714 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE;
1715 drm_connector_attach_encoder(&tc->connector, tc->bridge.encoder);
1716
1717 return 0;
1718aux_unregister:
1719 drm_dp_aux_unregister(&tc->aux);
1720 return ret;
1721}
1722
1723static void tc_edp_bridge_detach(struct drm_bridge *bridge)
1724{
1725 drm_dp_aux_unregister(&bridge_to_tc(bridge)->aux);
1726}
1727
1728#define MAX_INPUT_SEL_FORMATS 1
1729
1730static u32 *
1731tc_dpi_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
1732 struct drm_bridge_state *bridge_state,
1733 struct drm_crtc_state *crtc_state,
1734 struct drm_connector_state *conn_state,
1735 u32 output_fmt,
1736 unsigned int *num_input_fmts)
1737{
1738 u32 *input_fmts;
1739
1740 *num_input_fmts = 0;
1741
1742 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
1743 GFP_KERNEL);
1744 if (!input_fmts)
1745 return NULL;
1746
1747 /* This is the DSI-end bus format */
1748 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
1749 *num_input_fmts = 1;
1750
1751 return input_fmts;
1752}
1753
1754static const struct drm_bridge_funcs tc_dpi_bridge_funcs = {
1755 .attach = tc_dpi_bridge_attach,
1756 .mode_valid = tc_dpi_mode_valid,
1757 .mode_set = tc_bridge_mode_set,
1758 .atomic_check = tc_dpi_atomic_check,
1759 .atomic_enable = tc_dpi_bridge_atomic_enable,
1760 .atomic_disable = tc_dpi_bridge_atomic_disable,
1761 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1762 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1763 .atomic_reset = drm_atomic_helper_bridge_reset,
1764 .atomic_get_input_bus_fmts = tc_dpi_atomic_get_input_bus_fmts,
1765};
1766
1767static const struct drm_bridge_funcs tc_edp_bridge_funcs = {
1768 .attach = tc_edp_bridge_attach,
1769 .detach = tc_edp_bridge_detach,
1770 .mode_valid = tc_edp_mode_valid,
1771 .mode_set = tc_bridge_mode_set,
1772 .atomic_check = tc_edp_atomic_check,
1773 .atomic_enable = tc_edp_bridge_atomic_enable,
1774 .atomic_disable = tc_edp_bridge_atomic_disable,
1775 .detect = tc_bridge_detect,
1776 .get_edid = tc_get_edid,
1777 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1778 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1779 .atomic_reset = drm_atomic_helper_bridge_reset,
1780};
1781
1782static bool tc_readable_reg(struct device *dev, unsigned int reg)
1783{
1784 switch (reg) {
1785 /* DSI D-PHY Layer */
1786 case 0x004:
1787 case 0x020:
1788 case 0x024:
1789 case 0x028:
1790 case 0x02c:
1791 case 0x030:
1792 case 0x038:
1793 case 0x040:
1794 case 0x044:
1795 case 0x048:
1796 case 0x04c:
1797 case 0x050:
1798 case 0x054:
1799 /* DSI PPI Layer */
1800 case PPI_STARTPPI:
1801 case 0x108:
1802 case 0x110:
1803 case PPI_LPTXTIMECNT:
1804 case PPI_LANEENABLE:
1805 case PPI_TX_RX_TA:
1806 case 0x140:
1807 case PPI_D0S_ATMR:
1808 case PPI_D1S_ATMR:
1809 case 0x14c:
1810 case 0x150:
1811 case PPI_D0S_CLRSIPOCOUNT:
1812 case PPI_D1S_CLRSIPOCOUNT:
1813 case PPI_D2S_CLRSIPOCOUNT:
1814 case PPI_D3S_CLRSIPOCOUNT:
1815 case 0x180:
1816 case 0x184:
1817 case 0x188:
1818 case 0x18c:
1819 case 0x190:
1820 case 0x1a0:
1821 case 0x1a4:
1822 case 0x1a8:
1823 case 0x1ac:
1824 case 0x1b0:
1825 case 0x1c0:
1826 case 0x1c4:
1827 case 0x1c8:
1828 case 0x1cc:
1829 case 0x1d0:
1830 case 0x1e0:
1831 case 0x1e4:
1832 case 0x1f0:
1833 case 0x1f4:
1834 /* DSI Protocol Layer */
1835 case DSI_STARTDSI:
1836 case 0x208:
1837 case DSI_LANEENABLE:
1838 case 0x214:
1839 case 0x218:
1840 case 0x220:
1841 case 0x224:
1842 case 0x228:
1843 case 0x230:
1844 /* DSI General */
1845 case 0x300:
1846 /* DSI Application Layer */
1847 case 0x400:
1848 case 0x404:
1849 /* DPI */
1850 case DPIPXLFMT:
1851 /* Parallel Output */
1852 case POCTRL:
1853 /* Video Path0 Configuration */
1854 case VPCTRL0:
1855 case HTIM01:
1856 case HTIM02:
1857 case VTIM01:
1858 case VTIM02:
1859 case VFUEN0:
1860 /* System */
1861 case TC_IDREG:
1862 case 0x504:
1863 case SYSSTAT:
1864 case SYSRSTENB:
1865 case SYSCTRL:
1866 /* I2C */
1867 case 0x520:
1868 /* GPIO */
1869 case GPIOM:
1870 case GPIOC:
1871 case GPIOO:
1872 case GPIOI:
1873 /* Interrupt */
1874 case INTCTL_G:
1875 case INTSTS_G:
1876 case 0x570:
1877 case 0x574:
1878 case INT_GP0_LCNT:
1879 case INT_GP1_LCNT:
1880 /* DisplayPort Control */
1881 case DP0CTL:
1882 /* DisplayPort Clock */
1883 case DP0_VIDMNGEN0:
1884 case DP0_VIDMNGEN1:
1885 case DP0_VMNGENSTATUS:
1886 case 0x628:
1887 case 0x62c:
1888 case 0x630:
1889 /* DisplayPort Main Channel */
1890 case DP0_SECSAMPLE:
1891 case DP0_VIDSYNCDELAY:
1892 case DP0_TOTALVAL:
1893 case DP0_STARTVAL:
1894 case DP0_ACTIVEVAL:
1895 case DP0_SYNCVAL:
1896 case DP0_MISC:
1897 /* DisplayPort Aux Channel */
1898 case DP0_AUXCFG0:
1899 case DP0_AUXCFG1:
1900 case DP0_AUXADDR:
1901 case 0x66c:
1902 case 0x670:
1903 case 0x674:
1904 case 0x678:
1905 case 0x67c:
1906 case 0x680:
1907 case 0x684:
1908 case 0x688:
1909 case DP0_AUXSTATUS:
1910 case DP0_AUXI2CADR:
1911 /* DisplayPort Link Training */
1912 case DP0_SRCCTRL:
1913 case DP0_LTSTAT:
1914 case DP0_SNKLTCHGREQ:
1915 case DP0_LTLOOPCTRL:
1916 case DP0_SNKLTCTRL:
1917 case 0x6e8:
1918 case 0x6ec:
1919 case 0x6f0:
1920 case 0x6f4:
1921 /* DisplayPort Audio */
1922 case 0x700:
1923 case 0x704:
1924 case 0x708:
1925 case 0x70c:
1926 case 0x710:
1927 case 0x714:
1928 case 0x718:
1929 case 0x71c:
1930 case 0x720:
1931 /* DisplayPort Source Control */
1932 case DP1_SRCCTRL:
1933 /* DisplayPort PHY */
1934 case DP_PHY_CTRL:
1935 case 0x810:
1936 case 0x814:
1937 case 0x820:
1938 case 0x840:
1939 /* I2S */
1940 case 0x880:
1941 case 0x888:
1942 case 0x88c:
1943 case 0x890:
1944 case 0x894:
1945 case 0x898:
1946 case 0x89c:
1947 case 0x8a0:
1948 case 0x8a4:
1949 case 0x8a8:
1950 case 0x8ac:
1951 case 0x8b0:
1952 case 0x8b4:
1953 /* PLL */
1954 case DP0_PLLCTRL:
1955 case DP1_PLLCTRL:
1956 case PXL_PLLCTRL:
1957 case PXL_PLLPARAM:
1958 case SYS_PLLPARAM:
1959 /* HDCP */
1960 case 0x980:
1961 case 0x984:
1962 case 0x988:
1963 case 0x98c:
1964 case 0x990:
1965 case 0x994:
1966 case 0x998:
1967 case 0x99c:
1968 case 0x9a0:
1969 case 0x9a4:
1970 case 0x9a8:
1971 case 0x9ac:
1972 /* Debug */
1973 case TSTCTL:
1974 case PLL_DBG:
1975 return true;
1976 }
1977 return false;
1978}
1979
1980static const struct regmap_range tc_volatile_ranges[] = {
1981 regmap_reg_range(DP0_AUXWDATA(0), DP0_AUXSTATUS),
1982 regmap_reg_range(DP0_LTSTAT, DP0_SNKLTCHGREQ),
1983 regmap_reg_range(DP_PHY_CTRL, DP_PHY_CTRL),
1984 regmap_reg_range(DP0_PLLCTRL, PXL_PLLCTRL),
1985 regmap_reg_range(VFUEN0, VFUEN0),
1986 regmap_reg_range(INTSTS_G, INTSTS_G),
1987 regmap_reg_range(GPIOI, GPIOI),
1988};
1989
1990static const struct regmap_access_table tc_volatile_table = {
1991 .yes_ranges = tc_volatile_ranges,
1992 .n_yes_ranges = ARRAY_SIZE(tc_volatile_ranges),
1993};
1994
1995static bool tc_writeable_reg(struct device *dev, unsigned int reg)
1996{
1997 return (reg != TC_IDREG) &&
1998 (reg != DP0_LTSTAT) &&
1999 (reg != DP0_SNKLTCHGREQ);
2000}
2001
2002static const struct regmap_config tc_regmap_config = {
2003 .name = "tc358767",
2004 .reg_bits = 16,
2005 .val_bits = 32,
2006 .reg_stride = 4,
2007 .max_register = PLL_DBG,
2008 .cache_type = REGCACHE_MAPLE,
2009 .readable_reg = tc_readable_reg,
2010 .volatile_table = &tc_volatile_table,
2011 .writeable_reg = tc_writeable_reg,
2012 .reg_format_endian = REGMAP_ENDIAN_BIG,
2013 .val_format_endian = REGMAP_ENDIAN_LITTLE,
2014};
2015
2016static irqreturn_t tc_irq_handler(int irq, void *arg)
2017{
2018 struct tc_data *tc = arg;
2019 u32 val;
2020 int r;
2021
2022 r = regmap_read(tc->regmap, INTSTS_G, &val);
2023 if (r)
2024 return IRQ_NONE;
2025
2026 if (!val)
2027 return IRQ_NONE;
2028
2029 if (val & INT_SYSERR) {
2030 u32 stat = 0;
2031
2032 regmap_read(tc->regmap, SYSSTAT, &stat);
2033
2034 dev_err(tc->dev, "syserr %x\n", stat);
2035 }
2036
2037 if (tc->hpd_pin >= 0 && tc->bridge.dev) {
2038 /*
2039 * H is triggered when the GPIO goes high.
2040 *
2041 * LC is triggered when the GPIO goes low and stays low for
2042 * the duration of LCNT
2043 */
2044 bool h = val & INT_GPIO_H(tc->hpd_pin);
2045 bool lc = val & INT_GPIO_LC(tc->hpd_pin);
2046
2047 dev_dbg(tc->dev, "GPIO%d: %s %s\n", tc->hpd_pin,
2048 h ? "H" : "", lc ? "LC" : "");
2049
2050 if (h || lc)
2051 drm_kms_helper_hotplug_event(tc->bridge.dev);
2052 }
2053
2054 regmap_write(tc->regmap, INTSTS_G, val);
2055
2056 return IRQ_HANDLED;
2057}
2058
2059static int tc_mipi_dsi_host_attach(struct tc_data *tc)
2060{
2061 struct device *dev = tc->dev;
2062 struct device_node *host_node;
2063 struct device_node *endpoint;
2064 struct mipi_dsi_device *dsi;
2065 struct mipi_dsi_host *host;
2066 const struct mipi_dsi_device_info info = {
2067 .type = "tc358767",
2068 .channel = 0,
2069 .node = NULL,
2070 };
2071 int dsi_lanes, ret;
2072
2073 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1);
2074 dsi_lanes = drm_of_get_data_lanes_count(endpoint, 1, 4);
2075 host_node = of_graph_get_remote_port_parent(endpoint);
2076 host = of_find_mipi_dsi_host_by_node(host_node);
2077 of_node_put(host_node);
2078 of_node_put(endpoint);
2079
2080 if (!host)
2081 return -EPROBE_DEFER;
2082
2083 if (dsi_lanes < 0)
2084 return dsi_lanes;
2085
2086 dsi = devm_mipi_dsi_device_register_full(dev, host, &info);
2087 if (IS_ERR(dsi))
2088 return dev_err_probe(dev, PTR_ERR(dsi),
2089 "failed to create dsi device\n");
2090
2091 tc->dsi = dsi;
2092 dsi->lanes = dsi_lanes;
2093 dsi->format = MIPI_DSI_FMT_RGB888;
2094 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
2095 MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS;
2096
2097 ret = devm_mipi_dsi_attach(dev, dsi);
2098 if (ret < 0) {
2099 dev_err(dev, "failed to attach dsi to host: %d\n", ret);
2100 return ret;
2101 }
2102
2103 return 0;
2104}
2105
2106static int tc_probe_dpi_bridge_endpoint(struct tc_data *tc)
2107{
2108 struct device *dev = tc->dev;
2109 struct drm_bridge *bridge;
2110 struct drm_panel *panel;
2111 int ret;
2112
2113 /* port@1 is the DPI input/output port */
2114 ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, &bridge);
2115 if (ret && ret != -ENODEV)
2116 return ret;
2117
2118 if (panel) {
2119 bridge = devm_drm_panel_bridge_add(dev, panel);
2120 if (IS_ERR(bridge))
2121 return PTR_ERR(bridge);
2122 }
2123
2124 if (bridge) {
2125 tc->panel_bridge = bridge;
2126 tc->bridge.type = DRM_MODE_CONNECTOR_DPI;
2127 tc->bridge.funcs = &tc_dpi_bridge_funcs;
2128
2129 return 0;
2130 }
2131
2132 return ret;
2133}
2134
2135static int tc_probe_edp_bridge_endpoint(struct tc_data *tc)
2136{
2137 struct device *dev = tc->dev;
2138 struct drm_panel *panel;
2139 int ret;
2140
2141 /* port@2 is the output port */
2142 ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &panel, NULL);
2143 if (ret && ret != -ENODEV)
2144 return ret;
2145
2146 if (panel) {
2147 struct drm_bridge *panel_bridge;
2148
2149 panel_bridge = devm_drm_panel_bridge_add(dev, panel);
2150 if (IS_ERR(panel_bridge))
2151 return PTR_ERR(panel_bridge);
2152
2153 tc->panel_bridge = panel_bridge;
2154 tc->bridge.type = DRM_MODE_CONNECTOR_eDP;
2155 } else {
2156 tc->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
2157 }
2158
2159 tc->bridge.funcs = &tc_edp_bridge_funcs;
2160 if (tc->hpd_pin >= 0)
2161 tc->bridge.ops |= DRM_BRIDGE_OP_DETECT;
2162 tc->bridge.ops |= DRM_BRIDGE_OP_EDID;
2163
2164 return 0;
2165}
2166
2167static int tc_probe_bridge_endpoint(struct tc_data *tc)
2168{
2169 struct device *dev = tc->dev;
2170 struct of_endpoint endpoint;
2171 struct device_node *node = NULL;
2172 const u8 mode_dpi_to_edp = BIT(1) | BIT(2);
2173 const u8 mode_dpi_to_dp = BIT(1);
2174 const u8 mode_dsi_to_edp = BIT(0) | BIT(2);
2175 const u8 mode_dsi_to_dp = BIT(0);
2176 const u8 mode_dsi_to_dpi = BIT(0) | BIT(1);
2177 u8 mode = 0;
2178
2179 /*
2180 * Determine bridge configuration.
2181 *
2182 * Port allocation:
2183 * port@0 - DSI input
2184 * port@1 - DPI input/output
2185 * port@2 - eDP output
2186 *
2187 * Possible connections:
2188 * DPI -> port@1 -> port@2 -> eDP :: [port@0 is not connected]
2189 * DSI -> port@0 -> port@2 -> eDP :: [port@1 is not connected]
2190 * DSI -> port@0 -> port@1 -> DPI :: [port@2 is not connected]
2191 */
2192
2193 for_each_endpoint_of_node(dev->of_node, node) {
2194 of_graph_parse_endpoint(node, &endpoint);
2195 if (endpoint.port > 2) {
2196 of_node_put(node);
2197 return -EINVAL;
2198 }
2199 mode |= BIT(endpoint.port);
2200 }
2201
2202 if (mode == mode_dpi_to_edp || mode == mode_dpi_to_dp) {
2203 tc->input_connector_dsi = false;
2204 return tc_probe_edp_bridge_endpoint(tc);
2205 } else if (mode == mode_dsi_to_dpi) {
2206 tc->input_connector_dsi = true;
2207 return tc_probe_dpi_bridge_endpoint(tc);
2208 } else if (mode == mode_dsi_to_edp || mode == mode_dsi_to_dp) {
2209 tc->input_connector_dsi = true;
2210 return tc_probe_edp_bridge_endpoint(tc);
2211 }
2212
2213 dev_warn(dev, "Invalid mode (0x%x) is not supported!\n", mode);
2214
2215 return -EINVAL;
2216}
2217
2218static int tc_probe(struct i2c_client *client)
2219{
2220 struct device *dev = &client->dev;
2221 struct tc_data *tc;
2222 int ret;
2223
2224 tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL);
2225 if (!tc)
2226 return -ENOMEM;
2227
2228 tc->dev = dev;
2229
2230 ret = tc_probe_bridge_endpoint(tc);
2231 if (ret)
2232 return ret;
2233
2234 tc->refclk = devm_clk_get_enabled(dev, "ref");
2235 if (IS_ERR(tc->refclk))
2236 return dev_err_probe(dev, PTR_ERR(tc->refclk),
2237 "Failed to get and enable the ref clk\n");
2238
2239 /* tRSTW = 100 cycles , at 13 MHz that is ~7.69 us */
2240 usleep_range(10, 15);
2241
2242 /* Shut down GPIO is optional */
2243 tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH);
2244 if (IS_ERR(tc->sd_gpio))
2245 return PTR_ERR(tc->sd_gpio);
2246
2247 if (tc->sd_gpio) {
2248 gpiod_set_value_cansleep(tc->sd_gpio, 0);
2249 usleep_range(5000, 10000);
2250 }
2251
2252 /* Reset GPIO is optional */
2253 tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
2254 if (IS_ERR(tc->reset_gpio))
2255 return PTR_ERR(tc->reset_gpio);
2256
2257 if (tc->reset_gpio) {
2258 gpiod_set_value_cansleep(tc->reset_gpio, 1);
2259 usleep_range(5000, 10000);
2260 }
2261
2262 tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config);
2263 if (IS_ERR(tc->regmap)) {
2264 ret = PTR_ERR(tc->regmap);
2265 dev_err(dev, "Failed to initialize regmap: %d\n", ret);
2266 return ret;
2267 }
2268
2269 ret = of_property_read_u32(dev->of_node, "toshiba,hpd-pin",
2270 &tc->hpd_pin);
2271 if (ret) {
2272 tc->hpd_pin = -ENODEV;
2273 } else {
2274 if (tc->hpd_pin < 0 || tc->hpd_pin > 1) {
2275 dev_err(dev, "failed to parse HPD number\n");
2276 return -EINVAL;
2277 }
2278 }
2279
2280 if (client->irq > 0) {
2281 /* enable SysErr */
2282 regmap_write(tc->regmap, INTCTL_G, INT_SYSERR);
2283
2284 ret = devm_request_threaded_irq(dev, client->irq,
2285 NULL, tc_irq_handler,
2286 IRQF_ONESHOT,
2287 "tc358767-irq", tc);
2288 if (ret) {
2289 dev_err(dev, "failed to register dp interrupt\n");
2290 return ret;
2291 }
2292
2293 tc->have_irq = true;
2294 }
2295
2296 ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev);
2297 if (ret) {
2298 dev_err(tc->dev, "can not read device ID: %d\n", ret);
2299 return ret;
2300 }
2301
2302 if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) {
2303 dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev);
2304 return -EINVAL;
2305 }
2306
2307 tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */
2308
2309 if (!tc->reset_gpio) {
2310 /*
2311 * If the reset pin isn't present, do a software reset. It isn't
2312 * as thorough as the hardware reset, as we can't reset the I2C
2313 * communication block for obvious reasons, but it's getting the
2314 * chip into a defined state.
2315 */
2316 regmap_update_bits(tc->regmap, SYSRSTENB,
2317 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP,
2318 0);
2319 regmap_update_bits(tc->regmap, SYSRSTENB,
2320 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP,
2321 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP);
2322 usleep_range(5000, 10000);
2323 }
2324
2325 if (tc->hpd_pin >= 0) {
2326 u32 lcnt_reg = tc->hpd_pin == 0 ? INT_GP0_LCNT : INT_GP1_LCNT;
2327 u32 h_lc = INT_GPIO_H(tc->hpd_pin) | INT_GPIO_LC(tc->hpd_pin);
2328
2329 /* Set LCNT to 2ms */
2330 regmap_write(tc->regmap, lcnt_reg,
2331 clk_get_rate(tc->refclk) * 2 / 1000);
2332 /* We need the "alternate" mode for HPD */
2333 regmap_write(tc->regmap, GPIOM, BIT(tc->hpd_pin));
2334
2335 if (tc->have_irq) {
2336 /* enable H & LC */
2337 regmap_update_bits(tc->regmap, INTCTL_G, h_lc, h_lc);
2338 }
2339 }
2340
2341 if (tc->bridge.type != DRM_MODE_CONNECTOR_DPI) { /* (e)DP output */
2342 ret = tc_aux_link_setup(tc);
2343 if (ret)
2344 return ret;
2345 }
2346
2347 tc->bridge.of_node = dev->of_node;
2348 drm_bridge_add(&tc->bridge);
2349
2350 i2c_set_clientdata(client, tc);
2351
2352 if (tc->input_connector_dsi) { /* DSI input */
2353 ret = tc_mipi_dsi_host_attach(tc);
2354 if (ret) {
2355 drm_bridge_remove(&tc->bridge);
2356 return ret;
2357 }
2358 }
2359
2360 return 0;
2361}
2362
2363static void tc_remove(struct i2c_client *client)
2364{
2365 struct tc_data *tc = i2c_get_clientdata(client);
2366
2367 drm_bridge_remove(&tc->bridge);
2368}
2369
2370static const struct i2c_device_id tc358767_i2c_ids[] = {
2371 { "tc358767", 0 },
2372 { }
2373};
2374MODULE_DEVICE_TABLE(i2c, tc358767_i2c_ids);
2375
2376static const struct of_device_id tc358767_of_ids[] = {
2377 { .compatible = "toshiba,tc358767", },
2378 { }
2379};
2380MODULE_DEVICE_TABLE(of, tc358767_of_ids);
2381
2382static struct i2c_driver tc358767_driver = {
2383 .driver = {
2384 .name = "tc358767",
2385 .of_match_table = tc358767_of_ids,
2386 },
2387 .id_table = tc358767_i2c_ids,
2388 .probe = tc_probe,
2389 .remove = tc_remove,
2390};
2391module_i2c_driver(tc358767_driver);
2392
2393MODULE_AUTHOR("Andrey Gusakov <andrey.gusakov@cogentembedded.com>");
2394MODULE_DESCRIPTION("tc358767 eDP encoder driver");
2395MODULE_LICENSE("GPL");