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1/* SPDX-License-Identifier: GPL-2.0 */
2/* iommu.h: Definitions for the sun4m IOMMU.
3 *
4 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
5 */
6#ifndef _SPARC_IOMMU_H
7#define _SPARC_IOMMU_H
8
9#include <asm/page.h>
10#include <asm/bitext.h>
11
12/* The iommu handles all virtual to physical address translations
13 * that occur between the SBUS and physical memory. Access by
14 * the cpu to IO registers and similar go over the mbus so are
15 * translated by the on chip SRMMU. The iommu and the srmmu do
16 * not need to have the same translations at all, in fact most
17 * of the time the translations they handle are a disjunct set.
18 * Basically the iommu handles all dvma sbus activity.
19 */
20
21/* The IOMMU registers occupy three pages in IO space. */
22struct iommu_regs {
23 /* First page */
24 volatile unsigned long control; /* IOMMU control */
25 volatile unsigned long base; /* Physical base of iopte page table */
26 volatile unsigned long _unused1[3];
27 volatile unsigned long tlbflush; /* write only */
28 volatile unsigned long pageflush; /* write only */
29 volatile unsigned long _unused2[1017];
30 /* Second page */
31 volatile unsigned long afsr; /* Async-fault status register */
32 volatile unsigned long afar; /* Async-fault physical address */
33 volatile unsigned long _unused3[2];
34 volatile unsigned long sbuscfg0; /* SBUS configuration registers, per-slot */
35 volatile unsigned long sbuscfg1;
36 volatile unsigned long sbuscfg2;
37 volatile unsigned long sbuscfg3;
38 volatile unsigned long mfsr; /* Memory-fault status register */
39 volatile unsigned long mfar; /* Memory-fault physical address */
40 volatile unsigned long _unused4[1014];
41 /* Third page */
42 volatile unsigned long mid; /* IOMMU module-id */
43};
44
45#define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
46#define IOMMU_CTRL_VERS 0x0f000000 /* Version */
47#define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
48#define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
49#define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
50#define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
51#define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */
52#define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */
53#define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */
54#define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */
55#define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */
56#define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */
57
58#define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */
59#define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after transaction */
60#define IOMMU_AFSR_TO 0x20000000 /* Write access took more than 12.8 us. */
61#define IOMMU_AFSR_BE 0x10000000 /* Write access received error acknowledge */
62#define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */
63#define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
64#define IOMMU_AFSR_RESV 0x00f00000 /* Reserver, forced to 0x8 by hardware */
65#define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */
66#define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */
67#define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */
68
69#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when bypass enabled */
70#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
71#define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
72#define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
73 produced by this device as pure
74 physical. */
75
76#define IOMMU_MFSR_ERR 0x80000000 /* One or more of PERR1 or PERR0 */
77#define IOMMU_MFSR_S 0x01000000 /* Sparc was in supervisor mode */
78#define IOMMU_MFSR_CPU 0x00800000 /* CPU transaction caused parity error */
79#define IOMMU_MFSR_ME 0x00080000 /* Multiple parity errors occurred */
80#define IOMMU_MFSR_PERR 0x00006000 /* high bit indicates parity error occurred
81 on the even word of the access, low bit
82 indicated odd word caused the parity error */
83#define IOMMU_MFSR_BM 0x00001000 /* Error occurred while in boot mode */
84#define IOMMU_MFSR_C 0x00000800 /* Address causing error was marked cacheable */
85#define IOMMU_MFSR_RTYP 0x000000f0 /* Memory request transaction type */
86
87#define IOMMU_MID_SBAE 0x001f0000 /* SBus arbitration enable */
88#define IOMMU_MID_SE 0x00100000 /* Enables SCSI/ETHERNET arbitration */
89#define IOMMU_MID_SB3 0x00080000 /* Enable SBUS device 3 arbitration */
90#define IOMMU_MID_SB2 0x00040000 /* Enable SBUS device 2 arbitration */
91#define IOMMU_MID_SB1 0x00020000 /* Enable SBUS device 1 arbitration */
92#define IOMMU_MID_SB0 0x00010000 /* Enable SBUS device 0 arbitration */
93#define IOMMU_MID_MID 0x0000000f /* Module-id, hardcoded to 0x8 */
94
95/* The format of an iopte in the page tables */
96#define IOPTE_PAGE 0x07ffff00 /* Physical page number (PA[30:12]) */
97#define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or Viking/MXCC) */
98#define IOPTE_WRITE 0x00000004 /* Writeable */
99#define IOPTE_VALID 0x00000002 /* IOPTE is valid */
100#define IOPTE_WAZ 0x00000001 /* Write as zeros */
101
102struct iommu_struct {
103 struct iommu_regs __iomem *regs;
104 iopte_t *page_table;
105 /* For convenience */
106 unsigned long start; /* First managed virtual address */
107 unsigned long end; /* Last managed virtual address */
108
109 struct bit_map usemap;
110};
111
112static inline void iommu_invalidate(struct iommu_regs __iomem *regs)
113{
114 sbus_writel(0, ®s->tlbflush);
115}
116
117static inline void iommu_invalidate_page(struct iommu_regs __iomem *regs, unsigned long ba)
118{
119 sbus_writel(ba & PAGE_MASK, ®s->pageflush);
120}
121
122#endif /* !(_SPARC_IOMMU_H) */
1/* SPDX-License-Identifier: GPL-2.0 */
2/* iommu.h: Definitions for the sun4m IOMMU.
3 *
4 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
5 */
6#ifndef _SPARC_IOMMU_H
7#define _SPARC_IOMMU_H
8
9#include <asm/page.h>
10#include <asm/bitext.h>
11
12/* The iommu handles all virtual to physical address translations
13 * that occur between the SBUS and physical memory. Access by
14 * the cpu to IO registers and similar go over the mbus so are
15 * translated by the on chip SRMMU. The iommu and the srmmu do
16 * not need to have the same translations at all, in fact most
17 * of the time the translations they handle are a disjunct set.
18 * Basically the iommu handles all dvma sbus activity.
19 */
20
21/* The IOMMU registers occupy three pages in IO space. */
22struct iommu_regs {
23 /* First page */
24 volatile unsigned long control; /* IOMMU control */
25 volatile unsigned long base; /* Physical base of iopte page table */
26 volatile unsigned long _unused1[3];
27 volatile unsigned long tlbflush; /* write only */
28 volatile unsigned long pageflush; /* write only */
29 volatile unsigned long _unused2[1017];
30 /* Second page */
31 volatile unsigned long afsr; /* Async-fault status register */
32 volatile unsigned long afar; /* Async-fault physical address */
33 volatile unsigned long _unused3[2];
34 volatile unsigned long sbuscfg0; /* SBUS configuration registers, per-slot */
35 volatile unsigned long sbuscfg1;
36 volatile unsigned long sbuscfg2;
37 volatile unsigned long sbuscfg3;
38 volatile unsigned long mfsr; /* Memory-fault status register */
39 volatile unsigned long mfar; /* Memory-fault physical address */
40 volatile unsigned long _unused4[1014];
41 /* Third page */
42 volatile unsigned long mid; /* IOMMU module-id */
43};
44
45#define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
46#define IOMMU_CTRL_VERS 0x0f000000 /* Version */
47#define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
48#define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
49#define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
50#define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
51#define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */
52#define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */
53#define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */
54#define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */
55#define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */
56#define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */
57
58#define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */
59#define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after transaction */
60#define IOMMU_AFSR_TO 0x20000000 /* Write access took more than 12.8 us. */
61#define IOMMU_AFSR_BE 0x10000000 /* Write access received error acknowledge */
62#define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */
63#define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
64#define IOMMU_AFSR_RESV 0x00f00000 /* Reserver, forced to 0x8 by hardware */
65#define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */
66#define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */
67#define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */
68
69#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when bypass enabled */
70#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
71#define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
72#define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
73 produced by this device as pure
74 physical. */
75
76#define IOMMU_MFSR_ERR 0x80000000 /* One or more of PERR1 or PERR0 */
77#define IOMMU_MFSR_S 0x01000000 /* Sparc was in supervisor mode */
78#define IOMMU_MFSR_CPU 0x00800000 /* CPU transaction caused parity error */
79#define IOMMU_MFSR_ME 0x00080000 /* Multiple parity errors occurred */
80#define IOMMU_MFSR_PERR 0x00006000 /* high bit indicates parity error occurred
81 on the even word of the access, low bit
82 indicated odd word caused the parity error */
83#define IOMMU_MFSR_BM 0x00001000 /* Error occurred while in boot mode */
84#define IOMMU_MFSR_C 0x00000800 /* Address causing error was marked cacheable */
85#define IOMMU_MFSR_RTYP 0x000000f0 /* Memory request transaction type */
86
87#define IOMMU_MID_SBAE 0x001f0000 /* SBus arbitration enable */
88#define IOMMU_MID_SE 0x00100000 /* Enables SCSI/ETHERNET arbitration */
89#define IOMMU_MID_SB3 0x00080000 /* Enable SBUS device 3 arbitration */
90#define IOMMU_MID_SB2 0x00040000 /* Enable SBUS device 2 arbitration */
91#define IOMMU_MID_SB1 0x00020000 /* Enable SBUS device 1 arbitration */
92#define IOMMU_MID_SB0 0x00010000 /* Enable SBUS device 0 arbitration */
93#define IOMMU_MID_MID 0x0000000f /* Module-id, hardcoded to 0x8 */
94
95/* The format of an iopte in the page tables */
96#define IOPTE_PAGE 0x07ffff00 /* Physical page number (PA[30:12]) */
97#define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or Viking/MXCC) */
98#define IOPTE_WRITE 0x00000004 /* Writeable */
99#define IOPTE_VALID 0x00000002 /* IOPTE is valid */
100#define IOPTE_WAZ 0x00000001 /* Write as zeros */
101
102struct iommu_struct {
103 struct iommu_regs __iomem *regs;
104 iopte_t *page_table;
105 /* For convenience */
106 unsigned long start; /* First managed virtual address */
107 unsigned long end; /* Last managed virtual address */
108
109 struct bit_map usemap;
110};
111
112static inline void iommu_invalidate(struct iommu_regs __iomem *regs)
113{
114 sbus_writel(0, ®s->tlbflush);
115}
116
117static inline void iommu_invalidate_page(struct iommu_regs __iomem *regs, unsigned long ba)
118{
119 sbus_writel(ba & PAGE_MASK, ®s->pageflush);
120}
121
122#endif /* !(_SPARC_IOMMU_H) */