1/*
  2 * This file contains low level CPU setup functions.
  3 *    Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
  4 *
  5 * This program is free software; you can redistribute it and/or
  6 * modify it under the terms of the GNU General Public License
  7 * as published by the Free Software Foundation; either version
  8 * 2 of the License, or (at your option) any later version.
  9 *
 10 */
 11
 12#include <asm/processor.h>
 13#include <asm/page.h>
 14#include <asm/cputable.h>
 15#include <asm/ppc_asm.h>
 16#include <asm/asm-offsets.h>
 17#include <asm/cache.h>
 18#include <asm/book3s/64/mmu-hash.h>
 19
 20/* Entry: r3 = crap, r4 = ptr to cputable entry
 21 *
 22 * Note that we can be called twice for pseudo-PVRs
 23 */
 24_GLOBAL(__setup_cpu_power7)
 25	mflr	r11
 26	bl	__init_hvmode_206
 27	mtlr	r11
 28	beqlr
 29	li	r0,0
 30	mtspr	SPRN_LPID,r0
 31	mtspr	SPRN_PCR,r0
 32	mfspr	r3,SPRN_LPCR
 33	li	r4,(LPCR_LPES1 >> LPCR_LPES_SH)
 34	bl	__init_LPCR_ISA206
 35	mtlr	r11
 36	blr
 37
 38_GLOBAL(__restore_cpu_power7)
 39	mflr	r11
 40	mfmsr	r3
 41	rldicl.	r0,r3,4,63
 42	beqlr
 43	li	r0,0
 44	mtspr	SPRN_LPID,r0
 45	mtspr	SPRN_PCR,r0
 46	mfspr	r3,SPRN_LPCR
 47	li	r4,(LPCR_LPES1 >> LPCR_LPES_SH)
 48	bl	__init_LPCR_ISA206
 49	mtlr	r11
 50	blr
 51
 52_GLOBAL(__setup_cpu_power8)
 53	mflr	r11
 54	bl	__init_FSCR
 55	bl	__init_PMU
 56	bl	__init_PMU_ISA207
 57	bl	__init_hvmode_206
 58	mtlr	r11
 59	beqlr
 60	li	r0,0
 61	mtspr	SPRN_LPID,r0
 62	mtspr	SPRN_PCR,r0
 63	mfspr	r3,SPRN_LPCR
 64	ori	r3, r3, LPCR_PECEDH
 65	li	r4,0 /* LPES = 0 */
 66	bl	__init_LPCR_ISA206
 67	bl	__init_HFSCR
 68	bl	__init_PMU_HV
 69	bl	__init_PMU_HV_ISA207
 70	mtlr	r11
 71	blr
 72
 73_GLOBAL(__restore_cpu_power8)
 74	mflr	r11
 75	bl	__init_FSCR
 76	bl	__init_PMU
 77	bl	__init_PMU_ISA207
 78	mfmsr	r3
 79	rldicl.	r0,r3,4,63
 80	mtlr	r11
 81	beqlr
 82	li	r0,0
 83	mtspr	SPRN_LPID,r0
 84	mtspr	SPRN_PCR,r0
 85	mfspr   r3,SPRN_LPCR
 86	ori	r3, r3, LPCR_PECEDH
 87	li	r4,0 /* LPES = 0 */
 88	bl	__init_LPCR_ISA206
 89	bl	__init_HFSCR
 90	bl	__init_PMU_HV
 91	bl	__init_PMU_HV_ISA207
 92	mtlr	r11
 93	blr
 94
 95_GLOBAL(__setup_cpu_power9)
 96	mflr	r11
 97	bl	__init_FSCR
 98	bl	__init_PMU
 99	bl	__init_hvmode_206
100	mtlr	r11
101	beqlr
102	li	r0,0
103	mtspr	SPRN_PSSCR,r0
104	mtspr	SPRN_LPID,r0
105	mtspr	SPRN_PID,r0
106	mtspr	SPRN_PCR,r0
107	mfspr	r3,SPRN_LPCR
108	LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE  | LPCR_HEIC)
109	or	r3, r3, r4
110	LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
111	andc	r3, r3, r4
112	li	r4,0 /* LPES = 0 */
113	bl	__init_LPCR_ISA300
114	bl	__init_HFSCR
115	bl	__init_PMU_HV
116	mtlr	r11
117	blr
118
119_GLOBAL(__restore_cpu_power9)
120	mflr	r11
121	bl	__init_FSCR
122	bl	__init_PMU
123	mfmsr	r3
124	rldicl.	r0,r3,4,63
125	mtlr	r11
126	beqlr
127	li	r0,0
128	mtspr	SPRN_PSSCR,r0
129	mtspr	SPRN_LPID,r0
130	mtspr	SPRN_PID,r0
131	mtspr	SPRN_PCR,r0
132	mfspr   r3,SPRN_LPCR
133	LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE | LPCR_HEIC)
134	or	r3, r3, r4
135	LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
136	andc	r3, r3, r4
137	li	r4,0 /* LPES = 0 */
138	bl	__init_LPCR_ISA300
139	bl	__init_HFSCR
140	bl	__init_PMU_HV
141	mtlr	r11
142	blr
143
144__init_hvmode_206:
145	/* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
146	mfmsr	r3
147	rldicl.	r0,r3,4,63
148	bnelr
149	ld	r5,CPU_SPEC_FEATURES(r4)
150	LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE)
151	xor	r5,r5,r6
152	std	r5,CPU_SPEC_FEATURES(r4)
153	blr
154
155__init_LPCR_ISA206:
156	/* Setup a sane LPCR:
157	 *   Called with initial LPCR in R3 and desired LPES 2-bit value in R4
158	 *
159	 *   LPES = 0b01 (HSRR0/1 used for 0x500)
160	 *   PECE = 0b111
161	 *   DPFD = 4
162	 *   HDICE = 0
163	 *   VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
164	 *   VRMASD = 0b10000 (L=1, LP=00)
165	 *
166	 * Other bits untouched for now
167	 */
168	li	r5,0x10
169	rldimi	r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
170
171	/* POWER9 has no VRMASD */
172__init_LPCR_ISA300:
173	rldimi	r3,r4, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
174	ori	r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
175	li	r5,4
176	rldimi	r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
177	clrrdi	r3,r3,1		/* clear HDICE */
178	li	r5,4
179	rldimi	r3,r5, LPCR_VC_SH, 0
180	mtspr	SPRN_LPCR,r3
181	isync
182	blr
183
184__init_FSCR:
185	mfspr	r3,SPRN_FSCR
186	ori	r3,r3,FSCR_TAR|FSCR_DSCR|FSCR_EBB
187	mtspr	SPRN_FSCR,r3
188	blr
189
190__init_HFSCR:
191	mfspr	r3,SPRN_HFSCR
192	ori	r3,r3,HFSCR_TAR|HFSCR_TM|HFSCR_BHRB|HFSCR_PM|\
193		      HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB|HFSCR_MSGP
194	mtspr	SPRN_HFSCR,r3
195	blr
196
197__init_PMU_HV:
198	li	r5,0
199	mtspr	SPRN_MMCRC,r5
200	blr
201
202__init_PMU_HV_ISA207:
203	li	r5,0
204	mtspr	SPRN_MMCRH,r5
205	blr
206
207__init_PMU:
208	li	r5,0
209	mtspr	SPRN_MMCRA,r5
210	mtspr	SPRN_MMCR0,r5
211	mtspr	SPRN_MMCR1,r5
212	mtspr	SPRN_MMCR2,r5
213	blr
214
215__init_PMU_ISA207:
216	li	r5,0
217	mtspr	SPRN_MMCRS,r5
218	blr