1/*
  2 *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
  3 *  JZ4740 platform devices
  4 *
  5 *  This program is free software; you can redistribute it and/or modify it
  6 *  under  the terms of the GNU General	 Public License as published by the
  7 *  Free Software Foundation;  either version 2 of the License, or (at your
  8 *  option) any later version.
  9 *
 10 *  You should have received a copy of the GNU General Public License along
 11 *  with this program; if not, write to the Free Software Foundation, Inc.,
 12 *  675 Mass Ave, Cambridge, MA 02139, USA.
 13 *
 14 */
 15
 16#include <linux/clk.h>
 17#include <linux/device.h>
 18#include <linux/kernel.h>
 19#include <linux/platform_device.h>
 20#include <linux/resource.h>
 21
 22#include <linux/dma-mapping.h>
 23
 24#include <linux/usb/musb.h>
 25
 26#include <asm/mach-jz4740/platform.h>
 27#include <asm/mach-jz4740/base.h>
 28#include <asm/mach-jz4740/irq.h>
 29
 30#include <linux/serial_core.h>
 31#include <linux/serial_8250.h>
 32
 33#include "clock.h"
 34
 35/* USB Device Controller */
 36struct platform_device jz4740_udc_xceiv_device = {
 37	.name = "usb_phy_generic",
 38	.id   = 0,
 39};
 40
 41static struct resource jz4740_udc_resources[] = {
 42	[0] = {
 43		.start = JZ4740_UDC_BASE_ADDR,
 44		.end   = JZ4740_UDC_BASE_ADDR + 0x10000 - 1,
 45		.flags = IORESOURCE_MEM,
 46	},
 47	[1] = {
 48		.start = JZ4740_IRQ_UDC,
 49		.end   = JZ4740_IRQ_UDC,
 50		.flags = IORESOURCE_IRQ,
 51		.name  = "mc",
 52	},
 53};
 54
 55struct platform_device jz4740_udc_device = {
 56	.name = "musb-jz4740",
 57	.id   = -1,
 58	.dev  = {
 59		.dma_mask          = &jz4740_udc_device.dev.coherent_dma_mask,
 60		.coherent_dma_mask = DMA_BIT_MASK(32),
 61	},
 62	.num_resources = ARRAY_SIZE(jz4740_udc_resources),
 63	.resource      = jz4740_udc_resources,
 64};
 65
 66/* MMC/SD controller */
 67static struct resource jz4740_mmc_resources[] = {
 68	{
 69		.start	= JZ4740_MSC_BASE_ADDR,
 70		.end	= JZ4740_MSC_BASE_ADDR + 0x1000 - 1,
 71		.flags	= IORESOURCE_MEM,
 72	},
 73	{
 74		.start	= JZ4740_IRQ_MSC,
 75		.end	= JZ4740_IRQ_MSC,
 76		.flags	= IORESOURCE_IRQ,
 77	}
 78};
 79
 80struct platform_device jz4740_mmc_device = {
 81	.name		= "jz4740-mmc",
 82	.id		= 0,
 83	.dev = {
 84		.dma_mask = &jz4740_mmc_device.dev.coherent_dma_mask,
 85		.coherent_dma_mask = DMA_BIT_MASK(32),
 86	},
 87	.num_resources	= ARRAY_SIZE(jz4740_mmc_resources),
 88	.resource	= jz4740_mmc_resources,
 89};
 90
 91/* I2C controller */
 92static struct resource jz4740_i2c_resources[] = {
 93	{
 94		.start	= JZ4740_I2C_BASE_ADDR,
 95		.end	= JZ4740_I2C_BASE_ADDR + 0x1000 - 1,
 96		.flags	= IORESOURCE_MEM,
 97	},
 98	{
 99		.start	= JZ4740_IRQ_I2C,
100		.end	= JZ4740_IRQ_I2C,
101		.flags	= IORESOURCE_IRQ,
102	}
103};
104
105struct platform_device jz4740_i2c_device = {
106	.name		= "jz4740-i2c",
107	.id		= 0,
108	.num_resources	= ARRAY_SIZE(jz4740_i2c_resources),
109	.resource	= jz4740_i2c_resources,
110};
111
112/* NAND controller */
113static struct resource jz4740_nand_resources[] = {
114	{
115		.name	= "mmio",
116		.start	= JZ4740_EMC_BASE_ADDR,
117		.end	= JZ4740_EMC_BASE_ADDR + 0x1000 - 1,
118		.flags	= IORESOURCE_MEM,
119	},
120	{
121		.name	= "bank1",
122		.start	= 0x18000000,
123		.end	= 0x180C0000 - 1,
124		.flags = IORESOURCE_MEM,
125	},
126	{
127		.name	= "bank2",
128		.start	= 0x14000000,
129		.end	= 0x140C0000 - 1,
130		.flags = IORESOURCE_MEM,
131	},
132	{
133		.name	= "bank3",
134		.start	= 0x0C000000,
135		.end	= 0x0C0C0000 - 1,
136		.flags = IORESOURCE_MEM,
137	},
138	{
139		.name	= "bank4",
140		.start	= 0x08000000,
141		.end	= 0x080C0000 - 1,
142		.flags = IORESOURCE_MEM,
143	},
144};
145
146struct platform_device jz4740_nand_device = {
147	.name = "jz4740-nand",
148	.num_resources = ARRAY_SIZE(jz4740_nand_resources),
149	.resource = jz4740_nand_resources,
150};
151
152/* LCD controller */
153static struct resource jz4740_framebuffer_resources[] = {
154	{
155		.start	= JZ4740_LCD_BASE_ADDR,
156		.end	= JZ4740_LCD_BASE_ADDR + 0x1000 - 1,
157		.flags	= IORESOURCE_MEM,
158	},
159};
160
161struct platform_device jz4740_framebuffer_device = {
162	.name		= "jz4740-fb",
163	.id		= -1,
164	.num_resources	= ARRAY_SIZE(jz4740_framebuffer_resources),
165	.resource	= jz4740_framebuffer_resources,
166	.dev = {
167		.dma_mask = &jz4740_framebuffer_device.dev.coherent_dma_mask,
168		.coherent_dma_mask = DMA_BIT_MASK(32),
169	},
170};
171
172/* I2S controller */
173static struct resource jz4740_i2s_resources[] = {
174	{
175		.start	= JZ4740_AIC_BASE_ADDR,
176		.end	= JZ4740_AIC_BASE_ADDR + 0x38 - 1,
177		.flags	= IORESOURCE_MEM,
178	},
179};
180
181struct platform_device jz4740_i2s_device = {
182	.name		= "jz4740-i2s",
183	.id		= -1,
184	.num_resources	= ARRAY_SIZE(jz4740_i2s_resources),
185	.resource	= jz4740_i2s_resources,
186};
187
188/* PCM */
189struct platform_device jz4740_pcm_device = {
190	.name		= "jz4740-pcm-audio",
191	.id		= -1,
192};
193
194/* Codec */
195static struct resource jz4740_codec_resources[] = {
196	{
197		.start	= JZ4740_AIC_BASE_ADDR + 0x80,
198		.end	= JZ4740_AIC_BASE_ADDR + 0x88 - 1,
199		.flags	= IORESOURCE_MEM,
200	},
201};
202
203struct platform_device jz4740_codec_device = {
204	.name		= "jz4740-codec",
205	.id		= -1,
206	.num_resources	= ARRAY_SIZE(jz4740_codec_resources),
207	.resource	= jz4740_codec_resources,
208};
209
210/* ADC controller */
211static struct resource jz4740_adc_resources[] = {
212	{
213		.start	= JZ4740_SADC_BASE_ADDR,
214		.end	= JZ4740_SADC_BASE_ADDR + 0x30,
215		.flags	= IORESOURCE_MEM,
216	},
217	{
218		.start	= JZ4740_IRQ_SADC,
219		.end	= JZ4740_IRQ_SADC,
220		.flags	= IORESOURCE_IRQ,
221	},
222	{
223		.start	= JZ4740_IRQ_ADC_BASE,
224		.end	= JZ4740_IRQ_ADC_BASE,
225		.flags	= IORESOURCE_IRQ,
226	},
227};
228
229struct platform_device jz4740_adc_device = {
230	.name		= "jz4740-adc",
231	.id		= -1,
232	.num_resources	= ARRAY_SIZE(jz4740_adc_resources),
233	.resource	= jz4740_adc_resources,
234};
235
236/* Watchdog */
237static struct resource jz4740_wdt_resources[] = {
238	{
239		.start = JZ4740_WDT_BASE_ADDR,
240		.end   = JZ4740_WDT_BASE_ADDR + 0x10 - 1,
241		.flags = IORESOURCE_MEM,
242	},
243};
244
245struct platform_device jz4740_wdt_device = {
246	.name	       = "jz4740-wdt",
247	.id	       = -1,
248	.num_resources = ARRAY_SIZE(jz4740_wdt_resources),
249	.resource      = jz4740_wdt_resources,
250};
251
252/* PWM */
253struct platform_device jz4740_pwm_device = {
254	.name = "jz4740-pwm",
255	.id   = -1,
256};
257
258/* DMA */
259static struct resource jz4740_dma_resources[] = {
260	{
261		.start	= JZ4740_DMAC_BASE_ADDR,
262		.end	= JZ4740_DMAC_BASE_ADDR + 0x400 - 1,
263		.flags	= IORESOURCE_MEM,
264	},
265	{
266		.start	= JZ4740_IRQ_DMAC,
267		.end	= JZ4740_IRQ_DMAC,
268		.flags	= IORESOURCE_IRQ,
269	},
270};
271
272struct platform_device jz4740_dma_device = {
273	.name		= "jz4740-dma",
274	.id		= -1,
275	.num_resources	= ARRAY_SIZE(jz4740_dma_resources),
276	.resource	= jz4740_dma_resources,
277};