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1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2//
3// Device Tree Source for UniPhier sLD8 SoC
4//
5// Copyright (C) 2015-2016 Socionext Inc.
6// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7
8#include <dt-bindings/gpio/uniphier-gpio.h>
9
10/ {
11 compatible = "socionext,uniphier-sld8";
12 #address-cells = <1>;
13 #size-cells = <1>;
14
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 cpu@0 {
20 device_type = "cpu";
21 compatible = "arm,cortex-a9";
22 reg = <0>;
23 enable-method = "psci";
24 next-level-cache = <&l2>;
25 };
26 };
27
28 psci {
29 compatible = "arm,psci-0.2";
30 method = "smc";
31 };
32
33 clocks {
34 refclk: ref {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <25000000>;
38 };
39
40 arm_timer_clk: arm-timer {
41 #clock-cells = <0>;
42 compatible = "fixed-clock";
43 clock-frequency = <50000000>;
44 };
45 };
46
47 soc {
48 compatible = "simple-bus";
49 #address-cells = <1>;
50 #size-cells = <1>;
51 ranges;
52 interrupt-parent = <&intc>;
53
54 l2: l2-cache@500c0000 {
55 compatible = "socionext,uniphier-system-cache";
56 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
57 <0x506c0000 0x400>;
58 interrupts = <0 174 4>, <0 175 4>;
59 cache-unified;
60 cache-size = <(256 * 1024)>;
61 cache-sets = <256>;
62 cache-line-size = <128>;
63 cache-level = <2>;
64 };
65
66 serial0: serial@54006800 {
67 compatible = "socionext,uniphier-uart";
68 status = "disabled";
69 reg = <0x54006800 0x40>;
70 interrupts = <0 33 4>;
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_uart0>;
73 clocks = <&peri_clk 0>;
74 resets = <&peri_rst 0>;
75 };
76
77 serial1: serial@54006900 {
78 compatible = "socionext,uniphier-uart";
79 status = "disabled";
80 reg = <0x54006900 0x40>;
81 interrupts = <0 35 4>;
82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_uart1>;
84 clocks = <&peri_clk 1>;
85 resets = <&peri_rst 1>;
86 };
87
88 serial2: serial@54006a00 {
89 compatible = "socionext,uniphier-uart";
90 status = "disabled";
91 reg = <0x54006a00 0x40>;
92 interrupts = <0 37 4>;
93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_uart2>;
95 clocks = <&peri_clk 2>;
96 resets = <&peri_rst 2>;
97 };
98
99 serial3: serial@54006b00 {
100 compatible = "socionext,uniphier-uart";
101 status = "disabled";
102 reg = <0x54006b00 0x40>;
103 interrupts = <0 29 4>;
104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_uart3>;
106 clocks = <&peri_clk 3>;
107 resets = <&peri_rst 3>;
108 };
109
110 gpio: gpio@55000000 {
111 compatible = "socionext,uniphier-gpio";
112 reg = <0x55000000 0x200>;
113 interrupt-parent = <&aidet>;
114 interrupt-controller;
115 #interrupt-cells = <2>;
116 gpio-controller;
117 #gpio-cells = <2>;
118 gpio-ranges = <&pinctrl 0 0 0>,
119 <&pinctrl 104 0 0>,
120 <&pinctrl 112 0 0>;
121 gpio-ranges-group-names = "gpio_range0",
122 "gpio_range1",
123 "gpio_range2";
124 ngpios = <136>;
125 socionext,interrupt-ranges = <0 48 13>, <14 62 2>;
126 };
127
128 i2c0: i2c@58400000 {
129 compatible = "socionext,uniphier-i2c";
130 status = "disabled";
131 reg = <0x58400000 0x40>;
132 #address-cells = <1>;
133 #size-cells = <0>;
134 interrupts = <0 41 1>;
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_i2c0>;
137 clocks = <&peri_clk 4>;
138 resets = <&peri_rst 4>;
139 clock-frequency = <100000>;
140 };
141
142 i2c1: i2c@58480000 {
143 compatible = "socionext,uniphier-i2c";
144 status = "disabled";
145 reg = <0x58480000 0x40>;
146 #address-cells = <1>;
147 #size-cells = <0>;
148 interrupts = <0 42 1>;
149 pinctrl-names = "default";
150 pinctrl-0 = <&pinctrl_i2c1>;
151 clocks = <&peri_clk 5>;
152 resets = <&peri_rst 5>;
153 clock-frequency = <100000>;
154 };
155
156 /* chip-internal connection for DMD */
157 i2c2: i2c@58500000 {
158 compatible = "socionext,uniphier-i2c";
159 reg = <0x58500000 0x40>;
160 #address-cells = <1>;
161 #size-cells = <0>;
162 interrupts = <0 43 1>;
163 pinctrl-names = "default";
164 pinctrl-0 = <&pinctrl_i2c2>;
165 clocks = <&peri_clk 6>;
166 resets = <&peri_rst 6>;
167 clock-frequency = <400000>;
168 };
169
170 i2c3: i2c@58580000 {
171 compatible = "socionext,uniphier-i2c";
172 status = "disabled";
173 reg = <0x58580000 0x40>;
174 #address-cells = <1>;
175 #size-cells = <0>;
176 interrupts = <0 44 1>;
177 pinctrl-names = "default";
178 pinctrl-0 = <&pinctrl_i2c3>;
179 clocks = <&peri_clk 7>;
180 resets = <&peri_rst 7>;
181 clock-frequency = <100000>;
182 };
183
184 system_bus: system-bus@58c00000 {
185 compatible = "socionext,uniphier-system-bus";
186 status = "disabled";
187 reg = <0x58c00000 0x400>;
188 #address-cells = <2>;
189 #size-cells = <1>;
190 pinctrl-names = "default";
191 pinctrl-0 = <&pinctrl_system_bus>;
192 };
193
194 smpctrl@59801000 {
195 compatible = "socionext,uniphier-smpctrl";
196 reg = <0x59801000 0x400>;
197 };
198
199 mioctrl@59810000 {
200 compatible = "socionext,uniphier-sld8-mioctrl",
201 "simple-mfd", "syscon";
202 reg = <0x59810000 0x800>;
203
204 mio_clk: clock {
205 compatible = "socionext,uniphier-sld8-mio-clock";
206 #clock-cells = <1>;
207 };
208
209 mio_rst: reset {
210 compatible = "socionext,uniphier-sld8-mio-reset";
211 #reset-cells = <1>;
212 };
213 };
214
215 perictrl@59820000 {
216 compatible = "socionext,uniphier-sld8-perictrl",
217 "simple-mfd", "syscon";
218 reg = <0x59820000 0x200>;
219
220 peri_clk: clock {
221 compatible = "socionext,uniphier-sld8-peri-clock";
222 #clock-cells = <1>;
223 };
224
225 peri_rst: reset {
226 compatible = "socionext,uniphier-sld8-peri-reset";
227 #reset-cells = <1>;
228 };
229 };
230
231 usb0: usb@5a800100 {
232 compatible = "socionext,uniphier-ehci", "generic-ehci";
233 status = "disabled";
234 reg = <0x5a800100 0x100>;
235 interrupts = <0 80 4>;
236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_usb0>;
238 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
239 <&mio_clk 12>;
240 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
241 <&mio_rst 12>;
242 has-transaction-translator;
243 };
244
245 usb1: usb@5a810100 {
246 compatible = "socionext,uniphier-ehci", "generic-ehci";
247 status = "disabled";
248 reg = <0x5a810100 0x100>;
249 interrupts = <0 81 4>;
250 pinctrl-names = "default";
251 pinctrl-0 = <&pinctrl_usb1>;
252 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
253 <&mio_clk 13>;
254 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
255 <&mio_rst 13>;
256 has-transaction-translator;
257 };
258
259 usb2: usb@5a820100 {
260 compatible = "socionext,uniphier-ehci", "generic-ehci";
261 status = "disabled";
262 reg = <0x5a820100 0x100>;
263 interrupts = <0 82 4>;
264 pinctrl-names = "default";
265 pinctrl-0 = <&pinctrl_usb2>;
266 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
267 <&mio_clk 14>;
268 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
269 <&mio_rst 14>;
270 has-transaction-translator;
271 };
272
273 soc-glue@5f800000 {
274 compatible = "socionext,uniphier-sld8-soc-glue",
275 "simple-mfd", "syscon";
276 reg = <0x5f800000 0x2000>;
277
278 pinctrl: pinctrl {
279 compatible = "socionext,uniphier-sld8-pinctrl";
280 };
281 };
282
283 soc-glue@5f900000 {
284 compatible = "socionext,uniphier-sld8-soc-glue-debug",
285 "simple-mfd";
286 #address-cells = <1>;
287 #size-cells = <1>;
288 ranges = <0 0x5f900000 0x2000>;
289
290 efuse@100 {
291 compatible = "socionext,uniphier-efuse";
292 reg = <0x100 0x28>;
293 };
294
295 efuse@200 {
296 compatible = "socionext,uniphier-efuse";
297 reg = <0x200 0x14>;
298 };
299 };
300
301 timer@60000200 {
302 compatible = "arm,cortex-a9-global-timer";
303 reg = <0x60000200 0x20>;
304 interrupts = <1 11 0x104>;
305 clocks = <&arm_timer_clk>;
306 };
307
308 timer@60000600 {
309 compatible = "arm,cortex-a9-twd-timer";
310 reg = <0x60000600 0x20>;
311 interrupts = <1 13 0x104>;
312 clocks = <&arm_timer_clk>;
313 };
314
315 intc: interrupt-controller@60001000 {
316 compatible = "arm,cortex-a9-gic";
317 reg = <0x60001000 0x1000>,
318 <0x60000100 0x100>;
319 #interrupt-cells = <3>;
320 interrupt-controller;
321 };
322
323 aidet: aidet@61830000 {
324 compatible = "socionext,uniphier-sld8-aidet";
325 reg = <0x61830000 0x200>;
326 interrupt-controller;
327 #interrupt-cells = <2>;
328 };
329
330 sysctrl@61840000 {
331 compatible = "socionext,uniphier-sld8-sysctrl",
332 "simple-mfd", "syscon";
333 reg = <0x61840000 0x10000>;
334
335 sys_clk: clock {
336 compatible = "socionext,uniphier-sld8-clock";
337 #clock-cells = <1>;
338 };
339
340 sys_rst: reset {
341 compatible = "socionext,uniphier-sld8-reset";
342 #reset-cells = <1>;
343 };
344 };
345
346 nand: nand@68000000 {
347 compatible = "socionext,uniphier-denali-nand-v5a";
348 status = "disabled";
349 reg-names = "nand_data", "denali_reg";
350 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
351 interrupts = <0 65 4>;
352 pinctrl-names = "default";
353 pinctrl-0 = <&pinctrl_nand2cs>;
354 clocks = <&sys_clk 2>;
355 resets = <&sys_rst 2>;
356 };
357 };
358};
359
360#include "uniphier-pinctrl.dtsi"