1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
  2/*
  3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
  4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
  5 */
  6#include <dt-bindings/interrupt-controller/arm-gic.h>
  7
  8/ {
  9	#address-cells = <1>;
 10	#size-cells = <1>;
 11
 12	cpus {
 13		#address-cells = <1>;
 14		#size-cells = <0>;
 15
 16		cpu0: cpu@0 {
 17			compatible = "arm,cortex-a7";
 18			device_type = "cpu";
 19			reg = <0>;
 20		};
 21
 22		cpu1: cpu@1 {
 23			compatible = "arm,cortex-a7";
 24			device_type = "cpu";
 25			reg = <1>;
 26		};
 27	};
 28
 29	psci {
 30		compatible = "arm,psci";
 31		method = "smc";
 32		cpu_off = <0x84000002>;
 33		cpu_on = <0x84000003>;
 34	};
 35
 36	aliases {
 37		gpio0 = &gpioa;
 38		gpio1 = &gpiob;
 39		gpio2 = &gpioc;
 40		gpio3 = &gpiod;
 41		gpio4 = &gpioe;
 42		gpio5 = &gpiof;
 43		gpio6 = &gpiog;
 44		gpio7 = &gpioh;
 45		gpio8 = &gpioi;
 46		gpio9 = &gpioj;
 47		gpio10 = &gpiok;
 48	};
 49
 50	intc: interrupt-controller@a0021000 {
 51		compatible = "arm,cortex-a7-gic";
 52		#interrupt-cells = <3>;
 53		interrupt-controller;
 54		reg = <0xa0021000 0x1000>,
 55		      <0xa0022000 0x2000>;
 56	};
 57
 58	timer {
 59		compatible = "arm,armv7-timer";
 60		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 61			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 62			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 63			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 64		interrupt-parent = <&intc>;
 65	};
 66
 67	clocks {
 68		clk_hse: clk-hse {
 69			#clock-cells = <0>;
 70			compatible = "fixed-clock";
 71			clock-frequency = <24000000>;
 72		};
 73
 74		clk_pll_per: clk-pll-per {
 75			#clock-cells = <0>;
 76			compatible = "fixed-clock";
 77			clock-frequency = <64000000>;
 78		};
 79
 80		clk_hsi: clk-hsi {
 81			#clock-cells = <0>;
 82			compatible = "fixed-clock";
 83			clock-frequency = <64000000>;
 84		};
 85
 86		clk_lse: clk-lse {
 87			#clock-cells = <0>;
 88			compatible = "fixed-clock";
 89			clock-frequency = <32768>;
 90		};
 91
 92		clk_lsi: clk-lsi {
 93			#clock-cells = <0>;
 94			compatible = "fixed-clock";
 95			clock-frequency = <32000>;
 96		};
 97
 98		clk_csi: clk-csi {
 99			#clock-cells = <0>;
100			compatible = "fixed-clock";
101			clock-frequency = <4000000>;
102		};
103
104		clk_pclk1: clk-pclk1 {
105			#clock-cells = <0>;
106			compatible = "fixed-clock";
107			clock-frequency = <86000000>;
108		};
109
110		clk_pll3_p: clk-pll3_p {
111			#clock-cells = <0>;
112			compatible = "fixed-clock";
113			clock-frequency = <172000000>;
114		};
115
116		clk_pll2_p: clk-pll2_p {
117			#clock-cells = <0>;
118			compatible = "fixed-clock";
119			clock-frequency = <264000000>;
120		};
121	};
122
123	soc {
124		compatible = "simple-bus";
125		#address-cells = <1>;
126		#size-cells = <1>;
127		interrupt-parent = <&intc>;
128		ranges;
129
130		usart2: serial@4000e000 {
131			compatible = "st,stm32h7-uart";
132			reg = <0x4000e000 0x400>;
133			interrupts = <GIC_SPI 38 IRQ_TYPE_NONE>;
134			clocks = <&clk_pclk1>;
135			status = "disabled";
136		};
137
138		usart3: serial@4000f000 {
139			compatible = "st,stm32h7-uart";
140			reg = <0x4000f000 0x400>;
141			interrupts = <GIC_SPI 39 IRQ_TYPE_NONE>;
142			clocks = <&clk_pclk1>;
143			status = "disabled";
144		};
145
146		uart4: serial@40010000 {
147			compatible = "st,stm32h7-uart";
148			reg = <0x40010000 0x400>;
149			interrupts = <GIC_SPI 52 IRQ_TYPE_NONE>;
150			clocks = <&clk_pclk1>;
151			status = "disabled";
152		};
153
154		uart5: serial@40011000 {
155			compatible = "st,stm32h7-uart";
156			reg = <0x40011000 0x400>;
157			interrupts = <GIC_SPI 53 IRQ_TYPE_NONE>;
158			clocks = <&clk_pclk1>;
159			status = "disabled";
160		};
161
162		uart7: serial@40018000 {
163			compatible = "st,stm32h7-uart";
164			reg = <0x40018000 0x400>;
165			interrupts = <GIC_SPI 82 IRQ_TYPE_NONE>;
166			clocks = <&clk_pclk1>;
167			status = "disabled";
168		};
169
170		uart8: serial@40019000 {
171			compatible = "st,stm32h7-uart";
172			reg = <0x40019000 0x400>;
173			interrupts = <GIC_SPI 83 IRQ_TYPE_NONE>;
174			clocks = <&clk_pclk1>;
175			status = "disabled";
176		};
177
178		usart6: serial@44003000 {
179			compatible = "st,stm32h7-uart";
180			reg = <0x44003000 0x400>;
181			interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
182			clocks = <&clk_pclk1>;
183			status = "disabled";
184		};
185
186		usart1: serial@5c000000 {
187			compatible = "st,stm32h7-uart";
188			reg = <0x5c000000 0x400>;
189			interrupts = <GIC_SPI 37 IRQ_TYPE_NONE>;
190			clocks = <&clk_pclk1>;
191			status = "disabled";
192		};
193	};
194};