1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Samsung's S3C2416 SoC device tree source
  4 *
  5 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
  6 */
  7
  8#include <dt-bindings/clock/s3c2443.h>
  9#include "s3c24xx.dtsi"
 10#include "s3c2416-pinctrl.dtsi"
 11
 12/ {
 13	model = "Samsung S3C2416 SoC";
 14	compatible = "samsung,s3c2416";
 15
 16	aliases {
 17		serial3 = &uart_3;
 18	};
 19
 20	cpus {
 21		#address-cells = <1>;
 22		#size-cells = <0>;
 23
 24		cpu {
 25			compatible = "arm,arm926ej-s";
 26		};
 27	};
 28
 29	interrupt-controller@4a000000 {
 30		compatible = "samsung,s3c2416-irq";
 31	};
 32
 33	clocks: clock-controller@0x4c000000 {
 34		compatible = "samsung,s3c2416-clock";
 35		reg = <0x4c000000 0x40>;
 36		#clock-cells = <1>;
 37	};
 38
 39	pinctrl@56000000 {
 40		compatible = "samsung,s3c2416-pinctrl";
 41	};
 42
 43	timer@51000000 {
 44		clocks = <&clocks PCLK_PWM>;
 45		clock-names = "timers";
 46	};
 47
 48	uart_0: serial@50000000 {
 49		compatible = "samsung,s3c2440-uart";
 50		clock-names = "uart", "clk_uart_baud2",
 51				"clk_uart_baud3";
 52		clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
 53				<&clocks SCLK_UART>;
 54	};
 55
 56	uart_1: serial@50004000 {
 57		compatible = "samsung,s3c2440-uart";
 58		clock-names = "uart", "clk_uart_baud2",
 59				"clk_uart_baud3";
 60		clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
 61				<&clocks SCLK_UART>;
 62	};
 63
 64	uart_2: serial@50008000 {
 65		compatible = "samsung,s3c2440-uart";
 66		clock-names = "uart", "clk_uart_baud2",
 67				"clk_uart_baud3";
 68		clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
 69				<&clocks SCLK_UART>;
 70	};
 71
 72	uart_3: serial@5000C000 {
 73		compatible = "samsung,s3c2440-uart";
 74		reg = <0x5000C000 0x4000>;
 75		interrupts = <1 18 24 4>, <1 18 25 4>;
 76		clock-names = "uart", "clk_uart_baud2",
 77				"clk_uart_baud3";
 78		clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>,
 79				<&clocks SCLK_UART>;
 80		status = "disabled";
 81	};
 82
 83	sdhci_1: sdhci@4AC00000 {
 84		compatible = "samsung,s3c6410-sdhci";
 85		reg = <0x4AC00000 0x100>;
 86		interrupts = <0 0 21 3>;
 87		clock-names = "hsmmc", "mmc_busclk.0",
 88				"mmc_busclk.2";
 89		clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
 90				<&clocks MUX_HSMMC0>;
 91		status = "disabled";
 92	};
 93
 94	sdhci_0: sdhci@4A800000 {
 95		compatible = "samsung,s3c6410-sdhci";
 96		reg = <0x4A800000 0x100>;
 97		interrupts = <0 0 20 3>;
 98		clock-names = "hsmmc", "mmc_busclk.0",
 99				"mmc_busclk.2";
100		clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
101				<&clocks MUX_HSMMC1>;
102		status = "disabled";
103	};
104
105	watchdog: watchdog@53000000 {
106		interrupts = <1 9 27 3>;
107		clocks = <&clocks PCLK_WDT>;
108		clock-names = "watchdog";
109	};
110
111	rtc: rtc@57000000 {
112		compatible = "samsung,s3c2416-rtc";
113		clocks = <&clocks PCLK_RTC>;
114		clock-names = "rtc";
115	};
116
117	i2c@54000000 {
118		compatible = "samsung,s3c2440-i2c";
119		clocks = <&clocks PCLK_I2C0>;
120		clock-names = "i2c";
121	};
122};