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1/*
2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14/dts-v1/;
15
16#include "skeleton.dtsi"
17#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
18#include <dt-bindings/interrupt-controller/arm-gic.h>
19#include <dt-bindings/interrupt-controller/irq.h>
20
21/ {
22 model = "Qualcomm Technologies, Inc. IPQ4019";
23 compatible = "qcom,ipq4019";
24 interrupt-parent = <&intc>;
25
26 aliases {
27 spi0 = &spi_0;
28 i2c0 = &i2c_0;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34 cpu@0 {
35 device_type = "cpu";
36 compatible = "arm,cortex-a7";
37 enable-method = "qcom,kpss-acc-v1";
38 qcom,acc = <&acc0>;
39 qcom,saw = <&saw0>;
40 reg = <0x0>;
41 clocks = <&gcc GCC_APPS_CLK_SRC>;
42 clock-frequency = <0>;
43 operating-points = <
44 /* kHz uV (fixed) */
45 48000 1100000
46 200000 1100000
47 500000 1100000
48 666000 1100000
49 >;
50 clock-latency = <256000>;
51 };
52
53 cpu@1 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a7";
56 enable-method = "qcom,kpss-acc-v1";
57 qcom,acc = <&acc1>;
58 qcom,saw = <&saw1>;
59 reg = <0x1>;
60 clocks = <&gcc GCC_APPS_CLK_SRC>;
61 clock-frequency = <0>;
62 };
63
64 cpu@2 {
65 device_type = "cpu";
66 compatible = "arm,cortex-a7";
67 enable-method = "qcom,kpss-acc-v1";
68 qcom,acc = <&acc2>;
69 qcom,saw = <&saw2>;
70 reg = <0x2>;
71 clocks = <&gcc GCC_APPS_CLK_SRC>;
72 clock-frequency = <0>;
73 };
74
75 cpu@3 {
76 device_type = "cpu";
77 compatible = "arm,cortex-a7";
78 enable-method = "qcom,kpss-acc-v1";
79 qcom,acc = <&acc3>;
80 qcom,saw = <&saw3>;
81 reg = <0x3>;
82 clocks = <&gcc GCC_APPS_CLK_SRC>;
83 clock-frequency = <0>;
84 };
85 };
86
87 pmu {
88 compatible = "arm,cortex-a7-pmu";
89 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
90 IRQ_TYPE_LEVEL_HIGH)>;
91 };
92
93 clocks {
94 sleep_clk: sleep_clk {
95 compatible = "fixed-clock";
96 clock-frequency = <32768>;
97 #clock-cells = <0>;
98 };
99
100 xo: xo {
101 compatible = "fixed-clock";
102 clock-frequency = <48000000>;
103 #clock-cells = <0>;
104 };
105 };
106
107 timer {
108 compatible = "arm,armv7-timer";
109 interrupts = <1 2 0xf08>,
110 <1 3 0xf08>,
111 <1 4 0xf08>,
112 <1 1 0xf08>;
113 clock-frequency = <48000000>;
114 };
115
116 soc {
117 #address-cells = <1>;
118 #size-cells = <1>;
119 ranges;
120 compatible = "simple-bus";
121
122 intc: interrupt-controller@b000000 {
123 compatible = "qcom,msm-qgic2";
124 interrupt-controller;
125 #interrupt-cells = <3>;
126 reg = <0x0b000000 0x1000>,
127 <0x0b002000 0x1000>;
128 };
129
130 gcc: clock-controller@1800000 {
131 compatible = "qcom,gcc-ipq4019";
132 #clock-cells = <1>;
133 #reset-cells = <1>;
134 reg = <0x1800000 0x60000>;
135 };
136
137 rng@22000 {
138 compatible = "qcom,prng";
139 reg = <0x22000 0x140>;
140 clocks = <&gcc GCC_PRNG_AHB_CLK>;
141 clock-names = "core";
142 status = "disabled";
143 };
144
145 tlmm: pinctrl@1000000 {
146 compatible = "qcom,ipq4019-pinctrl";
147 reg = <0x01000000 0x300000>;
148 gpio-controller;
149 #gpio-cells = <2>;
150 interrupt-controller;
151 #interrupt-cells = <2>;
152 interrupts = <0 208 0>;
153 };
154
155 blsp_dma: dma@7884000 {
156 compatible = "qcom,bam-v1.7.0";
157 reg = <0x07884000 0x23000>;
158 interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
159 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
160 clock-names = "bam_clk";
161 #dma-cells = <1>;
162 qcom,ee = <0>;
163 status = "disabled";
164 };
165
166 spi_0: spi@78b5000 {
167 compatible = "qcom,spi-qup-v2.2.1";
168 reg = <0x78b5000 0x600>;
169 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
170 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
171 <&gcc GCC_BLSP1_AHB_CLK>;
172 clock-names = "core", "iface";
173 #address-cells = <1>;
174 #size-cells = <0>;
175 status = "disabled";
176 };
177
178 i2c_0: i2c@78b7000 {
179 compatible = "qcom,i2c-qup-v2.2.1";
180 reg = <0x78b7000 0x600>;
181 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
182 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
183 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
184 clock-names = "iface", "core";
185 #address-cells = <1>;
186 #size-cells = <0>;
187 status = "disabled";
188 };
189
190
191 cryptobam: dma@8e04000 {
192 compatible = "qcom,bam-v1.7.0";
193 reg = <0x08e04000 0x20000>;
194 interrupts = <GIC_SPI 207 0>;
195 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
196 clock-names = "bam_clk";
197 #dma-cells = <1>;
198 qcom,ee = <1>;
199 qcom,controlled-remotely;
200 status = "disabled";
201 };
202
203 crypto@8e3a000 {
204 compatible = "qcom,crypto-v5.1";
205 reg = <0x08e3a000 0x6000>;
206 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
207 <&gcc GCC_CRYPTO_AXI_CLK>,
208 <&gcc GCC_CRYPTO_CLK>;
209 clock-names = "iface", "bus", "core";
210 dmas = <&cryptobam 2>, <&cryptobam 3>;
211 dma-names = "rx", "tx";
212 status = "disabled";
213 };
214
215 acc0: clock-controller@b088000 {
216 compatible = "qcom,kpss-acc-v1";
217 reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
218 };
219
220 acc1: clock-controller@b098000 {
221 compatible = "qcom,kpss-acc-v1";
222 reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
223 };
224
225 acc2: clock-controller@b0a8000 {
226 compatible = "qcom,kpss-acc-v1";
227 reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
228 };
229
230 acc3: clock-controller@b0b8000 {
231 compatible = "qcom,kpss-acc-v1";
232 reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
233 };
234
235 saw0: regulator@b089000 {
236 compatible = "qcom,saw2";
237 reg = <0x02089000 0x1000>, <0x0b009000 0x1000>;
238 regulator;
239 };
240
241 saw1: regulator@b099000 {
242 compatible = "qcom,saw2";
243 reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
244 regulator;
245 };
246
247 saw2: regulator@b0a9000 {
248 compatible = "qcom,saw2";
249 reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
250 regulator;
251 };
252
253 saw3: regulator@b0b9000 {
254 compatible = "qcom,saw2";
255 reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
256 regulator;
257 };
258
259 serial@78af000 {
260 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
261 reg = <0x78af000 0x200>;
262 interrupts = <0 107 0>;
263 status = "disabled";
264 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
265 <&gcc GCC_BLSP1_AHB_CLK>;
266 clock-names = "core", "iface";
267 dmas = <&blsp_dma 1>, <&blsp_dma 0>;
268 dma-names = "rx", "tx";
269 };
270
271 serial@78b0000 {
272 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
273 reg = <0x78b0000 0x200>;
274 interrupts = <0 108 0>;
275 status = "disabled";
276 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
277 <&gcc GCC_BLSP1_AHB_CLK>;
278 clock-names = "core", "iface";
279 dmas = <&blsp_dma 3>, <&blsp_dma 2>;
280 dma-names = "rx", "tx";
281 };
282
283 watchdog@b017000 {
284 compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019";
285 reg = <0xb017000 0x40>;
286 clocks = <&sleep_clk>;
287 timeout-sec = <10>;
288 status = "disabled";
289 };
290
291 restart@4ab000 {
292 compatible = "qcom,pshold";
293 reg = <0x4ab000 0x4>;
294 };
295
296 wifi0: wifi@a000000 {
297 compatible = "qcom,ipq4019-wifi";
298 reg = <0xa000000 0x200000>;
299 resets = <&gcc WIFI0_CPU_INIT_RESET>,
300 <&gcc WIFI0_RADIO_SRIF_RESET>,
301 <&gcc WIFI0_RADIO_WARM_RESET>,
302 <&gcc WIFI0_RADIO_COLD_RESET>,
303 <&gcc WIFI0_CORE_WARM_RESET>,
304 <&gcc WIFI0_CORE_COLD_RESET>;
305 reset-names = "wifi_cpu_init", "wifi_radio_srif",
306 "wifi_radio_warm", "wifi_radio_cold",
307 "wifi_core_warm", "wifi_core_cold";
308 clocks = <&gcc GCC_WCSS2G_CLK>,
309 <&gcc GCC_WCSS2G_REF_CLK>,
310 <&gcc GCC_WCSS2G_RTC_CLK>;
311 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
312 "wifi_wcss_rtc";
313 interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
314 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
315 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
316 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
317 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
318 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
319 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
320 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
321 <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
322 <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
323 <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
324 <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
325 <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
326 <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
327 <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
328 <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
329 <GIC_SPI 168 IRQ_TYPE_NONE>;
330 interrupt-names = "msi0", "msi1", "msi2", "msi3",
331 "msi4", "msi5", "msi6", "msi7",
332 "msi8", "msi9", "msi10", "msi11",
333 "msi12", "msi13", "msi14", "msi15",
334 "legacy";
335 status = "disabled";
336 };
337
338 wifi1: wifi@a800000 {
339 compatible = "qcom,ipq4019-wifi";
340 reg = <0xa800000 0x200000>;
341 resets = <&gcc WIFI1_CPU_INIT_RESET>,
342 <&gcc WIFI1_RADIO_SRIF_RESET>,
343 <&gcc WIFI1_RADIO_WARM_RESET>,
344 <&gcc WIFI1_RADIO_COLD_RESET>,
345 <&gcc WIFI1_CORE_WARM_RESET>,
346 <&gcc WIFI1_CORE_COLD_RESET>;
347 reset-names = "wifi_cpu_init", "wifi_radio_srif",
348 "wifi_radio_warm", "wifi_radio_cold",
349 "wifi_core_warm", "wifi_core_cold";
350 clocks = <&gcc GCC_WCSS5G_CLK>,
351 <&gcc GCC_WCSS5G_REF_CLK>,
352 <&gcc GCC_WCSS5G_RTC_CLK>;
353 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
354 "wifi_wcss_rtc";
355 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
356 <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
357 <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
358 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
359 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
360 <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
361 <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
362 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
363 <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>,
364 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
365 <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
366 <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
367 <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
368 <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
369 <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
370 <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
371 <GIC_SPI 169 IRQ_TYPE_NONE>;
372 interrupt-names = "msi0", "msi1", "msi2", "msi3",
373 "msi4", "msi5", "msi6", "msi7",
374 "msi8", "msi9", "msi10", "msi11",
375 "msi12", "msi13", "msi14", "msi15",
376 "legacy";
377 status = "disabled";
378 };
379 };
380};