1/*
  2 * Copyright 2013 Greg Ungerer <gerg@uclinux.org>
  3 * Copyright 2011 Freescale Semiconductor, Inc.
  4 * Copyright 2011 Linaro Ltd.
  5 *
  6 * The code contained herein is licensed under the GNU General Public
  7 * License. You may obtain a copy of the GNU General Public License
  8 * Version 2 or later at the following locations:
  9 *
 10 * http://www.opensource.org/licenses/gpl-license.html
 11 * http://www.gnu.org/copyleft/gpl.html
 12 */
 13
 14/dts-v1/;
 15#include "imx50.dtsi"
 16
 17/ {
 18	model = "Freescale i.MX50 Evaluation Kit";
 19	compatible = "fsl,imx50-evk", "fsl,imx50";
 20
 21	memory@70000000 {
 22		reg = <0x70000000 0x80000000>;
 23	};
 24};
 25
 26&cspi {
 27	pinctrl-names = "default";
 28	pinctrl-0 = <&pinctrl_cspi>;
 29	cs-gpios = <&gpio4 11 0>, <&gpio4 13 0>;
 30	status = "okay";
 31
 32	flash: m25p32@1 {
 33		#address-cells = <1>;
 34		#size-cells = <1>;
 35		compatible = "m25p32", "jedec,spi-nor";
 36		spi-max-frequency = <25000000>;
 37		reg = <1>;
 38
 39		partition@0 {
 40			label = "bootloader";
 41			reg = <0x0 0x100000>;
 42			read-only;
 43		};
 44
 45		partition@100000 {
 46			label = "kernel";
 47			reg = <0x100000 0x300000>;
 48		};
 49	};
 50};
 51
 52&fec {
 53	pinctrl-names = "default";
 54	pinctrl-0 = <&pinctrl_fec>;
 55	phy-mode = "rmii";
 56	phy-reset-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
 57	status = "okay";
 58};
 59
 60&iomuxc {
 61	imx50-evk {
 62		pinctrl_cspi: cspigrp {
 63			fsl,pins = <
 64				MX50_PAD_CSPI_SCLK__CSPI_SCLK		0x00
 65				MX50_PAD_CSPI_MISO__CSPI_MISO		0x00
 66				MX50_PAD_CSPI_MOSI__CSPI_MOSI		0x00
 67				MX50_PAD_CSPI_SS0__GPIO4_11		0xc4
 68				MX50_PAD_ECSPI1_MOSI__CSPI_SS1		0xf4
 69			>;
 70		};
 71
 72		pinctrl_fec: fecgrp {
 73			fsl,pins = <
 74				MX50_PAD_SSI_RXFS__FEC_MDC		0x80
 75				MX50_PAD_SSI_RXC__FEC_MDIO		0x80
 76				MX50_PAD_DISP_D0__FEC_TX_CLK		0x80
 77				MX50_PAD_DISP_D1__FEC_RX_ERR		0x80
 78				MX50_PAD_DISP_D2__FEC_RX_DV		0x80
 79				MX50_PAD_DISP_D3__FEC_RDATA_1		0x80
 80				MX50_PAD_DISP_D4__FEC_RDATA_0		0x80
 81				MX50_PAD_DISP_D5__FEC_TX_EN		0x80
 82				MX50_PAD_DISP_D6__FEC_TDATA_1		0x80
 83				MX50_PAD_DISP_D7__FEC_TDATA_0		0x80
 84			>;
 85		};
 86
 87		pinctrl_uart1: uart1grp {
 88			fsl,pins = <
 89				MX50_PAD_UART1_TXD__UART1_TXD_MUX	0x1e4
 90				MX50_PAD_UART1_RXD__UART1_RXD_MUX	0x1e4
 91				MX50_PAD_UART1_RTS__UART1_RTS		0x1e4
 92				MX50_PAD_UART1_CTS__UART1_CTS		0x1e4
 93			>;
 94		};
 95	};
 96};
 97
 98&uart1 {
 99	pinctrl-names = "default";
100	pinctrl-0 = <&pinctrl_uart1>;
101	status = "okay";
102};
103
104&usbh1 {
105	status = "okay";
106};
107
108&usbh2 {
109	status = "okay";
110};
111
112&usbh3 {
113	status = "okay";
114};
115
116&usbotg {
117	status = "okay";
118};