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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SAMSUNG EXYNOS5410 SoC device tree source
4 *
5 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 *
8 * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
9 * EXYNOS5410 based board files can include this file and provide
10 * values for board specfic bindings.
11 */
12
13#include "exynos54xx.dtsi"
14#include <dt-bindings/clock/exynos5410.h>
15#include <dt-bindings/clock/exynos-audss-clk.h>
16#include <dt-bindings/interrupt-controller/arm-gic.h>
17
18/ {
19 compatible = "samsung,exynos5410", "samsung,exynos5";
20 interrupt-parent = <&gic>;
21
22 aliases {
23 pinctrl0 = &pinctrl_0;
24 pinctrl1 = &pinctrl_1;
25 pinctrl2 = &pinctrl_2;
26 pinctrl3 = &pinctrl_3;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 cpu0: cpu@0 {
34 device_type = "cpu";
35 compatible = "arm,cortex-a15";
36 reg = <0x0>;
37 clock-frequency = <1600000000>;
38 };
39
40 cpu1: cpu@1 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a15";
43 reg = <0x1>;
44 clock-frequency = <1600000000>;
45 };
46
47 cpu2: cpu@2 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a15";
50 reg = <0x2>;
51 clock-frequency = <1600000000>;
52 };
53
54 cpu3: cpu@3 {
55 device_type = "cpu";
56 compatible = "arm,cortex-a15";
57 reg = <0x3>;
58 clock-frequency = <1600000000>;
59 };
60 };
61
62 soc: soc {
63 compatible = "simple-bus";
64 #address-cells = <1>;
65 #size-cells = <1>;
66 ranges;
67
68 pmu_system_controller: system-controller@10040000 {
69 compatible = "samsung,exynos5410-pmu", "syscon";
70 reg = <0x10040000 0x5000>;
71 clock-names = "clkout16";
72 clocks = <&fin_pll>;
73 #clock-cells = <1>;
74 };
75
76 clock: clock-controller@10010000 {
77 compatible = "samsung,exynos5410-clock";
78 reg = <0x10010000 0x30000>;
79 #clock-cells = <1>;
80 };
81
82 clock_audss: audss-clock-controller@3810000 {
83 compatible = "samsung,exynos5410-audss-clock";
84 reg = <0x03810000 0x0C>;
85 #clock-cells = <1>;
86 clocks = <&fin_pll>, <&clock CLK_FOUT_EPLL>;
87 clock-names = "pll_ref", "pll_in";
88 };
89
90 tmu_cpu0: tmu@10060000 {
91 compatible = "samsung,exynos5420-tmu";
92 reg = <0x10060000 0x100>;
93 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
94 clocks = <&clock CLK_TMU>;
95 clock-names = "tmu_apbif";
96 #include "exynos4412-tmu-sensor-conf.dtsi"
97 };
98
99 tmu_cpu1: tmu@10064000 {
100 compatible = "samsung,exynos5420-tmu";
101 reg = <0x10064000 0x100>;
102 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
103 clocks = <&clock CLK_TMU>;
104 clock-names = "tmu_apbif";
105 #include "exynos4412-tmu-sensor-conf.dtsi"
106 };
107
108 tmu_cpu2: tmu@10068000 {
109 compatible = "samsung,exynos5420-tmu";
110 reg = <0x10068000 0x100>;
111 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
112 clocks = <&clock CLK_TMU>;
113 clock-names = "tmu_apbif";
114 #include "exynos4412-tmu-sensor-conf.dtsi"
115 };
116
117 tmu_cpu3: tmu@1006c000 {
118 compatible = "samsung,exynos5420-tmu";
119 reg = <0x1006c000 0x100>;
120 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
121 clocks = <&clock CLK_TMU>;
122 clock-names = "tmu_apbif";
123 #include "exynos4412-tmu-sensor-conf.dtsi"
124 };
125
126 mmc_0: mmc@12200000 {
127 compatible = "samsung,exynos5250-dw-mshc";
128 reg = <0x12200000 0x1000>;
129 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
130 #address-cells = <1>;
131 #size-cells = <0>;
132 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
133 clock-names = "biu", "ciu";
134 fifo-depth = <0x80>;
135 status = "disabled";
136 };
137
138 mmc_1: mmc@12210000 {
139 compatible = "samsung,exynos5250-dw-mshc";
140 reg = <0x12210000 0x1000>;
141 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
142 #address-cells = <1>;
143 #size-cells = <0>;
144 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
145 clock-names = "biu", "ciu";
146 fifo-depth = <0x80>;
147 status = "disabled";
148 };
149
150 mmc_2: mmc@12220000 {
151 compatible = "samsung,exynos5250-dw-mshc";
152 reg = <0x12220000 0x1000>;
153 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
154 #address-cells = <1>;
155 #size-cells = <0>;
156 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
157 clock-names = "biu", "ciu";
158 fifo-depth = <0x80>;
159 status = "disabled";
160 };
161
162 pinctrl_0: pinctrl@13400000 {
163 compatible = "samsung,exynos5410-pinctrl";
164 reg = <0x13400000 0x1000>;
165 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
166
167 wakeup-interrupt-controller {
168 compatible = "samsung,exynos4210-wakeup-eint";
169 interrupt-parent = <&gic>;
170 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
171 };
172 };
173
174 pinctrl_1: pinctrl@14000000 {
175 compatible = "samsung,exynos5410-pinctrl";
176 reg = <0x14000000 0x1000>;
177 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
178 };
179
180 pinctrl_2: pinctrl@10d10000 {
181 compatible = "samsung,exynos5410-pinctrl";
182 reg = <0x10d10000 0x1000>;
183 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
184 };
185
186 pinctrl_3: pinctrl@3860000 {
187 compatible = "samsung,exynos5410-pinctrl";
188 reg = <0x03860000 0x1000>;
189 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
190 };
191
192 amba {
193 #address-cells = <1>;
194 #size-cells = <1>;
195 compatible = "simple-bus";
196 interrupt-parent = <&gic>;
197 ranges;
198
199 pdma0: pdma@121a0000 {
200 compatible = "arm,pl330", "arm,primecell";
201 reg = <0x121a0000 0x1000>;
202 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
203 clocks = <&clock CLK_PDMA0>;
204 clock-names = "apb_pclk";
205 #dma-cells = <1>;
206 #dma-channels = <8>;
207 #dma-requests = <32>;
208 };
209
210 pdma1: pdma@121b0000 {
211 compatible = "arm,pl330", "arm,primecell";
212 reg = <0x121b0000 0x1000>;
213 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&clock CLK_PDMA1>;
215 clock-names = "apb_pclk";
216 #dma-cells = <1>;
217 #dma-channels = <8>;
218 #dma-requests = <32>;
219 };
220 };
221
222 audi2s0: i2s@3830000 {
223 compatible = "samsung,exynos5420-i2s";
224 reg = <0x03830000 0x100>;
225 dmas = <&pdma0 10
226 &pdma0 9
227 &pdma0 8>;
228 dma-names = "tx", "rx", "tx-sec";
229 clocks = <&clock_audss EXYNOS_I2S_BUS>,
230 <&clock_audss EXYNOS_I2S_BUS>,
231 <&clock_audss EXYNOS_SCLK_I2S>;
232 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
233 #clock-cells = <1>;
234 clock-output-names = "i2s_cdclk0";
235 #sound-dai-cells = <1>;
236 samsung,idma-addr = <0x03000000>;
237 pinctrl-names = "default";
238 pinctrl-0 = <&audi2s0_bus>;
239 status = "disabled";
240 };
241 };
242
243 thermal-zones {
244 cpu0_thermal: cpu0-thermal {
245 thermal-sensors = <&tmu_cpu0>;
246 #include "exynos5420-trip-points.dtsi"
247 };
248 cpu1_thermal: cpu1-thermal {
249 thermal-sensors = <&tmu_cpu1>;
250 #include "exynos5420-trip-points.dtsi"
251 };
252 cpu2_thermal: cpu2-thermal {
253 thermal-sensors = <&tmu_cpu2>;
254 #include "exynos5420-trip-points.dtsi"
255 };
256 cpu3_thermal: cpu3-thermal {
257 thermal-sensors = <&tmu_cpu3>;
258 #include "exynos5420-trip-points.dtsi"
259 };
260 };
261};
262
263&arm_a15_pmu {
264 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
265 status = "okay";
266};
267
268&i2c_0 {
269 clocks = <&clock CLK_I2C0>;
270 clock-names = "i2c";
271 pinctrl-names = "default";
272 pinctrl-0 = <&i2c0_bus>;
273};
274
275&i2c_1 {
276 clocks = <&clock CLK_I2C1>;
277 clock-names = "i2c";
278 pinctrl-names = "default";
279 pinctrl-0 = <&i2c1_bus>;
280};
281
282&i2c_2 {
283 clocks = <&clock CLK_I2C2>;
284 clock-names = "i2c";
285 pinctrl-names = "default";
286 pinctrl-0 = <&i2c2_bus>;
287};
288
289&i2c_3 {
290 clocks = <&clock CLK_I2C3>;
291 clock-names = "i2c";
292 pinctrl-names = "default";
293 pinctrl-0 = <&i2c3_bus>;
294};
295
296&hsi2c_4 {
297 clocks = <&clock CLK_USI0>;
298 clock-names = "hsi2c";
299 pinctrl-names = "default";
300 pinctrl-0 = <&i2c4_hs_bus>;
301};
302
303&hsi2c_5 {
304 clocks = <&clock CLK_USI1>;
305 clock-names = "hsi2c";
306 pinctrl-names = "default";
307 pinctrl-0 = <&i2c5_hs_bus>;
308};
309
310&hsi2c_6 {
311 clocks = <&clock CLK_USI2>;
312 clock-names = "hsi2c";
313 pinctrl-names = "default";
314 pinctrl-0 = <&i2c6_hs_bus>;
315};
316
317&hsi2c_7 {
318 clocks = <&clock CLK_USI3>;
319 clock-names = "hsi2c";
320 pinctrl-names = "default";
321 pinctrl-0 = <&i2c7_hs_bus>;
322};
323
324&mct {
325 clocks = <&fin_pll>, <&clock CLK_MCT>;
326 clock-names = "fin_pll", "mct";
327};
328
329&prng {
330 clocks = <&clock CLK_SSS>;
331 clock-names = "secss";
332};
333
334&pwm {
335 clocks = <&clock CLK_PWM>;
336 clock-names = "timers";
337};
338
339&rtc {
340 clocks = <&clock CLK_RTC>;
341 clock-names = "rtc";
342 status = "disabled";
343};
344
345&serial_0 {
346 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
347 clock-names = "uart", "clk_uart_baud0";
348 dmas = <&pdma0 13>, <&pdma0 14>;
349 dma-names = "rx", "tx";
350};
351
352&serial_1 {
353 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
354 clock-names = "uart", "clk_uart_baud0";
355 dmas = <&pdma1 15>, <&pdma1 16>;
356 dma-names = "rx", "tx";
357};
358
359&serial_2 {
360 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
361 clock-names = "uart", "clk_uart_baud0";
362 dmas = <&pdma0 15>, <&pdma0 16>;
363 dma-names = "rx", "tx";
364};
365
366&serial_3 {
367 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
368 clock-names = "uart", "clk_uart_baud0";
369 dmas = <&pdma1 17>, <&pdma1 18>;
370 dma-names = "rx", "tx";
371};
372
373&sss {
374 clocks = <&clock CLK_SSS>;
375 clock-names = "secss";
376};
377
378&sromc {
379 #address-cells = <2>;
380 #size-cells = <1>;
381 ranges = <0 0 0x04000000 0x20000
382 1 0 0x05000000 0x20000
383 2 0 0x06000000 0x20000
384 3 0 0x07000000 0x20000>;
385};
386
387&trng {
388 clocks = <&clock CLK_SSS>;
389 clock-names = "secss";
390};
391
392&usbdrd3_0 {
393 clocks = <&clock CLK_USBD300>;
394 clock-names = "usbdrd30";
395};
396
397&usbdrd_phy0 {
398 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
399 clock-names = "phy", "ref";
400 samsung,pmu-syscon = <&pmu_system_controller>;
401};
402
403&usbdrd3_1 {
404 clocks = <&clock CLK_USBD301>;
405 clock-names = "usbdrd30";
406};
407
408&usbdrd_dwc3_1 {
409 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
410};
411
412&usbdrd_phy1 {
413 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
414 clock-names = "phy", "ref";
415 samsung,pmu-syscon = <&pmu_system_controller>;
416};
417
418&usbhost1 {
419 clocks = <&clock CLK_USBH20>;
420 clock-names = "usbhost";
421};
422
423&usbhost2 {
424 clocks = <&clock CLK_USBH20>;
425 clock-names = "usbhost";
426};
427
428&usb2_phy {
429 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
430 clock-names = "phy", "ref";
431 samsung,sysreg-phandle = <&sysreg_system_controller>;
432 samsung,pmureg-phandle = <&pmu_system_controller>;
433};
434
435&watchdog {
436 clocks = <&clock CLK_WDT>;
437 clock-names = "watchdog";
438 samsung,syscon-phandle = <&pmu_system_controller>;
439};
440
441#include "exynos5410-pinctrl.dtsi"