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1/*
2 * R-Car PWM Timer driver
3 *
4 * Copyright (C) 2015 Renesas Electronics Corporation
5 *
6 * This is free software; you can redistribute it and/or modify
7 * it under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/clk.h>
12#include <linux/err.h>
13#include <linux/io.h>
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/platform_device.h>
17#include <linux/pm_runtime.h>
18#include <linux/pwm.h>
19#include <linux/slab.h>
20
21#define RCAR_PWM_MAX_DIVISION 24
22#define RCAR_PWM_MAX_CYCLE 1023
23
24#define RCAR_PWMCR 0x00
25#define RCAR_PWMCR_CC0_MASK 0x000f0000
26#define RCAR_PWMCR_CC0_SHIFT 16
27#define RCAR_PWMCR_CCMD BIT(15)
28#define RCAR_PWMCR_SYNC BIT(11)
29#define RCAR_PWMCR_SS0 BIT(4)
30#define RCAR_PWMCR_EN0 BIT(0)
31
32#define RCAR_PWMCNT 0x04
33#define RCAR_PWMCNT_CYC0_MASK 0x03ff0000
34#define RCAR_PWMCNT_CYC0_SHIFT 16
35#define RCAR_PWMCNT_PH0_MASK 0x000003ff
36#define RCAR_PWMCNT_PH0_SHIFT 0
37
38struct rcar_pwm_chip {
39 struct pwm_chip chip;
40 void __iomem *base;
41 struct clk *clk;
42};
43
44static inline struct rcar_pwm_chip *to_rcar_pwm_chip(struct pwm_chip *chip)
45{
46 return container_of(chip, struct rcar_pwm_chip, chip);
47}
48
49static void rcar_pwm_write(struct rcar_pwm_chip *rp, u32 data,
50 unsigned int offset)
51{
52 writel(data, rp->base + offset);
53}
54
55static u32 rcar_pwm_read(struct rcar_pwm_chip *rp, unsigned int offset)
56{
57 return readl(rp->base + offset);
58}
59
60static void rcar_pwm_update(struct rcar_pwm_chip *rp, u32 mask, u32 data,
61 unsigned int offset)
62{
63 u32 value;
64
65 value = rcar_pwm_read(rp, offset);
66 value &= ~mask;
67 value |= data & mask;
68 rcar_pwm_write(rp, value, offset);
69}
70
71static int rcar_pwm_get_clock_division(struct rcar_pwm_chip *rp, int period_ns)
72{
73 unsigned long clk_rate = clk_get_rate(rp->clk);
74 unsigned long long max; /* max cycle / nanoseconds */
75 unsigned int div;
76
77 if (clk_rate == 0)
78 return -EINVAL;
79
80 for (div = 0; div <= RCAR_PWM_MAX_DIVISION; div++) {
81 max = (unsigned long long)NSEC_PER_SEC * RCAR_PWM_MAX_CYCLE *
82 (1 << div);
83 do_div(max, clk_rate);
84 if (period_ns <= max)
85 break;
86 }
87
88 return (div <= RCAR_PWM_MAX_DIVISION) ? div : -ERANGE;
89}
90
91static void rcar_pwm_set_clock_control(struct rcar_pwm_chip *rp,
92 unsigned int div)
93{
94 u32 value;
95
96 value = rcar_pwm_read(rp, RCAR_PWMCR);
97 value &= ~(RCAR_PWMCR_CCMD | RCAR_PWMCR_CC0_MASK);
98
99 if (div & 1)
100 value |= RCAR_PWMCR_CCMD;
101
102 div >>= 1;
103
104 value |= div << RCAR_PWMCR_CC0_SHIFT;
105 rcar_pwm_write(rp, value, RCAR_PWMCR);
106}
107
108static int rcar_pwm_set_counter(struct rcar_pwm_chip *rp, int div, int duty_ns,
109 int period_ns)
110{
111 unsigned long long one_cycle, tmp; /* 0.01 nanoseconds */
112 unsigned long clk_rate = clk_get_rate(rp->clk);
113 u32 cyc, ph;
114
115 one_cycle = (unsigned long long)NSEC_PER_SEC * 100ULL * (1 << div);
116 do_div(one_cycle, clk_rate);
117
118 tmp = period_ns * 100ULL;
119 do_div(tmp, one_cycle);
120 cyc = (tmp << RCAR_PWMCNT_CYC0_SHIFT) & RCAR_PWMCNT_CYC0_MASK;
121
122 tmp = duty_ns * 100ULL;
123 do_div(tmp, one_cycle);
124 ph = tmp & RCAR_PWMCNT_PH0_MASK;
125
126 /* Avoid prohibited setting */
127 if (cyc == 0 || ph == 0)
128 return -EINVAL;
129
130 rcar_pwm_write(rp, cyc | ph, RCAR_PWMCNT);
131
132 return 0;
133}
134
135static int rcar_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
136{
137 return pm_runtime_get_sync(chip->dev);
138}
139
140static void rcar_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
141{
142 pm_runtime_put(chip->dev);
143}
144
145static int rcar_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
146 int duty_ns, int period_ns)
147{
148 struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip);
149 int div, ret;
150
151 div = rcar_pwm_get_clock_division(rp, period_ns);
152 if (div < 0)
153 return div;
154
155 /*
156 * Let the core driver set pwm->period if disabled and duty_ns == 0.
157 * But, this driver should prevent to set the new duty_ns if current
158 * duty_cycle is not set
159 */
160 if (!pwm_is_enabled(pwm) && !duty_ns && !pwm->state.duty_cycle)
161 return 0;
162
163 rcar_pwm_update(rp, RCAR_PWMCR_SYNC, RCAR_PWMCR_SYNC, RCAR_PWMCR);
164
165 ret = rcar_pwm_set_counter(rp, div, duty_ns, period_ns);
166 if (!ret)
167 rcar_pwm_set_clock_control(rp, div);
168
169 /* The SYNC should be set to 0 even if rcar_pwm_set_counter failed */
170 rcar_pwm_update(rp, RCAR_PWMCR_SYNC, 0, RCAR_PWMCR);
171
172 return ret;
173}
174
175static int rcar_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
176{
177 struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip);
178 u32 value;
179
180 /* Don't enable the PWM device if CYC0 or PH0 is 0 */
181 value = rcar_pwm_read(rp, RCAR_PWMCNT);
182 if ((value & RCAR_PWMCNT_CYC0_MASK) == 0 ||
183 (value & RCAR_PWMCNT_PH0_MASK) == 0)
184 return -EINVAL;
185
186 rcar_pwm_update(rp, RCAR_PWMCR_EN0, RCAR_PWMCR_EN0, RCAR_PWMCR);
187
188 return 0;
189}
190
191static void rcar_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
192{
193 struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip);
194
195 rcar_pwm_update(rp, RCAR_PWMCR_EN0, 0, RCAR_PWMCR);
196}
197
198static const struct pwm_ops rcar_pwm_ops = {
199 .request = rcar_pwm_request,
200 .free = rcar_pwm_free,
201 .config = rcar_pwm_config,
202 .enable = rcar_pwm_enable,
203 .disable = rcar_pwm_disable,
204 .owner = THIS_MODULE,
205};
206
207static int rcar_pwm_probe(struct platform_device *pdev)
208{
209 struct rcar_pwm_chip *rcar_pwm;
210 struct resource *res;
211 int ret;
212
213 rcar_pwm = devm_kzalloc(&pdev->dev, sizeof(*rcar_pwm), GFP_KERNEL);
214 if (rcar_pwm == NULL)
215 return -ENOMEM;
216
217 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
218 rcar_pwm->base = devm_ioremap_resource(&pdev->dev, res);
219 if (IS_ERR(rcar_pwm->base))
220 return PTR_ERR(rcar_pwm->base);
221
222 rcar_pwm->clk = devm_clk_get(&pdev->dev, NULL);
223 if (IS_ERR(rcar_pwm->clk)) {
224 dev_err(&pdev->dev, "cannot get clock\n");
225 return PTR_ERR(rcar_pwm->clk);
226 }
227
228 platform_set_drvdata(pdev, rcar_pwm);
229
230 rcar_pwm->chip.dev = &pdev->dev;
231 rcar_pwm->chip.ops = &rcar_pwm_ops;
232 rcar_pwm->chip.base = -1;
233 rcar_pwm->chip.npwm = 1;
234
235 ret = pwmchip_add(&rcar_pwm->chip);
236 if (ret < 0) {
237 dev_err(&pdev->dev, "failed to register PWM chip: %d\n", ret);
238 return ret;
239 }
240
241 pm_runtime_enable(&pdev->dev);
242
243 return 0;
244}
245
246static int rcar_pwm_remove(struct platform_device *pdev)
247{
248 struct rcar_pwm_chip *rcar_pwm = platform_get_drvdata(pdev);
249
250 pm_runtime_disable(&pdev->dev);
251
252 return pwmchip_remove(&rcar_pwm->chip);
253}
254
255static const struct of_device_id rcar_pwm_of_table[] = {
256 { .compatible = "renesas,pwm-rcar", },
257 { },
258};
259MODULE_DEVICE_TABLE(of, rcar_pwm_of_table);
260
261#ifdef CONFIG_PM_SLEEP
262static struct pwm_device *rcar_pwm_dev_to_pwm_dev(struct device *dev)
263{
264 struct platform_device *pdev = to_platform_device(dev);
265 struct rcar_pwm_chip *rcar_pwm = platform_get_drvdata(pdev);
266 struct pwm_chip *chip = &rcar_pwm->chip;
267
268 return &chip->pwms[0];
269}
270
271static int rcar_pwm_suspend(struct device *dev)
272{
273 struct pwm_device *pwm = rcar_pwm_dev_to_pwm_dev(dev);
274
275 if (!test_bit(PWMF_REQUESTED, &pwm->flags))
276 return 0;
277
278 pm_runtime_put(dev);
279
280 return 0;
281}
282
283static int rcar_pwm_resume(struct device *dev)
284{
285 struct pwm_device *pwm = rcar_pwm_dev_to_pwm_dev(dev);
286
287 if (!test_bit(PWMF_REQUESTED, &pwm->flags))
288 return 0;
289
290 pm_runtime_get_sync(dev);
291
292 rcar_pwm_config(pwm->chip, pwm, pwm->state.duty_cycle,
293 pwm->state.period);
294 if (pwm_is_enabled(pwm))
295 rcar_pwm_enable(pwm->chip, pwm);
296
297 return 0;
298}
299#endif /* CONFIG_PM_SLEEP */
300static SIMPLE_DEV_PM_OPS(rcar_pwm_pm_ops, rcar_pwm_suspend, rcar_pwm_resume);
301
302static struct platform_driver rcar_pwm_driver = {
303 .probe = rcar_pwm_probe,
304 .remove = rcar_pwm_remove,
305 .driver = {
306 .name = "pwm-rcar",
307 .pm = &rcar_pwm_pm_ops,
308 .of_match_table = of_match_ptr(rcar_pwm_of_table),
309 }
310};
311module_platform_driver(rcar_pwm_driver);
312
313MODULE_AUTHOR("Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>");
314MODULE_DESCRIPTION("Renesas PWM Timer Driver");
315MODULE_LICENSE("GPL v2");
316MODULE_ALIAS("platform:pwm-rcar");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * R-Car PWM Timer driver
4 *
5 * Copyright (C) 2015 Renesas Electronics Corporation
6 *
7 * Limitations:
8 * - The hardware cannot generate a 0% duty cycle.
9 */
10
11#include <linux/clk.h>
12#include <linux/err.h>
13#include <linux/io.h>
14#include <linux/log2.h>
15#include <linux/math64.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/platform_device.h>
19#include <linux/pm_runtime.h>
20#include <linux/pwm.h>
21#include <linux/slab.h>
22
23#define RCAR_PWM_MAX_DIVISION 24
24#define RCAR_PWM_MAX_CYCLE 1023
25
26#define RCAR_PWMCR 0x00
27#define RCAR_PWMCR_CC0_MASK 0x000f0000
28#define RCAR_PWMCR_CC0_SHIFT 16
29#define RCAR_PWMCR_CCMD BIT(15)
30#define RCAR_PWMCR_SYNC BIT(11)
31#define RCAR_PWMCR_SS0 BIT(4)
32#define RCAR_PWMCR_EN0 BIT(0)
33
34#define RCAR_PWMCNT 0x04
35#define RCAR_PWMCNT_CYC0_MASK 0x03ff0000
36#define RCAR_PWMCNT_CYC0_SHIFT 16
37#define RCAR_PWMCNT_PH0_MASK 0x000003ff
38#define RCAR_PWMCNT_PH0_SHIFT 0
39
40struct rcar_pwm_chip {
41 struct pwm_chip chip;
42 void __iomem *base;
43 struct clk *clk;
44};
45
46static inline struct rcar_pwm_chip *to_rcar_pwm_chip(struct pwm_chip *chip)
47{
48 return container_of(chip, struct rcar_pwm_chip, chip);
49}
50
51static void rcar_pwm_write(struct rcar_pwm_chip *rp, u32 data,
52 unsigned int offset)
53{
54 writel(data, rp->base + offset);
55}
56
57static u32 rcar_pwm_read(struct rcar_pwm_chip *rp, unsigned int offset)
58{
59 return readl(rp->base + offset);
60}
61
62static void rcar_pwm_update(struct rcar_pwm_chip *rp, u32 mask, u32 data,
63 unsigned int offset)
64{
65 u32 value;
66
67 value = rcar_pwm_read(rp, offset);
68 value &= ~mask;
69 value |= data & mask;
70 rcar_pwm_write(rp, value, offset);
71}
72
73static int rcar_pwm_get_clock_division(struct rcar_pwm_chip *rp, int period_ns)
74{
75 unsigned long clk_rate = clk_get_rate(rp->clk);
76 u64 div, tmp;
77
78 if (clk_rate == 0)
79 return -EINVAL;
80
81 div = (u64)NSEC_PER_SEC * RCAR_PWM_MAX_CYCLE;
82 tmp = (u64)period_ns * clk_rate + div - 1;
83 tmp = div64_u64(tmp, div);
84 div = ilog2(tmp - 1) + 1;
85
86 return (div <= RCAR_PWM_MAX_DIVISION) ? div : -ERANGE;
87}
88
89static void rcar_pwm_set_clock_control(struct rcar_pwm_chip *rp,
90 unsigned int div)
91{
92 u32 value;
93
94 value = rcar_pwm_read(rp, RCAR_PWMCR);
95 value &= ~(RCAR_PWMCR_CCMD | RCAR_PWMCR_CC0_MASK);
96
97 if (div & 1)
98 value |= RCAR_PWMCR_CCMD;
99
100 div >>= 1;
101
102 value |= div << RCAR_PWMCR_CC0_SHIFT;
103 rcar_pwm_write(rp, value, RCAR_PWMCR);
104}
105
106static int rcar_pwm_set_counter(struct rcar_pwm_chip *rp, int div, int duty_ns,
107 int period_ns)
108{
109 unsigned long long one_cycle, tmp; /* 0.01 nanoseconds */
110 unsigned long clk_rate = clk_get_rate(rp->clk);
111 u32 cyc, ph;
112
113 one_cycle = NSEC_PER_SEC * 100ULL << div;
114 do_div(one_cycle, clk_rate);
115
116 tmp = period_ns * 100ULL;
117 do_div(tmp, one_cycle);
118 cyc = (tmp << RCAR_PWMCNT_CYC0_SHIFT) & RCAR_PWMCNT_CYC0_MASK;
119
120 tmp = duty_ns * 100ULL;
121 do_div(tmp, one_cycle);
122 ph = tmp & RCAR_PWMCNT_PH0_MASK;
123
124 /* Avoid prohibited setting */
125 if (cyc == 0 || ph == 0)
126 return -EINVAL;
127
128 rcar_pwm_write(rp, cyc | ph, RCAR_PWMCNT);
129
130 return 0;
131}
132
133static int rcar_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
134{
135 return pm_runtime_get_sync(chip->dev);
136}
137
138static void rcar_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
139{
140 pm_runtime_put(chip->dev);
141}
142
143static int rcar_pwm_enable(struct rcar_pwm_chip *rp)
144{
145 u32 value;
146
147 /* Don't enable the PWM device if CYC0 or PH0 is 0 */
148 value = rcar_pwm_read(rp, RCAR_PWMCNT);
149 if ((value & RCAR_PWMCNT_CYC0_MASK) == 0 ||
150 (value & RCAR_PWMCNT_PH0_MASK) == 0)
151 return -EINVAL;
152
153 rcar_pwm_update(rp, RCAR_PWMCR_EN0, RCAR_PWMCR_EN0, RCAR_PWMCR);
154
155 return 0;
156}
157
158static void rcar_pwm_disable(struct rcar_pwm_chip *rp)
159{
160 rcar_pwm_update(rp, RCAR_PWMCR_EN0, 0, RCAR_PWMCR);
161}
162
163static int rcar_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
164 const struct pwm_state *state)
165{
166 struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip);
167 int div, ret;
168
169 /* This HW/driver only supports normal polarity */
170 if (state->polarity != PWM_POLARITY_NORMAL)
171 return -EINVAL;
172
173 if (!state->enabled) {
174 rcar_pwm_disable(rp);
175 return 0;
176 }
177
178 div = rcar_pwm_get_clock_division(rp, state->period);
179 if (div < 0)
180 return div;
181
182 rcar_pwm_update(rp, RCAR_PWMCR_SYNC, RCAR_PWMCR_SYNC, RCAR_PWMCR);
183
184 ret = rcar_pwm_set_counter(rp, div, state->duty_cycle, state->period);
185 if (!ret)
186 rcar_pwm_set_clock_control(rp, div);
187
188 /* The SYNC should be set to 0 even if rcar_pwm_set_counter failed */
189 rcar_pwm_update(rp, RCAR_PWMCR_SYNC, 0, RCAR_PWMCR);
190
191 if (!ret)
192 ret = rcar_pwm_enable(rp);
193
194 return ret;
195}
196
197static const struct pwm_ops rcar_pwm_ops = {
198 .request = rcar_pwm_request,
199 .free = rcar_pwm_free,
200 .apply = rcar_pwm_apply,
201};
202
203static int rcar_pwm_probe(struct platform_device *pdev)
204{
205 struct rcar_pwm_chip *rcar_pwm;
206 int ret;
207
208 rcar_pwm = devm_kzalloc(&pdev->dev, sizeof(*rcar_pwm), GFP_KERNEL);
209 if (rcar_pwm == NULL)
210 return -ENOMEM;
211
212 rcar_pwm->base = devm_platform_ioremap_resource(pdev, 0);
213 if (IS_ERR(rcar_pwm->base))
214 return PTR_ERR(rcar_pwm->base);
215
216 rcar_pwm->clk = devm_clk_get(&pdev->dev, NULL);
217 if (IS_ERR(rcar_pwm->clk)) {
218 dev_err(&pdev->dev, "cannot get clock\n");
219 return PTR_ERR(rcar_pwm->clk);
220 }
221
222 platform_set_drvdata(pdev, rcar_pwm);
223
224 rcar_pwm->chip.dev = &pdev->dev;
225 rcar_pwm->chip.ops = &rcar_pwm_ops;
226 rcar_pwm->chip.npwm = 1;
227
228 pm_runtime_enable(&pdev->dev);
229
230 ret = pwmchip_add(&rcar_pwm->chip);
231 if (ret < 0) {
232 dev_err(&pdev->dev, "failed to register PWM chip: %d\n", ret);
233 pm_runtime_disable(&pdev->dev);
234 return ret;
235 }
236
237 return 0;
238}
239
240static void rcar_pwm_remove(struct platform_device *pdev)
241{
242 struct rcar_pwm_chip *rcar_pwm = platform_get_drvdata(pdev);
243
244 pwmchip_remove(&rcar_pwm->chip);
245
246 pm_runtime_disable(&pdev->dev);
247}
248
249static const struct of_device_id rcar_pwm_of_table[] = {
250 { .compatible = "renesas,pwm-rcar", },
251 { },
252};
253MODULE_DEVICE_TABLE(of, rcar_pwm_of_table);
254
255static struct platform_driver rcar_pwm_driver = {
256 .probe = rcar_pwm_probe,
257 .remove_new = rcar_pwm_remove,
258 .driver = {
259 .name = "pwm-rcar",
260 .of_match_table = rcar_pwm_of_table,
261 }
262};
263module_platform_driver(rcar_pwm_driver);
264
265MODULE_AUTHOR("Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>");
266MODULE_DESCRIPTION("Renesas PWM Timer Driver");
267MODULE_LICENSE("GPL v2");
268MODULE_ALIAS("platform:pwm-rcar");