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1/*
2 * BSD LICENSE
3 *
4 * Copyright(c) 2017 Broadcom. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
15 * distribution.
16 * * Neither the name of Broadcom Corporation nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#ifndef _CLOCK_BCM_SR_H
34#define _CLOCK_BCM_SR_H
35
36/* GENPLL 0 clock channel ID SCR HSLS FS PCIE */
37#define BCM_SR_GENPLL0 0
38#define BCM_SR_GENPLL0_SATA_CLK 1
39#define BCM_SR_GENPLL0_SCR_CLK 2
40#define BCM_SR_GENPLL0_250M_CLK 3
41#define BCM_SR_GENPLL0_PCIE_AXI_CLK 4
42#define BCM_SR_GENPLL0_PAXC_AXI_X2_CLK 5
43#define BCM_SR_GENPLL0_PAXC_AXI_CLK 6
44
45/* GENPLL 1 clock channel ID MHB PCIE NITRO */
46#define BCM_SR_GENPLL1 0
47#define BCM_SR_GENPLL1_PCIE_TL_CLK 1
48#define BCM_SR_GENPLL1_MHB_APB_CLK 2
49
50/* GENPLL 2 clock channel ID NITRO MHB*/
51#define BCM_SR_GENPLL2 0
52#define BCM_SR_GENPLL2_NIC_CLK 1
53#define BCM_SR_GENPLL2_250_NITRO_CLK 2
54#define BCM_SR_GENPLL2_125_NITRO_CLK 3
55#define BCM_SR_GENPLL2_CHIMP_CLK 4
56
57/* GENPLL 3 HSLS clock channel ID */
58#define BCM_SR_GENPLL3 0
59#define BCM_SR_GENPLL3_HSLS_CLK 1
60#define BCM_SR_GENPLL3_SDIO_CLK 2
61
62/* GENPLL 4 SCR clock channel ID */
63#define BCM_SR_GENPLL4 0
64#define BCM_SR_GENPLL4_CCN_CLK 1
65
66/* GENPLL 5 FS4 clock channel ID */
67#define BCM_SR_GENPLL5 0
68#define BCM_SR_GENPLL5_FS_CLK 1
69#define BCM_SR_GENPLL5_SPU_CLK 2
70
71/* GENPLL 6 NITRO clock channel ID */
72#define BCM_SR_GENPLL6 0
73#define BCM_SR_GENPLL6_48_USB_CLK 1
74
75/* LCPLL0 clock channel ID */
76#define BCM_SR_LCPLL0 0
77#define BCM_SR_LCPLL0_SATA_REF_CLK 1
78#define BCM_SR_LCPLL0_USB_REF_CLK 2
79#define BCM_SR_LCPLL0_SATA_REFPN_CLK 3
80
81/* LCPLL1 clock channel ID */
82#define BCM_SR_LCPLL1 0
83#define BCM_SR_LCPLL1_WAN_CLK 1
84
85/* LCPLL PCIE clock channel ID */
86#define BCM_SR_LCPLL_PCIE 0
87#define BCM_SR_LCPLL_PCIE_PHY_REF_CLK 1
88
89/* GENPLL EMEM0 clock channel ID */
90#define BCM_SR_EMEMPLL0 0
91#define BCM_SR_EMEMPLL0_EMEM_CLK 1
92
93/* GENPLL EMEM0 clock channel ID */
94#define BCM_SR_EMEMPLL1 0
95#define BCM_SR_EMEMPLL1_EMEM_CLK 1
96
97/* GENPLL EMEM0 clock channel ID */
98#define BCM_SR_EMEMPLL2 0
99#define BCM_SR_EMEMPLL2_EMEM_CLK 1
100
101#endif /* _CLOCK_BCM_SR_H */
1/*
2 * BSD LICENSE
3 *
4 * Copyright(c) 2017 Broadcom. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
15 * distribution.
16 * * Neither the name of Broadcom Corporation nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#ifndef _CLOCK_BCM_SR_H
34#define _CLOCK_BCM_SR_H
35
36/* GENPLL 0 clock channel ID SCR HSLS FS PCIE */
37#define BCM_SR_GENPLL0 0
38#define BCM_SR_GENPLL0_125M_CLK 1
39#define BCM_SR_GENPLL0_SCR_CLK 2
40#define BCM_SR_GENPLL0_250M_CLK 3
41#define BCM_SR_GENPLL0_PCIE_AXI_CLK 4
42#define BCM_SR_GENPLL0_PAXC_AXI_X2_CLK 5
43#define BCM_SR_GENPLL0_PAXC_AXI_CLK 6
44
45/* GENPLL 1 clock channel ID MHB PCIE NITRO */
46#define BCM_SR_GENPLL1 0
47#define BCM_SR_GENPLL1_PCIE_TL_CLK 1
48#define BCM_SR_GENPLL1_MHB_APB_CLK 2
49
50/* GENPLL 2 clock channel ID NITRO MHB*/
51#define BCM_SR_GENPLL2 0
52#define BCM_SR_GENPLL2_NIC_CLK 1
53#define BCM_SR_GENPLL2_TS_500_CLK 2
54#define BCM_SR_GENPLL2_125_NITRO_CLK 3
55#define BCM_SR_GENPLL2_CHIMP_CLK 4
56#define BCM_SR_GENPLL2_NIC_FLASH_CLK 5
57#define BCM_SR_GENPLL2_FS4_CLK 6
58
59/* GENPLL 3 HSLS clock channel ID */
60#define BCM_SR_GENPLL3 0
61#define BCM_SR_GENPLL3_HSLS_CLK 1
62#define BCM_SR_GENPLL3_SDIO_CLK 2
63
64/* GENPLL 4 SCR clock channel ID */
65#define BCM_SR_GENPLL4 0
66#define BCM_SR_GENPLL4_CCN_CLK 1
67#define BCM_SR_GENPLL4_TPIU_PLL_CLK 2
68#define BCM_SR_GENPLL4_NOC_CLK 3
69#define BCM_SR_GENPLL4_CHCLK_FS4_CLK 4
70#define BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK 5
71
72/* GENPLL 5 FS4 clock channel ID */
73#define BCM_SR_GENPLL5 0
74#define BCM_SR_GENPLL5_FS4_HF_CLK 1
75#define BCM_SR_GENPLL5_CRYPTO_AE_CLK 2
76#define BCM_SR_GENPLL5_RAID_AE_CLK 3
77
78/* GENPLL 6 NITRO clock channel ID */
79#define BCM_SR_GENPLL6 0
80#define BCM_SR_GENPLL6_48_USB_CLK 1
81
82/* LCPLL0 clock channel ID */
83#define BCM_SR_LCPLL0 0
84#define BCM_SR_LCPLL0_SATA_REFP_CLK 1
85#define BCM_SR_LCPLL0_SATA_REFN_CLK 2
86#define BCM_SR_LCPLL0_SATA_350_CLK 3
87#define BCM_SR_LCPLL0_SATA_500_CLK 4
88
89/* LCPLL1 clock channel ID */
90#define BCM_SR_LCPLL1 0
91#define BCM_SR_LCPLL1_WAN_CLK 1
92#define BCM_SR_LCPLL1_USB_REF_CLK 2
93#define BCM_SR_LCPLL1_CRMU_TS_CLK 3
94
95/* LCPLL PCIE clock channel ID */
96#define BCM_SR_LCPLL_PCIE 0
97#define BCM_SR_LCPLL_PCIE_PHY_REF_CLK 1
98
99/* GENPLL EMEM0 clock channel ID */
100#define BCM_SR_EMEMPLL0 0
101#define BCM_SR_EMEMPLL0_EMEM_CLK 1
102
103/* GENPLL EMEM0 clock channel ID */
104#define BCM_SR_EMEMPLL1 0
105#define BCM_SR_EMEMPLL1_EMEM_CLK 1
106
107/* GENPLL EMEM0 clock channel ID */
108#define BCM_SR_EMEMPLL2 0
109#define BCM_SR_EMEMPLL2_EMEM_CLK 1
110
111#endif /* _CLOCK_BCM_SR_H */