Loading...
1/*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright (c) 2016 BayLibre, SAS.
8 * Author: Neil Armstrong <narmstrong@baylibre.com>
9 * Copyright (C) 2014 Amlogic, Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, see <http://www.gnu.org/licenses/>.
22 * The full GNU General Public License is included in this distribution
23 * in the file called COPYING.
24 *
25 * BSD LICENSE
26 *
27 * Copyright (c) 2016 BayLibre, SAS.
28 * Author: Neil Armstrong <narmstrong@baylibre.com>
29 * Copyright (C) 2014 Amlogic, Inc.
30 *
31 * Redistribution and use in source and binary forms, with or without
32 * modification, are permitted provided that the following conditions
33 * are met:
34 *
35 * * Redistributions of source code must retain the above copyright
36 * notice, this list of conditions and the following disclaimer.
37 * * Redistributions in binary form must reproduce the above copyright
38 * notice, this list of conditions and the following disclaimer in
39 * the documentation and/or other materials provided with the
40 * distribution.
41 * * Neither the name of Intel Corporation nor the names of its
42 * contributors may be used to endorse or promote products derived
43 * from this software without specific prior written permission.
44 *
45 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
46 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
47 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
48 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
49 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
50 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
51 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
52 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
53 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
54 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
55 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
56 */
57
58#include <linux/clk.h>
59#include <linux/clk-provider.h>
60#include <linux/err.h>
61#include <linux/io.h>
62#include <linux/kernel.h>
63#include <linux/module.h>
64#include <linux/of.h>
65#include <linux/of_device.h>
66#include <linux/platform_device.h>
67#include <linux/pwm.h>
68#include <linux/slab.h>
69#include <linux/spinlock.h>
70
71#define REG_PWM_A 0x0
72#define REG_PWM_B 0x4
73#define PWM_HIGH_SHIFT 16
74
75#define REG_MISC_AB 0x8
76#define MISC_B_CLK_EN BIT(23)
77#define MISC_A_CLK_EN BIT(15)
78#define MISC_CLK_DIV_MASK 0x7f
79#define MISC_B_CLK_DIV_SHIFT 16
80#define MISC_A_CLK_DIV_SHIFT 8
81#define MISC_B_CLK_SEL_SHIFT 6
82#define MISC_A_CLK_SEL_SHIFT 4
83#define MISC_CLK_SEL_WIDTH 2
84#define MISC_B_EN BIT(1)
85#define MISC_A_EN BIT(0)
86
87static const unsigned int mux_reg_shifts[] = {
88 MISC_A_CLK_SEL_SHIFT,
89 MISC_B_CLK_SEL_SHIFT
90};
91
92struct meson_pwm_channel {
93 unsigned int hi;
94 unsigned int lo;
95 u8 pre_div;
96
97 struct pwm_state state;
98
99 struct clk *clk_parent;
100 struct clk_mux mux;
101 struct clk *clk;
102};
103
104struct meson_pwm_data {
105 const char * const *parent_names;
106 unsigned int num_parents;
107};
108
109struct meson_pwm {
110 struct pwm_chip chip;
111 const struct meson_pwm_data *data;
112 void __iomem *base;
113 u8 inverter_mask;
114 spinlock_t lock;
115};
116
117static inline struct meson_pwm *to_meson_pwm(struct pwm_chip *chip)
118{
119 return container_of(chip, struct meson_pwm, chip);
120}
121
122static int meson_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
123{
124 struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
125 struct device *dev = chip->dev;
126 int err;
127
128 if (!channel)
129 return -ENODEV;
130
131 if (channel->clk_parent) {
132 err = clk_set_parent(channel->clk, channel->clk_parent);
133 if (err < 0) {
134 dev_err(dev, "failed to set parent %s for %s: %d\n",
135 __clk_get_name(channel->clk_parent),
136 __clk_get_name(channel->clk), err);
137 return err;
138 }
139 }
140
141 err = clk_prepare_enable(channel->clk);
142 if (err < 0) {
143 dev_err(dev, "failed to enable clock %s: %d\n",
144 __clk_get_name(channel->clk), err);
145 return err;
146 }
147
148 chip->ops->get_state(chip, pwm, &channel->state);
149
150 return 0;
151}
152
153static void meson_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
154{
155 struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
156
157 if (channel)
158 clk_disable_unprepare(channel->clk);
159}
160
161static int meson_pwm_calc(struct meson_pwm *meson,
162 struct meson_pwm_channel *channel, unsigned int id,
163 unsigned int duty, unsigned int period)
164{
165 unsigned int pre_div, cnt, duty_cnt;
166 unsigned long fin_freq = -1;
167 u64 fin_ps;
168
169 if (~(meson->inverter_mask >> id) & 0x1)
170 duty = period - duty;
171
172 if (period == channel->state.period &&
173 duty == channel->state.duty_cycle)
174 return 0;
175
176 fin_freq = clk_get_rate(channel->clk);
177 if (fin_freq == 0) {
178 dev_err(meson->chip.dev, "invalid source clock frequency\n");
179 return -EINVAL;
180 }
181
182 dev_dbg(meson->chip.dev, "fin_freq: %lu Hz\n", fin_freq);
183 fin_ps = (u64)NSEC_PER_SEC * 1000;
184 do_div(fin_ps, fin_freq);
185
186 /* Calc pre_div with the period */
187 for (pre_div = 0; pre_div < MISC_CLK_DIV_MASK; pre_div++) {
188 cnt = DIV_ROUND_CLOSEST_ULL((u64)period * 1000,
189 fin_ps * (pre_div + 1));
190 dev_dbg(meson->chip.dev, "fin_ps=%llu pre_div=%u cnt=%u\n",
191 fin_ps, pre_div, cnt);
192 if (cnt <= 0xffff)
193 break;
194 }
195
196 if (pre_div == MISC_CLK_DIV_MASK) {
197 dev_err(meson->chip.dev, "unable to get period pre_div\n");
198 return -EINVAL;
199 }
200
201 dev_dbg(meson->chip.dev, "period=%u pre_div=%u cnt=%u\n", period,
202 pre_div, cnt);
203
204 if (duty == period) {
205 channel->pre_div = pre_div;
206 channel->hi = cnt;
207 channel->lo = 0;
208 } else if (duty == 0) {
209 channel->pre_div = pre_div;
210 channel->hi = 0;
211 channel->lo = cnt;
212 } else {
213 /* Then check is we can have the duty with the same pre_div */
214 duty_cnt = DIV_ROUND_CLOSEST_ULL((u64)duty * 1000,
215 fin_ps * (pre_div + 1));
216 if (duty_cnt > 0xffff) {
217 dev_err(meson->chip.dev, "unable to get duty cycle\n");
218 return -EINVAL;
219 }
220
221 dev_dbg(meson->chip.dev, "duty=%u pre_div=%u duty_cnt=%u\n",
222 duty, pre_div, duty_cnt);
223
224 channel->pre_div = pre_div;
225 channel->hi = duty_cnt;
226 channel->lo = cnt - duty_cnt;
227 }
228
229 return 0;
230}
231
232static void meson_pwm_enable(struct meson_pwm *meson,
233 struct meson_pwm_channel *channel,
234 unsigned int id)
235{
236 u32 value, clk_shift, clk_enable, enable;
237 unsigned int offset;
238
239 switch (id) {
240 case 0:
241 clk_shift = MISC_A_CLK_DIV_SHIFT;
242 clk_enable = MISC_A_CLK_EN;
243 enable = MISC_A_EN;
244 offset = REG_PWM_A;
245 break;
246
247 case 1:
248 clk_shift = MISC_B_CLK_DIV_SHIFT;
249 clk_enable = MISC_B_CLK_EN;
250 enable = MISC_B_EN;
251 offset = REG_PWM_B;
252 break;
253
254 default:
255 return;
256 }
257
258 value = readl(meson->base + REG_MISC_AB);
259 value &= ~(MISC_CLK_DIV_MASK << clk_shift);
260 value |= channel->pre_div << clk_shift;
261 value |= clk_enable;
262 writel(value, meson->base + REG_MISC_AB);
263
264 value = (channel->hi << PWM_HIGH_SHIFT) | channel->lo;
265 writel(value, meson->base + offset);
266
267 value = readl(meson->base + REG_MISC_AB);
268 value |= enable;
269 writel(value, meson->base + REG_MISC_AB);
270}
271
272static void meson_pwm_disable(struct meson_pwm *meson, unsigned int id)
273{
274 u32 value, enable;
275
276 switch (id) {
277 case 0:
278 enable = MISC_A_EN;
279 break;
280
281 case 1:
282 enable = MISC_B_EN;
283 break;
284
285 default:
286 return;
287 }
288
289 value = readl(meson->base + REG_MISC_AB);
290 value &= ~enable;
291 writel(value, meson->base + REG_MISC_AB);
292}
293
294static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
295 struct pwm_state *state)
296{
297 struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
298 struct meson_pwm *meson = to_meson_pwm(chip);
299 unsigned long flags;
300 int err = 0;
301
302 if (!state)
303 return -EINVAL;
304
305 spin_lock_irqsave(&meson->lock, flags);
306
307 if (!state->enabled) {
308 meson_pwm_disable(meson, pwm->hwpwm);
309 channel->state.enabled = false;
310
311 goto unlock;
312 }
313
314 if (state->period != channel->state.period ||
315 state->duty_cycle != channel->state.duty_cycle ||
316 state->polarity != channel->state.polarity) {
317 if (channel->state.enabled) {
318 meson_pwm_disable(meson, pwm->hwpwm);
319 channel->state.enabled = false;
320 }
321
322 if (state->polarity != channel->state.polarity) {
323 if (state->polarity == PWM_POLARITY_NORMAL)
324 meson->inverter_mask |= BIT(pwm->hwpwm);
325 else
326 meson->inverter_mask &= ~BIT(pwm->hwpwm);
327 }
328
329 err = meson_pwm_calc(meson, channel, pwm->hwpwm,
330 state->duty_cycle, state->period);
331 if (err < 0)
332 goto unlock;
333
334 channel->state.polarity = state->polarity;
335 channel->state.period = state->period;
336 channel->state.duty_cycle = state->duty_cycle;
337 }
338
339 if (state->enabled && !channel->state.enabled) {
340 meson_pwm_enable(meson, channel, pwm->hwpwm);
341 channel->state.enabled = true;
342 }
343
344unlock:
345 spin_unlock_irqrestore(&meson->lock, flags);
346 return err;
347}
348
349static void meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
350 struct pwm_state *state)
351{
352 struct meson_pwm *meson = to_meson_pwm(chip);
353 u32 value, mask;
354
355 if (!state)
356 return;
357
358 switch (pwm->hwpwm) {
359 case 0:
360 mask = MISC_A_EN;
361 break;
362
363 case 1:
364 mask = MISC_B_EN;
365 break;
366
367 default:
368 return;
369 }
370
371 value = readl(meson->base + REG_MISC_AB);
372 state->enabled = (value & mask) != 0;
373}
374
375static const struct pwm_ops meson_pwm_ops = {
376 .request = meson_pwm_request,
377 .free = meson_pwm_free,
378 .apply = meson_pwm_apply,
379 .get_state = meson_pwm_get_state,
380 .owner = THIS_MODULE,
381};
382
383static const char * const pwm_meson8b_parent_names[] = {
384 "xtal", "vid_pll", "fclk_div4", "fclk_div3"
385};
386
387static const struct meson_pwm_data pwm_meson8b_data = {
388 .parent_names = pwm_meson8b_parent_names,
389 .num_parents = ARRAY_SIZE(pwm_meson8b_parent_names),
390};
391
392static const char * const pwm_gxbb_parent_names[] = {
393 "xtal", "hdmi_pll", "fclk_div4", "fclk_div3"
394};
395
396static const struct meson_pwm_data pwm_gxbb_data = {
397 .parent_names = pwm_gxbb_parent_names,
398 .num_parents = ARRAY_SIZE(pwm_gxbb_parent_names),
399};
400
401/*
402 * Only the 2 first inputs of the GXBB AO PWMs are valid
403 * The last 2 are grounded
404 */
405static const char * const pwm_gxbb_ao_parent_names[] = {
406 "xtal", "clk81"
407};
408
409static const struct meson_pwm_data pwm_gxbb_ao_data = {
410 .parent_names = pwm_gxbb_ao_parent_names,
411 .num_parents = ARRAY_SIZE(pwm_gxbb_ao_parent_names),
412};
413
414static const char * const pwm_axg_ee_parent_names[] = {
415 "xtal", "fclk_div5", "fclk_div4", "fclk_div3"
416};
417
418static const struct meson_pwm_data pwm_axg_ee_data = {
419 .parent_names = pwm_axg_ee_parent_names,
420 .num_parents = ARRAY_SIZE(pwm_axg_ee_parent_names),
421};
422
423static const char * const pwm_axg_ao_parent_names[] = {
424 "aoclk81", "xtal", "fclk_div4", "fclk_div5"
425};
426
427static const struct meson_pwm_data pwm_axg_ao_data = {
428 .parent_names = pwm_axg_ao_parent_names,
429 .num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names),
430};
431
432static const struct of_device_id meson_pwm_matches[] = {
433 {
434 .compatible = "amlogic,meson8b-pwm",
435 .data = &pwm_meson8b_data
436 },
437 {
438 .compatible = "amlogic,meson-gxbb-pwm",
439 .data = &pwm_gxbb_data
440 },
441 {
442 .compatible = "amlogic,meson-gxbb-ao-pwm",
443 .data = &pwm_gxbb_ao_data
444 },
445 {
446 .compatible = "amlogic,meson-axg-ee-pwm",
447 .data = &pwm_axg_ee_data
448 },
449 {
450 .compatible = "amlogic,meson-axg-ao-pwm",
451 .data = &pwm_axg_ao_data
452 },
453 {},
454};
455MODULE_DEVICE_TABLE(of, meson_pwm_matches);
456
457static int meson_pwm_init_channels(struct meson_pwm *meson,
458 struct meson_pwm_channel *channels)
459{
460 struct device *dev = meson->chip.dev;
461 struct device_node *np = dev->of_node;
462 struct clk_init_data init;
463 unsigned int i;
464 char name[255];
465 int err;
466
467 for (i = 0; i < meson->chip.npwm; i++) {
468 struct meson_pwm_channel *channel = &channels[i];
469
470 snprintf(name, sizeof(name), "%pOF#mux%u", np, i);
471
472 init.name = name;
473 init.ops = &clk_mux_ops;
474 init.flags = CLK_IS_BASIC;
475 init.parent_names = meson->data->parent_names;
476 init.num_parents = meson->data->num_parents;
477
478 channel->mux.reg = meson->base + REG_MISC_AB;
479 channel->mux.shift = mux_reg_shifts[i];
480 channel->mux.mask = BIT(MISC_CLK_SEL_WIDTH) - 1;
481 channel->mux.flags = 0;
482 channel->mux.lock = &meson->lock;
483 channel->mux.table = NULL;
484 channel->mux.hw.init = &init;
485
486 channel->clk = devm_clk_register(dev, &channel->mux.hw);
487 if (IS_ERR(channel->clk)) {
488 err = PTR_ERR(channel->clk);
489 dev_err(dev, "failed to register %s: %d\n", name, err);
490 return err;
491 }
492
493 snprintf(name, sizeof(name), "clkin%u", i);
494
495 channel->clk_parent = devm_clk_get(dev, name);
496 if (IS_ERR(channel->clk_parent)) {
497 err = PTR_ERR(channel->clk_parent);
498 if (err == -EPROBE_DEFER)
499 return err;
500
501 channel->clk_parent = NULL;
502 }
503 }
504
505 return 0;
506}
507
508static void meson_pwm_add_channels(struct meson_pwm *meson,
509 struct meson_pwm_channel *channels)
510{
511 unsigned int i;
512
513 for (i = 0; i < meson->chip.npwm; i++)
514 pwm_set_chip_data(&meson->chip.pwms[i], &channels[i]);
515}
516
517static int meson_pwm_probe(struct platform_device *pdev)
518{
519 struct meson_pwm_channel *channels;
520 struct meson_pwm *meson;
521 struct resource *regs;
522 int err;
523
524 meson = devm_kzalloc(&pdev->dev, sizeof(*meson), GFP_KERNEL);
525 if (!meson)
526 return -ENOMEM;
527
528 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
529 meson->base = devm_ioremap_resource(&pdev->dev, regs);
530 if (IS_ERR(meson->base))
531 return PTR_ERR(meson->base);
532
533 spin_lock_init(&meson->lock);
534 meson->chip.dev = &pdev->dev;
535 meson->chip.ops = &meson_pwm_ops;
536 meson->chip.base = -1;
537 meson->chip.npwm = 2;
538 meson->chip.of_xlate = of_pwm_xlate_with_flags;
539 meson->chip.of_pwm_n_cells = 3;
540
541 meson->data = of_device_get_match_data(&pdev->dev);
542 meson->inverter_mask = BIT(meson->chip.npwm) - 1;
543
544 channels = devm_kcalloc(&pdev->dev, meson->chip.npwm, sizeof(*meson),
545 GFP_KERNEL);
546 if (!channels)
547 return -ENOMEM;
548
549 err = meson_pwm_init_channels(meson, channels);
550 if (err < 0)
551 return err;
552
553 err = pwmchip_add(&meson->chip);
554 if (err < 0) {
555 dev_err(&pdev->dev, "failed to register PWM chip: %d\n", err);
556 return err;
557 }
558
559 meson_pwm_add_channels(meson, channels);
560
561 platform_set_drvdata(pdev, meson);
562
563 return 0;
564}
565
566static int meson_pwm_remove(struct platform_device *pdev)
567{
568 struct meson_pwm *meson = platform_get_drvdata(pdev);
569
570 return pwmchip_remove(&meson->chip);
571}
572
573static struct platform_driver meson_pwm_driver = {
574 .driver = {
575 .name = "meson-pwm",
576 .of_match_table = meson_pwm_matches,
577 },
578 .probe = meson_pwm_probe,
579 .remove = meson_pwm_remove,
580};
581module_platform_driver(meson_pwm_driver);
582
583MODULE_DESCRIPTION("Amlogic Meson PWM Generator driver");
584MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
585MODULE_LICENSE("Dual BSD/GPL");
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/*
3 * PWM controller driver for Amlogic Meson SoCs.
4 *
5 * This PWM is only a set of Gates, Dividers and Counters:
6 * PWM output is achieved by calculating a clock that permits calculating
7 * two periods (low and high). The counter then has to be set to switch after
8 * N cycles for the first half period.
9 * The hardware has no "polarity" setting. This driver reverses the period
10 * cycles (the low length is inverted with the high length) for
11 * PWM_POLARITY_INVERSED. This means that .get_state cannot read the polarity
12 * from the hardware.
13 * Setting the duty cycle will disable and re-enable the PWM output.
14 * Disabling the PWM stops the output immediately (without waiting for the
15 * current period to complete first).
16 *
17 * The public S912 (GXM) datasheet contains some documentation for this PWM
18 * controller starting on page 543:
19 * https://dl.khadas.com/Hardware/VIM2/Datasheet/S912_Datasheet_V0.220170314publicversion-Wesion.pdf
20 * An updated version of this IP block is found in S922X (G12B) SoCs. The
21 * datasheet contains the description for this IP block revision starting at
22 * page 1084:
23 * https://dn.odroid.com/S922X/ODROID-N2/Datasheet/S922X_Public_Datasheet_V0.2.pdf
24 *
25 * Copyright (c) 2016 BayLibre, SAS.
26 * Author: Neil Armstrong <narmstrong@baylibre.com>
27 * Copyright (C) 2014 Amlogic, Inc.
28 */
29
30#include <linux/bitfield.h>
31#include <linux/bits.h>
32#include <linux/clk.h>
33#include <linux/clk-provider.h>
34#include <linux/err.h>
35#include <linux/io.h>
36#include <linux/kernel.h>
37#include <linux/math64.h>
38#include <linux/module.h>
39#include <linux/of.h>
40#include <linux/of_device.h>
41#include <linux/platform_device.h>
42#include <linux/pwm.h>
43#include <linux/slab.h>
44#include <linux/spinlock.h>
45
46#define REG_PWM_A 0x0
47#define REG_PWM_B 0x4
48#define PWM_LOW_MASK GENMASK(15, 0)
49#define PWM_HIGH_MASK GENMASK(31, 16)
50
51#define REG_MISC_AB 0x8
52#define MISC_B_CLK_EN BIT(23)
53#define MISC_A_CLK_EN BIT(15)
54#define MISC_CLK_DIV_MASK 0x7f
55#define MISC_B_CLK_DIV_SHIFT 16
56#define MISC_A_CLK_DIV_SHIFT 8
57#define MISC_B_CLK_SEL_SHIFT 6
58#define MISC_A_CLK_SEL_SHIFT 4
59#define MISC_CLK_SEL_MASK 0x3
60#define MISC_B_EN BIT(1)
61#define MISC_A_EN BIT(0)
62
63#define MESON_NUM_PWMS 2
64
65static struct meson_pwm_channel_data {
66 u8 reg_offset;
67 u8 clk_sel_shift;
68 u8 clk_div_shift;
69 u32 clk_en_mask;
70 u32 pwm_en_mask;
71} meson_pwm_per_channel_data[MESON_NUM_PWMS] = {
72 {
73 .reg_offset = REG_PWM_A,
74 .clk_sel_shift = MISC_A_CLK_SEL_SHIFT,
75 .clk_div_shift = MISC_A_CLK_DIV_SHIFT,
76 .clk_en_mask = MISC_A_CLK_EN,
77 .pwm_en_mask = MISC_A_EN,
78 },
79 {
80 .reg_offset = REG_PWM_B,
81 .clk_sel_shift = MISC_B_CLK_SEL_SHIFT,
82 .clk_div_shift = MISC_B_CLK_DIV_SHIFT,
83 .clk_en_mask = MISC_B_CLK_EN,
84 .pwm_en_mask = MISC_B_EN,
85 }
86};
87
88struct meson_pwm_channel {
89 unsigned int hi;
90 unsigned int lo;
91 u8 pre_div;
92
93 struct clk *clk_parent;
94 struct clk_mux mux;
95 struct clk *clk;
96};
97
98struct meson_pwm_data {
99 const char * const *parent_names;
100 unsigned int num_parents;
101};
102
103struct meson_pwm {
104 struct pwm_chip chip;
105 const struct meson_pwm_data *data;
106 struct meson_pwm_channel channels[MESON_NUM_PWMS];
107 void __iomem *base;
108 /*
109 * Protects register (write) access to the REG_MISC_AB register
110 * that is shared between the two PWMs.
111 */
112 spinlock_t lock;
113};
114
115static inline struct meson_pwm *to_meson_pwm(struct pwm_chip *chip)
116{
117 return container_of(chip, struct meson_pwm, chip);
118}
119
120static int meson_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
121{
122 struct meson_pwm *meson = to_meson_pwm(chip);
123 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
124 struct device *dev = chip->dev;
125 int err;
126
127 if (channel->clk_parent) {
128 err = clk_set_parent(channel->clk, channel->clk_parent);
129 if (err < 0) {
130 dev_err(dev, "failed to set parent %s for %s: %d\n",
131 __clk_get_name(channel->clk_parent),
132 __clk_get_name(channel->clk), err);
133 return err;
134 }
135 }
136
137 err = clk_prepare_enable(channel->clk);
138 if (err < 0) {
139 dev_err(dev, "failed to enable clock %s: %d\n",
140 __clk_get_name(channel->clk), err);
141 return err;
142 }
143
144 return 0;
145}
146
147static void meson_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
148{
149 struct meson_pwm *meson = to_meson_pwm(chip);
150 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
151
152 clk_disable_unprepare(channel->clk);
153}
154
155static int meson_pwm_calc(struct meson_pwm *meson, struct pwm_device *pwm,
156 const struct pwm_state *state)
157{
158 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
159 unsigned int duty, period, pre_div, cnt, duty_cnt;
160 unsigned long fin_freq;
161
162 duty = state->duty_cycle;
163 period = state->period;
164
165 if (state->polarity == PWM_POLARITY_INVERSED)
166 duty = period - duty;
167
168 fin_freq = clk_get_rate(channel->clk);
169 if (fin_freq == 0) {
170 dev_err(meson->chip.dev, "invalid source clock frequency\n");
171 return -EINVAL;
172 }
173
174 dev_dbg(meson->chip.dev, "fin_freq: %lu Hz\n", fin_freq);
175
176 pre_div = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * 0xffffLL);
177 if (pre_div > MISC_CLK_DIV_MASK) {
178 dev_err(meson->chip.dev, "unable to get period pre_div\n");
179 return -EINVAL;
180 }
181
182 cnt = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * (pre_div + 1));
183 if (cnt > 0xffff) {
184 dev_err(meson->chip.dev, "unable to get period cnt\n");
185 return -EINVAL;
186 }
187
188 dev_dbg(meson->chip.dev, "period=%u pre_div=%u cnt=%u\n", period,
189 pre_div, cnt);
190
191 if (duty == period) {
192 channel->pre_div = pre_div;
193 channel->hi = cnt;
194 channel->lo = 0;
195 } else if (duty == 0) {
196 channel->pre_div = pre_div;
197 channel->hi = 0;
198 channel->lo = cnt;
199 } else {
200 /* Then check is we can have the duty with the same pre_div */
201 duty_cnt = div64_u64(fin_freq * (u64)duty,
202 NSEC_PER_SEC * (pre_div + 1));
203 if (duty_cnt > 0xffff) {
204 dev_err(meson->chip.dev, "unable to get duty cycle\n");
205 return -EINVAL;
206 }
207
208 dev_dbg(meson->chip.dev, "duty=%u pre_div=%u duty_cnt=%u\n",
209 duty, pre_div, duty_cnt);
210
211 channel->pre_div = pre_div;
212 channel->hi = duty_cnt;
213 channel->lo = cnt - duty_cnt;
214 }
215
216 return 0;
217}
218
219static void meson_pwm_enable(struct meson_pwm *meson, struct pwm_device *pwm)
220{
221 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
222 struct meson_pwm_channel_data *channel_data;
223 unsigned long flags;
224 u32 value;
225
226 channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
227
228 spin_lock_irqsave(&meson->lock, flags);
229
230 value = readl(meson->base + REG_MISC_AB);
231 value &= ~(MISC_CLK_DIV_MASK << channel_data->clk_div_shift);
232 value |= channel->pre_div << channel_data->clk_div_shift;
233 value |= channel_data->clk_en_mask;
234 writel(value, meson->base + REG_MISC_AB);
235
236 value = FIELD_PREP(PWM_HIGH_MASK, channel->hi) |
237 FIELD_PREP(PWM_LOW_MASK, channel->lo);
238 writel(value, meson->base + channel_data->reg_offset);
239
240 value = readl(meson->base + REG_MISC_AB);
241 value |= channel_data->pwm_en_mask;
242 writel(value, meson->base + REG_MISC_AB);
243
244 spin_unlock_irqrestore(&meson->lock, flags);
245}
246
247static void meson_pwm_disable(struct meson_pwm *meson, struct pwm_device *pwm)
248{
249 unsigned long flags;
250 u32 value;
251
252 spin_lock_irqsave(&meson->lock, flags);
253
254 value = readl(meson->base + REG_MISC_AB);
255 value &= ~meson_pwm_per_channel_data[pwm->hwpwm].pwm_en_mask;
256 writel(value, meson->base + REG_MISC_AB);
257
258 spin_unlock_irqrestore(&meson->lock, flags);
259}
260
261static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
262 const struct pwm_state *state)
263{
264 struct meson_pwm *meson = to_meson_pwm(chip);
265 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm];
266 int err = 0;
267
268 if (!state->enabled) {
269 if (state->polarity == PWM_POLARITY_INVERSED) {
270 /*
271 * This IP block revision doesn't have an "always high"
272 * setting which we can use for "inverted disabled".
273 * Instead we achieve this using the same settings
274 * that we use a pre_div of 0 (to get the shortest
275 * possible duration for one "count") and
276 * "period == duty_cycle". This results in a signal
277 * which is LOW for one "count", while being HIGH for
278 * the rest of the (so the signal is HIGH for slightly
279 * less than 100% of the period, but this is the best
280 * we can achieve).
281 */
282 channel->pre_div = 0;
283 channel->hi = ~0;
284 channel->lo = 0;
285
286 meson_pwm_enable(meson, pwm);
287 } else {
288 meson_pwm_disable(meson, pwm);
289 }
290 } else {
291 err = meson_pwm_calc(meson, pwm, state);
292 if (err < 0)
293 return err;
294
295 meson_pwm_enable(meson, pwm);
296 }
297
298 return 0;
299}
300
301static unsigned int meson_pwm_cnt_to_ns(struct pwm_chip *chip,
302 struct pwm_device *pwm, u32 cnt)
303{
304 struct meson_pwm *meson = to_meson_pwm(chip);
305 struct meson_pwm_channel *channel;
306 unsigned long fin_freq;
307 u32 fin_ns;
308
309 /* to_meson_pwm() can only be used after .get_state() is called */
310 channel = &meson->channels[pwm->hwpwm];
311
312 fin_freq = clk_get_rate(channel->clk);
313 if (fin_freq == 0)
314 return 0;
315
316 fin_ns = div_u64(NSEC_PER_SEC, fin_freq);
317
318 return cnt * fin_ns * (channel->pre_div + 1);
319}
320
321static int meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
322 struct pwm_state *state)
323{
324 struct meson_pwm *meson = to_meson_pwm(chip);
325 struct meson_pwm_channel_data *channel_data;
326 struct meson_pwm_channel *channel;
327 u32 value, tmp;
328
329 if (!state)
330 return 0;
331
332 channel = &meson->channels[pwm->hwpwm];
333 channel_data = &meson_pwm_per_channel_data[pwm->hwpwm];
334
335 value = readl(meson->base + REG_MISC_AB);
336
337 tmp = channel_data->pwm_en_mask | channel_data->clk_en_mask;
338 state->enabled = (value & tmp) == tmp;
339
340 tmp = value >> channel_data->clk_div_shift;
341 channel->pre_div = FIELD_GET(MISC_CLK_DIV_MASK, tmp);
342
343 value = readl(meson->base + channel_data->reg_offset);
344
345 channel->lo = FIELD_GET(PWM_LOW_MASK, value);
346 channel->hi = FIELD_GET(PWM_HIGH_MASK, value);
347
348 if (channel->lo == 0) {
349 state->period = meson_pwm_cnt_to_ns(chip, pwm, channel->hi);
350 state->duty_cycle = state->period;
351 } else if (channel->lo >= channel->hi) {
352 state->period = meson_pwm_cnt_to_ns(chip, pwm,
353 channel->lo + channel->hi);
354 state->duty_cycle = meson_pwm_cnt_to_ns(chip, pwm,
355 channel->hi);
356 } else {
357 state->period = 0;
358 state->duty_cycle = 0;
359 }
360
361 return 0;
362}
363
364static const struct pwm_ops meson_pwm_ops = {
365 .request = meson_pwm_request,
366 .free = meson_pwm_free,
367 .apply = meson_pwm_apply,
368 .get_state = meson_pwm_get_state,
369 .owner = THIS_MODULE,
370};
371
372static const char * const pwm_meson8b_parent_names[] = {
373 "xtal", "vid_pll", "fclk_div4", "fclk_div3"
374};
375
376static const struct meson_pwm_data pwm_meson8b_data = {
377 .parent_names = pwm_meson8b_parent_names,
378 .num_parents = ARRAY_SIZE(pwm_meson8b_parent_names),
379};
380
381static const char * const pwm_gxbb_parent_names[] = {
382 "xtal", "hdmi_pll", "fclk_div4", "fclk_div3"
383};
384
385static const struct meson_pwm_data pwm_gxbb_data = {
386 .parent_names = pwm_gxbb_parent_names,
387 .num_parents = ARRAY_SIZE(pwm_gxbb_parent_names),
388};
389
390/*
391 * Only the 2 first inputs of the GXBB AO PWMs are valid
392 * The last 2 are grounded
393 */
394static const char * const pwm_gxbb_ao_parent_names[] = {
395 "xtal", "clk81"
396};
397
398static const struct meson_pwm_data pwm_gxbb_ao_data = {
399 .parent_names = pwm_gxbb_ao_parent_names,
400 .num_parents = ARRAY_SIZE(pwm_gxbb_ao_parent_names),
401};
402
403static const char * const pwm_axg_ee_parent_names[] = {
404 "xtal", "fclk_div5", "fclk_div4", "fclk_div3"
405};
406
407static const struct meson_pwm_data pwm_axg_ee_data = {
408 .parent_names = pwm_axg_ee_parent_names,
409 .num_parents = ARRAY_SIZE(pwm_axg_ee_parent_names),
410};
411
412static const char * const pwm_axg_ao_parent_names[] = {
413 "aoclk81", "xtal", "fclk_div4", "fclk_div5"
414};
415
416static const struct meson_pwm_data pwm_axg_ao_data = {
417 .parent_names = pwm_axg_ao_parent_names,
418 .num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names),
419};
420
421static const char * const pwm_g12a_ao_ab_parent_names[] = {
422 "xtal", "aoclk81", "fclk_div4", "fclk_div5"
423};
424
425static const struct meson_pwm_data pwm_g12a_ao_ab_data = {
426 .parent_names = pwm_g12a_ao_ab_parent_names,
427 .num_parents = ARRAY_SIZE(pwm_g12a_ao_ab_parent_names),
428};
429
430static const char * const pwm_g12a_ao_cd_parent_names[] = {
431 "xtal", "aoclk81",
432};
433
434static const struct meson_pwm_data pwm_g12a_ao_cd_data = {
435 .parent_names = pwm_g12a_ao_cd_parent_names,
436 .num_parents = ARRAY_SIZE(pwm_g12a_ao_cd_parent_names),
437};
438
439static const char * const pwm_g12a_ee_parent_names[] = {
440 "xtal", "hdmi_pll", "fclk_div4", "fclk_div3"
441};
442
443static const struct meson_pwm_data pwm_g12a_ee_data = {
444 .parent_names = pwm_g12a_ee_parent_names,
445 .num_parents = ARRAY_SIZE(pwm_g12a_ee_parent_names),
446};
447
448static const struct of_device_id meson_pwm_matches[] = {
449 {
450 .compatible = "amlogic,meson8b-pwm",
451 .data = &pwm_meson8b_data
452 },
453 {
454 .compatible = "amlogic,meson-gxbb-pwm",
455 .data = &pwm_gxbb_data
456 },
457 {
458 .compatible = "amlogic,meson-gxbb-ao-pwm",
459 .data = &pwm_gxbb_ao_data
460 },
461 {
462 .compatible = "amlogic,meson-axg-ee-pwm",
463 .data = &pwm_axg_ee_data
464 },
465 {
466 .compatible = "amlogic,meson-axg-ao-pwm",
467 .data = &pwm_axg_ao_data
468 },
469 {
470 .compatible = "amlogic,meson-g12a-ee-pwm",
471 .data = &pwm_g12a_ee_data
472 },
473 {
474 .compatible = "amlogic,meson-g12a-ao-pwm-ab",
475 .data = &pwm_g12a_ao_ab_data
476 },
477 {
478 .compatible = "amlogic,meson-g12a-ao-pwm-cd",
479 .data = &pwm_g12a_ao_cd_data
480 },
481 {},
482};
483MODULE_DEVICE_TABLE(of, meson_pwm_matches);
484
485static int meson_pwm_init_channels(struct meson_pwm *meson)
486{
487 struct device *dev = meson->chip.dev;
488 struct clk_init_data init;
489 unsigned int i;
490 char name[255];
491 int err;
492
493 for (i = 0; i < meson->chip.npwm; i++) {
494 struct meson_pwm_channel *channel = &meson->channels[i];
495
496 snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i);
497
498 init.name = name;
499 init.ops = &clk_mux_ops;
500 init.flags = 0;
501 init.parent_names = meson->data->parent_names;
502 init.num_parents = meson->data->num_parents;
503
504 channel->mux.reg = meson->base + REG_MISC_AB;
505 channel->mux.shift =
506 meson_pwm_per_channel_data[i].clk_sel_shift;
507 channel->mux.mask = MISC_CLK_SEL_MASK;
508 channel->mux.flags = 0;
509 channel->mux.lock = &meson->lock;
510 channel->mux.table = NULL;
511 channel->mux.hw.init = &init;
512
513 channel->clk = devm_clk_register(dev, &channel->mux.hw);
514 if (IS_ERR(channel->clk)) {
515 err = PTR_ERR(channel->clk);
516 dev_err(dev, "failed to register %s: %d\n", name, err);
517 return err;
518 }
519
520 snprintf(name, sizeof(name), "clkin%u", i);
521
522 channel->clk_parent = devm_clk_get_optional(dev, name);
523 if (IS_ERR(channel->clk_parent))
524 return PTR_ERR(channel->clk_parent);
525 }
526
527 return 0;
528}
529
530static int meson_pwm_probe(struct platform_device *pdev)
531{
532 struct meson_pwm *meson;
533 int err;
534
535 meson = devm_kzalloc(&pdev->dev, sizeof(*meson), GFP_KERNEL);
536 if (!meson)
537 return -ENOMEM;
538
539 meson->base = devm_platform_ioremap_resource(pdev, 0);
540 if (IS_ERR(meson->base))
541 return PTR_ERR(meson->base);
542
543 spin_lock_init(&meson->lock);
544 meson->chip.dev = &pdev->dev;
545 meson->chip.ops = &meson_pwm_ops;
546 meson->chip.npwm = MESON_NUM_PWMS;
547
548 meson->data = of_device_get_match_data(&pdev->dev);
549
550 err = meson_pwm_init_channels(meson);
551 if (err < 0)
552 return err;
553
554 err = devm_pwmchip_add(&pdev->dev, &meson->chip);
555 if (err < 0) {
556 dev_err(&pdev->dev, "failed to register PWM chip: %d\n", err);
557 return err;
558 }
559
560 return 0;
561}
562
563static struct platform_driver meson_pwm_driver = {
564 .driver = {
565 .name = "meson-pwm",
566 .of_match_table = meson_pwm_matches,
567 },
568 .probe = meson_pwm_probe,
569};
570module_platform_driver(meson_pwm_driver);
571
572MODULE_DESCRIPTION("Amlogic Meson PWM Generator driver");
573MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
574MODULE_LICENSE("Dual BSD/GPL");