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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2018, Intel Corporation. */
3
4#ifndef _ICE_TXRX_H_
5#define _ICE_TXRX_H_
6
7#define ICE_DFLT_IRQ_WORK 256
8#define ICE_RXBUF_2048 2048
9#define ICE_MAX_CHAINED_RX_BUFS 5
10#define ICE_MAX_BUF_TXD 8
11#define ICE_MIN_TX_LEN 17
12
13/* The size limit for a transmit buffer in a descriptor is (16K - 1).
14 * In order to align with the read requests we will align the value to
15 * the nearest 4K which represents our maximum read request size.
16 */
17#define ICE_MAX_READ_REQ_SIZE 4096
18#define ICE_MAX_DATA_PER_TXD (16 * 1024 - 1)
19#define ICE_MAX_DATA_PER_TXD_ALIGNED \
20 (~(ICE_MAX_READ_REQ_SIZE - 1) & ICE_MAX_DATA_PER_TXD)
21
22#define ICE_RX_BUF_WRITE 16 /* Must be power of 2 */
23#define ICE_MAX_TXQ_PER_TXQG 128
24
25/* Tx Descriptors needed, worst case */
26#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
27#define ICE_DESC_UNUSED(R) \
28 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
29 (R)->next_to_clean - (R)->next_to_use - 1)
30
31#define ICE_TX_FLAGS_TSO BIT(0)
32#define ICE_TX_FLAGS_HW_VLAN BIT(1)
33#define ICE_TX_FLAGS_SW_VLAN BIT(2)
34#define ICE_TX_FLAGS_VLAN_M 0xffff0000
35#define ICE_TX_FLAGS_VLAN_S 16
36
37struct ice_tx_buf {
38 struct ice_tx_desc *next_to_watch;
39 struct sk_buff *skb;
40 unsigned int bytecount;
41 unsigned short gso_segs;
42 u32 tx_flags;
43 DEFINE_DMA_UNMAP_ADDR(dma);
44 DEFINE_DMA_UNMAP_LEN(len);
45};
46
47struct ice_tx_offload_params {
48 u8 header_len;
49 u32 td_cmd;
50 u32 td_offset;
51 u32 td_l2tag1;
52 u16 cd_l2tag2;
53 u32 cd_tunnel_params;
54 u64 cd_qw1;
55 struct ice_ring *tx_ring;
56};
57
58struct ice_rx_buf {
59 struct sk_buff *skb;
60 dma_addr_t dma;
61 struct page *page;
62 unsigned int page_offset;
63};
64
65struct ice_q_stats {
66 u64 pkts;
67 u64 bytes;
68};
69
70struct ice_txq_stats {
71 u64 restart_q;
72 u64 tx_busy;
73 u64 tx_linearize;
74};
75
76struct ice_rxq_stats {
77 u64 non_eop_descs;
78 u64 alloc_page_failed;
79 u64 alloc_buf_failed;
80 u64 page_reuse_count;
81};
82
83/* this enum matches hardware bits and is meant to be used by DYN_CTLN
84 * registers and QINT registers or more generally anywhere in the manual
85 * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any
86 * register but instead is a special value meaning "don't update" ITR0/1/2.
87 */
88enum ice_dyn_idx_t {
89 ICE_IDX_ITR0 = 0,
90 ICE_IDX_ITR1 = 1,
91 ICE_IDX_ITR2 = 2,
92 ICE_ITR_NONE = 3 /* ITR_NONE must not be used as an index */
93};
94
95/* Header split modes defined by DTYPE field of Rx RLAN context */
96enum ice_rx_dtype {
97 ICE_RX_DTYPE_NO_SPLIT = 0,
98 ICE_RX_DTYPE_HEADER_SPLIT = 1,
99 ICE_RX_DTYPE_SPLIT_ALWAYS = 2,
100};
101
102/* indices into GLINT_ITR registers */
103#define ICE_RX_ITR ICE_IDX_ITR0
104#define ICE_TX_ITR ICE_IDX_ITR1
105#define ICE_ITR_DYNAMIC 0x8000 /* use top bit as a flag */
106#define ICE_ITR_8K 0x003E
107
108/* apply ITR HW granularity translation to program the HW registers */
109#define ITR_TO_REG(val, itr_gran) (((val) & ~ICE_ITR_DYNAMIC) >> (itr_gran))
110
111/* Legacy or Advanced Mode Queue */
112#define ICE_TX_ADVANCED 0
113#define ICE_TX_LEGACY 1
114
115/* descriptor ring, associated with a VSI */
116struct ice_ring {
117 struct ice_ring *next; /* pointer to next ring in q_vector */
118 void *desc; /* Descriptor ring memory */
119 struct device *dev; /* Used for DMA mapping */
120 struct net_device *netdev; /* netdev ring maps to */
121 struct ice_vsi *vsi; /* Backreference to associated VSI */
122 struct ice_q_vector *q_vector; /* Backreference to associated vector */
123 u8 __iomem *tail;
124 union {
125 struct ice_tx_buf *tx_buf;
126 struct ice_rx_buf *rx_buf;
127 };
128 u16 q_index; /* Queue number of ring */
129 u32 txq_teid; /* Added Tx queue TEID */
130
131 /* high bit set means dynamic, use accessor routines to read/write.
132 * hardware supports 2us/1us resolution for the ITR registers.
133 * these values always store the USER setting, and must be converted
134 * before programming to a register.
135 */
136 u16 rx_itr_setting;
137 u16 tx_itr_setting;
138
139 u16 count; /* Number of descriptors */
140 u16 reg_idx; /* HW register index of the ring */
141
142 /* used in interrupt processing */
143 u16 next_to_use;
144 u16 next_to_clean;
145
146 bool ring_active; /* is ring online or not */
147
148 /* stats structs */
149 struct ice_q_stats stats;
150 struct u64_stats_sync syncp;
151 union {
152 struct ice_txq_stats tx_stats;
153 struct ice_rxq_stats rx_stats;
154 };
155
156 unsigned int size; /* length of descriptor ring in bytes */
157 dma_addr_t dma; /* physical address of ring */
158 struct rcu_head rcu; /* to avoid race on free */
159 u16 next_to_alloc;
160} ____cacheline_internodealigned_in_smp;
161
162enum ice_latency_range {
163 ICE_LOWEST_LATENCY = 0,
164 ICE_LOW_LATENCY = 1,
165 ICE_BULK_LATENCY = 2,
166 ICE_ULTRA_LATENCY = 3,
167};
168
169struct ice_ring_container {
170 /* array of pointers to rings */
171 struct ice_ring *ring;
172 unsigned int total_bytes; /* total bytes processed this int */
173 unsigned int total_pkts; /* total packets processed this int */
174 enum ice_latency_range latency_range;
175 u16 itr;
176};
177
178/* iterator for handling rings in ring container */
179#define ice_for_each_ring(pos, head) \
180 for (pos = (head).ring; pos; pos = pos->next)
181
182bool ice_alloc_rx_bufs(struct ice_ring *rxr, u16 cleaned_count);
183netdev_tx_t ice_start_xmit(struct sk_buff *skb, struct net_device *netdev);
184void ice_clean_tx_ring(struct ice_ring *tx_ring);
185void ice_clean_rx_ring(struct ice_ring *rx_ring);
186int ice_setup_tx_ring(struct ice_ring *tx_ring);
187int ice_setup_rx_ring(struct ice_ring *rx_ring);
188void ice_free_tx_ring(struct ice_ring *tx_ring);
189void ice_free_rx_ring(struct ice_ring *rx_ring);
190int ice_napi_poll(struct napi_struct *napi, int budget);
191
192#endif /* _ICE_TXRX_H_ */
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2018, Intel Corporation. */
3
4#ifndef _ICE_TXRX_H_
5#define _ICE_TXRX_H_
6
7#include "ice_type.h"
8
9#define ICE_DFLT_IRQ_WORK 256
10#define ICE_RXBUF_3072 3072
11#define ICE_RXBUF_2048 2048
12#define ICE_RXBUF_1536 1536
13#define ICE_MAX_CHAINED_RX_BUFS 5
14#define ICE_MAX_BUF_TXD 8
15#define ICE_MIN_TX_LEN 17
16
17/* The size limit for a transmit buffer in a descriptor is (16K - 1).
18 * In order to align with the read requests we will align the value to
19 * the nearest 4K which represents our maximum read request size.
20 */
21#define ICE_MAX_READ_REQ_SIZE 4096
22#define ICE_MAX_DATA_PER_TXD (16 * 1024 - 1)
23#define ICE_MAX_DATA_PER_TXD_ALIGNED \
24 (~(ICE_MAX_READ_REQ_SIZE - 1) & ICE_MAX_DATA_PER_TXD)
25
26#define ICE_MAX_TXQ_PER_TXQG 128
27
28/* Attempt to maximize the headroom available for incoming frames. We use a 2K
29 * buffer for MTUs <= 1500 and need 1536/1534 to store the data for the frame.
30 * This leaves us with 512 bytes of room. From that we need to deduct the
31 * space needed for the shared info and the padding needed to IP align the
32 * frame.
33 *
34 * Note: For cache line sizes 256 or larger this value is going to end
35 * up negative. In these cases we should fall back to the legacy
36 * receive path.
37 */
38#if (PAGE_SIZE < 8192)
39#define ICE_2K_TOO_SMALL_WITH_PADDING \
40 ((unsigned int)(NET_SKB_PAD + ICE_RXBUF_1536) > \
41 SKB_WITH_OVERHEAD(ICE_RXBUF_2048))
42
43/**
44 * ice_compute_pad - compute the padding
45 * @rx_buf_len: buffer length
46 *
47 * Figure out the size of half page based on given buffer length and
48 * then subtract the skb_shared_info followed by subtraction of the
49 * actual buffer length; this in turn results in the actual space that
50 * is left for padding usage
51 */
52static inline int ice_compute_pad(int rx_buf_len)
53{
54 int half_page_size;
55
56 half_page_size = ALIGN(rx_buf_len, PAGE_SIZE / 2);
57 return SKB_WITH_OVERHEAD(half_page_size) - rx_buf_len;
58}
59
60/**
61 * ice_skb_pad - determine the padding that we can supply
62 *
63 * Figure out the right Rx buffer size and based on that calculate the
64 * padding
65 */
66static inline int ice_skb_pad(void)
67{
68 int rx_buf_len;
69
70 /* If a 2K buffer cannot handle a standard Ethernet frame then
71 * optimize padding for a 3K buffer instead of a 1.5K buffer.
72 *
73 * For a 3K buffer we need to add enough padding to allow for
74 * tailroom due to NET_IP_ALIGN possibly shifting us out of
75 * cache-line alignment.
76 */
77 if (ICE_2K_TOO_SMALL_WITH_PADDING)
78 rx_buf_len = ICE_RXBUF_3072 + SKB_DATA_ALIGN(NET_IP_ALIGN);
79 else
80 rx_buf_len = ICE_RXBUF_1536;
81
82 /* if needed make room for NET_IP_ALIGN */
83 rx_buf_len -= NET_IP_ALIGN;
84
85 return ice_compute_pad(rx_buf_len);
86}
87
88#define ICE_SKB_PAD ice_skb_pad()
89#else
90#define ICE_2K_TOO_SMALL_WITH_PADDING false
91#define ICE_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
92#endif
93
94/* We are assuming that the cache line is always 64 Bytes here for ice.
95 * In order to make sure that is a correct assumption there is a check in probe
96 * to print a warning if the read from GLPCI_CNF2 tells us that the cache line
97 * size is 128 bytes. We do it this way because we do not want to read the
98 * GLPCI_CNF2 register or a variable containing the value on every pass through
99 * the Tx path.
100 */
101#define ICE_CACHE_LINE_BYTES 64
102#define ICE_DESCS_PER_CACHE_LINE (ICE_CACHE_LINE_BYTES / \
103 sizeof(struct ice_tx_desc))
104#define ICE_DESCS_FOR_CTX_DESC 1
105#define ICE_DESCS_FOR_SKB_DATA_PTR 1
106/* Tx descriptors needed, worst case */
107#define DESC_NEEDED (MAX_SKB_FRAGS + ICE_DESCS_FOR_CTX_DESC + \
108 ICE_DESCS_PER_CACHE_LINE + ICE_DESCS_FOR_SKB_DATA_PTR)
109#define ICE_DESC_UNUSED(R) \
110 (u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
111 (R)->next_to_clean - (R)->next_to_use - 1)
112
113#define ICE_RING_QUARTER(R) ((R)->count >> 2)
114
115#define ICE_TX_FLAGS_TSO BIT(0)
116#define ICE_TX_FLAGS_HW_VLAN BIT(1)
117#define ICE_TX_FLAGS_SW_VLAN BIT(2)
118/* ICE_TX_FLAGS_DUMMY_PKT is used to mark dummy packets that should be
119 * freed instead of returned like skb packets.
120 */
121#define ICE_TX_FLAGS_DUMMY_PKT BIT(3)
122#define ICE_TX_FLAGS_TSYN BIT(4)
123#define ICE_TX_FLAGS_IPV4 BIT(5)
124#define ICE_TX_FLAGS_IPV6 BIT(6)
125#define ICE_TX_FLAGS_TUNNEL BIT(7)
126#define ICE_TX_FLAGS_HW_OUTER_SINGLE_VLAN BIT(8)
127#define ICE_TX_FLAGS_VLAN_M 0xffff0000
128#define ICE_TX_FLAGS_VLAN_PR_M 0xe0000000
129#define ICE_TX_FLAGS_VLAN_PR_S 29
130#define ICE_TX_FLAGS_VLAN_S 16
131
132#define ICE_XDP_PASS 0
133#define ICE_XDP_CONSUMED BIT(0)
134#define ICE_XDP_TX BIT(1)
135#define ICE_XDP_REDIR BIT(2)
136#define ICE_XDP_EXIT BIT(3)
137
138#define ICE_RX_DMA_ATTR \
139 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
140
141#define ICE_ETH_PKT_HDR_PAD (ETH_HLEN + ETH_FCS_LEN + (VLAN_HLEN * 2))
142
143#define ICE_TXD_LAST_DESC_CMD (ICE_TX_DESC_CMD_EOP | ICE_TX_DESC_CMD_RS)
144
145struct ice_tx_buf {
146 struct ice_tx_desc *next_to_watch;
147 union {
148 struct sk_buff *skb;
149 void *raw_buf; /* used for XDP */
150 };
151 unsigned int bytecount;
152 unsigned short gso_segs;
153 u32 tx_flags;
154 DEFINE_DMA_UNMAP_LEN(len);
155 DEFINE_DMA_UNMAP_ADDR(dma);
156};
157
158struct ice_tx_offload_params {
159 u64 cd_qw1;
160 struct ice_tx_ring *tx_ring;
161 u32 td_cmd;
162 u32 td_offset;
163 u32 td_l2tag1;
164 u32 cd_tunnel_params;
165 u16 cd_l2tag2;
166 u8 header_len;
167};
168
169struct ice_rx_buf {
170 dma_addr_t dma;
171 struct page *page;
172 unsigned int page_offset;
173 u16 pagecnt_bias;
174};
175
176struct ice_q_stats {
177 u64 pkts;
178 u64 bytes;
179};
180
181struct ice_txq_stats {
182 u64 restart_q;
183 u64 tx_busy;
184 u64 tx_linearize;
185 int prev_pkt; /* negative if no pending Tx descriptors */
186};
187
188struct ice_rxq_stats {
189 u64 non_eop_descs;
190 u64 alloc_page_failed;
191 u64 alloc_buf_failed;
192};
193
194struct ice_ring_stats {
195 struct rcu_head rcu; /* to avoid race on free */
196 struct ice_q_stats stats;
197 struct u64_stats_sync syncp;
198 union {
199 struct ice_txq_stats tx_stats;
200 struct ice_rxq_stats rx_stats;
201 };
202};
203
204enum ice_ring_state_t {
205 ICE_TX_XPS_INIT_DONE,
206 ICE_TX_NBITS,
207};
208
209/* this enum matches hardware bits and is meant to be used by DYN_CTLN
210 * registers and QINT registers or more generally anywhere in the manual
211 * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any
212 * register but instead is a special value meaning "don't update" ITR0/1/2.
213 */
214enum ice_dyn_idx_t {
215 ICE_IDX_ITR0 = 0,
216 ICE_IDX_ITR1 = 1,
217 ICE_IDX_ITR2 = 2,
218 ICE_ITR_NONE = 3 /* ITR_NONE must not be used as an index */
219};
220
221/* Header split modes defined by DTYPE field of Rx RLAN context */
222enum ice_rx_dtype {
223 ICE_RX_DTYPE_NO_SPLIT = 0,
224 ICE_RX_DTYPE_HEADER_SPLIT = 1,
225 ICE_RX_DTYPE_SPLIT_ALWAYS = 2,
226};
227
228/* indices into GLINT_ITR registers */
229#define ICE_RX_ITR ICE_IDX_ITR0
230#define ICE_TX_ITR ICE_IDX_ITR1
231#define ICE_ITR_8K 124
232#define ICE_ITR_20K 50
233#define ICE_ITR_MAX 8160 /* 0x1FE0 */
234#define ICE_DFLT_TX_ITR ICE_ITR_20K
235#define ICE_DFLT_RX_ITR ICE_ITR_20K
236enum ice_dynamic_itr {
237 ITR_STATIC = 0,
238 ITR_DYNAMIC = 1
239};
240
241#define ITR_IS_DYNAMIC(rc) ((rc)->itr_mode == ITR_DYNAMIC)
242#define ICE_ITR_GRAN_S 1 /* ITR granularity is always 2us */
243#define ICE_ITR_GRAN_US BIT(ICE_ITR_GRAN_S)
244#define ICE_ITR_MASK 0x1FFE /* ITR register value alignment mask */
245#define ITR_REG_ALIGN(setting) ((setting) & ICE_ITR_MASK)
246
247#define ICE_DFLT_INTRL 0
248#define ICE_MAX_INTRL 236
249
250#define ICE_IN_WB_ON_ITR_MODE 255
251/* Sets WB_ON_ITR and assumes INTENA bit is already cleared, which allows
252 * setting the MSK_M bit to tell hardware to ignore the INTENA_M bit. Also,
253 * set the write-back latency to the usecs passed in.
254 */
255#define ICE_GLINT_DYN_CTL_WB_ON_ITR(usecs, itr_idx) \
256 ((((usecs) << (GLINT_DYN_CTL_INTERVAL_S - ICE_ITR_GRAN_S)) & \
257 GLINT_DYN_CTL_INTERVAL_M) | \
258 (((itr_idx) << GLINT_DYN_CTL_ITR_INDX_S) & \
259 GLINT_DYN_CTL_ITR_INDX_M) | GLINT_DYN_CTL_INTENA_MSK_M | \
260 GLINT_DYN_CTL_WB_ON_ITR_M)
261
262/* Legacy or Advanced Mode Queue */
263#define ICE_TX_ADVANCED 0
264#define ICE_TX_LEGACY 1
265
266/* descriptor ring, associated with a VSI */
267struct ice_rx_ring {
268 /* CL1 - 1st cacheline starts here */
269 struct ice_rx_ring *next; /* pointer to next ring in q_vector */
270 void *desc; /* Descriptor ring memory */
271 struct device *dev; /* Used for DMA mapping */
272 struct net_device *netdev; /* netdev ring maps to */
273 struct ice_vsi *vsi; /* Backreference to associated VSI */
274 struct ice_q_vector *q_vector; /* Backreference to associated vector */
275 u8 __iomem *tail;
276 union {
277 struct ice_rx_buf *rx_buf;
278 struct xdp_buff **xdp_buf;
279 };
280 /* CL2 - 2nd cacheline starts here */
281 struct xdp_rxq_info xdp_rxq;
282 /* CL3 - 3rd cacheline starts here */
283 u16 q_index; /* Queue number of ring */
284
285 u16 count; /* Number of descriptors */
286 u16 reg_idx; /* HW register index of the ring */
287
288 /* used in interrupt processing */
289 u16 next_to_use;
290 u16 next_to_clean;
291 u16 next_to_alloc;
292 u16 rx_offset;
293 u16 rx_buf_len;
294
295 /* stats structs */
296 struct ice_ring_stats *ring_stats;
297
298 struct rcu_head rcu; /* to avoid race on free */
299 /* CL4 - 3rd cacheline starts here */
300 struct ice_channel *ch;
301 struct bpf_prog *xdp_prog;
302 struct ice_tx_ring *xdp_ring;
303 struct xsk_buff_pool *xsk_pool;
304 struct sk_buff *skb;
305 dma_addr_t dma; /* physical address of ring */
306 u64 cached_phctime;
307 u8 dcb_tc; /* Traffic class of ring */
308 u8 ptp_rx;
309#define ICE_RX_FLAGS_RING_BUILD_SKB BIT(1)
310#define ICE_RX_FLAGS_CRC_STRIP_DIS BIT(2)
311 u8 flags;
312} ____cacheline_internodealigned_in_smp;
313
314struct ice_tx_ring {
315 /* CL1 - 1st cacheline starts here */
316 struct ice_tx_ring *next; /* pointer to next ring in q_vector */
317 void *desc; /* Descriptor ring memory */
318 struct device *dev; /* Used for DMA mapping */
319 u8 __iomem *tail;
320 struct ice_tx_buf *tx_buf;
321 struct ice_q_vector *q_vector; /* Backreference to associated vector */
322 struct net_device *netdev; /* netdev ring maps to */
323 struct ice_vsi *vsi; /* Backreference to associated VSI */
324 /* CL2 - 2nd cacheline starts here */
325 dma_addr_t dma; /* physical address of ring */
326 struct xsk_buff_pool *xsk_pool;
327 u16 next_to_use;
328 u16 next_to_clean;
329 u16 next_rs;
330 u16 next_dd;
331 u16 q_handle; /* Queue handle per TC */
332 u16 reg_idx; /* HW register index of the ring */
333 u16 count; /* Number of descriptors */
334 u16 q_index; /* Queue number of ring */
335 /* stats structs */
336 struct ice_ring_stats *ring_stats;
337 /* CL3 - 3rd cacheline starts here */
338 struct rcu_head rcu; /* to avoid race on free */
339 DECLARE_BITMAP(xps_state, ICE_TX_NBITS); /* XPS Config State */
340 struct ice_channel *ch;
341 struct ice_ptp_tx *tx_tstamps;
342 spinlock_t tx_lock;
343 u32 txq_teid; /* Added Tx queue TEID */
344 /* CL4 - 4th cacheline starts here */
345 u16 xdp_tx_active;
346#define ICE_TX_FLAGS_RING_XDP BIT(0)
347#define ICE_TX_FLAGS_RING_VLAN_L2TAG1 BIT(1)
348#define ICE_TX_FLAGS_RING_VLAN_L2TAG2 BIT(2)
349 u8 flags;
350 u8 dcb_tc; /* Traffic class of ring */
351 u8 ptp_tx;
352} ____cacheline_internodealigned_in_smp;
353
354static inline bool ice_ring_uses_build_skb(struct ice_rx_ring *ring)
355{
356 return !!(ring->flags & ICE_RX_FLAGS_RING_BUILD_SKB);
357}
358
359static inline void ice_set_ring_build_skb_ena(struct ice_rx_ring *ring)
360{
361 ring->flags |= ICE_RX_FLAGS_RING_BUILD_SKB;
362}
363
364static inline void ice_clear_ring_build_skb_ena(struct ice_rx_ring *ring)
365{
366 ring->flags &= ~ICE_RX_FLAGS_RING_BUILD_SKB;
367}
368
369static inline bool ice_ring_ch_enabled(struct ice_tx_ring *ring)
370{
371 return !!ring->ch;
372}
373
374static inline bool ice_ring_is_xdp(struct ice_tx_ring *ring)
375{
376 return !!(ring->flags & ICE_TX_FLAGS_RING_XDP);
377}
378
379enum ice_container_type {
380 ICE_RX_CONTAINER,
381 ICE_TX_CONTAINER,
382};
383
384struct ice_ring_container {
385 /* head of linked-list of rings */
386 union {
387 struct ice_rx_ring *rx_ring;
388 struct ice_tx_ring *tx_ring;
389 };
390 struct dim dim; /* data for net_dim algorithm */
391 u16 itr_idx; /* index in the interrupt vector */
392 /* this matches the maximum number of ITR bits, but in usec
393 * values, so it is shifted left one bit (bit zero is ignored)
394 */
395 union {
396 struct {
397 u16 itr_setting:13;
398 u16 itr_reserved:2;
399 u16 itr_mode:1;
400 };
401 u16 itr_settings;
402 };
403 enum ice_container_type type;
404};
405
406struct ice_coalesce_stored {
407 u16 itr_tx;
408 u16 itr_rx;
409 u8 intrl;
410 u8 tx_valid;
411 u8 rx_valid;
412};
413
414/* iterator for handling rings in ring container */
415#define ice_for_each_rx_ring(pos, head) \
416 for (pos = (head).rx_ring; pos; pos = pos->next)
417
418#define ice_for_each_tx_ring(pos, head) \
419 for (pos = (head).tx_ring; pos; pos = pos->next)
420
421static inline unsigned int ice_rx_pg_order(struct ice_rx_ring *ring)
422{
423#if (PAGE_SIZE < 8192)
424 if (ring->rx_buf_len > (PAGE_SIZE / 2))
425 return 1;
426#endif
427 return 0;
428}
429
430#define ice_rx_pg_size(_ring) (PAGE_SIZE << ice_rx_pg_order(_ring))
431
432union ice_32b_rx_flex_desc;
433
434bool ice_alloc_rx_bufs(struct ice_rx_ring *rxr, u16 cleaned_count);
435netdev_tx_t ice_start_xmit(struct sk_buff *skb, struct net_device *netdev);
436u16
437ice_select_queue(struct net_device *dev, struct sk_buff *skb,
438 struct net_device *sb_dev);
439void ice_clean_tx_ring(struct ice_tx_ring *tx_ring);
440void ice_clean_rx_ring(struct ice_rx_ring *rx_ring);
441int ice_setup_tx_ring(struct ice_tx_ring *tx_ring);
442int ice_setup_rx_ring(struct ice_rx_ring *rx_ring);
443void ice_free_tx_ring(struct ice_tx_ring *tx_ring);
444void ice_free_rx_ring(struct ice_rx_ring *rx_ring);
445int ice_napi_poll(struct napi_struct *napi, int budget);
446int
447ice_prgm_fdir_fltr(struct ice_vsi *vsi, struct ice_fltr_desc *fdir_desc,
448 u8 *raw_packet);
449int ice_clean_rx_irq(struct ice_rx_ring *rx_ring, int budget);
450void ice_clean_ctrl_tx_irq(struct ice_tx_ring *tx_ring);
451#endif /* _ICE_TXRX_H_ */