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1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __AMDGPU_TTM_H__
25#define __AMDGPU_TTM_H__
26
27#include "amdgpu.h"
28#include <drm/gpu_scheduler.h>
29
30#define AMDGPU_PL_GDS (TTM_PL_PRIV + 0)
31#define AMDGPU_PL_GWS (TTM_PL_PRIV + 1)
32#define AMDGPU_PL_OA (TTM_PL_PRIV + 2)
33
34#define AMDGPU_PL_FLAG_GDS (TTM_PL_FLAG_PRIV << 0)
35#define AMDGPU_PL_FLAG_GWS (TTM_PL_FLAG_PRIV << 1)
36#define AMDGPU_PL_FLAG_OA (TTM_PL_FLAG_PRIV << 2)
37
38#define AMDGPU_GTT_MAX_TRANSFER_SIZE 512
39#define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 2
40
41struct amdgpu_mman {
42 struct ttm_bo_global_ref bo_global_ref;
43 struct drm_global_reference mem_global_ref;
44 struct ttm_bo_device bdev;
45 bool mem_global_referenced;
46 bool initialized;
47 void __iomem *aper_base_kaddr;
48
49#if defined(CONFIG_DEBUG_FS)
50 struct dentry *debugfs_entries[8];
51#endif
52
53 /* buffer handling */
54 const struct amdgpu_buffer_funcs *buffer_funcs;
55 struct amdgpu_ring *buffer_funcs_ring;
56 bool buffer_funcs_enabled;
57
58 struct mutex gtt_window_lock;
59 /* Scheduler entity for buffer moves */
60 struct drm_sched_entity entity;
61};
62
63struct amdgpu_copy_mem {
64 struct ttm_buffer_object *bo;
65 struct ttm_mem_reg *mem;
66 unsigned long offset;
67};
68
69extern const struct ttm_mem_type_manager_func amdgpu_gtt_mgr_func;
70extern const struct ttm_mem_type_manager_func amdgpu_vram_mgr_func;
71
72bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_mem_reg *mem);
73uint64_t amdgpu_gtt_mgr_usage(struct ttm_mem_type_manager *man);
74int amdgpu_gtt_mgr_recover(struct ttm_mem_type_manager *man);
75
76uint64_t amdgpu_vram_mgr_usage(struct ttm_mem_type_manager *man);
77uint64_t amdgpu_vram_mgr_vis_usage(struct ttm_mem_type_manager *man);
78
79int amdgpu_ttm_init(struct amdgpu_device *adev);
80void amdgpu_ttm_fini(struct amdgpu_device *adev);
81void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev,
82 bool enable);
83
84int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
85 uint64_t dst_offset, uint32_t byte_count,
86 struct reservation_object *resv,
87 struct dma_fence **fence, bool direct_submit,
88 bool vm_needs_flush);
89int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
90 struct amdgpu_copy_mem *src,
91 struct amdgpu_copy_mem *dst,
92 uint64_t size,
93 struct reservation_object *resv,
94 struct dma_fence **f);
95int amdgpu_fill_buffer(struct amdgpu_bo *bo,
96 uint32_t src_data,
97 struct reservation_object *resv,
98 struct dma_fence **fence);
99
100int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
101int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
102int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);
103
104int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
105void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages);
106void amdgpu_ttm_tt_mark_user_pages(struct ttm_tt *ttm);
107int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
108 uint32_t flags);
109bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
110struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
111bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
112 unsigned long end);
113bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
114 int *last_invalidated);
115bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm);
116bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
117uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
118 struct ttm_mem_reg *mem);
119
120#endif
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __AMDGPU_TTM_H__
25#define __AMDGPU_TTM_H__
26
27#include <linux/dma-direction.h>
28#include <drm/gpu_scheduler.h>
29#include "amdgpu_vram_mgr.h"
30#include "amdgpu.h"
31
32#define AMDGPU_PL_GDS (TTM_PL_PRIV + 0)
33#define AMDGPU_PL_GWS (TTM_PL_PRIV + 1)
34#define AMDGPU_PL_OA (TTM_PL_PRIV + 2)
35#define AMDGPU_PL_PREEMPT (TTM_PL_PRIV + 3)
36
37#define AMDGPU_GTT_MAX_TRANSFER_SIZE 512
38#define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 2
39
40#define AMDGPU_POISON 0xd0bed0be
41
42struct hmm_range;
43
44struct amdgpu_gtt_mgr {
45 struct ttm_resource_manager manager;
46 struct drm_mm mm;
47 spinlock_t lock;
48};
49
50struct amdgpu_mman {
51 struct ttm_device bdev;
52 bool initialized;
53 void __iomem *aper_base_kaddr;
54
55 /* buffer handling */
56 const struct amdgpu_buffer_funcs *buffer_funcs;
57 struct amdgpu_ring *buffer_funcs_ring;
58 bool buffer_funcs_enabled;
59
60 struct mutex gtt_window_lock;
61 /* Scheduler entity for buffer moves */
62 struct drm_sched_entity entity;
63
64 struct amdgpu_vram_mgr vram_mgr;
65 struct amdgpu_gtt_mgr gtt_mgr;
66 struct ttm_resource_manager preempt_mgr;
67
68 uint64_t stolen_vga_size;
69 struct amdgpu_bo *stolen_vga_memory;
70 uint64_t stolen_extended_size;
71 struct amdgpu_bo *stolen_extended_memory;
72 bool keep_stolen_vga_memory;
73
74 struct amdgpu_bo *stolen_reserved_memory;
75 uint64_t stolen_reserved_offset;
76 uint64_t stolen_reserved_size;
77
78 /* discovery */
79 uint8_t *discovery_bin;
80 uint32_t discovery_tmr_size;
81 struct amdgpu_bo *discovery_memory;
82
83 /* firmware VRAM reservation */
84 u64 fw_vram_usage_start_offset;
85 u64 fw_vram_usage_size;
86 struct amdgpu_bo *fw_vram_usage_reserved_bo;
87 void *fw_vram_usage_va;
88
89 /* driver VRAM reservation */
90 u64 drv_vram_usage_start_offset;
91 u64 drv_vram_usage_size;
92 struct amdgpu_bo *drv_vram_usage_reserved_bo;
93 void *drv_vram_usage_va;
94
95 /* PAGE_SIZE'd BO for process memory r/w over SDMA. */
96 struct amdgpu_bo *sdma_access_bo;
97 void *sdma_access_ptr;
98};
99
100struct amdgpu_copy_mem {
101 struct ttm_buffer_object *bo;
102 struct ttm_resource *mem;
103 unsigned long offset;
104};
105
106int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size);
107void amdgpu_gtt_mgr_fini(struct amdgpu_device *adev);
108int amdgpu_preempt_mgr_init(struct amdgpu_device *adev);
109void amdgpu_preempt_mgr_fini(struct amdgpu_device *adev);
110int amdgpu_vram_mgr_init(struct amdgpu_device *adev);
111void amdgpu_vram_mgr_fini(struct amdgpu_device *adev);
112
113bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_resource *mem);
114void amdgpu_gtt_mgr_recover(struct amdgpu_gtt_mgr *mgr);
115
116uint64_t amdgpu_preempt_mgr_usage(struct ttm_resource_manager *man);
117
118u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo);
119int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev,
120 struct ttm_resource *mem,
121 u64 offset, u64 size,
122 struct device *dev,
123 enum dma_data_direction dir,
124 struct sg_table **sgt);
125void amdgpu_vram_mgr_free_sgt(struct device *dev,
126 enum dma_data_direction dir,
127 struct sg_table *sgt);
128uint64_t amdgpu_vram_mgr_vis_usage(struct amdgpu_vram_mgr *mgr);
129int amdgpu_vram_mgr_reserve_range(struct amdgpu_vram_mgr *mgr,
130 uint64_t start, uint64_t size);
131int amdgpu_vram_mgr_query_page_status(struct amdgpu_vram_mgr *mgr,
132 uint64_t start);
133
134int amdgpu_ttm_init(struct amdgpu_device *adev);
135void amdgpu_ttm_fini(struct amdgpu_device *adev);
136void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev,
137 bool enable);
138
139int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
140 uint64_t dst_offset, uint32_t byte_count,
141 struct dma_resv *resv,
142 struct dma_fence **fence, bool direct_submit,
143 bool vm_needs_flush, bool tmz);
144int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
145 const struct amdgpu_copy_mem *src,
146 const struct amdgpu_copy_mem *dst,
147 uint64_t size, bool tmz,
148 struct dma_resv *resv,
149 struct dma_fence **f);
150int amdgpu_fill_buffer(struct amdgpu_bo *bo,
151 uint32_t src_data,
152 struct dma_resv *resv,
153 struct dma_fence **fence);
154
155int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
156void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);
157uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type);
158
159#if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
160int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages,
161 struct hmm_range **range);
162void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm,
163 struct hmm_range *range);
164bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm,
165 struct hmm_range *range);
166#else
167static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo,
168 struct page **pages,
169 struct hmm_range **range)
170{
171 return -EPERM;
172}
173static inline void amdgpu_ttm_tt_discard_user_pages(struct ttm_tt *ttm,
174 struct hmm_range *range)
175{
176}
177static inline bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm,
178 struct hmm_range *range)
179{
180 return false;
181}
182#endif
183
184void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages);
185int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo,
186 uint64_t *user_addr);
187int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
188 uint64_t addr, uint32_t flags);
189bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
190struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
191bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
192 unsigned long end, unsigned long *userptr);
193bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
194 int *last_invalidated);
195bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm);
196bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
197uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem);
198uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
199 struct ttm_resource *mem);
200int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type);
201
202void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
203
204#endif