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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_OBJECT_H__
29#define __AMDGPU_OBJECT_H__
30
31#include <drm/amdgpu_drm.h>
32#include "amdgpu.h"
33
34#define AMDGPU_BO_INVALID_OFFSET LONG_MAX
35
36/* bo virtual addresses in a vm */
37struct amdgpu_bo_va_mapping {
38 struct amdgpu_bo_va *bo_va;
39 struct list_head list;
40 struct rb_node rb;
41 uint64_t start;
42 uint64_t last;
43 uint64_t __subtree_last;
44 uint64_t offset;
45 uint64_t flags;
46};
47
48/* User space allocated BO in a VM */
49struct amdgpu_bo_va {
50 struct amdgpu_vm_bo_base base;
51
52 /* protected by bo being reserved */
53 unsigned ref_count;
54
55 /* all other members protected by the VM PD being reserved */
56 struct dma_fence *last_pt_update;
57
58 /* mappings for this bo_va */
59 struct list_head invalids;
60 struct list_head valids;
61
62 /* If the mappings are cleared or filled */
63 bool cleared;
64};
65
66struct amdgpu_bo {
67 /* Protected by tbo.reserved */
68 u32 preferred_domains;
69 u32 allowed_domains;
70 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
71 struct ttm_placement placement;
72 struct ttm_buffer_object tbo;
73 struct ttm_bo_kmap_obj kmap;
74 u64 flags;
75 unsigned pin_count;
76 u64 tiling_flags;
77 u64 metadata_flags;
78 void *metadata;
79 u32 metadata_size;
80 unsigned prime_shared_count;
81 /* list of all virtual address to which this bo is associated to */
82 struct list_head va;
83 /* Constant after initialization */
84 struct drm_gem_object gem_base;
85 struct amdgpu_bo *parent;
86 struct amdgpu_bo *shadow;
87
88 struct ttm_bo_kmap_obj dma_buf_vmap;
89 struct amdgpu_mn *mn;
90
91 union {
92 struct list_head mn_list;
93 struct list_head shadow_list;
94 };
95
96 struct kgd_mem *kfd_bo;
97};
98
99static inline struct amdgpu_bo *ttm_to_amdgpu_bo(struct ttm_buffer_object *tbo)
100{
101 return container_of(tbo, struct amdgpu_bo, tbo);
102}
103
104/**
105 * amdgpu_mem_type_to_domain - return domain corresponding to mem_type
106 * @mem_type: ttm memory type
107 *
108 * Returns corresponding domain of the ttm mem_type
109 */
110static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type)
111{
112 switch (mem_type) {
113 case TTM_PL_VRAM:
114 return AMDGPU_GEM_DOMAIN_VRAM;
115 case TTM_PL_TT:
116 return AMDGPU_GEM_DOMAIN_GTT;
117 case TTM_PL_SYSTEM:
118 return AMDGPU_GEM_DOMAIN_CPU;
119 case AMDGPU_PL_GDS:
120 return AMDGPU_GEM_DOMAIN_GDS;
121 case AMDGPU_PL_GWS:
122 return AMDGPU_GEM_DOMAIN_GWS;
123 case AMDGPU_PL_OA:
124 return AMDGPU_GEM_DOMAIN_OA;
125 default:
126 break;
127 }
128 return 0;
129}
130
131/**
132 * amdgpu_bo_reserve - reserve bo
133 * @bo: bo structure
134 * @no_intr: don't return -ERESTARTSYS on pending signal
135 *
136 * Returns:
137 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
138 * a signal. Release all buffer reservations and return to user-space.
139 */
140static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr)
141{
142 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
143 int r;
144
145 r = ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL);
146 if (unlikely(r != 0)) {
147 if (r != -ERESTARTSYS)
148 dev_err(adev->dev, "%p reserve failed\n", bo);
149 return r;
150 }
151 return 0;
152}
153
154static inline void amdgpu_bo_unreserve(struct amdgpu_bo *bo)
155{
156 ttm_bo_unreserve(&bo->tbo);
157}
158
159static inline unsigned long amdgpu_bo_size(struct amdgpu_bo *bo)
160{
161 return bo->tbo.num_pages << PAGE_SHIFT;
162}
163
164static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo)
165{
166 return (bo->tbo.num_pages << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
167}
168
169static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo)
170{
171 return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
172}
173
174/**
175 * amdgpu_bo_mmap_offset - return mmap offset of bo
176 * @bo: amdgpu object for which we query the offset
177 *
178 * Returns mmap offset of the object.
179 */
180static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo)
181{
182 return drm_vma_node_offset_addr(&bo->tbo.vma_node);
183}
184
185/**
186 * amdgpu_bo_gpu_accessible - return whether the bo is currently in memory that
187 * is accessible to the GPU.
188 */
189static inline bool amdgpu_bo_gpu_accessible(struct amdgpu_bo *bo)
190{
191 switch (bo->tbo.mem.mem_type) {
192 case TTM_PL_TT: return amdgpu_gtt_mgr_has_gart_addr(&bo->tbo.mem);
193 case TTM_PL_VRAM: return true;
194 default: return false;
195 }
196}
197
198/**
199 * amdgpu_bo_explicit_sync - return whether the bo is explicitly synced
200 */
201static inline bool amdgpu_bo_explicit_sync(struct amdgpu_bo *bo)
202{
203 return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
204}
205
206int amdgpu_bo_create(struct amdgpu_device *adev, unsigned long size,
207 int byte_align, u32 domain,
208 u64 flags, enum ttm_bo_type type,
209 struct reservation_object *resv,
210 struct amdgpu_bo **bo_ptr);
211int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
212 unsigned long size, int align,
213 u32 domain, struct amdgpu_bo **bo_ptr,
214 u64 *gpu_addr, void **cpu_addr);
215int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
216 unsigned long size, int align,
217 u32 domain, struct amdgpu_bo **bo_ptr,
218 u64 *gpu_addr, void **cpu_addr);
219void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
220 void **cpu_addr);
221int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr);
222void *amdgpu_bo_kptr(struct amdgpu_bo *bo);
223void amdgpu_bo_kunmap(struct amdgpu_bo *bo);
224struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo);
225void amdgpu_bo_unref(struct amdgpu_bo **bo);
226int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr);
227int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
228 u64 min_offset, u64 max_offset,
229 u64 *gpu_addr);
230int amdgpu_bo_unpin(struct amdgpu_bo *bo);
231int amdgpu_bo_evict_vram(struct amdgpu_device *adev);
232int amdgpu_bo_init(struct amdgpu_device *adev);
233void amdgpu_bo_fini(struct amdgpu_device *adev);
234int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
235 struct vm_area_struct *vma);
236int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);
237void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);
238int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
239 uint32_t metadata_size, uint64_t flags);
240int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
241 size_t buffer_size, uint32_t *metadata_size,
242 uint64_t *flags);
243void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
244 bool evict,
245 struct ttm_mem_reg *new_mem);
246int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
247void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
248 bool shared);
249u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo);
250int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev,
251 struct amdgpu_ring *ring,
252 struct amdgpu_bo *bo,
253 struct reservation_object *resv,
254 struct dma_fence **fence, bool direct);
255int amdgpu_bo_validate(struct amdgpu_bo *bo);
256int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev,
257 struct amdgpu_ring *ring,
258 struct amdgpu_bo *bo,
259 struct reservation_object *resv,
260 struct dma_fence **fence,
261 bool direct);
262
263
264/*
265 * sub allocation
266 */
267
268static inline uint64_t amdgpu_sa_bo_gpu_addr(struct amdgpu_sa_bo *sa_bo)
269{
270 return sa_bo->manager->gpu_addr + sa_bo->soffset;
271}
272
273static inline void * amdgpu_sa_bo_cpu_addr(struct amdgpu_sa_bo *sa_bo)
274{
275 return sa_bo->manager->cpu_ptr + sa_bo->soffset;
276}
277
278int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
279 struct amdgpu_sa_manager *sa_manager,
280 unsigned size, u32 align, u32 domain);
281void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
282 struct amdgpu_sa_manager *sa_manager);
283int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev,
284 struct amdgpu_sa_manager *sa_manager);
285int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
286 struct amdgpu_sa_bo **sa_bo,
287 unsigned size, unsigned align);
288void amdgpu_sa_bo_free(struct amdgpu_device *adev,
289 struct amdgpu_sa_bo **sa_bo,
290 struct dma_fence *fence);
291#if defined(CONFIG_DEBUG_FS)
292void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
293 struct seq_file *m);
294#endif
295
296
297#endif
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_OBJECT_H__
29#define __AMDGPU_OBJECT_H__
30
31#include <drm/amdgpu_drm.h>
32#include "amdgpu.h"
33#include "amdgpu_res_cursor.h"
34
35#ifdef CONFIG_MMU_NOTIFIER
36#include <linux/mmu_notifier.h>
37#endif
38
39#define AMDGPU_BO_INVALID_OFFSET LONG_MAX
40#define AMDGPU_BO_MAX_PLACEMENTS 3
41
42/* BO flag to indicate a KFD userptr BO */
43#define AMDGPU_AMDKFD_CREATE_USERPTR_BO (1ULL << 63)
44
45#define to_amdgpu_bo_user(abo) container_of((abo), struct amdgpu_bo_user, bo)
46#define to_amdgpu_bo_vm(abo) container_of((abo), struct amdgpu_bo_vm, bo)
47
48struct amdgpu_bo_param {
49 unsigned long size;
50 int byte_align;
51 u32 bo_ptr_size;
52 u32 domain;
53 u32 preferred_domain;
54 u64 flags;
55 enum ttm_bo_type type;
56 bool no_wait_gpu;
57 struct dma_resv *resv;
58 void (*destroy)(struct ttm_buffer_object *bo);
59};
60
61/* bo virtual addresses in a vm */
62struct amdgpu_bo_va_mapping {
63 struct amdgpu_bo_va *bo_va;
64 struct list_head list;
65 struct rb_node rb;
66 uint64_t start;
67 uint64_t last;
68 uint64_t __subtree_last;
69 uint64_t offset;
70 uint64_t flags;
71};
72
73/* User space allocated BO in a VM */
74struct amdgpu_bo_va {
75 struct amdgpu_vm_bo_base base;
76
77 /* protected by bo being reserved */
78 unsigned ref_count;
79
80 /* all other members protected by the VM PD being reserved */
81 struct dma_fence *last_pt_update;
82
83 /* mappings for this bo_va */
84 struct list_head invalids;
85 struct list_head valids;
86
87 /* If the mappings are cleared or filled */
88 bool cleared;
89
90 bool is_xgmi;
91};
92
93struct amdgpu_bo {
94 /* Protected by tbo.reserved */
95 u32 preferred_domains;
96 u32 allowed_domains;
97 struct ttm_place placements[AMDGPU_BO_MAX_PLACEMENTS];
98 struct ttm_placement placement;
99 struct ttm_buffer_object tbo;
100 struct ttm_bo_kmap_obj kmap;
101 u64 flags;
102 /* per VM structure for page tables and with virtual addresses */
103 struct amdgpu_vm_bo_base *vm_bo;
104 /* Constant after initialization */
105 struct amdgpu_bo *parent;
106
107#ifdef CONFIG_MMU_NOTIFIER
108 struct mmu_interval_notifier notifier;
109#endif
110 struct kgd_mem *kfd_bo;
111};
112
113struct amdgpu_bo_user {
114 struct amdgpu_bo bo;
115 u64 tiling_flags;
116 u64 metadata_flags;
117 void *metadata;
118 u32 metadata_size;
119
120};
121
122struct amdgpu_bo_vm {
123 struct amdgpu_bo bo;
124 struct amdgpu_bo *shadow;
125 struct list_head shadow_list;
126 struct amdgpu_vm_bo_base entries[];
127};
128
129static inline struct amdgpu_bo *ttm_to_amdgpu_bo(struct ttm_buffer_object *tbo)
130{
131 return container_of(tbo, struct amdgpu_bo, tbo);
132}
133
134/**
135 * amdgpu_mem_type_to_domain - return domain corresponding to mem_type
136 * @mem_type: ttm memory type
137 *
138 * Returns corresponding domain of the ttm mem_type
139 */
140static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type)
141{
142 switch (mem_type) {
143 case TTM_PL_VRAM:
144 return AMDGPU_GEM_DOMAIN_VRAM;
145 case TTM_PL_TT:
146 return AMDGPU_GEM_DOMAIN_GTT;
147 case TTM_PL_SYSTEM:
148 return AMDGPU_GEM_DOMAIN_CPU;
149 case AMDGPU_PL_GDS:
150 return AMDGPU_GEM_DOMAIN_GDS;
151 case AMDGPU_PL_GWS:
152 return AMDGPU_GEM_DOMAIN_GWS;
153 case AMDGPU_PL_OA:
154 return AMDGPU_GEM_DOMAIN_OA;
155 default:
156 break;
157 }
158 return 0;
159}
160
161/**
162 * amdgpu_bo_reserve - reserve bo
163 * @bo: bo structure
164 * @no_intr: don't return -ERESTARTSYS on pending signal
165 *
166 * Returns:
167 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
168 * a signal. Release all buffer reservations and return to user-space.
169 */
170static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr)
171{
172 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
173 int r;
174
175 r = ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL);
176 if (unlikely(r != 0)) {
177 if (r != -ERESTARTSYS)
178 dev_err(adev->dev, "%p reserve failed\n", bo);
179 return r;
180 }
181 return 0;
182}
183
184static inline void amdgpu_bo_unreserve(struct amdgpu_bo *bo)
185{
186 ttm_bo_unreserve(&bo->tbo);
187}
188
189static inline unsigned long amdgpu_bo_size(struct amdgpu_bo *bo)
190{
191 return bo->tbo.base.size;
192}
193
194static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo)
195{
196 return bo->tbo.base.size / AMDGPU_GPU_PAGE_SIZE;
197}
198
199static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo)
200{
201 return (bo->tbo.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
202}
203
204/**
205 * amdgpu_bo_mmap_offset - return mmap offset of bo
206 * @bo: amdgpu object for which we query the offset
207 *
208 * Returns mmap offset of the object.
209 */
210static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo)
211{
212 return drm_vma_node_offset_addr(&bo->tbo.base.vma_node);
213}
214
215/**
216 * amdgpu_bo_in_cpu_visible_vram - check if BO is (partly) in visible VRAM
217 */
218static inline bool amdgpu_bo_in_cpu_visible_vram(struct amdgpu_bo *bo)
219{
220 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
221 struct amdgpu_res_cursor cursor;
222
223 if (bo->tbo.resource->mem_type != TTM_PL_VRAM)
224 return false;
225
226 amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &cursor);
227 while (cursor.remaining) {
228 if (cursor.start < adev->gmc.visible_vram_size)
229 return true;
230
231 amdgpu_res_next(&cursor, cursor.size);
232 }
233
234 return false;
235}
236
237/**
238 * amdgpu_bo_explicit_sync - return whether the bo is explicitly synced
239 */
240static inline bool amdgpu_bo_explicit_sync(struct amdgpu_bo *bo)
241{
242 return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
243}
244
245/**
246 * amdgpu_bo_encrypted - test if the BO is encrypted
247 * @bo: pointer to a buffer object
248 *
249 * Return true if the buffer object is encrypted, false otherwise.
250 */
251static inline bool amdgpu_bo_encrypted(struct amdgpu_bo *bo)
252{
253 return bo->flags & AMDGPU_GEM_CREATE_ENCRYPTED;
254}
255
256/**
257 * amdgpu_bo_shadowed - check if the BO is shadowed
258 *
259 * @bo: BO to be tested.
260 *
261 * Returns:
262 * NULL if not shadowed or else return a BO pointer.
263 */
264static inline struct amdgpu_bo *amdgpu_bo_shadowed(struct amdgpu_bo *bo)
265{
266 if (bo->tbo.type == ttm_bo_type_kernel)
267 return to_amdgpu_bo_vm(bo)->shadow;
268
269 return NULL;
270}
271
272bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
273void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
274
275int amdgpu_bo_create(struct amdgpu_device *adev,
276 struct amdgpu_bo_param *bp,
277 struct amdgpu_bo **bo_ptr);
278int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
279 unsigned long size, int align,
280 u32 domain, struct amdgpu_bo **bo_ptr,
281 u64 *gpu_addr, void **cpu_addr);
282int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
283 unsigned long size, int align,
284 u32 domain, struct amdgpu_bo **bo_ptr,
285 u64 *gpu_addr, void **cpu_addr);
286int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
287 uint64_t offset, uint64_t size,
288 struct amdgpu_bo **bo_ptr, void **cpu_addr);
289int amdgpu_bo_create_user(struct amdgpu_device *adev,
290 struct amdgpu_bo_param *bp,
291 struct amdgpu_bo_user **ubo_ptr);
292int amdgpu_bo_create_vm(struct amdgpu_device *adev,
293 struct amdgpu_bo_param *bp,
294 struct amdgpu_bo_vm **ubo_ptr);
295void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
296 void **cpu_addr);
297int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr);
298void *amdgpu_bo_kptr(struct amdgpu_bo *bo);
299void amdgpu_bo_kunmap(struct amdgpu_bo *bo);
300struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo);
301void amdgpu_bo_unref(struct amdgpu_bo **bo);
302int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain);
303int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
304 u64 min_offset, u64 max_offset);
305void amdgpu_bo_unpin(struct amdgpu_bo *bo);
306int amdgpu_bo_init(struct amdgpu_device *adev);
307void amdgpu_bo_fini(struct amdgpu_device *adev);
308int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);
309void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);
310int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
311 uint32_t metadata_size, uint64_t flags);
312int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
313 size_t buffer_size, uint32_t *metadata_size,
314 uint64_t *flags);
315void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
316 bool evict,
317 struct ttm_resource *new_mem);
318void amdgpu_bo_release_notify(struct ttm_buffer_object *bo);
319vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
320void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
321 bool shared);
322int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv,
323 enum amdgpu_sync_mode sync_mode, void *owner,
324 bool intr);
325int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr);
326u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo);
327u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo);
328void amdgpu_bo_get_memory(struct amdgpu_bo *bo, uint64_t *vram_mem,
329 uint64_t *gtt_mem, uint64_t *cpu_mem);
330void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm *vmbo);
331int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow,
332 struct dma_fence **fence);
333uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev,
334 uint32_t domain);
335
336/*
337 * sub allocation
338 */
339
340static inline uint64_t amdgpu_sa_bo_gpu_addr(struct amdgpu_sa_bo *sa_bo)
341{
342 return sa_bo->manager->gpu_addr + sa_bo->soffset;
343}
344
345static inline void * amdgpu_sa_bo_cpu_addr(struct amdgpu_sa_bo *sa_bo)
346{
347 return sa_bo->manager->cpu_ptr + sa_bo->soffset;
348}
349
350int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
351 struct amdgpu_sa_manager *sa_manager,
352 unsigned size, u32 align, u32 domain);
353void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
354 struct amdgpu_sa_manager *sa_manager);
355int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev,
356 struct amdgpu_sa_manager *sa_manager);
357int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
358 struct amdgpu_sa_bo **sa_bo,
359 unsigned size, unsigned align);
360void amdgpu_sa_bo_free(struct amdgpu_device *adev,
361 struct amdgpu_sa_bo **sa_bo,
362 struct dma_fence *fence);
363#if defined(CONFIG_DEBUG_FS)
364void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
365 struct seq_file *m);
366u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m);
367#endif
368void amdgpu_debugfs_sa_init(struct amdgpu_device *adev);
369
370bool amdgpu_bo_support_uswc(u64 bo_flags);
371
372
373#endif