1/* SPDX-License-Identifier: GPL-2.0 */
 2#ifndef _ASM_X86_CACHEINFO_H
 3#define _ASM_X86_CACHEINFO_H
 4
 5/* Kernel controls MTRR and/or PAT MSRs. */
 6extern unsigned int memory_caching_control;
 7#define CACHE_MTRR 0x01
 8#define CACHE_PAT  0x02
 9
10void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, int cpu);
11void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c, int cpu);
12
13void cache_disable(void);
14void cache_enable(void);
15void set_cache_aps_delayed_init(bool val);
16bool get_cache_aps_delayed_init(void);
17void cache_bp_init(void);
18void cache_bp_restore(void);
19void cache_aps_init(void);
20
21#endif /* _ASM_X86_CACHEINFO_H */