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1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _ASM_X86_BITOPS_H
3#define _ASM_X86_BITOPS_H
4
5/*
6 * Copyright 1992, Linus Torvalds.
7 *
8 * Note: inlines with more than a single statement should be marked
9 * __always_inline to avoid problems with older gcc's inlining heuristics.
10 */
11
12#ifndef _LINUX_BITOPS_H
13#error only <linux/bitops.h> can be included directly
14#endif
15
16#include <linux/compiler.h>
17#include <asm/alternative.h>
18#include <asm/rmwcc.h>
19#include <asm/barrier.h>
20
21#if BITS_PER_LONG == 32
22# define _BITOPS_LONG_SHIFT 5
23#elif BITS_PER_LONG == 64
24# define _BITOPS_LONG_SHIFT 6
25#else
26# error "Unexpected BITS_PER_LONG"
27#endif
28
29#define BIT_64(n) (U64_C(1) << (n))
30
31/*
32 * These have to be done with inline assembly: that way the bit-setting
33 * is guaranteed to be atomic. All bit operations return 0 if the bit
34 * was cleared before the operation and != 0 if it was not.
35 *
36 * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
37 */
38
39#if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ < 1)
40/* Technically wrong, but this avoids compilation errors on some gcc
41 versions. */
42#define BITOP_ADDR(x) "=m" (*(volatile long *) (x))
43#else
44#define BITOP_ADDR(x) "+m" (*(volatile long *) (x))
45#endif
46
47#define ADDR BITOP_ADDR(addr)
48
49/*
50 * We do the locked ops that don't return the old value as
51 * a mask operation on a byte.
52 */
53#define IS_IMMEDIATE(nr) (__builtin_constant_p(nr))
54#define CONST_MASK_ADDR(nr, addr) BITOP_ADDR((void *)(addr) + ((nr)>>3))
55#define CONST_MASK(nr) (1 << ((nr) & 7))
56
57/**
58 * set_bit - Atomically set a bit in memory
59 * @nr: the bit to set
60 * @addr: the address to start counting from
61 *
62 * This function is atomic and may not be reordered. See __set_bit()
63 * if you do not require the atomic guarantees.
64 *
65 * Note: there are no guarantees that this function will not be reordered
66 * on non x86 architectures, so if you are writing portable code,
67 * make sure not to rely on its reordering guarantees.
68 *
69 * Note that @nr may be almost arbitrarily large; this function is not
70 * restricted to acting on a single-word quantity.
71 */
72static __always_inline void
73set_bit(long nr, volatile unsigned long *addr)
74{
75 if (IS_IMMEDIATE(nr)) {
76 asm volatile(LOCK_PREFIX "orb %1,%0"
77 : CONST_MASK_ADDR(nr, addr)
78 : "iq" ((u8)CONST_MASK(nr))
79 : "memory");
80 } else {
81 asm volatile(LOCK_PREFIX __ASM_SIZE(bts) " %1,%0"
82 : BITOP_ADDR(addr) : "Ir" (nr) : "memory");
83 }
84}
85
86/**
87 * __set_bit - Set a bit in memory
88 * @nr: the bit to set
89 * @addr: the address to start counting from
90 *
91 * Unlike set_bit(), this function is non-atomic and may be reordered.
92 * If it's called on the same region of memory simultaneously, the effect
93 * may be that only one operation succeeds.
94 */
95static __always_inline void __set_bit(long nr, volatile unsigned long *addr)
96{
97 asm volatile(__ASM_SIZE(bts) " %1,%0" : ADDR : "Ir" (nr) : "memory");
98}
99
100/**
101 * clear_bit - Clears a bit in memory
102 * @nr: Bit to clear
103 * @addr: Address to start counting from
104 *
105 * clear_bit() is atomic and may not be reordered. However, it does
106 * not contain a memory barrier, so if it is used for locking purposes,
107 * you should call smp_mb__before_atomic() and/or smp_mb__after_atomic()
108 * in order to ensure changes are visible on other processors.
109 */
110static __always_inline void
111clear_bit(long nr, volatile unsigned long *addr)
112{
113 if (IS_IMMEDIATE(nr)) {
114 asm volatile(LOCK_PREFIX "andb %1,%0"
115 : CONST_MASK_ADDR(nr, addr)
116 : "iq" ((u8)~CONST_MASK(nr)));
117 } else {
118 asm volatile(LOCK_PREFIX __ASM_SIZE(btr) " %1,%0"
119 : BITOP_ADDR(addr)
120 : "Ir" (nr));
121 }
122}
123
124/*
125 * clear_bit_unlock - Clears a bit in memory
126 * @nr: Bit to clear
127 * @addr: Address to start counting from
128 *
129 * clear_bit() is atomic and implies release semantics before the memory
130 * operation. It can be used for an unlock.
131 */
132static __always_inline void clear_bit_unlock(long nr, volatile unsigned long *addr)
133{
134 barrier();
135 clear_bit(nr, addr);
136}
137
138static __always_inline void __clear_bit(long nr, volatile unsigned long *addr)
139{
140 asm volatile(__ASM_SIZE(btr) " %1,%0" : ADDR : "Ir" (nr));
141}
142
143static __always_inline bool clear_bit_unlock_is_negative_byte(long nr, volatile unsigned long *addr)
144{
145 bool negative;
146 asm volatile(LOCK_PREFIX "andb %2,%1"
147 CC_SET(s)
148 : CC_OUT(s) (negative), ADDR
149 : "ir" ((char) ~(1 << nr)) : "memory");
150 return negative;
151}
152
153// Let everybody know we have it
154#define clear_bit_unlock_is_negative_byte clear_bit_unlock_is_negative_byte
155
156/*
157 * __clear_bit_unlock - Clears a bit in memory
158 * @nr: Bit to clear
159 * @addr: Address to start counting from
160 *
161 * __clear_bit() is non-atomic and implies release semantics before the memory
162 * operation. It can be used for an unlock if no other CPUs can concurrently
163 * modify other bits in the word.
164 *
165 * No memory barrier is required here, because x86 cannot reorder stores past
166 * older loads. Same principle as spin_unlock.
167 */
168static __always_inline void __clear_bit_unlock(long nr, volatile unsigned long *addr)
169{
170 barrier();
171 __clear_bit(nr, addr);
172}
173
174/**
175 * __change_bit - Toggle a bit in memory
176 * @nr: the bit to change
177 * @addr: the address to start counting from
178 *
179 * Unlike change_bit(), this function is non-atomic and may be reordered.
180 * If it's called on the same region of memory simultaneously, the effect
181 * may be that only one operation succeeds.
182 */
183static __always_inline void __change_bit(long nr, volatile unsigned long *addr)
184{
185 asm volatile(__ASM_SIZE(btc) " %1,%0" : ADDR : "Ir" (nr));
186}
187
188/**
189 * change_bit - Toggle a bit in memory
190 * @nr: Bit to change
191 * @addr: Address to start counting from
192 *
193 * change_bit() is atomic and may not be reordered.
194 * Note that @nr may be almost arbitrarily large; this function is not
195 * restricted to acting on a single-word quantity.
196 */
197static __always_inline void change_bit(long nr, volatile unsigned long *addr)
198{
199 if (IS_IMMEDIATE(nr)) {
200 asm volatile(LOCK_PREFIX "xorb %1,%0"
201 : CONST_MASK_ADDR(nr, addr)
202 : "iq" ((u8)CONST_MASK(nr)));
203 } else {
204 asm volatile(LOCK_PREFIX __ASM_SIZE(btc) " %1,%0"
205 : BITOP_ADDR(addr)
206 : "Ir" (nr));
207 }
208}
209
210/**
211 * test_and_set_bit - Set a bit and return its old value
212 * @nr: Bit to set
213 * @addr: Address to count from
214 *
215 * This operation is atomic and cannot be reordered.
216 * It also implies a memory barrier.
217 */
218static __always_inline bool test_and_set_bit(long nr, volatile unsigned long *addr)
219{
220 GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(bts),
221 *addr, "Ir", nr, "%0", c);
222}
223
224/**
225 * test_and_set_bit_lock - Set a bit and return its old value for lock
226 * @nr: Bit to set
227 * @addr: Address to count from
228 *
229 * This is the same as test_and_set_bit on x86.
230 */
231static __always_inline bool
232test_and_set_bit_lock(long nr, volatile unsigned long *addr)
233{
234 return test_and_set_bit(nr, addr);
235}
236
237/**
238 * __test_and_set_bit - Set a bit and return its old value
239 * @nr: Bit to set
240 * @addr: Address to count from
241 *
242 * This operation is non-atomic and can be reordered.
243 * If two examples of this operation race, one can appear to succeed
244 * but actually fail. You must protect multiple accesses with a lock.
245 */
246static __always_inline bool __test_and_set_bit(long nr, volatile unsigned long *addr)
247{
248 bool oldbit;
249
250 asm(__ASM_SIZE(bts) " %2,%1"
251 CC_SET(c)
252 : CC_OUT(c) (oldbit), ADDR
253 : "Ir" (nr));
254 return oldbit;
255}
256
257/**
258 * test_and_clear_bit - Clear a bit and return its old value
259 * @nr: Bit to clear
260 * @addr: Address to count from
261 *
262 * This operation is atomic and cannot be reordered.
263 * It also implies a memory barrier.
264 */
265static __always_inline bool test_and_clear_bit(long nr, volatile unsigned long *addr)
266{
267 GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(btr),
268 *addr, "Ir", nr, "%0", c);
269}
270
271/**
272 * __test_and_clear_bit - Clear a bit and return its old value
273 * @nr: Bit to clear
274 * @addr: Address to count from
275 *
276 * This operation is non-atomic and can be reordered.
277 * If two examples of this operation race, one can appear to succeed
278 * but actually fail. You must protect multiple accesses with a lock.
279 *
280 * Note: the operation is performed atomically with respect to
281 * the local CPU, but not other CPUs. Portable code should not
282 * rely on this behaviour.
283 * KVM relies on this behaviour on x86 for modifying memory that is also
284 * accessed from a hypervisor on the same CPU if running in a VM: don't change
285 * this without also updating arch/x86/kernel/kvm.c
286 */
287static __always_inline bool __test_and_clear_bit(long nr, volatile unsigned long *addr)
288{
289 bool oldbit;
290
291 asm volatile(__ASM_SIZE(btr) " %2,%1"
292 CC_SET(c)
293 : CC_OUT(c) (oldbit), ADDR
294 : "Ir" (nr));
295 return oldbit;
296}
297
298/* WARNING: non atomic and it can be reordered! */
299static __always_inline bool __test_and_change_bit(long nr, volatile unsigned long *addr)
300{
301 bool oldbit;
302
303 asm volatile(__ASM_SIZE(btc) " %2,%1"
304 CC_SET(c)
305 : CC_OUT(c) (oldbit), ADDR
306 : "Ir" (nr) : "memory");
307
308 return oldbit;
309}
310
311/**
312 * test_and_change_bit - Change a bit and return its old value
313 * @nr: Bit to change
314 * @addr: Address to count from
315 *
316 * This operation is atomic and cannot be reordered.
317 * It also implies a memory barrier.
318 */
319static __always_inline bool test_and_change_bit(long nr, volatile unsigned long *addr)
320{
321 GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(btc),
322 *addr, "Ir", nr, "%0", c);
323}
324
325static __always_inline bool constant_test_bit(long nr, const volatile unsigned long *addr)
326{
327 return ((1UL << (nr & (BITS_PER_LONG-1))) &
328 (addr[nr >> _BITOPS_LONG_SHIFT])) != 0;
329}
330
331static __always_inline bool variable_test_bit(long nr, volatile const unsigned long *addr)
332{
333 bool oldbit;
334
335 asm volatile(__ASM_SIZE(bt) " %2,%1"
336 CC_SET(c)
337 : CC_OUT(c) (oldbit)
338 : "m" (*(unsigned long *)addr), "Ir" (nr));
339
340 return oldbit;
341}
342
343#if 0 /* Fool kernel-doc since it doesn't do macros yet */
344/**
345 * test_bit - Determine whether a bit is set
346 * @nr: bit number to test
347 * @addr: Address to start counting from
348 */
349static bool test_bit(int nr, const volatile unsigned long *addr);
350#endif
351
352#define test_bit(nr, addr) \
353 (__builtin_constant_p((nr)) \
354 ? constant_test_bit((nr), (addr)) \
355 : variable_test_bit((nr), (addr)))
356
357/**
358 * __ffs - find first set bit in word
359 * @word: The word to search
360 *
361 * Undefined if no bit exists, so code should check against 0 first.
362 */
363static __always_inline unsigned long __ffs(unsigned long word)
364{
365 asm("rep; bsf %1,%0"
366 : "=r" (word)
367 : "rm" (word));
368 return word;
369}
370
371/**
372 * ffz - find first zero bit in word
373 * @word: The word to search
374 *
375 * Undefined if no zero exists, so code should check against ~0UL first.
376 */
377static __always_inline unsigned long ffz(unsigned long word)
378{
379 asm("rep; bsf %1,%0"
380 : "=r" (word)
381 : "r" (~word));
382 return word;
383}
384
385/*
386 * __fls: find last set bit in word
387 * @word: The word to search
388 *
389 * Undefined if no set bit exists, so code should check against 0 first.
390 */
391static __always_inline unsigned long __fls(unsigned long word)
392{
393 asm("bsr %1,%0"
394 : "=r" (word)
395 : "rm" (word));
396 return word;
397}
398
399#undef ADDR
400
401#ifdef __KERNEL__
402/**
403 * ffs - find first set bit in word
404 * @x: the word to search
405 *
406 * This is defined the same way as the libc and compiler builtin ffs
407 * routines, therefore differs in spirit from the other bitops.
408 *
409 * ffs(value) returns 0 if value is 0 or the position of the first
410 * set bit if value is nonzero. The first (least significant) bit
411 * is at position 1.
412 */
413static __always_inline int ffs(int x)
414{
415 int r;
416
417#ifdef CONFIG_X86_64
418 /*
419 * AMD64 says BSFL won't clobber the dest reg if x==0; Intel64 says the
420 * dest reg is undefined if x==0, but their CPU architect says its
421 * value is written to set it to the same as before, except that the
422 * top 32 bits will be cleared.
423 *
424 * We cannot do this on 32 bits because at the very least some
425 * 486 CPUs did not behave this way.
426 */
427 asm("bsfl %1,%0"
428 : "=r" (r)
429 : "rm" (x), "0" (-1));
430#elif defined(CONFIG_X86_CMOV)
431 asm("bsfl %1,%0\n\t"
432 "cmovzl %2,%0"
433 : "=&r" (r) : "rm" (x), "r" (-1));
434#else
435 asm("bsfl %1,%0\n\t"
436 "jnz 1f\n\t"
437 "movl $-1,%0\n"
438 "1:" : "=r" (r) : "rm" (x));
439#endif
440 return r + 1;
441}
442
443/**
444 * fls - find last set bit in word
445 * @x: the word to search
446 *
447 * This is defined in a similar way as the libc and compiler builtin
448 * ffs, but returns the position of the most significant set bit.
449 *
450 * fls(value) returns 0 if value is 0 or the position of the last
451 * set bit if value is nonzero. The last (most significant) bit is
452 * at position 32.
453 */
454static __always_inline int fls(int x)
455{
456 int r;
457
458#ifdef CONFIG_X86_64
459 /*
460 * AMD64 says BSRL won't clobber the dest reg if x==0; Intel64 says the
461 * dest reg is undefined if x==0, but their CPU architect says its
462 * value is written to set it to the same as before, except that the
463 * top 32 bits will be cleared.
464 *
465 * We cannot do this on 32 bits because at the very least some
466 * 486 CPUs did not behave this way.
467 */
468 asm("bsrl %1,%0"
469 : "=r" (r)
470 : "rm" (x), "0" (-1));
471#elif defined(CONFIG_X86_CMOV)
472 asm("bsrl %1,%0\n\t"
473 "cmovzl %2,%0"
474 : "=&r" (r) : "rm" (x), "rm" (-1));
475#else
476 asm("bsrl %1,%0\n\t"
477 "jnz 1f\n\t"
478 "movl $-1,%0\n"
479 "1:" : "=r" (r) : "rm" (x));
480#endif
481 return r + 1;
482}
483
484/**
485 * fls64 - find last set bit in a 64-bit word
486 * @x: the word to search
487 *
488 * This is defined in a similar way as the libc and compiler builtin
489 * ffsll, but returns the position of the most significant set bit.
490 *
491 * fls64(value) returns 0 if value is 0 or the position of the last
492 * set bit if value is nonzero. The last (most significant) bit is
493 * at position 64.
494 */
495#ifdef CONFIG_X86_64
496static __always_inline int fls64(__u64 x)
497{
498 int bitpos = -1;
499 /*
500 * AMD64 says BSRQ won't clobber the dest reg if x==0; Intel64 says the
501 * dest reg is undefined if x==0, but their CPU architect says its
502 * value is written to set it to the same as before.
503 */
504 asm("bsrq %1,%q0"
505 : "+r" (bitpos)
506 : "rm" (x));
507 return bitpos + 1;
508}
509#else
510#include <asm-generic/bitops/fls64.h>
511#endif
512
513#include <asm-generic/bitops/find.h>
514
515#include <asm-generic/bitops/sched.h>
516
517#include <asm/arch_hweight.h>
518
519#include <asm-generic/bitops/const_hweight.h>
520
521#include <asm-generic/bitops/le.h>
522
523#include <asm-generic/bitops/ext2-atomic-setbit.h>
524
525#endif /* __KERNEL__ */
526#endif /* _ASM_X86_BITOPS_H */
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _ASM_X86_BITOPS_H
3#define _ASM_X86_BITOPS_H
4
5/*
6 * Copyright 1992, Linus Torvalds.
7 *
8 * Note: inlines with more than a single statement should be marked
9 * __always_inline to avoid problems with older gcc's inlining heuristics.
10 */
11
12#ifndef _LINUX_BITOPS_H
13#error only <linux/bitops.h> can be included directly
14#endif
15
16#include <linux/compiler.h>
17#include <asm/alternative.h>
18#include <asm/rmwcc.h>
19#include <asm/barrier.h>
20
21#if BITS_PER_LONG == 32
22# define _BITOPS_LONG_SHIFT 5
23#elif BITS_PER_LONG == 64
24# define _BITOPS_LONG_SHIFT 6
25#else
26# error "Unexpected BITS_PER_LONG"
27#endif
28
29#define BIT_64(n) (U64_C(1) << (n))
30
31/*
32 * These have to be done with inline assembly: that way the bit-setting
33 * is guaranteed to be atomic. All bit operations return 0 if the bit
34 * was cleared before the operation and != 0 if it was not.
35 *
36 * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
37 */
38
39#define RLONG_ADDR(x) "m" (*(volatile long *) (x))
40#define WBYTE_ADDR(x) "+m" (*(volatile char *) (x))
41
42#define ADDR RLONG_ADDR(addr)
43
44/*
45 * We do the locked ops that don't return the old value as
46 * a mask operation on a byte.
47 */
48#define CONST_MASK_ADDR(nr, addr) WBYTE_ADDR((void *)(addr) + ((nr)>>3))
49#define CONST_MASK(nr) (1 << ((nr) & 7))
50
51static __always_inline void
52arch_set_bit(long nr, volatile unsigned long *addr)
53{
54 if (__builtin_constant_p(nr)) {
55 asm volatile(LOCK_PREFIX "orb %b1,%0"
56 : CONST_MASK_ADDR(nr, addr)
57 : "iq" (CONST_MASK(nr))
58 : "memory");
59 } else {
60 asm volatile(LOCK_PREFIX __ASM_SIZE(bts) " %1,%0"
61 : : RLONG_ADDR(addr), "Ir" (nr) : "memory");
62 }
63}
64
65static __always_inline void
66arch___set_bit(unsigned long nr, volatile unsigned long *addr)
67{
68 asm volatile(__ASM_SIZE(bts) " %1,%0" : : ADDR, "Ir" (nr) : "memory");
69}
70
71static __always_inline void
72arch_clear_bit(long nr, volatile unsigned long *addr)
73{
74 if (__builtin_constant_p(nr)) {
75 asm volatile(LOCK_PREFIX "andb %b1,%0"
76 : CONST_MASK_ADDR(nr, addr)
77 : "iq" (~CONST_MASK(nr)));
78 } else {
79 asm volatile(LOCK_PREFIX __ASM_SIZE(btr) " %1,%0"
80 : : RLONG_ADDR(addr), "Ir" (nr) : "memory");
81 }
82}
83
84static __always_inline void
85arch_clear_bit_unlock(long nr, volatile unsigned long *addr)
86{
87 barrier();
88 arch_clear_bit(nr, addr);
89}
90
91static __always_inline void
92arch___clear_bit(unsigned long nr, volatile unsigned long *addr)
93{
94 asm volatile(__ASM_SIZE(btr) " %1,%0" : : ADDR, "Ir" (nr) : "memory");
95}
96
97static __always_inline bool
98arch_clear_bit_unlock_is_negative_byte(long nr, volatile unsigned long *addr)
99{
100 bool negative;
101 asm volatile(LOCK_PREFIX "andb %2,%1"
102 CC_SET(s)
103 : CC_OUT(s) (negative), WBYTE_ADDR(addr)
104 : "ir" ((char) ~(1 << nr)) : "memory");
105 return negative;
106}
107#define arch_clear_bit_unlock_is_negative_byte \
108 arch_clear_bit_unlock_is_negative_byte
109
110static __always_inline void
111arch___clear_bit_unlock(long nr, volatile unsigned long *addr)
112{
113 arch___clear_bit(nr, addr);
114}
115
116static __always_inline void
117arch___change_bit(unsigned long nr, volatile unsigned long *addr)
118{
119 asm volatile(__ASM_SIZE(btc) " %1,%0" : : ADDR, "Ir" (nr) : "memory");
120}
121
122static __always_inline void
123arch_change_bit(long nr, volatile unsigned long *addr)
124{
125 if (__builtin_constant_p(nr)) {
126 asm volatile(LOCK_PREFIX "xorb %b1,%0"
127 : CONST_MASK_ADDR(nr, addr)
128 : "iq" (CONST_MASK(nr)));
129 } else {
130 asm volatile(LOCK_PREFIX __ASM_SIZE(btc) " %1,%0"
131 : : RLONG_ADDR(addr), "Ir" (nr) : "memory");
132 }
133}
134
135static __always_inline bool
136arch_test_and_set_bit(long nr, volatile unsigned long *addr)
137{
138 return GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(bts), *addr, c, "Ir", nr);
139}
140
141static __always_inline bool
142arch_test_and_set_bit_lock(long nr, volatile unsigned long *addr)
143{
144 return arch_test_and_set_bit(nr, addr);
145}
146
147static __always_inline bool
148arch___test_and_set_bit(unsigned long nr, volatile unsigned long *addr)
149{
150 bool oldbit;
151
152 asm(__ASM_SIZE(bts) " %2,%1"
153 CC_SET(c)
154 : CC_OUT(c) (oldbit)
155 : ADDR, "Ir" (nr) : "memory");
156 return oldbit;
157}
158
159static __always_inline bool
160arch_test_and_clear_bit(long nr, volatile unsigned long *addr)
161{
162 return GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(btr), *addr, c, "Ir", nr);
163}
164
165/*
166 * Note: the operation is performed atomically with respect to
167 * the local CPU, but not other CPUs. Portable code should not
168 * rely on this behaviour.
169 * KVM relies on this behaviour on x86 for modifying memory that is also
170 * accessed from a hypervisor on the same CPU if running in a VM: don't change
171 * this without also updating arch/x86/kernel/kvm.c
172 */
173static __always_inline bool
174arch___test_and_clear_bit(unsigned long nr, volatile unsigned long *addr)
175{
176 bool oldbit;
177
178 asm volatile(__ASM_SIZE(btr) " %2,%1"
179 CC_SET(c)
180 : CC_OUT(c) (oldbit)
181 : ADDR, "Ir" (nr) : "memory");
182 return oldbit;
183}
184
185static __always_inline bool
186arch___test_and_change_bit(unsigned long nr, volatile unsigned long *addr)
187{
188 bool oldbit;
189
190 asm volatile(__ASM_SIZE(btc) " %2,%1"
191 CC_SET(c)
192 : CC_OUT(c) (oldbit)
193 : ADDR, "Ir" (nr) : "memory");
194
195 return oldbit;
196}
197
198static __always_inline bool
199arch_test_and_change_bit(long nr, volatile unsigned long *addr)
200{
201 return GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(btc), *addr, c, "Ir", nr);
202}
203
204static __always_inline bool constant_test_bit(long nr, const volatile unsigned long *addr)
205{
206 return ((1UL << (nr & (BITS_PER_LONG-1))) &
207 (addr[nr >> _BITOPS_LONG_SHIFT])) != 0;
208}
209
210static __always_inline bool constant_test_bit_acquire(long nr, const volatile unsigned long *addr)
211{
212 bool oldbit;
213
214 asm volatile("testb %2,%1"
215 CC_SET(nz)
216 : CC_OUT(nz) (oldbit)
217 : "m" (((unsigned char *)addr)[nr >> 3]),
218 "i" (1 << (nr & 7))
219 :"memory");
220
221 return oldbit;
222}
223
224static __always_inline bool variable_test_bit(long nr, volatile const unsigned long *addr)
225{
226 bool oldbit;
227
228 asm volatile(__ASM_SIZE(bt) " %2,%1"
229 CC_SET(c)
230 : CC_OUT(c) (oldbit)
231 : "m" (*(unsigned long *)addr), "Ir" (nr) : "memory");
232
233 return oldbit;
234}
235
236static __always_inline bool
237arch_test_bit(unsigned long nr, const volatile unsigned long *addr)
238{
239 return __builtin_constant_p(nr) ? constant_test_bit(nr, addr) :
240 variable_test_bit(nr, addr);
241}
242
243static __always_inline bool
244arch_test_bit_acquire(unsigned long nr, const volatile unsigned long *addr)
245{
246 return __builtin_constant_p(nr) ? constant_test_bit_acquire(nr, addr) :
247 variable_test_bit(nr, addr);
248}
249
250static __always_inline unsigned long variable__ffs(unsigned long word)
251{
252 asm("rep; bsf %1,%0"
253 : "=r" (word)
254 : "rm" (word));
255 return word;
256}
257
258/**
259 * __ffs - find first set bit in word
260 * @word: The word to search
261 *
262 * Undefined if no bit exists, so code should check against 0 first.
263 */
264#define __ffs(word) \
265 (__builtin_constant_p(word) ? \
266 (unsigned long)__builtin_ctzl(word) : \
267 variable__ffs(word))
268
269static __always_inline unsigned long variable_ffz(unsigned long word)
270{
271 asm("rep; bsf %1,%0"
272 : "=r" (word)
273 : "r" (~word));
274 return word;
275}
276
277/**
278 * ffz - find first zero bit in word
279 * @word: The word to search
280 *
281 * Undefined if no zero exists, so code should check against ~0UL first.
282 */
283#define ffz(word) \
284 (__builtin_constant_p(word) ? \
285 (unsigned long)__builtin_ctzl(~word) : \
286 variable_ffz(word))
287
288/*
289 * __fls: find last set bit in word
290 * @word: The word to search
291 *
292 * Undefined if no set bit exists, so code should check against 0 first.
293 */
294static __always_inline unsigned long __fls(unsigned long word)
295{
296 asm("bsr %1,%0"
297 : "=r" (word)
298 : "rm" (word));
299 return word;
300}
301
302#undef ADDR
303
304#ifdef __KERNEL__
305static __always_inline int variable_ffs(int x)
306{
307 int r;
308
309#ifdef CONFIG_X86_64
310 /*
311 * AMD64 says BSFL won't clobber the dest reg if x==0; Intel64 says the
312 * dest reg is undefined if x==0, but their CPU architect says its
313 * value is written to set it to the same as before, except that the
314 * top 32 bits will be cleared.
315 *
316 * We cannot do this on 32 bits because at the very least some
317 * 486 CPUs did not behave this way.
318 */
319 asm("bsfl %1,%0"
320 : "=r" (r)
321 : "rm" (x), "0" (-1));
322#elif defined(CONFIG_X86_CMOV)
323 asm("bsfl %1,%0\n\t"
324 "cmovzl %2,%0"
325 : "=&r" (r) : "rm" (x), "r" (-1));
326#else
327 asm("bsfl %1,%0\n\t"
328 "jnz 1f\n\t"
329 "movl $-1,%0\n"
330 "1:" : "=r" (r) : "rm" (x));
331#endif
332 return r + 1;
333}
334
335/**
336 * ffs - find first set bit in word
337 * @x: the word to search
338 *
339 * This is defined the same way as the libc and compiler builtin ffs
340 * routines, therefore differs in spirit from the other bitops.
341 *
342 * ffs(value) returns 0 if value is 0 or the position of the first
343 * set bit if value is nonzero. The first (least significant) bit
344 * is at position 1.
345 */
346#define ffs(x) (__builtin_constant_p(x) ? __builtin_ffs(x) : variable_ffs(x))
347
348/**
349 * fls - find last set bit in word
350 * @x: the word to search
351 *
352 * This is defined in a similar way as the libc and compiler builtin
353 * ffs, but returns the position of the most significant set bit.
354 *
355 * fls(value) returns 0 if value is 0 or the position of the last
356 * set bit if value is nonzero. The last (most significant) bit is
357 * at position 32.
358 */
359static __always_inline int fls(unsigned int x)
360{
361 int r;
362
363#ifdef CONFIG_X86_64
364 /*
365 * AMD64 says BSRL won't clobber the dest reg if x==0; Intel64 says the
366 * dest reg is undefined if x==0, but their CPU architect says its
367 * value is written to set it to the same as before, except that the
368 * top 32 bits will be cleared.
369 *
370 * We cannot do this on 32 bits because at the very least some
371 * 486 CPUs did not behave this way.
372 */
373 asm("bsrl %1,%0"
374 : "=r" (r)
375 : "rm" (x), "0" (-1));
376#elif defined(CONFIG_X86_CMOV)
377 asm("bsrl %1,%0\n\t"
378 "cmovzl %2,%0"
379 : "=&r" (r) : "rm" (x), "rm" (-1));
380#else
381 asm("bsrl %1,%0\n\t"
382 "jnz 1f\n\t"
383 "movl $-1,%0\n"
384 "1:" : "=r" (r) : "rm" (x));
385#endif
386 return r + 1;
387}
388
389/**
390 * fls64 - find last set bit in a 64-bit word
391 * @x: the word to search
392 *
393 * This is defined in a similar way as the libc and compiler builtin
394 * ffsll, but returns the position of the most significant set bit.
395 *
396 * fls64(value) returns 0 if value is 0 or the position of the last
397 * set bit if value is nonzero. The last (most significant) bit is
398 * at position 64.
399 */
400#ifdef CONFIG_X86_64
401static __always_inline int fls64(__u64 x)
402{
403 int bitpos = -1;
404 /*
405 * AMD64 says BSRQ won't clobber the dest reg if x==0; Intel64 says the
406 * dest reg is undefined if x==0, but their CPU architect says its
407 * value is written to set it to the same as before.
408 */
409 asm("bsrq %1,%q0"
410 : "+r" (bitpos)
411 : "rm" (x));
412 return bitpos + 1;
413}
414#else
415#include <asm-generic/bitops/fls64.h>
416#endif
417
418#include <asm-generic/bitops/sched.h>
419
420#include <asm/arch_hweight.h>
421
422#include <asm-generic/bitops/const_hweight.h>
423
424#include <asm-generic/bitops/instrumented-atomic.h>
425#include <asm-generic/bitops/instrumented-non-atomic.h>
426#include <asm-generic/bitops/instrumented-lock.h>
427
428#include <asm-generic/bitops/le.h>
429
430#include <asm-generic/bitops/ext2-atomic-setbit.h>
431
432#endif /* __KERNEL__ */
433#endif /* _ASM_X86_BITOPS_H */