Loading...
1/*
2 * Fault injection for both 32 and 64bit guests.
3 *
4 * Copyright (C) 2012,2013 - ARM Ltd
5 * Author: Marc Zyngier <marc.zyngier@arm.com>
6 *
7 * Based on arch/arm/kvm/emulate.c
8 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
9 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
10 *
11 * This program is free software: you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 */
23
24#include <linux/kvm_host.h>
25#include <asm/kvm_emulate.h>
26#include <asm/esr.h>
27
28#define PSTATE_FAULT_BITS_64 (PSR_MODE_EL1h | PSR_A_BIT | PSR_F_BIT | \
29 PSR_I_BIT | PSR_D_BIT)
30
31#define CURRENT_EL_SP_EL0_VECTOR 0x0
32#define CURRENT_EL_SP_ELx_VECTOR 0x200
33#define LOWER_EL_AArch64_VECTOR 0x400
34#define LOWER_EL_AArch32_VECTOR 0x600
35
36enum exception_type {
37 except_type_sync = 0,
38 except_type_irq = 0x80,
39 except_type_fiq = 0x100,
40 except_type_serror = 0x180,
41};
42
43static u64 get_except_vector(struct kvm_vcpu *vcpu, enum exception_type type)
44{
45 u64 exc_offset;
46
47 switch (*vcpu_cpsr(vcpu) & (PSR_MODE_MASK | PSR_MODE32_BIT)) {
48 case PSR_MODE_EL1t:
49 exc_offset = CURRENT_EL_SP_EL0_VECTOR;
50 break;
51 case PSR_MODE_EL1h:
52 exc_offset = CURRENT_EL_SP_ELx_VECTOR;
53 break;
54 case PSR_MODE_EL0t:
55 exc_offset = LOWER_EL_AArch64_VECTOR;
56 break;
57 default:
58 exc_offset = LOWER_EL_AArch32_VECTOR;
59 }
60
61 return vcpu_read_sys_reg(vcpu, VBAR_EL1) + exc_offset + type;
62}
63
64static void inject_abt64(struct kvm_vcpu *vcpu, bool is_iabt, unsigned long addr)
65{
66 unsigned long cpsr = *vcpu_cpsr(vcpu);
67 bool is_aarch32 = vcpu_mode_is_32bit(vcpu);
68 u32 esr = 0;
69
70 vcpu_write_elr_el1(vcpu, *vcpu_pc(vcpu));
71 *vcpu_pc(vcpu) = get_except_vector(vcpu, except_type_sync);
72
73 *vcpu_cpsr(vcpu) = PSTATE_FAULT_BITS_64;
74 vcpu_write_spsr(vcpu, cpsr);
75
76 vcpu_write_sys_reg(vcpu, addr, FAR_EL1);
77
78 /*
79 * Build an {i,d}abort, depending on the level and the
80 * instruction set. Report an external synchronous abort.
81 */
82 if (kvm_vcpu_trap_il_is32bit(vcpu))
83 esr |= ESR_ELx_IL;
84
85 /*
86 * Here, the guest runs in AArch64 mode when in EL1. If we get
87 * an AArch32 fault, it means we managed to trap an EL0 fault.
88 */
89 if (is_aarch32 || (cpsr & PSR_MODE_MASK) == PSR_MODE_EL0t)
90 esr |= (ESR_ELx_EC_IABT_LOW << ESR_ELx_EC_SHIFT);
91 else
92 esr |= (ESR_ELx_EC_IABT_CUR << ESR_ELx_EC_SHIFT);
93
94 if (!is_iabt)
95 esr |= ESR_ELx_EC_DABT_LOW << ESR_ELx_EC_SHIFT;
96
97 vcpu_write_sys_reg(vcpu, esr | ESR_ELx_FSC_EXTABT, ESR_EL1);
98}
99
100static void inject_undef64(struct kvm_vcpu *vcpu)
101{
102 unsigned long cpsr = *vcpu_cpsr(vcpu);
103 u32 esr = (ESR_ELx_EC_UNKNOWN << ESR_ELx_EC_SHIFT);
104
105 vcpu_write_elr_el1(vcpu, *vcpu_pc(vcpu));
106 *vcpu_pc(vcpu) = get_except_vector(vcpu, except_type_sync);
107
108 *vcpu_cpsr(vcpu) = PSTATE_FAULT_BITS_64;
109 vcpu_write_spsr(vcpu, cpsr);
110
111 /*
112 * Build an unknown exception, depending on the instruction
113 * set.
114 */
115 if (kvm_vcpu_trap_il_is32bit(vcpu))
116 esr |= ESR_ELx_IL;
117
118 vcpu_write_sys_reg(vcpu, esr, ESR_EL1);
119}
120
121/**
122 * kvm_inject_dabt - inject a data abort into the guest
123 * @vcpu: The VCPU to receive the undefined exception
124 * @addr: The address to report in the DFAR
125 *
126 * It is assumed that this code is called from the VCPU thread and that the
127 * VCPU therefore is not currently executing guest code.
128 */
129void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr)
130{
131 if (vcpu_el1_is_32bit(vcpu))
132 kvm_inject_dabt32(vcpu, addr);
133 else
134 inject_abt64(vcpu, false, addr);
135}
136
137/**
138 * kvm_inject_pabt - inject a prefetch abort into the guest
139 * @vcpu: The VCPU to receive the undefined exception
140 * @addr: The address to report in the DFAR
141 *
142 * It is assumed that this code is called from the VCPU thread and that the
143 * VCPU therefore is not currently executing guest code.
144 */
145void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr)
146{
147 if (vcpu_el1_is_32bit(vcpu))
148 kvm_inject_pabt32(vcpu, addr);
149 else
150 inject_abt64(vcpu, true, addr);
151}
152
153/**
154 * kvm_inject_undefined - inject an undefined instruction into the guest
155 *
156 * It is assumed that this code is called from the VCPU thread and that the
157 * VCPU therefore is not currently executing guest code.
158 */
159void kvm_inject_undefined(struct kvm_vcpu *vcpu)
160{
161 if (vcpu_el1_is_32bit(vcpu))
162 kvm_inject_undef32(vcpu);
163 else
164 inject_undef64(vcpu);
165}
166
167static void pend_guest_serror(struct kvm_vcpu *vcpu, u64 esr)
168{
169 vcpu_set_vsesr(vcpu, esr);
170 *vcpu_hcr(vcpu) |= HCR_VSE;
171}
172
173/**
174 * kvm_inject_vabt - inject an async abort / SError into the guest
175 * @vcpu: The VCPU to receive the exception
176 *
177 * It is assumed that this code is called from the VCPU thread and that the
178 * VCPU therefore is not currently executing guest code.
179 *
180 * Systems with the RAS Extensions specify an imp-def ESR (ISV/IDS = 1) with
181 * the remaining ISS all-zeros so that this error is not interpreted as an
182 * uncategorized RAS error. Without the RAS Extensions we can't specify an ESR
183 * value, so the CPU generates an imp-def value.
184 */
185void kvm_inject_vabt(struct kvm_vcpu *vcpu)
186{
187 pend_guest_serror(vcpu, ESR_ELx_ISV);
188}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Fault injection for both 32 and 64bit guests.
4 *
5 * Copyright (C) 2012,2013 - ARM Ltd
6 * Author: Marc Zyngier <marc.zyngier@arm.com>
7 *
8 * Based on arch/arm/kvm/emulate.c
9 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
10 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
11 */
12
13#include <linux/kvm_host.h>
14#include <asm/kvm_emulate.h>
15#include <asm/esr.h>
16
17static void inject_abt64(struct kvm_vcpu *vcpu, bool is_iabt, unsigned long addr)
18{
19 unsigned long cpsr = *vcpu_cpsr(vcpu);
20 bool is_aarch32 = vcpu_mode_is_32bit(vcpu);
21 u64 esr = 0;
22
23 kvm_pend_exception(vcpu, EXCEPT_AA64_EL1_SYNC);
24
25 vcpu_write_sys_reg(vcpu, addr, FAR_EL1);
26
27 /*
28 * Build an {i,d}abort, depending on the level and the
29 * instruction set. Report an external synchronous abort.
30 */
31 if (kvm_vcpu_trap_il_is32bit(vcpu))
32 esr |= ESR_ELx_IL;
33
34 /*
35 * Here, the guest runs in AArch64 mode when in EL1. If we get
36 * an AArch32 fault, it means we managed to trap an EL0 fault.
37 */
38 if (is_aarch32 || (cpsr & PSR_MODE_MASK) == PSR_MODE_EL0t)
39 esr |= (ESR_ELx_EC_IABT_LOW << ESR_ELx_EC_SHIFT);
40 else
41 esr |= (ESR_ELx_EC_IABT_CUR << ESR_ELx_EC_SHIFT);
42
43 if (!is_iabt)
44 esr |= ESR_ELx_EC_DABT_LOW << ESR_ELx_EC_SHIFT;
45
46 vcpu_write_sys_reg(vcpu, esr | ESR_ELx_FSC_EXTABT, ESR_EL1);
47}
48
49static void inject_undef64(struct kvm_vcpu *vcpu)
50{
51 u64 esr = (ESR_ELx_EC_UNKNOWN << ESR_ELx_EC_SHIFT);
52
53 kvm_pend_exception(vcpu, EXCEPT_AA64_EL1_SYNC);
54
55 /*
56 * Build an unknown exception, depending on the instruction
57 * set.
58 */
59 if (kvm_vcpu_trap_il_is32bit(vcpu))
60 esr |= ESR_ELx_IL;
61
62 vcpu_write_sys_reg(vcpu, esr, ESR_EL1);
63}
64
65#define DFSR_FSC_EXTABT_LPAE 0x10
66#define DFSR_FSC_EXTABT_nLPAE 0x08
67#define DFSR_LPAE BIT(9)
68#define TTBCR_EAE BIT(31)
69
70static void inject_undef32(struct kvm_vcpu *vcpu)
71{
72 kvm_pend_exception(vcpu, EXCEPT_AA32_UND);
73}
74
75/*
76 * Modelled after TakeDataAbortException() and TakePrefetchAbortException
77 * pseudocode.
78 */
79static void inject_abt32(struct kvm_vcpu *vcpu, bool is_pabt, u32 addr)
80{
81 u64 far;
82 u32 fsr;
83
84 /* Give the guest an IMPLEMENTATION DEFINED exception */
85 if (vcpu_read_sys_reg(vcpu, TCR_EL1) & TTBCR_EAE) {
86 fsr = DFSR_LPAE | DFSR_FSC_EXTABT_LPAE;
87 } else {
88 /* no need to shuffle FS[4] into DFSR[10] as its 0 */
89 fsr = DFSR_FSC_EXTABT_nLPAE;
90 }
91
92 far = vcpu_read_sys_reg(vcpu, FAR_EL1);
93
94 if (is_pabt) {
95 kvm_pend_exception(vcpu, EXCEPT_AA32_IABT);
96 far &= GENMASK(31, 0);
97 far |= (u64)addr << 32;
98 vcpu_write_sys_reg(vcpu, fsr, IFSR32_EL2);
99 } else { /* !iabt */
100 kvm_pend_exception(vcpu, EXCEPT_AA32_DABT);
101 far &= GENMASK(63, 32);
102 far |= addr;
103 vcpu_write_sys_reg(vcpu, fsr, ESR_EL1);
104 }
105
106 vcpu_write_sys_reg(vcpu, far, FAR_EL1);
107}
108
109/**
110 * kvm_inject_dabt - inject a data abort into the guest
111 * @vcpu: The VCPU to receive the data abort
112 * @addr: The address to report in the DFAR
113 *
114 * It is assumed that this code is called from the VCPU thread and that the
115 * VCPU therefore is not currently executing guest code.
116 */
117void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr)
118{
119 if (vcpu_el1_is_32bit(vcpu))
120 inject_abt32(vcpu, false, addr);
121 else
122 inject_abt64(vcpu, false, addr);
123}
124
125/**
126 * kvm_inject_pabt - inject a prefetch abort into the guest
127 * @vcpu: The VCPU to receive the prefetch abort
128 * @addr: The address to report in the DFAR
129 *
130 * It is assumed that this code is called from the VCPU thread and that the
131 * VCPU therefore is not currently executing guest code.
132 */
133void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr)
134{
135 if (vcpu_el1_is_32bit(vcpu))
136 inject_abt32(vcpu, true, addr);
137 else
138 inject_abt64(vcpu, true, addr);
139}
140
141void kvm_inject_size_fault(struct kvm_vcpu *vcpu)
142{
143 unsigned long addr, esr;
144
145 addr = kvm_vcpu_get_fault_ipa(vcpu);
146 addr |= kvm_vcpu_get_hfar(vcpu) & GENMASK(11, 0);
147
148 if (kvm_vcpu_trap_is_iabt(vcpu))
149 kvm_inject_pabt(vcpu, addr);
150 else
151 kvm_inject_dabt(vcpu, addr);
152
153 /*
154 * If AArch64 or LPAE, set FSC to 0 to indicate an Address
155 * Size Fault at level 0, as if exceeding PARange.
156 *
157 * Non-LPAE guests will only get the external abort, as there
158 * is no way to to describe the ASF.
159 */
160 if (vcpu_el1_is_32bit(vcpu) &&
161 !(vcpu_read_sys_reg(vcpu, TCR_EL1) & TTBCR_EAE))
162 return;
163
164 esr = vcpu_read_sys_reg(vcpu, ESR_EL1);
165 esr &= ~GENMASK_ULL(5, 0);
166 vcpu_write_sys_reg(vcpu, esr, ESR_EL1);
167}
168
169/**
170 * kvm_inject_undefined - inject an undefined instruction into the guest
171 * @vcpu: The vCPU in which to inject the exception
172 *
173 * It is assumed that this code is called from the VCPU thread and that the
174 * VCPU therefore is not currently executing guest code.
175 */
176void kvm_inject_undefined(struct kvm_vcpu *vcpu)
177{
178 if (vcpu_el1_is_32bit(vcpu))
179 inject_undef32(vcpu);
180 else
181 inject_undef64(vcpu);
182}
183
184void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 esr)
185{
186 vcpu_set_vsesr(vcpu, esr & ESR_ELx_ISS_MASK);
187 *vcpu_hcr(vcpu) |= HCR_VSE;
188}
189
190/**
191 * kvm_inject_vabt - inject an async abort / SError into the guest
192 * @vcpu: The VCPU to receive the exception
193 *
194 * It is assumed that this code is called from the VCPU thread and that the
195 * VCPU therefore is not currently executing guest code.
196 *
197 * Systems with the RAS Extensions specify an imp-def ESR (ISV/IDS = 1) with
198 * the remaining ISS all-zeros so that this error is not interpreted as an
199 * uncategorized RAS error. Without the RAS Extensions we can't specify an ESR
200 * value, so the CPU generates an imp-def value.
201 */
202void kvm_inject_vabt(struct kvm_vcpu *vcpu)
203{
204 kvm_set_sei_esr(vcpu, ESR_ELx_ISV);
205}