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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for AM642 SoC Family Main Domain peripherals
4 *
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8#include <dt-bindings/phy/phy-cadence.h>
9#include <dt-bindings/phy/phy-ti.h>
10
11/ {
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
16 };
17};
18
19&cbass_main {
20 oc_sram: sram@70000000 {
21 compatible = "mmio-sram";
22 reg = <0x00 0x70000000 0x00 0x200000>;
23 #address-cells = <1>;
24 #size-cells = <1>;
25 ranges = <0x0 0x00 0x70000000 0x200000>;
26
27 tfa-sram@1c0000 {
28 reg = <0x1c0000 0x20000>;
29 };
30
31 dmsc-sram@1e0000 {
32 reg = <0x1e0000 0x1c000>;
33 };
34
35 sproxy-sram@1fc000 {
36 reg = <0x1fc000 0x4000>;
37 };
38 };
39
40 main_conf: syscon@43000000 {
41 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
42 reg = <0x0 0x43000000 0x0 0x20000>;
43 #address-cells = <1>;
44 #size-cells = <1>;
45 ranges = <0x0 0x0 0x43000000 0x20000>;
46
47 serdes_ln_ctrl: mux-controller {
48 compatible = "mmio-mux";
49 #mux-control-cells = <1>;
50 mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */
51 };
52 };
53
54 gic500: interrupt-controller@1800000 {
55 compatible = "arm,gic-v3";
56 #address-cells = <2>;
57 #size-cells = <2>;
58 ranges;
59 #interrupt-cells = <3>;
60 interrupt-controller;
61 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
62 <0x00 0x01840000 0x00 0xC0000>, /* GICR */
63 <0x01 0x00000000 0x00 0x2000>, /* GICC */
64 <0x01 0x00010000 0x00 0x1000>, /* GICH */
65 <0x01 0x00020000 0x00 0x2000>; /* GICV */
66 /*
67 * vcpumntirq:
68 * virtual CPU interface maintenance interrupt
69 */
70 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
71
72 gic_its: msi-controller@1820000 {
73 compatible = "arm,gic-v3-its";
74 reg = <0x00 0x01820000 0x00 0x10000>;
75 socionext,synquacer-pre-its = <0x1000000 0x400000>;
76 msi-controller;
77 #msi-cells = <1>;
78 };
79 };
80
81 dmss: bus@48000000 {
82 compatible = "simple-mfd";
83 #address-cells = <2>;
84 #size-cells = <2>;
85 dma-ranges;
86 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
87
88 ti,sci-dev-id = <25>;
89
90 secure_proxy_main: mailbox@4d000000 {
91 compatible = "ti,am654-secure-proxy";
92 #mbox-cells = <1>;
93 reg-names = "target_data", "rt", "scfg";
94 reg = <0x00 0x4d000000 0x00 0x80000>,
95 <0x00 0x4a600000 0x00 0x80000>,
96 <0x00 0x4a400000 0x00 0x80000>;
97 interrupt-names = "rx_012";
98 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
99 };
100
101 inta_main_dmss: interrupt-controller@48000000 {
102 compatible = "ti,sci-inta";
103 reg = <0x00 0x48000000 0x00 0x100000>;
104 #interrupt-cells = <0>;
105 interrupt-controller;
106 interrupt-parent = <&gic500>;
107 msi-controller;
108 ti,sci = <&dmsc>;
109 ti,sci-dev-id = <28>;
110 ti,interrupt-ranges = <4 68 36>;
111 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
112 };
113
114 main_bcdma: dma-controller@485c0100 {
115 compatible = "ti,am64-dmss-bcdma";
116 reg = <0x00 0x485c0100 0x00 0x100>,
117 <0x00 0x4c000000 0x00 0x20000>,
118 <0x00 0x4a820000 0x00 0x20000>,
119 <0x00 0x4aa40000 0x00 0x20000>,
120 <0x00 0x4bc00000 0x00 0x100000>;
121 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
122 msi-parent = <&inta_main_dmss>;
123 #dma-cells = <3>;
124
125 ti,sci = <&dmsc>;
126 ti,sci-dev-id = <26>;
127 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
128 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
129 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
130 };
131
132 main_pktdma: dma-controller@485c0000 {
133 compatible = "ti,am64-dmss-pktdma";
134 reg = <0x00 0x485c0000 0x00 0x100>,
135 <0x00 0x4a800000 0x00 0x20000>,
136 <0x00 0x4aa00000 0x00 0x40000>,
137 <0x00 0x4b800000 0x00 0x400000>;
138 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
139 msi-parent = <&inta_main_dmss>;
140 #dma-cells = <2>;
141
142 ti,sci = <&dmsc>;
143 ti,sci-dev-id = <30>;
144 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
145 <0x24>, /* CPSW_TX_CHAN */
146 <0x25>, /* SAUL_TX_0_CHAN */
147 <0x26>, /* SAUL_TX_1_CHAN */
148 <0x27>, /* ICSSG_0_TX_CHAN */
149 <0x28>; /* ICSSG_1_TX_CHAN */
150 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
151 <0x11>, /* RING_CPSW_TX_CHAN */
152 <0x12>, /* RING_SAUL_TX_0_CHAN */
153 <0x13>, /* RING_SAUL_TX_1_CHAN */
154 <0x14>, /* RING_ICSSG_0_TX_CHAN */
155 <0x15>; /* RING_ICSSG_1_TX_CHAN */
156 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
157 <0x2b>, /* CPSW_RX_CHAN */
158 <0x2d>, /* SAUL_RX_0_CHAN */
159 <0x2f>, /* SAUL_RX_1_CHAN */
160 <0x31>, /* SAUL_RX_2_CHAN */
161 <0x33>, /* SAUL_RX_3_CHAN */
162 <0x35>, /* ICSSG_0_RX_CHAN */
163 <0x37>; /* ICSSG_1_RX_CHAN */
164 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
165 <0x2c>, /* FLOW_CPSW_RX_CHAN */
166 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
167 <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */
168 <0x36>, /* FLOW_ICSSG_0_RX_CHAN */
169 <0x38>; /* FLOW_ICSSG_1_RX_CHAN */
170 };
171 };
172
173 dmsc: system-controller@44043000 {
174 compatible = "ti,k2g-sci";
175 ti,host-id = <12>;
176 mbox-names = "rx", "tx";
177 mboxes = <&secure_proxy_main 12>,
178 <&secure_proxy_main 13>;
179 reg-names = "debug_messages";
180 reg = <0x00 0x44043000 0x00 0xfe0>;
181
182 k3_pds: power-controller {
183 compatible = "ti,sci-pm-domain";
184 #power-domain-cells = <2>;
185 };
186
187 k3_clks: clock-controller {
188 compatible = "ti,k2g-sci-clk";
189 #clock-cells = <2>;
190 };
191
192 k3_reset: reset-controller {
193 compatible = "ti,sci-reset";
194 #reset-cells = <2>;
195 };
196 };
197
198 main_pmx0: pinctrl@f4000 {
199 compatible = "pinctrl-single";
200 reg = <0x00 0xf4000 0x00 0x2d0>;
201 #pinctrl-cells = <1>;
202 pinctrl-single,register-width = <32>;
203 pinctrl-single,function-mask = <0xffffffff>;
204 };
205
206 main_conf: syscon@43000000 {
207 compatible = "syscon", "simple-mfd";
208 reg = <0x00 0x43000000 0x00 0x20000>;
209 #address-cells = <1>;
210 #size-cells = <1>;
211 ranges = <0x00 0x00 0x43000000 0x20000>;
212
213 chipid@14 {
214 compatible = "ti,am654-chipid";
215 reg = <0x00000014 0x4>;
216 };
217
218 phy_gmii_sel: phy@4044 {
219 compatible = "ti,am654-phy-gmii-sel";
220 reg = <0x4044 0x8>;
221 #phy-cells = <1>;
222 };
223
224 epwm_tbclk: clock@4140 {
225 compatible = "ti,am64-epwm-tbclk", "syscon";
226 reg = <0x4130 0x4>;
227 #clock-cells = <1>;
228 };
229 };
230
231 main_uart0: serial@2800000 {
232 compatible = "ti,am64-uart", "ti,am654-uart";
233 reg = <0x00 0x02800000 0x00 0x100>;
234 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
235 clock-frequency = <48000000>;
236 current-speed = <115200>;
237 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
238 clocks = <&k3_clks 146 0>;
239 clock-names = "fclk";
240 status = "disabled";
241 };
242
243 main_uart1: serial@2810000 {
244 compatible = "ti,am64-uart", "ti,am654-uart";
245 reg = <0x00 0x02810000 0x00 0x100>;
246 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
247 clock-frequency = <48000000>;
248 current-speed = <115200>;
249 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
250 clocks = <&k3_clks 152 0>;
251 clock-names = "fclk";
252 status = "disabled";
253 };
254
255 main_uart2: serial@2820000 {
256 compatible = "ti,am64-uart", "ti,am654-uart";
257 reg = <0x00 0x02820000 0x00 0x100>;
258 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
259 clock-frequency = <48000000>;
260 current-speed = <115200>;
261 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
262 clocks = <&k3_clks 153 0>;
263 clock-names = "fclk";
264 status = "disabled";
265 };
266
267 main_uart3: serial@2830000 {
268 compatible = "ti,am64-uart", "ti,am654-uart";
269 reg = <0x00 0x02830000 0x00 0x100>;
270 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
271 clock-frequency = <48000000>;
272 current-speed = <115200>;
273 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
274 clocks = <&k3_clks 154 0>;
275 clock-names = "fclk";
276 status = "disabled";
277 };
278
279 main_uart4: serial@2840000 {
280 compatible = "ti,am64-uart", "ti,am654-uart";
281 reg = <0x00 0x02840000 0x00 0x100>;
282 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
283 clock-frequency = <48000000>;
284 current-speed = <115200>;
285 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
286 clocks = <&k3_clks 155 0>;
287 clock-names = "fclk";
288 status = "disabled";
289 };
290
291 main_uart5: serial@2850000 {
292 compatible = "ti,am64-uart", "ti,am654-uart";
293 reg = <0x00 0x02850000 0x00 0x100>;
294 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
295 clock-frequency = <48000000>;
296 current-speed = <115200>;
297 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
298 clocks = <&k3_clks 156 0>;
299 clock-names = "fclk";
300 status = "disabled";
301 };
302
303 main_uart6: serial@2860000 {
304 compatible = "ti,am64-uart", "ti,am654-uart";
305 reg = <0x00 0x02860000 0x00 0x100>;
306 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
307 clock-frequency = <48000000>;
308 current-speed = <115200>;
309 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
310 clocks = <&k3_clks 158 0>;
311 clock-names = "fclk";
312 status = "disabled";
313 };
314
315 main_i2c0: i2c@20000000 {
316 compatible = "ti,am64-i2c", "ti,omap4-i2c";
317 reg = <0x00 0x20000000 0x00 0x100>;
318 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
319 #address-cells = <1>;
320 #size-cells = <0>;
321 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
322 clocks = <&k3_clks 102 2>;
323 clock-names = "fck";
324 status = "disabled";
325 };
326
327 main_i2c1: i2c@20010000 {
328 compatible = "ti,am64-i2c", "ti,omap4-i2c";
329 reg = <0x00 0x20010000 0x00 0x100>;
330 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
331 #address-cells = <1>;
332 #size-cells = <0>;
333 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
334 clocks = <&k3_clks 103 2>;
335 clock-names = "fck";
336 status = "disabled";
337 };
338
339 main_i2c2: i2c@20020000 {
340 compatible = "ti,am64-i2c", "ti,omap4-i2c";
341 reg = <0x00 0x20020000 0x00 0x100>;
342 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
343 #address-cells = <1>;
344 #size-cells = <0>;
345 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
346 clocks = <&k3_clks 104 2>;
347 clock-names = "fck";
348 status = "disabled";
349 };
350
351 main_i2c3: i2c@20030000 {
352 compatible = "ti,am64-i2c", "ti,omap4-i2c";
353 reg = <0x00 0x20030000 0x00 0x100>;
354 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
355 #address-cells = <1>;
356 #size-cells = <0>;
357 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
358 clocks = <&k3_clks 105 2>;
359 clock-names = "fck";
360 status = "disabled";
361 };
362
363 main_spi0: spi@20100000 {
364 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
365 reg = <0x00 0x20100000 0x00 0x400>;
366 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
367 #address-cells = <1>;
368 #size-cells = <0>;
369 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
370 clocks = <&k3_clks 141 0>;
371 dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>;
372 dma-names = "tx0", "rx0";
373 status = "disabled";
374 };
375
376 main_spi1: spi@20110000 {
377 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
378 reg = <0x00 0x20110000 0x00 0x400>;
379 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
380 #address-cells = <1>;
381 #size-cells = <0>;
382 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
383 clocks = <&k3_clks 142 0>;
384 status = "disabled";
385 };
386
387 main_spi2: spi@20120000 {
388 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
389 reg = <0x00 0x20120000 0x00 0x400>;
390 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
391 #address-cells = <1>;
392 #size-cells = <0>;
393 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
394 clocks = <&k3_clks 143 0>;
395 status = "disabled";
396 };
397
398 main_spi3: spi@20130000 {
399 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
400 reg = <0x00 0x20130000 0x00 0x400>;
401 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
402 #address-cells = <1>;
403 #size-cells = <0>;
404 power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
405 clocks = <&k3_clks 144 0>;
406 status = "disabled";
407 };
408
409 main_spi4: spi@20140000 {
410 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
411 reg = <0x00 0x20140000 0x00 0x400>;
412 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
413 #address-cells = <1>;
414 #size-cells = <0>;
415 power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>;
416 clocks = <&k3_clks 145 0>;
417 status = "disabled";
418 };
419
420 main_gpio_intr: interrupt-controller@a00000 {
421 compatible = "ti,sci-intr";
422 reg = <0x00 0x00a00000 0x00 0x800>;
423 ti,intr-trigger-type = <1>;
424 interrupt-controller;
425 interrupt-parent = <&gic500>;
426 #interrupt-cells = <1>;
427 ti,sci = <&dmsc>;
428 ti,sci-dev-id = <3>;
429 ti,interrupt-ranges = <0 32 16>;
430 };
431
432 main_gpio0: gpio@600000 {
433 compatible = "ti,am64-gpio", "ti,keystone-gpio";
434 reg = <0x0 0x00600000 0x0 0x100>;
435 gpio-controller;
436 #gpio-cells = <2>;
437 interrupt-parent = <&main_gpio_intr>;
438 interrupts = <190>, <191>, <192>,
439 <193>, <194>, <195>;
440 interrupt-controller;
441 #interrupt-cells = <2>;
442 ti,ngpio = <87>;
443 ti,davinci-gpio-unbanked = <0>;
444 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
445 clocks = <&k3_clks 77 0>;
446 clock-names = "gpio";
447 };
448
449 main_gpio1: gpio@601000 {
450 compatible = "ti,am64-gpio", "ti,keystone-gpio";
451 reg = <0x0 0x00601000 0x0 0x100>;
452 gpio-controller;
453 #gpio-cells = <2>;
454 interrupt-parent = <&main_gpio_intr>;
455 interrupts = <180>, <181>, <182>,
456 <183>, <184>, <185>;
457 interrupt-controller;
458 #interrupt-cells = <2>;
459 ti,ngpio = <88>;
460 ti,davinci-gpio-unbanked = <0>;
461 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
462 clocks = <&k3_clks 78 0>;
463 clock-names = "gpio";
464 };
465
466 sdhci0: mmc@fa10000 {
467 compatible = "ti,am64-sdhci-8bit";
468 reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
469 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
470 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
471 clocks = <&k3_clks 57 0>, <&k3_clks 57 1>;
472 clock-names = "clk_ahb", "clk_xin";
473 mmc-ddr-1_8v;
474 mmc-hs200-1_8v;
475 ti,trm-icp = <0x2>;
476 ti,otap-del-sel-legacy = <0x0>;
477 ti,otap-del-sel-mmc-hs = <0x0>;
478 ti,otap-del-sel-ddr52 = <0x6>;
479 ti,otap-del-sel-hs200 = <0x7>;
480 };
481
482 sdhci1: mmc@fa00000 {
483 compatible = "ti,am64-sdhci-4bit";
484 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
485 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
486 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
487 clocks = <&k3_clks 58 3>, <&k3_clks 58 4>;
488 clock-names = "clk_ahb", "clk_xin";
489 ti,trm-icp = <0x2>;
490 ti,otap-del-sel-legacy = <0x0>;
491 ti,otap-del-sel-sd-hs = <0xf>;
492 ti,otap-del-sel-sdr12 = <0xf>;
493 ti,otap-del-sel-sdr25 = <0xf>;
494 ti,otap-del-sel-sdr50 = <0xc>;
495 ti,otap-del-sel-sdr104 = <0x6>;
496 ti,otap-del-sel-ddr50 = <0x9>;
497 ti,clkbuf-sel = <0x7>;
498 };
499
500 cpsw3g: ethernet@8000000 {
501 compatible = "ti,am642-cpsw-nuss";
502 #address-cells = <2>;
503 #size-cells = <2>;
504 reg = <0x0 0x8000000 0x0 0x200000>;
505 reg-names = "cpsw_nuss";
506 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
507 clocks = <&k3_clks 13 0>;
508 assigned-clocks = <&k3_clks 13 1>;
509 assigned-clock-parents = <&k3_clks 13 9>;
510 clock-names = "fck";
511 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
512
513 dmas = <&main_pktdma 0xC500 15>,
514 <&main_pktdma 0xC501 15>,
515 <&main_pktdma 0xC502 15>,
516 <&main_pktdma 0xC503 15>,
517 <&main_pktdma 0xC504 15>,
518 <&main_pktdma 0xC505 15>,
519 <&main_pktdma 0xC506 15>,
520 <&main_pktdma 0xC507 15>,
521 <&main_pktdma 0x4500 15>;
522 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
523 "tx7", "rx";
524
525 ethernet-ports {
526 #address-cells = <1>;
527 #size-cells = <0>;
528
529 cpsw_port1: port@1 {
530 reg = <1>;
531 ti,mac-only;
532 label = "port1";
533 phys = <&phy_gmii_sel 1>;
534 mac-address = [00 00 00 00 00 00];
535 ti,syscon-efuse = <&main_conf 0x200>;
536 };
537
538 cpsw_port2: port@2 {
539 reg = <2>;
540 ti,mac-only;
541 label = "port2";
542 phys = <&phy_gmii_sel 2>;
543 mac-address = [00 00 00 00 00 00];
544 };
545 };
546
547 cpsw3g_mdio: mdio@f00 {
548 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
549 reg = <0x0 0xf00 0x0 0x100>;
550 #address-cells = <1>;
551 #size-cells = <0>;
552 clocks = <&k3_clks 13 0>;
553 clock-names = "fck";
554 bus_freq = <1000000>;
555 status = "disabled";
556 };
557
558 cpts@3d000 {
559 compatible = "ti,j721e-cpts";
560 reg = <0x0 0x3d000 0x0 0x400>;
561 clocks = <&k3_clks 13 1>;
562 clock-names = "cpts";
563 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
564 interrupt-names = "cpts";
565 ti,cpts-ext-ts-inputs = <4>;
566 ti,cpts-periodic-outputs = <2>;
567 };
568 };
569
570 main_cpts0: cpts@39000000 {
571 compatible = "ti,j721e-cpts";
572 reg = <0x0 0x39000000 0x0 0x400>;
573 reg-names = "cpts";
574 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
575 clocks = <&k3_clks 84 0>;
576 clock-names = "cpts";
577 assigned-clocks = <&k3_clks 84 0>;
578 assigned-clock-parents = <&k3_clks 84 8>;
579 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
580 interrupt-names = "cpts";
581 ti,cpts-periodic-outputs = <6>;
582 ti,cpts-ext-ts-inputs = <8>;
583 };
584
585 timesync_router: pinctrl@a40000 {
586 compatible = "pinctrl-single";
587 reg = <0x0 0xa40000 0x0 0x800>;
588 #pinctrl-cells = <1>;
589 pinctrl-single,register-width = <32>;
590 pinctrl-single,function-mask = <0x000107ff>;
591 };
592
593 usbss0: cdns-usb@f900000{
594 compatible = "ti,am64-usb";
595 reg = <0x00 0xf900000 0x00 0x100>;
596 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
597 clocks = <&k3_clks 161 9>, <&k3_clks 161 1>;
598 clock-names = "ref", "lpm";
599 assigned-clocks = <&k3_clks 161 9>; /* USB2_REFCLK */
600 assigned-clock-parents = <&k3_clks 161 10>; /* HF0SC0 */
601 #address-cells = <2>;
602 #size-cells = <2>;
603 ranges;
604 usb0: usb@f400000{
605 compatible = "cdns,usb3";
606 reg = <0x00 0xf400000 0x00 0x10000>,
607 <0x00 0xf410000 0x00 0x10000>,
608 <0x00 0xf420000 0x00 0x10000>;
609 reg-names = "otg",
610 "xhci",
611 "dev";
612 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
613 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
614 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */
615 interrupt-names = "host",
616 "peripheral",
617 "otg";
618 maximum-speed = "super-speed";
619 dr_mode = "otg";
620 };
621 };
622
623 tscadc0: tscadc@28001000 {
624 compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
625 reg = <0x00 0x28001000 0x00 0x1000>;
626 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
627 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
628 clocks = <&k3_clks 0 0>;
629 assigned-clocks = <&k3_clks 0 0>;
630 assigned-clock-parents = <&k3_clks 0 3>;
631 assigned-clock-rates = <60000000>;
632 clock-names = "fck";
633
634 adc {
635 #io-channel-cells = <1>;
636 compatible = "ti,am654-adc", "ti,am3359-adc";
637 };
638 };
639
640 fss: bus@fc00000 {
641 compatible = "simple-bus";
642 reg = <0x00 0x0fc00000 0x00 0x70000>;
643 #address-cells = <2>;
644 #size-cells = <2>;
645 ranges;
646
647 ospi0: spi@fc40000 {
648 compatible = "ti,am654-ospi", "cdns,qspi-nor";
649 reg = <0x00 0x0fc40000 0x00 0x100>,
650 <0x05 0x00000000 0x01 0x00000000>;
651 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
652 cdns,fifo-depth = <256>;
653 cdns,fifo-width = <4>;
654 cdns,trigger-address = <0x0>;
655 #address-cells = <0x1>;
656 #size-cells = <0x0>;
657 clocks = <&k3_clks 75 6>;
658 assigned-clocks = <&k3_clks 75 6>;
659 assigned-clock-parents = <&k3_clks 75 7>;
660 assigned-clock-rates = <166666666>;
661 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
662 };
663 };
664
665 hwspinlock: spinlock@2a000000 {
666 compatible = "ti,am64-hwspinlock";
667 reg = <0x00 0x2a000000 0x00 0x1000>;
668 #hwlock-cells = <1>;
669 };
670
671 mailbox0_cluster2: mailbox@29020000 {
672 compatible = "ti,am64-mailbox";
673 reg = <0x00 0x29020000 0x00 0x200>;
674 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
675 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
676 #mbox-cells = <1>;
677 ti,mbox-num-users = <4>;
678 ti,mbox-num-fifos = <16>;
679 };
680
681 mailbox0_cluster3: mailbox@29030000 {
682 compatible = "ti,am64-mailbox";
683 reg = <0x00 0x29030000 0x00 0x200>;
684 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
685 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
686 #mbox-cells = <1>;
687 ti,mbox-num-users = <4>;
688 ti,mbox-num-fifos = <16>;
689 };
690
691 mailbox0_cluster4: mailbox@29040000 {
692 compatible = "ti,am64-mailbox";
693 reg = <0x00 0x29040000 0x00 0x200>;
694 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
695 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
696 #mbox-cells = <1>;
697 ti,mbox-num-users = <4>;
698 ti,mbox-num-fifos = <16>;
699 };
700
701 mailbox0_cluster5: mailbox@29050000 {
702 compatible = "ti,am64-mailbox";
703 reg = <0x00 0x29050000 0x00 0x200>;
704 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
705 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
706 #mbox-cells = <1>;
707 ti,mbox-num-users = <4>;
708 ti,mbox-num-fifos = <16>;
709 };
710
711 mailbox0_cluster6: mailbox@29060000 {
712 compatible = "ti,am64-mailbox";
713 reg = <0x00 0x29060000 0x00 0x200>;
714 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
715 #mbox-cells = <1>;
716 ti,mbox-num-users = <4>;
717 ti,mbox-num-fifos = <16>;
718 };
719
720 mailbox0_cluster7: mailbox@29070000 {
721 compatible = "ti,am64-mailbox";
722 reg = <0x00 0x29070000 0x00 0x200>;
723 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
724 #mbox-cells = <1>;
725 ti,mbox-num-users = <4>;
726 ti,mbox-num-fifos = <16>;
727 };
728
729 main_r5fss0: r5fss@78000000 {
730 compatible = "ti,am64-r5fss";
731 ti,cluster-mode = <0>;
732 #address-cells = <1>;
733 #size-cells = <1>;
734 ranges = <0x78000000 0x00 0x78000000 0x10000>,
735 <0x78100000 0x00 0x78100000 0x10000>,
736 <0x78200000 0x00 0x78200000 0x08000>,
737 <0x78300000 0x00 0x78300000 0x08000>;
738 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
739
740 main_r5fss0_core0: r5f@78000000 {
741 compatible = "ti,am64-r5f";
742 reg = <0x78000000 0x00010000>,
743 <0x78100000 0x00010000>;
744 reg-names = "atcm", "btcm";
745 ti,sci = <&dmsc>;
746 ti,sci-dev-id = <121>;
747 ti,sci-proc-ids = <0x01 0xff>;
748 resets = <&k3_reset 121 1>;
749 firmware-name = "am64-main-r5f0_0-fw";
750 ti,atcm-enable = <1>;
751 ti,btcm-enable = <1>;
752 ti,loczrama = <1>;
753 };
754
755 main_r5fss0_core1: r5f@78200000 {
756 compatible = "ti,am64-r5f";
757 reg = <0x78200000 0x00008000>,
758 <0x78300000 0x00008000>;
759 reg-names = "atcm", "btcm";
760 ti,sci = <&dmsc>;
761 ti,sci-dev-id = <122>;
762 ti,sci-proc-ids = <0x02 0xff>;
763 resets = <&k3_reset 122 1>;
764 firmware-name = "am64-main-r5f0_1-fw";
765 ti,atcm-enable = <1>;
766 ti,btcm-enable = <1>;
767 ti,loczrama = <1>;
768 };
769 };
770
771 main_r5fss1: r5fss@78400000 {
772 compatible = "ti,am64-r5fss";
773 ti,cluster-mode = <0>;
774 #address-cells = <1>;
775 #size-cells = <1>;
776 ranges = <0x78400000 0x00 0x78400000 0x10000>,
777 <0x78500000 0x00 0x78500000 0x10000>,
778 <0x78600000 0x00 0x78600000 0x08000>,
779 <0x78700000 0x00 0x78700000 0x08000>;
780 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
781
782 main_r5fss1_core0: r5f@78400000 {
783 compatible = "ti,am64-r5f";
784 reg = <0x78400000 0x00010000>,
785 <0x78500000 0x00010000>;
786 reg-names = "atcm", "btcm";
787 ti,sci = <&dmsc>;
788 ti,sci-dev-id = <123>;
789 ti,sci-proc-ids = <0x06 0xff>;
790 resets = <&k3_reset 123 1>;
791 firmware-name = "am64-main-r5f1_0-fw";
792 ti,atcm-enable = <1>;
793 ti,btcm-enable = <1>;
794 ti,loczrama = <1>;
795 };
796
797 main_r5fss1_core1: r5f@78600000 {
798 compatible = "ti,am64-r5f";
799 reg = <0x78600000 0x00008000>,
800 <0x78700000 0x00008000>;
801 reg-names = "atcm", "btcm";
802 ti,sci = <&dmsc>;
803 ti,sci-dev-id = <124>;
804 ti,sci-proc-ids = <0x07 0xff>;
805 resets = <&k3_reset 124 1>;
806 firmware-name = "am64-main-r5f1_1-fw";
807 ti,atcm-enable = <1>;
808 ti,btcm-enable = <1>;
809 ti,loczrama = <1>;
810 };
811 };
812
813 serdes_wiz0: wiz@f000000 {
814 compatible = "ti,am64-wiz-10g";
815 #address-cells = <1>;
816 #size-cells = <1>;
817 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
818 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>;
819 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
820 num-lanes = <1>;
821 #reset-cells = <1>;
822 #clock-cells = <1>;
823 ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
824
825 assigned-clocks = <&k3_clks 162 1>;
826 assigned-clock-parents = <&k3_clks 162 5>;
827
828 serdes0: serdes@f000000 {
829 compatible = "ti,j721e-serdes-10g";
830 reg = <0x0f000000 0x00010000>;
831 reg-names = "torrent_phy";
832 resets = <&serdes_wiz0 0>;
833 reset-names = "torrent_reset";
834 clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
835 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
836 clock-names = "refclk", "phy_en_refclk";
837 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
838 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
839 <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
840 assigned-clock-parents = <&k3_clks 162 1>,
841 <&k3_clks 162 1>,
842 <&k3_clks 162 1>;
843 #address-cells = <1>;
844 #size-cells = <0>;
845 #clock-cells = <1>;
846 };
847 };
848
849 pcie0_rc: pcie@f102000 {
850 compatible = "ti,am64-pcie-host", "ti,j721e-pcie-host";
851 reg = <0x00 0x0f102000 0x00 0x1000>,
852 <0x00 0x0f100000 0x00 0x400>,
853 <0x00 0x0d000000 0x00 0x00800000>,
854 <0x00 0x68000000 0x00 0x00001000>;
855 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
856 interrupt-names = "link_state";
857 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
858 device_type = "pci";
859 ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
860 max-link-speed = <2>;
861 num-lanes = <1>;
862 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
863 clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>;
864 clock-names = "fck", "pcie_refclk";
865 #address-cells = <3>;
866 #size-cells = <2>;
867 bus-range = <0x0 0xff>;
868 cdns,no-bar-match-nbits = <64>;
869 vendor-id = <0x104c>;
870 device-id = <0xb010>;
871 msi-map = <0x0 &gic_its 0x0 0x10000>;
872 ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>,
873 <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>;
874 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>;
875 status = "disabled";
876 };
877
878 pcie0_ep: pcie-ep@f102000 {
879 compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep";
880 reg = <0x00 0x0f102000 0x00 0x1000>,
881 <0x00 0x0f100000 0x00 0x400>,
882 <0x00 0x0d000000 0x00 0x00800000>,
883 <0x00 0x68000000 0x00 0x08000000>;
884 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
885 interrupt-names = "link_state";
886 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
887 ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
888 max-link-speed = <2>;
889 num-lanes = <1>;
890 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
891 clocks = <&k3_clks 114 0>;
892 clock-names = "fck";
893 max-functions = /bits/ 8 <1>;
894 status = "disabled";
895 };
896
897 epwm0: pwm@23000000 {
898 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
899 #pwm-cells = <3>;
900 reg = <0x0 0x23000000 0x0 0x100>;
901 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
902 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
903 clock-names = "tbclk", "fck";
904 status = "disabled";
905 };
906
907 epwm1: pwm@23010000 {
908 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
909 #pwm-cells = <3>;
910 reg = <0x0 0x23010000 0x0 0x100>;
911 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
912 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
913 clock-names = "tbclk", "fck";
914 status = "disabled";
915 };
916
917 epwm2: pwm@23020000 {
918 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
919 #pwm-cells = <3>;
920 reg = <0x0 0x23020000 0x0 0x100>;
921 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
922 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
923 clock-names = "tbclk", "fck";
924 status = "disabled";
925 };
926
927 epwm3: pwm@23030000 {
928 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
929 #pwm-cells = <3>;
930 reg = <0x0 0x23030000 0x0 0x100>;
931 power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>;
932 clocks = <&epwm_tbclk 3>, <&k3_clks 89 0>;
933 clock-names = "tbclk", "fck";
934 status = "disabled";
935 };
936
937 epwm4: pwm@23040000 {
938 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
939 #pwm-cells = <3>;
940 reg = <0x0 0x23040000 0x0 0x100>;
941 power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>;
942 clocks = <&epwm_tbclk 4>, <&k3_clks 90 0>;
943 clock-names = "tbclk", "fck";
944 status = "disabled";
945 };
946
947 epwm5: pwm@23050000 {
948 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
949 #pwm-cells = <3>;
950 reg = <0x0 0x23050000 0x0 0x100>;
951 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
952 clocks = <&epwm_tbclk 5>, <&k3_clks 91 0>;
953 clock-names = "tbclk", "fck";
954 status = "disabled";
955 };
956
957 epwm6: pwm@23060000 {
958 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
959 #pwm-cells = <3>;
960 reg = <0x0 0x23060000 0x0 0x100>;
961 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
962 clocks = <&epwm_tbclk 6>, <&k3_clks 92 0>;
963 clock-names = "tbclk", "fck";
964 status = "disabled";
965 };
966
967 epwm7: pwm@23070000 {
968 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
969 #pwm-cells = <3>;
970 reg = <0x0 0x23070000 0x0 0x100>;
971 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
972 clocks = <&epwm_tbclk 7>, <&k3_clks 93 0>;
973 clock-names = "tbclk", "fck";
974 status = "disabled";
975 };
976
977 epwm8: pwm@23080000 {
978 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
979 #pwm-cells = <3>;
980 reg = <0x0 0x23080000 0x0 0x100>;
981 power-domains = <&k3_pds 94 TI_SCI_PD_EXCLUSIVE>;
982 clocks = <&epwm_tbclk 8>, <&k3_clks 94 0>;
983 clock-names = "tbclk", "fck";
984 status = "disabled";
985 };
986
987 ecap0: pwm@23100000 {
988 compatible = "ti,am64-ecap", "ti,am3352-ecap";
989 #pwm-cells = <3>;
990 reg = <0x0 0x23100000 0x0 0x60>;
991 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
992 clocks = <&k3_clks 51 0>;
993 clock-names = "fck";
994 status = "disabled";
995 };
996
997 ecap1: pwm@23110000 {
998 compatible = "ti,am64-ecap", "ti,am3352-ecap";
999 #pwm-cells = <3>;
1000 reg = <0x0 0x23110000 0x0 0x60>;
1001 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
1002 clocks = <&k3_clks 52 0>;
1003 clock-names = "fck";
1004 status = "disabled";
1005 };
1006
1007 ecap2: pwm@23120000 {
1008 compatible = "ti,am64-ecap", "ti,am3352-ecap";
1009 #pwm-cells = <3>;
1010 reg = <0x0 0x23120000 0x0 0x60>;
1011 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
1012 clocks = <&k3_clks 53 0>;
1013 clock-names = "fck";
1014 status = "disabled";
1015 };
1016
1017 main_rti0: watchdog@e000000 {
1018 compatible = "ti,j7-rti-wdt";
1019 reg = <0x00 0xe000000 0x00 0x100>;
1020 clocks = <&k3_clks 125 0>;
1021 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
1022 assigned-clocks = <&k3_clks 125 0>;
1023 assigned-clock-parents = <&k3_clks 125 2>;
1024 };
1025
1026 main_rti1: watchdog@e010000 {
1027 compatible = "ti,j7-rti-wdt";
1028 reg = <0x00 0xe010000 0x00 0x100>;
1029 clocks = <&k3_clks 126 0>;
1030 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
1031 assigned-clocks = <&k3_clks 126 0>;
1032 assigned-clock-parents = <&k3_clks 126 2>;
1033 };
1034
1035 icssg0: icssg@30000000 {
1036 compatible = "ti,am642-icssg";
1037 reg = <0x00 0x30000000 0x00 0x80000>;
1038 power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>;
1039 #address-cells = <1>;
1040 #size-cells = <1>;
1041 ranges = <0x0 0x00 0x30000000 0x80000>;
1042
1043 icssg0_mem: memories@0 {
1044 reg = <0x0 0x2000>,
1045 <0x2000 0x2000>,
1046 <0x10000 0x10000>;
1047 reg-names = "dram0", "dram1", "shrdram2";
1048 };
1049
1050 icssg0_cfg: cfg@26000 {
1051 compatible = "ti,pruss-cfg", "syscon";
1052 reg = <0x26000 0x200>;
1053 #address-cells = <1>;
1054 #size-cells = <1>;
1055 ranges = <0x0 0x26000 0x2000>;
1056
1057 clocks {
1058 #address-cells = <1>;
1059 #size-cells = <0>;
1060
1061 icssg0_coreclk_mux: coreclk-mux@3c {
1062 reg = <0x3c>;
1063 #clock-cells = <0>;
1064 clocks = <&k3_clks 81 0>, /* icssg0_core_clk */
1065 <&k3_clks 81 20>; /* icssg0_iclk */
1066 assigned-clocks = <&icssg0_coreclk_mux>;
1067 assigned-clock-parents = <&k3_clks 81 20>;
1068 };
1069
1070 icssg0_iepclk_mux: iepclk-mux@30 {
1071 reg = <0x30>;
1072 #clock-cells = <0>;
1073 clocks = <&k3_clks 81 3>, /* icssg0_iep_clk */
1074 <&icssg0_coreclk_mux>; /* icssg0_coreclk_mux */
1075 assigned-clocks = <&icssg0_iepclk_mux>;
1076 assigned-clock-parents = <&icssg0_coreclk_mux>;
1077 };
1078 };
1079 };
1080
1081 icssg0_mii_rt: mii-rt@32000 {
1082 compatible = "ti,pruss-mii", "syscon";
1083 reg = <0x32000 0x100>;
1084 };
1085
1086 icssg0_mii_g_rt: mii-g-rt@33000 {
1087 compatible = "ti,pruss-mii-g", "syscon";
1088 reg = <0x33000 0x1000>;
1089 };
1090
1091 icssg0_intc: interrupt-controller@20000 {
1092 compatible = "ti,icssg-intc";
1093 reg = <0x20000 0x2000>;
1094 interrupt-controller;
1095 #interrupt-cells = <3>;
1096 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1097 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
1098 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
1099 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
1100 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
1101 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
1102 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1103 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1104 interrupt-names = "host_intr0", "host_intr1",
1105 "host_intr2", "host_intr3",
1106 "host_intr4", "host_intr5",
1107 "host_intr6", "host_intr7";
1108 };
1109
1110 pru0_0: pru@34000 {
1111 compatible = "ti,am642-pru";
1112 reg = <0x34000 0x3000>,
1113 <0x22000 0x100>,
1114 <0x22400 0x100>;
1115 reg-names = "iram", "control", "debug";
1116 firmware-name = "am64x-pru0_0-fw";
1117 };
1118
1119 rtu0_0: rtu@4000 {
1120 compatible = "ti,am642-rtu";
1121 reg = <0x4000 0x2000>,
1122 <0x23000 0x100>,
1123 <0x23400 0x100>;
1124 reg-names = "iram", "control", "debug";
1125 firmware-name = "am64x-rtu0_0-fw";
1126 };
1127
1128 tx_pru0_0: txpru@a000 {
1129 compatible = "ti,am642-tx-pru";
1130 reg = <0xa000 0x1800>,
1131 <0x25000 0x100>,
1132 <0x25400 0x100>;
1133 reg-names = "iram", "control", "debug";
1134 firmware-name = "am64x-txpru0_0-fw";
1135 };
1136
1137 pru0_1: pru@38000 {
1138 compatible = "ti,am642-pru";
1139 reg = <0x38000 0x3000>,
1140 <0x24000 0x100>,
1141 <0x24400 0x100>;
1142 reg-names = "iram", "control", "debug";
1143 firmware-name = "am64x-pru0_1-fw";
1144 };
1145
1146 rtu0_1: rtu@6000 {
1147 compatible = "ti,am642-rtu";
1148 reg = <0x6000 0x2000>,
1149 <0x23800 0x100>,
1150 <0x23c00 0x100>;
1151 reg-names = "iram", "control", "debug";
1152 firmware-name = "am64x-rtu0_1-fw";
1153 };
1154
1155 tx_pru0_1: txpru@c000 {
1156 compatible = "ti,am642-tx-pru";
1157 reg = <0xc000 0x1800>,
1158 <0x25800 0x100>,
1159 <0x25c00 0x100>;
1160 reg-names = "iram", "control", "debug";
1161 firmware-name = "am64x-txpru0_1-fw";
1162 };
1163
1164 icssg0_mdio: mdio@32400 {
1165 compatible = "ti,davinci_mdio";
1166 reg = <0x32400 0x100>;
1167 clocks = <&k3_clks 62 3>;
1168 clock-names = "fck";
1169 #address-cells = <1>;
1170 #size-cells = <0>;
1171 bus_freq = <1000000>;
1172 status = "disabled";
1173 };
1174 };
1175
1176 icssg1: icssg@30080000 {
1177 compatible = "ti,am642-icssg";
1178 reg = <0x00 0x30080000 0x00 0x80000>;
1179 power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>;
1180 #address-cells = <1>;
1181 #size-cells = <1>;
1182 ranges = <0x0 0x00 0x30080000 0x80000>;
1183
1184 icssg1_mem: memories@0 {
1185 reg = <0x0 0x2000>,
1186 <0x2000 0x2000>,
1187 <0x10000 0x10000>;
1188 reg-names = "dram0", "dram1", "shrdram2";
1189 };
1190
1191 icssg1_cfg: cfg@26000 {
1192 compatible = "ti,pruss-cfg", "syscon";
1193 reg = <0x26000 0x200>;
1194 #address-cells = <1>;
1195 #size-cells = <1>;
1196 ranges = <0x0 0x26000 0x2000>;
1197
1198 clocks {
1199 #address-cells = <1>;
1200 #size-cells = <0>;
1201
1202 icssg1_coreclk_mux: coreclk-mux@3c {
1203 reg = <0x3c>;
1204 #clock-cells = <0>;
1205 clocks = <&k3_clks 82 0>, /* icssg1_core_clk */
1206 <&k3_clks 82 20>; /* icssg1_iclk */
1207 assigned-clocks = <&icssg1_coreclk_mux>;
1208 assigned-clock-parents = <&k3_clks 82 20>;
1209 };
1210
1211 icssg1_iepclk_mux: iepclk-mux@30 {
1212 reg = <0x30>;
1213 #clock-cells = <0>;
1214 clocks = <&k3_clks 82 3>, /* icssg1_iep_clk */
1215 <&icssg1_coreclk_mux>; /* icssg1_coreclk_mux */
1216 assigned-clocks = <&icssg1_iepclk_mux>;
1217 assigned-clock-parents = <&icssg1_coreclk_mux>;
1218 };
1219 };
1220 };
1221
1222 icssg1_mii_rt: mii-rt@32000 {
1223 compatible = "ti,pruss-mii", "syscon";
1224 reg = <0x32000 0x100>;
1225 };
1226
1227 icssg1_mii_g_rt: mii-g-rt@33000 {
1228 compatible = "ti,pruss-mii-g", "syscon";
1229 reg = <0x33000 0x1000>;
1230 };
1231
1232 icssg1_intc: interrupt-controller@20000 {
1233 compatible = "ti,icssg-intc";
1234 reg = <0x20000 0x2000>;
1235 interrupt-controller;
1236 #interrupt-cells = <3>;
1237 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
1238 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1239 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
1240 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
1241 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
1242 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
1243 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1244 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1245 interrupt-names = "host_intr0", "host_intr1",
1246 "host_intr2", "host_intr3",
1247 "host_intr4", "host_intr5",
1248 "host_intr6", "host_intr7";
1249 };
1250
1251 pru1_0: pru@34000 {
1252 compatible = "ti,am642-pru";
1253 reg = <0x34000 0x4000>,
1254 <0x22000 0x100>,
1255 <0x22400 0x100>;
1256 reg-names = "iram", "control", "debug";
1257 firmware-name = "am64x-pru1_0-fw";
1258 };
1259
1260 rtu1_0: rtu@4000 {
1261 compatible = "ti,am642-rtu";
1262 reg = <0x4000 0x2000>,
1263 <0x23000 0x100>,
1264 <0x23400 0x100>;
1265 reg-names = "iram", "control", "debug";
1266 firmware-name = "am64x-rtu1_0-fw";
1267 };
1268
1269 tx_pru1_0: txpru@a000 {
1270 compatible = "ti,am642-tx-pru";
1271 reg = <0xa000 0x1800>,
1272 <0x25000 0x100>,
1273 <0x25400 0x100>;
1274 reg-names = "iram", "control", "debug";
1275 firmware-name = "am64x-txpru1_0-fw";
1276 };
1277
1278 pru1_1: pru@38000 {
1279 compatible = "ti,am642-pru";
1280 reg = <0x38000 0x4000>,
1281 <0x24000 0x100>,
1282 <0x24400 0x100>;
1283 reg-names = "iram", "control", "debug";
1284 firmware-name = "am64x-pru1_1-fw";
1285 };
1286
1287 rtu1_1: rtu@6000 {
1288 compatible = "ti,am642-rtu";
1289 reg = <0x6000 0x2000>,
1290 <0x23800 0x100>,
1291 <0x23c00 0x100>;
1292 reg-names = "iram", "control", "debug";
1293 firmware-name = "am64x-rtu1_1-fw";
1294 };
1295
1296 tx_pru1_1: txpru@c000 {
1297 compatible = "ti,am642-tx-pru";
1298 reg = <0xc000 0x1800>,
1299 <0x25800 0x100>,
1300 <0x25c00 0x100>;
1301 reg-names = "iram", "control", "debug";
1302 firmware-name = "am64x-txpru1_1-fw";
1303 };
1304
1305 icssg1_mdio: mdio@32400 {
1306 compatible = "ti,davinci_mdio";
1307 reg = <0x32400 0x100>;
1308 #address-cells = <1>;
1309 #size-cells = <0>;
1310 clocks = <&k3_clks 82 0>;
1311 clock-names = "fck";
1312 bus_freq = <1000000>;
1313 status = "disabled";
1314 };
1315 };
1316
1317 main_mcan0: can@20701000 {
1318 compatible = "bosch,m_can";
1319 reg = <0x00 0x20701000 0x00 0x200>,
1320 <0x00 0x20708000 0x00 0x8000>;
1321 reg-names = "m_can", "message_ram";
1322 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
1323 clocks = <&k3_clks 98 5>, <&k3_clks 98 0>;
1324 clock-names = "hclk", "cclk";
1325 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1326 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1327 interrupt-names = "int0", "int1";
1328 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1329 status = "disabled";
1330 };
1331
1332 main_mcan1: can@20711000 {
1333 compatible = "bosch,m_can";
1334 reg = <0x00 0x20711000 0x00 0x200>,
1335 <0x00 0x20718000 0x00 0x8000>;
1336 reg-names = "m_can", "message_ram";
1337 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
1338 clocks = <&k3_clks 99 5>, <&k3_clks 99 0>;
1339 clock-names = "hclk", "cclk";
1340 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
1341 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1342 interrupt-names = "int0", "int1";
1343 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1344 status = "disabled";
1345 };
1346
1347 crypto: crypto@40900000 {
1348 compatible = "ti,am64-sa2ul";
1349 reg = <0x00 0x40900000 0x00 0x1200>;
1350 power-domains = <&k3_pds 133 TI_SCI_PD_SHARED>;
1351 #address-cells = <2>;
1352 #size-cells = <2>;
1353 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
1354 dmas = <&main_pktdma 0xc001 0>, <&main_pktdma 0x4002 0>,
1355 <&main_pktdma 0x4003 0>;
1356 dma-names = "tx", "rx1", "rx2";
1357
1358 rng: rng@40910000 {
1359 compatible = "inside-secure,safexcel-eip76";
1360 reg = <0x00 0x40910000 0x00 0x7d>;
1361 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1362 status = "disabled"; /* Used by OP-TEE */
1363 };
1364 };
1365
1366 gpmc0: memory-controller@3b000000 {
1367 compatible = "ti,am64-gpmc";
1368 power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
1369 clocks = <&k3_clks 80 0>;
1370 clock-names = "fck";
1371 reg = <0x00 0x3b000000 0x00 0x400>,
1372 <0x00 0x50000000 0x00 0x8000000>;
1373 reg-names = "cfg", "data";
1374 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1375 gpmc,num-cs = <3>;
1376 gpmc,num-waitpins = <2>;
1377 #address-cells = <2>;
1378 #size-cells = <1>;
1379 interrupt-controller;
1380 #interrupt-cells = <2>;
1381 gpio-controller;
1382 #gpio-cells = <2>;
1383 status = "disabled";
1384 };
1385
1386 elm0: ecc@25010000 {
1387 compatible = "ti,am64-elm";
1388 reg = <0x00 0x25010000 0x00 0x2000>;
1389 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
1390 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
1391 clocks = <&k3_clks 54 0>;
1392 clock-names = "fck";
1393 status = "disabled";
1394 };
1395};