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1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2016 Endless Computers, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
5 */
6
7#include "meson-gx.dtsi"
8#include <dt-bindings/clock/gxbb-clkc.h>
9#include <dt-bindings/clock/gxbb-aoclkc.h>
10#include <dt-bindings/gpio/meson-gxl-gpio.h>
11#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
12
13/ {
14 compatible = "amlogic,meson-gxl";
15
16 reserved-memory {
17 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
18 secmon_reserved_alt: secmon@5000000 {
19 reg = <0x0 0x05000000 0x0 0x300000>;
20 no-map;
21 };
22 };
23
24 soc {
25 usb0: usb@c9000000 {
26 status = "disabled";
27 compatible = "amlogic,meson-gxl-dwc3";
28 #address-cells = <2>;
29 #size-cells = <2>;
30 ranges;
31
32 clocks = <&clkc CLKID_USB>;
33 clock-names = "usb_general";
34 resets = <&reset RESET_USB_OTG>;
35 reset-names = "usb_otg";
36
37 dwc3: dwc3@c9000000 {
38 compatible = "snps,dwc3";
39 reg = <0x0 0xc9000000 0x0 0x100000>;
40 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
41 dr_mode = "host";
42 maximum-speed = "high-speed";
43 snps,dis_u2_susphy_quirk;
44 phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>;
45 };
46 };
47 };
48};
49
50&apb {
51 usb2_phy0: phy@78000 {
52 compatible = "amlogic,meson-gxl-usb2-phy";
53 #phy-cells = <0>;
54 reg = <0x0 0x78000 0x0 0x20>;
55 clocks = <&clkc CLKID_USB>;
56 clock-names = "phy";
57 resets = <&reset RESET_USB_OTG>;
58 reset-names = "phy";
59 status = "okay";
60 };
61
62 usb2_phy1: phy@78020 {
63 compatible = "amlogic,meson-gxl-usb2-phy";
64 #phy-cells = <0>;
65 reg = <0x0 0x78020 0x0 0x20>;
66 clocks = <&clkc CLKID_USB>;
67 clock-names = "phy";
68 resets = <&reset RESET_USB_OTG>;
69 reset-names = "phy";
70 status = "okay";
71 };
72
73 usb3_phy: phy@78080 {
74 compatible = "amlogic,meson-gxl-usb3-phy";
75 #phy-cells = <0>;
76 reg = <0x0 0x78080 0x0 0x20>;
77 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
78 clocks = <&clkc CLKID_USB>, <&clkc_AO CLKID_AO_CEC_32K>;
79 clock-names = "phy", "peripheral";
80 resets = <&reset RESET_USB_OTG>, <&reset RESET_USB_OTG>;
81 reset-names = "phy", "peripheral";
82 status = "okay";
83 };
84};
85
86ðmac {
87 reg = <0x0 0xc9410000 0x0 0x10000
88 0x0 0xc8834540 0x0 0x4>;
89
90 clocks = <&clkc CLKID_ETH>,
91 <&clkc CLKID_FCLK_DIV2>,
92 <&clkc CLKID_MPLL2>;
93 clock-names = "stmmaceth", "clkin0", "clkin1";
94
95 mdio0: mdio {
96 #address-cells = <1>;
97 #size-cells = <0>;
98 compatible = "snps,dwmac-mdio";
99 };
100};
101
102&aobus {
103 pinctrl_aobus: pinctrl@14 {
104 compatible = "amlogic,meson-gxl-aobus-pinctrl";
105 #address-cells = <2>;
106 #size-cells = <2>;
107 ranges;
108
109 gpio_ao: bank@14 {
110 reg = <0x0 0x00014 0x0 0x8>,
111 <0x0 0x0002c 0x0 0x4>,
112 <0x0 0x00024 0x0 0x8>;
113 reg-names = "mux", "pull", "gpio";
114 gpio-controller;
115 #gpio-cells = <2>;
116 gpio-ranges = <&pinctrl_aobus 0 0 14>;
117 };
118
119 uart_ao_a_pins: uart_ao_a {
120 mux {
121 groups = "uart_tx_ao_a", "uart_rx_ao_a";
122 function = "uart_ao";
123 };
124 };
125
126 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
127 mux {
128 groups = "uart_cts_ao_a",
129 "uart_rts_ao_a";
130 function = "uart_ao";
131 };
132 };
133
134 uart_ao_b_pins: uart_ao_b {
135 mux {
136 groups = "uart_tx_ao_b", "uart_rx_ao_b";
137 function = "uart_ao_b";
138 };
139 };
140
141 uart_ao_b_0_1_pins: uart_ao_b_0_1 {
142 mux {
143 groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
144 function = "uart_ao_b";
145 };
146 };
147
148 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
149 mux {
150 groups = "uart_cts_ao_b",
151 "uart_rts_ao_b";
152 function = "uart_ao_b";
153 };
154 };
155
156 remote_input_ao_pins: remote_input_ao {
157 mux {
158 groups = "remote_input_ao";
159 function = "remote_input_ao";
160 };
161 };
162
163 i2c_ao_pins: i2c_ao {
164 mux {
165 groups = "i2c_sck_ao",
166 "i2c_sda_ao";
167 function = "i2c_ao";
168 };
169 };
170
171 pwm_ao_a_3_pins: pwm_ao_a_3 {
172 mux {
173 groups = "pwm_ao_a_3";
174 function = "pwm_ao_a";
175 };
176 };
177
178 pwm_ao_a_8_pins: pwm_ao_a_8 {
179 mux {
180 groups = "pwm_ao_a_8";
181 function = "pwm_ao_a";
182 };
183 };
184
185 pwm_ao_b_pins: pwm_ao_b {
186 mux {
187 groups = "pwm_ao_b";
188 function = "pwm_ao_b";
189 };
190 };
191
192 pwm_ao_b_6_pins: pwm_ao_b_6 {
193 mux {
194 groups = "pwm_ao_b_6";
195 function = "pwm_ao_b";
196 };
197 };
198
199 i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
200 mux {
201 groups = "i2s_out_ch23_ao";
202 function = "i2s_out_ao";
203 };
204 };
205
206 i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
207 mux {
208 groups = "i2s_out_ch45_ao";
209 function = "i2s_out_ao";
210 };
211 };
212
213 spdif_out_ao_6_pins: spdif_out_ao_6 {
214 mux {
215 groups = "spdif_out_ao_6";
216 function = "spdif_out_ao";
217 };
218 };
219
220 spdif_out_ao_9_pins: spdif_out_ao_9 {
221 mux {
222 groups = "spdif_out_ao_9";
223 function = "spdif_out_ao";
224 };
225 };
226
227 ao_cec_pins: ao_cec {
228 mux {
229 groups = "ao_cec";
230 function = "cec_ao";
231 };
232 };
233
234 ee_cec_pins: ee_cec {
235 mux {
236 groups = "ee_cec";
237 function = "cec_ao";
238 };
239 };
240 };
241};
242
243&cec_AO {
244 clocks = <&clkc_AO CLKID_AO_CEC_32K>;
245 clock-names = "core";
246};
247
248&clkc_AO {
249 compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
250};
251
252&gpio_intc {
253 compatible = "amlogic,meson-gpio-intc",
254 "amlogic,meson-gxl-gpio-intc";
255 status = "okay";
256};
257
258&hdmi_tx {
259 compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
260 resets = <&reset RESET_HDMITX_CAPB3>,
261 <&reset RESET_HDMI_SYSTEM_RESET>,
262 <&reset RESET_HDMI_TX>;
263 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
264 clocks = <&clkc CLKID_HDMI_PCLK>,
265 <&clkc CLKID_CLK81>,
266 <&clkc CLKID_GCLK_VENCI_INT0>;
267 clock-names = "isfr", "iahb", "venci";
268};
269
270&hiubus {
271 clkc: clock-controller@0 {
272 compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc";
273 #clock-cells = <1>;
274 reg = <0x0 0x0 0x0 0x3db>;
275 };
276};
277
278&i2c_A {
279 clocks = <&clkc CLKID_I2C>;
280};
281
282&i2c_AO {
283 clocks = <&clkc CLKID_AO_I2C>;
284};
285
286&i2c_B {
287 clocks = <&clkc CLKID_I2C>;
288};
289
290&i2c_C {
291 clocks = <&clkc CLKID_I2C>;
292};
293
294&periphs {
295 pinctrl_periphs: pinctrl@4b0 {
296 compatible = "amlogic,meson-gxl-periphs-pinctrl";
297 #address-cells = <2>;
298 #size-cells = <2>;
299 ranges;
300
301 gpio: bank@4b0 {
302 reg = <0x0 0x004b0 0x0 0x28>,
303 <0x0 0x004e8 0x0 0x14>,
304 <0x0 0x00520 0x0 0x14>,
305 <0x0 0x00430 0x0 0x40>;
306 reg-names = "mux", "pull", "pull-enable", "gpio";
307 gpio-controller;
308 #gpio-cells = <2>;
309 gpio-ranges = <&pinctrl_periphs 0 0 100>;
310 };
311
312 emmc_pins: emmc {
313 mux {
314 groups = "emmc_nand_d07",
315 "emmc_cmd",
316 "emmc_clk";
317 function = "emmc";
318 };
319 };
320
321 emmc_ds_pins: emmc-ds {
322 mux {
323 groups = "emmc_ds";
324 function = "emmc";
325 };
326 };
327
328 emmc_clk_gate_pins: emmc_clk_gate {
329 mux {
330 groups = "BOOT_8";
331 function = "gpio_periphs";
332 };
333 cfg-pull-down {
334 pins = "BOOT_8";
335 bias-pull-down;
336 };
337 };
338
339 nor_pins: nor {
340 mux {
341 groups = "nor_d",
342 "nor_q",
343 "nor_c",
344 "nor_cs";
345 function = "nor";
346 };
347 };
348
349 spi_pins: spi {
350 mux {
351 groups = "spi_miso",
352 "spi_mosi",
353 "spi_sclk";
354 function = "spi";
355 };
356 };
357
358 spi_ss0_pins: spi-ss0 {
359 mux {
360 groups = "spi_ss0";
361 function = "spi";
362 };
363 };
364
365 sdcard_pins: sdcard {
366 mux {
367 groups = "sdcard_d0",
368 "sdcard_d1",
369 "sdcard_d2",
370 "sdcard_d3",
371 "sdcard_cmd",
372 "sdcard_clk";
373 function = "sdcard";
374 };
375 };
376
377 sdcard_clk_gate_pins: sdcard_clk_gate {
378 mux {
379 groups = "CARD_2";
380 function = "gpio_periphs";
381 };
382 cfg-pull-down {
383 pins = "CARD_2";
384 bias-pull-down;
385 };
386 };
387
388 sdio_pins: sdio {
389 mux {
390 groups = "sdio_d0",
391 "sdio_d1",
392 "sdio_d2",
393 "sdio_d3",
394 "sdio_cmd",
395 "sdio_clk";
396 function = "sdio";
397 };
398 };
399
400 sdio_clk_gate_pins: sdio_clk_gate {
401 mux {
402 groups = "GPIOX_4";
403 function = "gpio_periphs";
404 };
405 cfg-pull-down {
406 pins = "GPIOX_4";
407 bias-pull-down;
408 };
409 };
410
411 sdio_irq_pins: sdio_irq {
412 mux {
413 groups = "sdio_irq";
414 function = "sdio";
415 };
416 };
417
418 uart_a_pins: uart_a {
419 mux {
420 groups = "uart_tx_a",
421 "uart_rx_a";
422 function = "uart_a";
423 };
424 };
425
426 uart_a_cts_rts_pins: uart_a_cts_rts {
427 mux {
428 groups = "uart_cts_a",
429 "uart_rts_a";
430 function = "uart_a";
431 };
432 };
433
434 uart_b_pins: uart_b {
435 mux {
436 groups = "uart_tx_b",
437 "uart_rx_b";
438 function = "uart_b";
439 };
440 };
441
442 uart_b_cts_rts_pins: uart_b_cts_rts {
443 mux {
444 groups = "uart_cts_b",
445 "uart_rts_b";
446 function = "uart_b";
447 };
448 };
449
450 uart_c_pins: uart_c {
451 mux {
452 groups = "uart_tx_c",
453 "uart_rx_c";
454 function = "uart_c";
455 };
456 };
457
458 uart_c_cts_rts_pins: uart_c_cts_rts {
459 mux {
460 groups = "uart_cts_c",
461 "uart_rts_c";
462 function = "uart_c";
463 };
464 };
465
466 i2c_a_pins: i2c_a {
467 mux {
468 groups = "i2c_sck_a",
469 "i2c_sda_a";
470 function = "i2c_a";
471 };
472 };
473
474 i2c_b_pins: i2c_b {
475 mux {
476 groups = "i2c_sck_b",
477 "i2c_sda_b";
478 function = "i2c_b";
479 };
480 };
481
482 i2c_c_pins: i2c_c {
483 mux {
484 groups = "i2c_sck_c",
485 "i2c_sda_c";
486 function = "i2c_c";
487 };
488 };
489
490 eth_pins: eth_c {
491 mux {
492 groups = "eth_mdio",
493 "eth_mdc",
494 "eth_clk_rx_clk",
495 "eth_rx_dv",
496 "eth_rxd0",
497 "eth_rxd1",
498 "eth_rxd2",
499 "eth_rxd3",
500 "eth_rgmii_tx_clk",
501 "eth_tx_en",
502 "eth_txd0",
503 "eth_txd1",
504 "eth_txd2",
505 "eth_txd3";
506 function = "eth";
507 };
508 };
509
510 eth_link_led_pins: eth_link_led {
511 mux {
512 groups = "eth_link_led";
513 function = "eth_led";
514 };
515 };
516
517 eth_act_led_pins: eth_act_led {
518 mux {
519 groups = "eth_act_led";
520 function = "eth_led";
521 };
522 };
523
524 pwm_a_pins: pwm_a {
525 mux {
526 groups = "pwm_a";
527 function = "pwm_a";
528 };
529 };
530
531 pwm_b_pins: pwm_b {
532 mux {
533 groups = "pwm_b";
534 function = "pwm_b";
535 };
536 };
537
538 pwm_c_pins: pwm_c {
539 mux {
540 groups = "pwm_c";
541 function = "pwm_c";
542 };
543 };
544
545 pwm_d_pins: pwm_d {
546 mux {
547 groups = "pwm_d";
548 function = "pwm_d";
549 };
550 };
551
552 pwm_e_pins: pwm_e {
553 mux {
554 groups = "pwm_e";
555 function = "pwm_e";
556 };
557 };
558
559 pwm_f_clk_pins: pwm_f_clk {
560 mux {
561 groups = "pwm_f_clk";
562 function = "pwm_f";
563 };
564 };
565
566 pwm_f_x_pins: pwm_f_x {
567 mux {
568 groups = "pwm_f_x";
569 function = "pwm_f";
570 };
571 };
572
573 hdmi_hpd_pins: hdmi_hpd {
574 mux {
575 groups = "hdmi_hpd";
576 function = "hdmi_hpd";
577 };
578 };
579
580 hdmi_i2c_pins: hdmi_i2c {
581 mux {
582 groups = "hdmi_sda", "hdmi_scl";
583 function = "hdmi_i2c";
584 };
585 };
586
587 i2s_am_clk_pins: i2s_am_clk {
588 mux {
589 groups = "i2s_am_clk";
590 function = "i2s_out";
591 };
592 };
593
594 i2s_out_ao_clk_pins: i2s_out_ao_clk {
595 mux {
596 groups = "i2s_out_ao_clk";
597 function = "i2s_out";
598 };
599 };
600
601 i2s_out_lr_clk_pins: i2s_out_lr_clk {
602 mux {
603 groups = "i2s_out_lr_clk";
604 function = "i2s_out";
605 };
606 };
607
608 i2s_out_ch01_pins: i2s_out_ch01 {
609 mux {
610 groups = "i2s_out_ch01";
611 function = "i2s_out";
612 };
613 };
614 i2sout_ch23_z_pins: i2sout_ch23_z {
615 mux {
616 groups = "i2sout_ch23_z";
617 function = "i2s_out";
618 };
619 };
620
621 i2sout_ch45_z_pins: i2sout_ch45_z {
622 mux {
623 groups = "i2sout_ch45_z";
624 function = "i2s_out";
625 };
626 };
627
628 i2sout_ch67_z_pins: i2sout_ch67_z {
629 mux {
630 groups = "i2sout_ch67_z";
631 function = "i2s_out";
632 };
633 };
634
635 spdif_out_h_pins: spdif_out_ao_h {
636 mux {
637 groups = "spdif_out_h";
638 function = "spdif_out";
639 };
640 };
641 };
642
643 eth-phy-mux {
644 compatible = "mdio-mux-mmioreg", "mdio-mux";
645 #address-cells = <1>;
646 #size-cells = <0>;
647 reg = <0x0 0x55c 0x0 0x4>;
648 mux-mask = <0xffffffff>;
649 mdio-parent-bus = <&mdio0>;
650
651 internal_mdio: mdio@e40908ff {
652 reg = <0xe40908ff>;
653 #address-cells = <1>;
654 #size-cells = <0>;
655
656 internal_phy: ethernet-phy@8 {
657 compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
658 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
659 reg = <8>;
660 max-speed = <100>;
661 };
662 };
663
664 external_mdio: mdio@2009087f {
665 reg = <0x2009087f>;
666 #address-cells = <1>;
667 #size-cells = <0>;
668 };
669 };
670};
671
672&pwrc_vpu {
673 resets = <&reset RESET_VIU>,
674 <&reset RESET_VENC>,
675 <&reset RESET_VCBUS>,
676 <&reset RESET_BT656>,
677 <&reset RESET_DVIN_RESET>,
678 <&reset RESET_RDMA>,
679 <&reset RESET_VENCI>,
680 <&reset RESET_VENCP>,
681 <&reset RESET_VDAC>,
682 <&reset RESET_VDI6>,
683 <&reset RESET_VENCL>,
684 <&reset RESET_VID_LOCK>;
685 clocks = <&clkc CLKID_VPU>,
686 <&clkc CLKID_VAPB>;
687 clock-names = "vpu", "vapb";
688 /*
689 * VPU clocking is provided by two identical clock paths
690 * VPU_0 and VPU_1 muxed to a single clock by a glitch
691 * free mux to safely change frequency while running.
692 * Same for VAPB but with a final gate after the glitch free mux.
693 */
694 assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
695 <&clkc CLKID_VPU_0>,
696 <&clkc CLKID_VPU>, /* Glitch free mux */
697 <&clkc CLKID_VAPB_0_SEL>,
698 <&clkc CLKID_VAPB_0>,
699 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
700 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
701 <0>, /* Do Nothing */
702 <&clkc CLKID_VPU_0>,
703 <&clkc CLKID_FCLK_DIV4>,
704 <0>, /* Do Nothing */
705 <&clkc CLKID_VAPB_0>;
706 assigned-clock-rates = <0>, /* Do Nothing */
707 <666666666>,
708 <0>, /* Do Nothing */
709 <0>, /* Do Nothing */
710 <250000000>,
711 <0>; /* Do Nothing */
712};
713
714&saradc {
715 compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
716 clocks = <&xtal>,
717 <&clkc CLKID_SAR_ADC>,
718 <&clkc CLKID_SAR_ADC_CLK>,
719 <&clkc CLKID_SAR_ADC_SEL>;
720 clock-names = "clkin", "core", "adc_clk", "adc_sel";
721};
722
723&sd_emmc_a {
724 clocks = <&clkc CLKID_SD_EMMC_A>,
725 <&clkc CLKID_SD_EMMC_A_CLK0>,
726 <&clkc CLKID_FCLK_DIV2>;
727 clock-names = "core", "clkin0", "clkin1";
728};
729
730&sd_emmc_b {
731 clocks = <&clkc CLKID_SD_EMMC_B>,
732 <&clkc CLKID_SD_EMMC_B_CLK0>,
733 <&clkc CLKID_FCLK_DIV2>;
734 clock-names = "core", "clkin0", "clkin1";
735};
736
737&sd_emmc_c {
738 clocks = <&clkc CLKID_SD_EMMC_C>,
739 <&clkc CLKID_SD_EMMC_C_CLK0>,
740 <&clkc CLKID_FCLK_DIV2>;
741 clock-names = "core", "clkin0", "clkin1";
742};
743
744&spicc {
745 clocks = <&clkc CLKID_SPICC>;
746 clock-names = "core";
747 resets = <&reset RESET_PERIPHS_SPICC>;
748 num-cs = <1>;
749};
750
751&spifc {
752 clocks = <&clkc CLKID_SPI>;
753};
754
755&uart_A {
756 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
757 clock-names = "xtal", "pclk", "baud";
758};
759
760&uart_AO {
761 clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
762 clock-names = "xtal", "pclk", "baud";
763};
764
765&uart_AO_B {
766 clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
767 clock-names = "xtal", "pclk", "baud";
768};
769
770&uart_B {
771 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
772 clock-names = "xtal", "pclk", "baud";
773};
774
775&uart_C {
776 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
777 clock-names = "xtal", "pclk", "baud";
778};
779
780&vpu {
781 compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
782 power-domains = <&pwrc_vpu>;
783};
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2016 Endless Computers, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
5 */
6
7#include "meson-gx.dtsi"
8#include <dt-bindings/clock/gxbb-clkc.h>
9#include <dt-bindings/clock/gxbb-aoclkc.h>
10#include <dt-bindings/gpio/meson-gxl-gpio.h>
11#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
12
13/ {
14 compatible = "amlogic,meson-gxl";
15
16 soc {
17 usb: usb@d0078080 {
18 compatible = "amlogic,meson-gxl-usb-ctrl";
19 reg = <0x0 0xd0078080 0x0 0x20>;
20 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
21 #address-cells = <2>;
22 #size-cells = <2>;
23 ranges;
24
25 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
26 clock-names = "usb_ctrl", "ddr";
27 resets = <&reset RESET_USB_OTG>;
28
29 dr_mode = "otg";
30
31 phys = <&usb2_phy0>, <&usb2_phy1>;
32 phy-names = "usb2-phy0", "usb2-phy1";
33
34 dwc2: usb@c9100000 {
35 compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
36 reg = <0x0 0xc9100000 0x0 0x40000>;
37 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
38 clocks = <&clkc CLKID_USB1>;
39 clock-names = "otg";
40 phys = <&usb2_phy1>;
41 dr_mode = "peripheral";
42 g-rx-fifo-size = <192>;
43 g-np-tx-fifo-size = <128>;
44 g-tx-fifo-size = <128 128 16 16 16>;
45 };
46
47 dwc3: usb@c9000000 {
48 compatible = "snps,dwc3";
49 reg = <0x0 0xc9000000 0x0 0x100000>;
50 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
51 dr_mode = "host";
52 maximum-speed = "high-speed";
53 snps,dis_u2_susphy_quirk;
54 };
55 };
56
57 acodec: audio-controller@c8832000 {
58 compatible = "amlogic,t9015";
59 reg = <0x0 0xc8832000 0x0 0x14>;
60 #sound-dai-cells = <0>;
61 sound-name-prefix = "ACODEC";
62 clocks = <&clkc CLKID_ACODEC>;
63 clock-names = "pclk";
64 resets = <&reset RESET_ACODEC>;
65 status = "disabled";
66 };
67
68 crypto: crypto@c883e000 {
69 compatible = "amlogic,gxl-crypto";
70 reg = <0x0 0xc883e000 0x0 0x36>;
71 interrupts = <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
72 <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
73 clocks = <&clkc CLKID_BLKMV>;
74 clock-names = "blkmv";
75 status = "okay";
76 };
77 };
78};
79
80&aiu {
81 compatible = "amlogic,aiu-gxl", "amlogic,aiu";
82 clocks = <&clkc CLKID_AIU_GLUE>,
83 <&clkc CLKID_I2S_OUT>,
84 <&clkc CLKID_AOCLK_GATE>,
85 <&clkc CLKID_CTS_AMCLK>,
86 <&clkc CLKID_MIXER_IFACE>,
87 <&clkc CLKID_IEC958>,
88 <&clkc CLKID_IEC958_GATE>,
89 <&clkc CLKID_CTS_MCLK_I958>,
90 <&clkc CLKID_CTS_I958>;
91 clock-names = "pclk",
92 "i2s_pclk",
93 "i2s_aoclk",
94 "i2s_mclk",
95 "i2s_mixer",
96 "spdif_pclk",
97 "spdif_aoclk",
98 "spdif_mclk",
99 "spdif_mclk_sel";
100 resets = <&reset RESET_AIU>;
101};
102
103&apb {
104 usb2_phy0: phy@78000 {
105 compatible = "amlogic,meson-gxl-usb2-phy";
106 #phy-cells = <0>;
107 reg = <0x0 0x78000 0x0 0x20>;
108 clocks = <&clkc CLKID_USB>;
109 clock-names = "phy";
110 resets = <&reset RESET_USB_OTG>;
111 reset-names = "phy";
112 status = "okay";
113 };
114
115 usb2_phy1: phy@78020 {
116 compatible = "amlogic,meson-gxl-usb2-phy";
117 #phy-cells = <0>;
118 reg = <0x0 0x78020 0x0 0x20>;
119 clocks = <&clkc CLKID_USB>;
120 clock-names = "phy";
121 resets = <&reset RESET_USB_OTG>;
122 reset-names = "phy";
123 status = "okay";
124 };
125};
126
127&efuse {
128 clocks = <&clkc CLKID_EFUSE>;
129};
130
131ðmac {
132 clocks = <&clkc CLKID_ETH>,
133 <&clkc CLKID_FCLK_DIV2>,
134 <&clkc CLKID_MPLL2>,
135 <&clkc CLKID_FCLK_DIV2>;
136 clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
137
138 mdio0: mdio {
139 #address-cells = <1>;
140 #size-cells = <0>;
141 compatible = "snps,dwmac-mdio";
142 };
143};
144
145&aobus {
146 pinctrl_aobus: pinctrl@14 {
147 compatible = "amlogic,meson-gxl-aobus-pinctrl";
148 #address-cells = <2>;
149 #size-cells = <2>;
150 ranges;
151
152 gpio_ao: bank@14 {
153 reg = <0x0 0x00014 0x0 0x8>,
154 <0x0 0x0002c 0x0 0x4>,
155 <0x0 0x00024 0x0 0x8>;
156 reg-names = "mux", "pull", "gpio";
157 gpio-controller;
158 #gpio-cells = <2>;
159 gpio-ranges = <&pinctrl_aobus 0 0 14>;
160 };
161
162 uart_ao_a_pins: uart_ao_a {
163 mux {
164 groups = "uart_tx_ao_a", "uart_rx_ao_a";
165 function = "uart_ao";
166 bias-disable;
167 };
168 };
169
170 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
171 mux {
172 groups = "uart_cts_ao_a",
173 "uart_rts_ao_a";
174 function = "uart_ao";
175 bias-disable;
176 };
177 };
178
179 uart_ao_b_pins: uart_ao_b {
180 mux {
181 groups = "uart_tx_ao_b", "uart_rx_ao_b";
182 function = "uart_ao_b";
183 bias-disable;
184 };
185 };
186
187 uart_ao_b_0_1_pins: uart_ao_b_0_1 {
188 mux {
189 groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
190 function = "uart_ao_b";
191 bias-disable;
192 };
193 };
194
195 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
196 mux {
197 groups = "uart_cts_ao_b",
198 "uart_rts_ao_b";
199 function = "uart_ao_b";
200 bias-disable;
201 };
202 };
203
204 remote_input_ao_pins: remote_input_ao {
205 mux {
206 groups = "remote_input_ao";
207 function = "remote_input_ao";
208 bias-disable;
209 };
210 };
211
212 i2c_ao_pins: i2c_ao {
213 mux {
214 groups = "i2c_sck_ao",
215 "i2c_sda_ao";
216 function = "i2c_ao";
217 bias-disable;
218 };
219 };
220
221 pwm_ao_a_3_pins: pwm_ao_a_3 {
222 mux {
223 groups = "pwm_ao_a_3";
224 function = "pwm_ao_a";
225 bias-disable;
226 };
227 };
228
229 pwm_ao_a_8_pins: pwm_ao_a_8 {
230 mux {
231 groups = "pwm_ao_a_8";
232 function = "pwm_ao_a";
233 bias-disable;
234 };
235 };
236
237 pwm_ao_b_pins: pwm_ao_b {
238 mux {
239 groups = "pwm_ao_b";
240 function = "pwm_ao_b";
241 bias-disable;
242 };
243 };
244
245 pwm_ao_b_6_pins: pwm_ao_b_6 {
246 mux {
247 groups = "pwm_ao_b_6";
248 function = "pwm_ao_b";
249 bias-disable;
250 };
251 };
252
253 i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
254 mux {
255 groups = "i2s_out_ch23_ao";
256 function = "i2s_out_ao";
257 bias-disable;
258 };
259 };
260
261 i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
262 mux {
263 groups = "i2s_out_ch45_ao";
264 function = "i2s_out_ao";
265 bias-disable;
266 };
267 };
268
269 spdif_out_ao_6_pins: spdif_out_ao_6 {
270 mux {
271 groups = "spdif_out_ao_6";
272 function = "spdif_out_ao";
273 bias-disable;
274 };
275 };
276
277 spdif_out_ao_9_pins: spdif_out_ao_9 {
278 mux {
279 groups = "spdif_out_ao_9";
280 function = "spdif_out_ao";
281 bias-disable;
282 };
283 };
284
285 ao_cec_pins: ao_cec {
286 mux {
287 groups = "ao_cec";
288 function = "cec_ao";
289 bias-disable;
290 };
291 };
292
293 ee_cec_pins: ee_cec {
294 mux {
295 groups = "ee_cec";
296 function = "cec_ao";
297 bias-disable;
298 };
299 };
300 };
301};
302
303&cec_AO {
304 clocks = <&clkc_AO CLKID_AO_CEC_32K>;
305 clock-names = "core";
306};
307
308&clkc_AO {
309 compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
310 clocks = <&xtal>, <&clkc CLKID_CLK81>;
311 clock-names = "xtal", "mpeg-clk";
312};
313
314&gpio_intc {
315 compatible = "amlogic,meson-gpio-intc",
316 "amlogic,meson-gxl-gpio-intc";
317 status = "okay";
318};
319
320&hdmi_tx {
321 compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
322 resets = <&reset RESET_HDMITX_CAPB3>,
323 <&reset RESET_HDMI_SYSTEM_RESET>,
324 <&reset RESET_HDMI_TX>;
325 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
326 clocks = <&clkc CLKID_HDMI_PCLK>,
327 <&clkc CLKID_CLK81>,
328 <&clkc CLKID_GCLK_VENCI_INT0>;
329 clock-names = "isfr", "iahb", "venci";
330};
331
332&sysctrl {
333 clkc: clock-controller {
334 compatible = "amlogic,gxl-clkc";
335 #clock-cells = <1>;
336 clocks = <&xtal>;
337 clock-names = "xtal";
338 };
339};
340
341&hwrng {
342 clocks = <&clkc CLKID_RNG0>;
343 clock-names = "core";
344};
345
346&i2c_A {
347 clocks = <&clkc CLKID_I2C>;
348};
349
350&i2c_AO {
351 clocks = <&clkc CLKID_AO_I2C>;
352};
353
354&i2c_B {
355 clocks = <&clkc CLKID_I2C>;
356};
357
358&i2c_C {
359 clocks = <&clkc CLKID_I2C>;
360};
361
362&periphs {
363 pinctrl_periphs: pinctrl@4b0 {
364 compatible = "amlogic,meson-gxl-periphs-pinctrl";
365 #address-cells = <2>;
366 #size-cells = <2>;
367 ranges;
368
369 gpio: bank@4b0 {
370 reg = <0x0 0x004b0 0x0 0x28>,
371 <0x0 0x004e8 0x0 0x14>,
372 <0x0 0x00520 0x0 0x14>,
373 <0x0 0x00430 0x0 0x40>;
374 reg-names = "mux", "pull", "pull-enable", "gpio";
375 gpio-controller;
376 #gpio-cells = <2>;
377 gpio-ranges = <&pinctrl_periphs 0 0 100>;
378 };
379
380 emmc_pins: emmc {
381 mux-0 {
382 groups = "emmc_nand_d07",
383 "emmc_cmd";
384 function = "emmc";
385 bias-pull-up;
386 };
387
388 mux-1 {
389 groups = "emmc_clk";
390 function = "emmc";
391 bias-disable;
392 };
393 };
394
395 emmc_ds_pins: emmc-ds {
396 mux {
397 groups = "emmc_ds";
398 function = "emmc";
399 bias-pull-down;
400 };
401 };
402
403 emmc_clk_gate_pins: emmc_clk_gate {
404 mux {
405 groups = "BOOT_8";
406 function = "gpio_periphs";
407 bias-pull-down;
408 };
409 };
410
411 nor_pins: nor {
412 mux {
413 groups = "nor_d",
414 "nor_q",
415 "nor_c",
416 "nor_cs";
417 function = "nor";
418 bias-disable;
419 };
420 };
421
422 spi_pins: spi-pins {
423 mux {
424 groups = "spi_miso",
425 "spi_mosi",
426 "spi_sclk";
427 function = "spi";
428 bias-disable;
429 };
430 };
431
432 spi_idle_high_pins: spi-idle-high-pins {
433 mux {
434 groups = "spi_sclk";
435 bias-pull-up;
436 };
437 };
438
439 spi_idle_low_pins: spi-idle-low-pins {
440 mux {
441 groups = "spi_sclk";
442 bias-pull-down;
443 };
444 };
445
446 spi_ss0_pins: spi-ss0 {
447 mux {
448 groups = "spi_ss0";
449 function = "spi";
450 bias-disable;
451 };
452 };
453
454 sdcard_pins: sdcard {
455 mux-0 {
456 groups = "sdcard_d0",
457 "sdcard_d1",
458 "sdcard_d2",
459 "sdcard_d3",
460 "sdcard_cmd";
461 function = "sdcard";
462 bias-pull-up;
463 };
464
465 mux-1 {
466 groups = "sdcard_clk";
467 function = "sdcard";
468 bias-disable;
469 };
470 };
471
472 sdcard_clk_gate_pins: sdcard_clk_gate {
473 mux {
474 groups = "CARD_2";
475 function = "gpio_periphs";
476 bias-pull-down;
477 };
478 };
479
480 sdio_pins: sdio {
481 mux-0 {
482 groups = "sdio_d0",
483 "sdio_d1",
484 "sdio_d2",
485 "sdio_d3",
486 "sdio_cmd";
487 function = "sdio";
488 bias-pull-up;
489 };
490
491 mux-1 {
492 groups = "sdio_clk";
493 function = "sdio";
494 bias-disable;
495 };
496 };
497
498 sdio_clk_gate_pins: sdio_clk_gate {
499 mux {
500 groups = "GPIOX_4";
501 function = "gpio_periphs";
502 bias-pull-down;
503 };
504 };
505
506 sdio_irq_pins: sdio_irq {
507 mux {
508 groups = "sdio_irq";
509 function = "sdio";
510 bias-disable;
511 };
512 };
513
514 uart_a_pins: uart_a {
515 mux {
516 groups = "uart_tx_a",
517 "uart_rx_a";
518 function = "uart_a";
519 bias-disable;
520 };
521 };
522
523 uart_a_cts_rts_pins: uart_a_cts_rts {
524 mux {
525 groups = "uart_cts_a",
526 "uart_rts_a";
527 function = "uart_a";
528 bias-disable;
529 };
530 };
531
532 uart_b_pins: uart_b {
533 mux {
534 groups = "uart_tx_b",
535 "uart_rx_b";
536 function = "uart_b";
537 bias-disable;
538 };
539 };
540
541 uart_b_cts_rts_pins: uart_b_cts_rts {
542 mux {
543 groups = "uart_cts_b",
544 "uart_rts_b";
545 function = "uart_b";
546 bias-disable;
547 };
548 };
549
550 uart_c_pins: uart_c {
551 mux {
552 groups = "uart_tx_c",
553 "uart_rx_c";
554 function = "uart_c";
555 bias-disable;
556 };
557 };
558
559 uart_c_cts_rts_pins: uart_c_cts_rts {
560 mux {
561 groups = "uart_cts_c",
562 "uart_rts_c";
563 function = "uart_c";
564 bias-disable;
565 };
566 };
567
568 i2c_a_pins: i2c_a {
569 mux {
570 groups = "i2c_sck_a",
571 "i2c_sda_a";
572 function = "i2c_a";
573 bias-disable;
574 };
575 };
576
577 i2c_b_pins: i2c_b {
578 mux {
579 groups = "i2c_sck_b",
580 "i2c_sda_b";
581 function = "i2c_b";
582 bias-disable;
583 };
584 };
585
586 i2c_c_pins: i2c_c {
587 mux {
588 groups = "i2c_sck_c",
589 "i2c_sda_c";
590 function = "i2c_c";
591 bias-disable;
592 };
593 };
594
595 i2c_c_dv18_pins: i2c_c_dv18 {
596 mux {
597 groups = "i2c_sck_c_dv19",
598 "i2c_sda_c_dv18";
599 function = "i2c_c";
600 bias-disable;
601 };
602 };
603
604 eth_pins: eth_c {
605 mux {
606 groups = "eth_mdio",
607 "eth_mdc",
608 "eth_clk_rx_clk",
609 "eth_rx_dv",
610 "eth_rxd0",
611 "eth_rxd1",
612 "eth_rxd2",
613 "eth_rxd3",
614 "eth_rgmii_tx_clk",
615 "eth_tx_en",
616 "eth_txd0",
617 "eth_txd1",
618 "eth_txd2",
619 "eth_txd3";
620 function = "eth";
621 bias-disable;
622 };
623 };
624
625 eth_link_led_pins: eth_link_led {
626 mux {
627 groups = "eth_link_led";
628 function = "eth_led";
629 bias-disable;
630 };
631 };
632
633 eth_act_led_pins: eth_act_led {
634 mux {
635 groups = "eth_act_led";
636 function = "eth_led";
637 };
638 };
639
640 pwm_a_pins: pwm_a {
641 mux {
642 groups = "pwm_a";
643 function = "pwm_a";
644 bias-disable;
645 };
646 };
647
648 pwm_b_pins: pwm_b {
649 mux {
650 groups = "pwm_b";
651 function = "pwm_b";
652 bias-disable;
653 };
654 };
655
656 pwm_c_pins: pwm_c {
657 mux {
658 groups = "pwm_c";
659 function = "pwm_c";
660 bias-disable;
661 };
662 };
663
664 pwm_d_pins: pwm_d {
665 mux {
666 groups = "pwm_d";
667 function = "pwm_d";
668 bias-disable;
669 };
670 };
671
672 pwm_e_pins: pwm_e {
673 mux {
674 groups = "pwm_e";
675 function = "pwm_e";
676 bias-disable;
677 };
678 };
679
680 pwm_f_clk_pins: pwm_f_clk {
681 mux {
682 groups = "pwm_f_clk";
683 function = "pwm_f";
684 bias-disable;
685 };
686 };
687
688 pwm_f_x_pins: pwm_f_x {
689 mux {
690 groups = "pwm_f_x";
691 function = "pwm_f";
692 bias-disable;
693 };
694 };
695
696 hdmi_hpd_pins: hdmi_hpd {
697 mux {
698 groups = "hdmi_hpd";
699 function = "hdmi_hpd";
700 bias-disable;
701 };
702 };
703
704 hdmi_i2c_pins: hdmi_i2c {
705 mux {
706 groups = "hdmi_sda", "hdmi_scl";
707 function = "hdmi_i2c";
708 bias-disable;
709 };
710 };
711
712 i2s_am_clk_pins: i2s_am_clk {
713 mux {
714 groups = "i2s_am_clk";
715 function = "i2s_out";
716 bias-disable;
717 };
718 };
719
720 i2s_out_ao_clk_pins: i2s_out_ao_clk {
721 mux {
722 groups = "i2s_out_ao_clk";
723 function = "i2s_out";
724 bias-disable;
725 };
726 };
727
728 i2s_out_lr_clk_pins: i2s_out_lr_clk {
729 mux {
730 groups = "i2s_out_lr_clk";
731 function = "i2s_out";
732 bias-disable;
733 };
734 };
735
736 i2s_out_ch01_pins: i2s_out_ch01 {
737 mux {
738 groups = "i2s_out_ch01";
739 function = "i2s_out";
740 bias-disable;
741 };
742 };
743 i2sout_ch23_z_pins: i2sout_ch23_z {
744 mux {
745 groups = "i2sout_ch23_z";
746 function = "i2s_out";
747 bias-disable;
748 };
749 };
750
751 i2sout_ch45_z_pins: i2sout_ch45_z {
752 mux {
753 groups = "i2sout_ch45_z";
754 function = "i2s_out";
755 bias-disable;
756 };
757 };
758
759 i2sout_ch67_z_pins: i2sout_ch67_z {
760 mux {
761 groups = "i2sout_ch67_z";
762 function = "i2s_out";
763 bias-disable;
764 };
765 };
766
767 spdif_out_h_pins: spdif_out_ao_h {
768 mux {
769 groups = "spdif_out_h";
770 function = "spdif_out";
771 bias-disable;
772 };
773 };
774 };
775
776 eth-phy-mux {
777 compatible = "mdio-mux-mmioreg", "mdio-mux";
778 #address-cells = <1>;
779 #size-cells = <0>;
780 reg = <0x0 0x55c 0x0 0x4>;
781 mux-mask = <0xffffffff>;
782 mdio-parent-bus = <&mdio0>;
783
784 internal_mdio: mdio@e40908ff {
785 reg = <0xe40908ff>;
786 #address-cells = <1>;
787 #size-cells = <0>;
788
789 internal_phy: ethernet-phy@8 {
790 compatible = "ethernet-phy-id0181.4400";
791 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
792 reg = <8>;
793 max-speed = <100>;
794 };
795 };
796
797 external_mdio: mdio@2009087f {
798 reg = <0x2009087f>;
799 #address-cells = <1>;
800 #size-cells = <0>;
801 };
802 };
803};
804
805&pwrc {
806 resets = <&reset RESET_VIU>,
807 <&reset RESET_VENC>,
808 <&reset RESET_VCBUS>,
809 <&reset RESET_BT656>,
810 <&reset RESET_DVIN_RESET>,
811 <&reset RESET_RDMA>,
812 <&reset RESET_VENCI>,
813 <&reset RESET_VENCP>,
814 <&reset RESET_VDAC>,
815 <&reset RESET_VDI6>,
816 <&reset RESET_VENCL>,
817 <&reset RESET_VID_LOCK>;
818 reset-names = "viu", "venc", "vcbus", "bt656",
819 "dvin", "rdma", "venci", "vencp",
820 "vdac", "vdi6", "vencl", "vid_lock";
821 clocks = <&clkc CLKID_VPU>,
822 <&clkc CLKID_VAPB>;
823 clock-names = "vpu", "vapb";
824 /*
825 * VPU clocking is provided by two identical clock paths
826 * VPU_0 and VPU_1 muxed to a single clock by a glitch
827 * free mux to safely change frequency while running.
828 * Same for VAPB but with a final gate after the glitch free mux.
829 */
830 assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
831 <&clkc CLKID_VPU_0>,
832 <&clkc CLKID_VPU>, /* Glitch free mux */
833 <&clkc CLKID_VAPB_0_SEL>,
834 <&clkc CLKID_VAPB_0>,
835 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
836 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
837 <0>, /* Do Nothing */
838 <&clkc CLKID_VPU_0>,
839 <&clkc CLKID_FCLK_DIV4>,
840 <0>, /* Do Nothing */
841 <&clkc CLKID_VAPB_0>;
842 assigned-clock-rates = <0>, /* Do Nothing */
843 <666666666>,
844 <0>, /* Do Nothing */
845 <0>, /* Do Nothing */
846 <250000000>,
847 <0>; /* Do Nothing */
848};
849
850&saradc {
851 compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
852 clocks = <&xtal>,
853 <&clkc CLKID_SAR_ADC>,
854 <&clkc CLKID_SAR_ADC_CLK>,
855 <&clkc CLKID_SAR_ADC_SEL>;
856 clock-names = "clkin", "core", "adc_clk", "adc_sel";
857};
858
859&sd_emmc_a {
860 clocks = <&clkc CLKID_SD_EMMC_A>,
861 <&clkc CLKID_SD_EMMC_A_CLK0>,
862 <&clkc CLKID_FCLK_DIV2>;
863 clock-names = "core", "clkin0", "clkin1";
864 resets = <&reset RESET_SD_EMMC_A>;
865};
866
867&sd_emmc_b {
868 clocks = <&clkc CLKID_SD_EMMC_B>,
869 <&clkc CLKID_SD_EMMC_B_CLK0>,
870 <&clkc CLKID_FCLK_DIV2>;
871 clock-names = "core", "clkin0", "clkin1";
872 resets = <&reset RESET_SD_EMMC_B>;
873};
874
875&sd_emmc_c {
876 clocks = <&clkc CLKID_SD_EMMC_C>,
877 <&clkc CLKID_SD_EMMC_C_CLK0>,
878 <&clkc CLKID_FCLK_DIV2>;
879 clock-names = "core", "clkin0", "clkin1";
880 resets = <&reset RESET_SD_EMMC_C>;
881};
882
883&simplefb_hdmi {
884 clocks = <&clkc CLKID_HDMI_PCLK>,
885 <&clkc CLKID_CLK81>,
886 <&clkc CLKID_GCLK_VENCI_INT0>;
887};
888
889&spicc {
890 clocks = <&clkc CLKID_SPICC>;
891 clock-names = "core";
892 resets = <&reset RESET_PERIPHS_SPICC>;
893 num-cs = <1>;
894};
895
896&spifc {
897 clocks = <&clkc CLKID_SPI>;
898};
899
900&uart_A {
901 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
902 clock-names = "xtal", "pclk", "baud";
903};
904
905&uart_AO {
906 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
907 clock-names = "xtal", "pclk", "baud";
908};
909
910&uart_AO_B {
911 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
912 clock-names = "xtal", "pclk", "baud";
913};
914
915&uart_B {
916 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
917 clock-names = "xtal", "pclk", "baud";
918};
919
920&uart_C {
921 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
922 clock-names = "xtal", "pclk", "baud";
923};
924
925&vpu {
926 compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
927 power-domains = <&pwrc PWRC_GXBB_VPU_ID>;
928};
929
930&vdec {
931 compatible = "amlogic,gxl-vdec", "amlogic,gx-vdec";
932 clocks = <&clkc CLKID_DOS_PARSER>,
933 <&clkc CLKID_DOS>,
934 <&clkc CLKID_VDEC_1>,
935 <&clkc CLKID_VDEC_HEVC>;
936 clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc";
937 resets = <&reset RESET_PARSER>;
938 reset-names = "esparser";
939};