1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2/*
  3 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
  4 */
  5
  6#include <dt-bindings/interrupt-controller/irq.h>
  7#include <dt-bindings/interrupt-controller/arm-gic.h>
  8#include <dt-bindings/gpio/meson-a1-gpio.h>
  9
 10/ {
 11	compatible = "amlogic,a1";
 12
 13	interrupt-parent = <&gic>;
 14	#address-cells = <2>;
 15	#size-cells = <2>;
 16
 17	cpus {
 18		#address-cells = <2>;
 19		#size-cells = <0>;
 20
 21		cpu0: cpu@0 {
 22			device_type = "cpu";
 23			compatible = "arm,cortex-a35";
 24			reg = <0x0 0x0>;
 25			enable-method = "psci";
 26			next-level-cache = <&l2>;
 27		};
 28
 29		cpu1: cpu@1 {
 30			device_type = "cpu";
 31			compatible = "arm,cortex-a35";
 32			reg = <0x0 0x1>;
 33			enable-method = "psci";
 34			next-level-cache = <&l2>;
 35		};
 36
 37		l2: l2-cache0 {
 38			compatible = "cache";
 39			cache-level = <2>;
 40		};
 41	};
 42
 43	psci {
 44		compatible = "arm,psci-1.0";
 45		method = "smc";
 46	};
 47
 48	reserved-memory {
 49		#address-cells = <2>;
 50		#size-cells = <2>;
 51		ranges;
 52
 53		linux,cma {
 54			compatible = "shared-dma-pool";
 55			reusable;
 56			size = <0x0 0x800000>;
 57			alignment = <0x0 0x400000>;
 58			linux,cma-default;
 59		};
 60	};
 61
 62	sm: secure-monitor {
 63		compatible = "amlogic,meson-gxbb-sm";
 64
 65		pwrc: power-controller {
 66			compatible = "amlogic,meson-a1-pwrc";
 67			#power-domain-cells = <1>;
 68			status = "okay";
 69		};
 70	};
 71
 72	soc {
 73		compatible = "simple-bus";
 74		#address-cells = <2>;
 75		#size-cells = <2>;
 76		ranges;
 77
 78		apb: bus@fe000000 {
 79			compatible = "simple-bus";
 80			reg = <0x0 0xfe000000 0x0 0x1000000>;
 81			#address-cells = <2>;
 82			#size-cells = <2>;
 83			ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>;
 84
 85
 86			reset: reset-controller@0 {
 87				compatible = "amlogic,meson-a1-reset";
 88				reg = <0x0 0x0 0x0 0x8c>;
 89				#reset-cells = <1>;
 90			};
 91
 92			periphs_pinctrl: pinctrl@400 {
 93				compatible = "amlogic,meson-a1-periphs-pinctrl";
 94				#address-cells = <2>;
 95				#size-cells = <2>;
 96				ranges;
 97
 98				gpio: bank@400 {
 99					reg = <0x0 0x0400 0x0 0x003c>,
100					      <0x0 0x0480 0x0 0x0118>;
101					reg-names = "mux", "gpio";
102					gpio-controller;
103					#gpio-cells = <2>;
104					gpio-ranges = <&periphs_pinctrl 0 0 62>;
105				};
106
107			};
108
109			uart_AO: serial@1c00 {
110				compatible = "amlogic,meson-gx-uart",
111					     "amlogic,meson-ao-uart";
112				reg = <0x0 0x1c00 0x0 0x18>;
113				interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
114				clocks = <&xtal>, <&xtal>, <&xtal>;
115				clock-names = "xtal", "pclk", "baud";
116				status = "disabled";
117			};
118
119			uart_AO_B: serial@2000 {
120				compatible = "amlogic,meson-gx-uart",
121					     "amlogic,meson-ao-uart";
122				reg = <0x0 0x2000 0x0 0x18>;
123				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
124				clocks = <&xtal>, <&xtal>, <&xtal>;
125				clock-names = "xtal", "pclk", "baud";
126				status = "disabled";
127			};
128		};
129
130		gic: interrupt-controller@ff901000 {
131			compatible = "arm,gic-400";
132			reg = <0x0 0xff901000 0x0 0x1000>,
133			      <0x0 0xff902000 0x0 0x2000>,
134			      <0x0 0xff904000 0x0 0x2000>,
135			      <0x0 0xff906000 0x0 0x2000>;
136			interrupt-controller;
137			interrupts = <GIC_PPI 9
138				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
139			#interrupt-cells = <3>;
140			#address-cells = <0>;
141		};
142	};
143
144	timer {
145		compatible = "arm,armv8-timer";
146		interrupts = <GIC_PPI 13
147			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
148			     <GIC_PPI 14
149			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
150			     <GIC_PPI 11
151			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
152			     <GIC_PPI 10
153			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
154	};
155
156	xtal: xtal-clk {
157		compatible = "fixed-clock";
158		clock-frequency = <24000000>;
159		clock-output-names = "xtal";
160		#clock-cells = <0>;
161	};
162};