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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ARM Ltd. Versatile Express
4 *
5 * Motherboard Express uATX
6 * V2M-P1
7 *
8 * HBI-0190D
9 *
10 * Original memory map ("Legacy memory map" in the board's
11 * Technical Reference Manual)
12 *
13 * WARNING! The hardware described in this file is independent from the
14 * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
15 * correspondence between the two configurations.
16 *
17 * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
18 * CHANGES TO vexpress-v2m-rs1.dtsi!
19 */
20
21 motherboard {
22 model = "V2M-P1";
23 arm,hbi = <0x190>;
24 arm,vexpress,site = <0>;
25 compatible = "arm,vexpress,v2m-p1", "simple-bus";
26 #address-cells = <2>; /* SMB chipselect number and offset */
27 #size-cells = <1>;
28 #interrupt-cells = <1>;
29 ranges;
30
31 flash@0,00000000 {
32 compatible = "arm,vexpress-flash", "cfi-flash";
33 reg = <0 0x00000000 0x04000000>,
34 <1 0x00000000 0x04000000>;
35 bank-width = <4>;
36 };
37
38 psram@2,00000000 {
39 compatible = "arm,vexpress-psram", "mtd-ram";
40 reg = <2 0x00000000 0x02000000>;
41 bank-width = <4>;
42 };
43
44 v2m_video_ram: vram@3,00000000 {
45 compatible = "arm,vexpress-vram";
46 reg = <3 0x00000000 0x00800000>;
47 };
48
49 ethernet@3,02000000 {
50 compatible = "smsc,lan9118", "smsc,lan9115";
51 reg = <3 0x02000000 0x10000>;
52 interrupts = <15>;
53 phy-mode = "mii";
54 reg-io-width = <4>;
55 smsc,irq-active-high;
56 smsc,irq-push-pull;
57 vdd33a-supply = <&v2m_fixed_3v3>;
58 vddvario-supply = <&v2m_fixed_3v3>;
59 };
60
61 usb@3,03000000 {
62 compatible = "nxp,usb-isp1761";
63 reg = <3 0x03000000 0x20000>;
64 interrupts = <16>;
65 port1-otg;
66 };
67
68 iofpga@7,00000000 {
69 compatible = "simple-bus";
70 #address-cells = <1>;
71 #size-cells = <1>;
72 ranges = <0 7 0 0x20000>;
73
74 v2m_sysreg: sysreg@0 {
75 compatible = "arm,vexpress-sysreg";
76 reg = <0x00000 0x1000>;
77
78 v2m_led_gpios: sys_led {
79 compatible = "arm,vexpress-sysreg,sys_led";
80 gpio-controller;
81 #gpio-cells = <2>;
82 };
83
84 v2m_mmc_gpios: sys_mci {
85 compatible = "arm,vexpress-sysreg,sys_mci";
86 gpio-controller;
87 #gpio-cells = <2>;
88 };
89
90 v2m_flash_gpios: sys_flash {
91 compatible = "arm,vexpress-sysreg,sys_flash";
92 gpio-controller;
93 #gpio-cells = <2>;
94 };
95 };
96
97 v2m_sysctl: sysctl@1000 {
98 compatible = "arm,sp810", "arm,primecell";
99 reg = <0x01000 0x1000>;
100 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
101 clock-names = "refclk", "timclk", "apb_pclk";
102 #clock-cells = <1>;
103 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
104 assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
105 assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
106 };
107
108 /* PCI-E I2C bus */
109 v2m_i2c_pcie: i2c@2000 {
110 compatible = "arm,versatile-i2c";
111 reg = <0x02000 0x1000>;
112
113 #address-cells = <1>;
114 #size-cells = <0>;
115
116 pcie-switch@60 {
117 compatible = "idt,89hpes32h8";
118 reg = <0x60>;
119 };
120 };
121
122 aaci@4000 {
123 compatible = "arm,pl041", "arm,primecell";
124 reg = <0x04000 0x1000>;
125 interrupts = <11>;
126 clocks = <&smbclk>;
127 clock-names = "apb_pclk";
128 };
129
130 mmci@5000 {
131 compatible = "arm,pl180", "arm,primecell";
132 reg = <0x05000 0x1000>;
133 interrupts = <9 10>;
134 cd-gpios = <&v2m_mmc_gpios 0 0>;
135 wp-gpios = <&v2m_mmc_gpios 1 0>;
136 max-frequency = <12000000>;
137 vmmc-supply = <&v2m_fixed_3v3>;
138 clocks = <&v2m_clk24mhz>, <&smbclk>;
139 clock-names = "mclk", "apb_pclk";
140 };
141
142 kmi@6000 {
143 compatible = "arm,pl050", "arm,primecell";
144 reg = <0x06000 0x1000>;
145 interrupts = <12>;
146 clocks = <&v2m_clk24mhz>, <&smbclk>;
147 clock-names = "KMIREFCLK", "apb_pclk";
148 };
149
150 kmi@7000 {
151 compatible = "arm,pl050", "arm,primecell";
152 reg = <0x07000 0x1000>;
153 interrupts = <13>;
154 clocks = <&v2m_clk24mhz>, <&smbclk>;
155 clock-names = "KMIREFCLK", "apb_pclk";
156 };
157
158 v2m_serial0: uart@9000 {
159 compatible = "arm,pl011", "arm,primecell";
160 reg = <0x09000 0x1000>;
161 interrupts = <5>;
162 clocks = <&v2m_oscclk2>, <&smbclk>;
163 clock-names = "uartclk", "apb_pclk";
164 };
165
166 v2m_serial1: uart@a000 {
167 compatible = "arm,pl011", "arm,primecell";
168 reg = <0x0a000 0x1000>;
169 interrupts = <6>;
170 clocks = <&v2m_oscclk2>, <&smbclk>;
171 clock-names = "uartclk", "apb_pclk";
172 };
173
174 v2m_serial2: uart@b000 {
175 compatible = "arm,pl011", "arm,primecell";
176 reg = <0x0b000 0x1000>;
177 interrupts = <7>;
178 clocks = <&v2m_oscclk2>, <&smbclk>;
179 clock-names = "uartclk", "apb_pclk";
180 };
181
182 v2m_serial3: uart@c000 {
183 compatible = "arm,pl011", "arm,primecell";
184 reg = <0x0c000 0x1000>;
185 interrupts = <8>;
186 clocks = <&v2m_oscclk2>, <&smbclk>;
187 clock-names = "uartclk", "apb_pclk";
188 };
189
190 wdt@f000 {
191 compatible = "arm,sp805", "arm,primecell";
192 reg = <0x0f000 0x1000>;
193 interrupts = <0>;
194 clocks = <&v2m_refclk32khz>, <&smbclk>;
195 clock-names = "wdogclk", "apb_pclk";
196 };
197
198 v2m_timer01: timer@11000 {
199 compatible = "arm,sp804", "arm,primecell";
200 reg = <0x11000 0x1000>;
201 interrupts = <2>;
202 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
203 clock-names = "timclken1", "timclken2", "apb_pclk";
204 };
205
206 v2m_timer23: timer@12000 {
207 compatible = "arm,sp804", "arm,primecell";
208 reg = <0x12000 0x1000>;
209 interrupts = <3>;
210 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
211 clock-names = "timclken1", "timclken2", "apb_pclk";
212 };
213
214 /* DVI I2C bus */
215 v2m_i2c_dvi: i2c@16000 {
216 compatible = "arm,versatile-i2c";
217 reg = <0x16000 0x1000>;
218
219 #address-cells = <1>;
220 #size-cells = <0>;
221
222 dvi-transmitter@39 {
223 compatible = "sil,sii9022-tpi", "sil,sii9022";
224 reg = <0x39>;
225 };
226
227 dvi-transmitter@60 {
228 compatible = "sil,sii9022-cpi", "sil,sii9022";
229 reg = <0x60>;
230 };
231 };
232
233 rtc@17000 {
234 compatible = "arm,pl031", "arm,primecell";
235 reg = <0x17000 0x1000>;
236 interrupts = <4>;
237 clocks = <&smbclk>;
238 clock-names = "apb_pclk";
239 };
240
241 compact-flash@1a000 {
242 compatible = "arm,vexpress-cf", "ata-generic";
243 reg = <0x1a000 0x100
244 0x1a100 0xf00>;
245 reg-shift = <2>;
246 };
247
248 clcd@1f000 {
249 compatible = "arm,pl111", "arm,primecell";
250 reg = <0x1f000 0x1000>;
251 interrupt-names = "combined";
252 interrupts = <14>;
253 clocks = <&v2m_oscclk1>, <&smbclk>;
254 clock-names = "clcdclk", "apb_pclk";
255 memory-region = <&v2m_video_ram>;
256 max-memory-bandwidth = <50350000>; /* 16bpp @ 25.175MHz */
257
258 port {
259 v2m_clcd_pads: endpoint {
260 remote-endpoint = <&v2m_clcd_panel>;
261 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
262 };
263 };
264
265 panel {
266 compatible = "panel-dpi";
267
268 port {
269 v2m_clcd_panel: endpoint {
270 remote-endpoint = <&v2m_clcd_pads>;
271 };
272 };
273
274 panel-timing {
275 clock-frequency = <25175000>;
276 hactive = <640>;
277 hback-porch = <40>;
278 hfront-porch = <24>;
279 hsync-len = <96>;
280 vactive = <480>;
281 vback-porch = <32>;
282 vfront-porch = <11>;
283 vsync-len = <2>;
284 };
285 };
286 };
287 };
288
289 v2m_fixed_3v3: fixed-regulator-0 {
290 compatible = "regulator-fixed";
291 regulator-name = "3V3";
292 regulator-min-microvolt = <3300000>;
293 regulator-max-microvolt = <3300000>;
294 regulator-always-on;
295 };
296
297 v2m_clk24mhz: clk24mhz {
298 compatible = "fixed-clock";
299 #clock-cells = <0>;
300 clock-frequency = <24000000>;
301 clock-output-names = "v2m:clk24mhz";
302 };
303
304 v2m_refclk1mhz: refclk1mhz {
305 compatible = "fixed-clock";
306 #clock-cells = <0>;
307 clock-frequency = <1000000>;
308 clock-output-names = "v2m:refclk1mhz";
309 };
310
311 v2m_refclk32khz: refclk32khz {
312 compatible = "fixed-clock";
313 #clock-cells = <0>;
314 clock-frequency = <32768>;
315 clock-output-names = "v2m:refclk32khz";
316 };
317
318 leds {
319 compatible = "gpio-leds";
320
321 user1 {
322 label = "v2m:green:user1";
323 gpios = <&v2m_led_gpios 0 0>;
324 linux,default-trigger = "heartbeat";
325 };
326
327 user2 {
328 label = "v2m:green:user2";
329 gpios = <&v2m_led_gpios 1 0>;
330 linux,default-trigger = "mmc0";
331 };
332
333 user3 {
334 label = "v2m:green:user3";
335 gpios = <&v2m_led_gpios 2 0>;
336 linux,default-trigger = "cpu0";
337 };
338
339 user4 {
340 label = "v2m:green:user4";
341 gpios = <&v2m_led_gpios 3 0>;
342 linux,default-trigger = "cpu1";
343 };
344
345 user5 {
346 label = "v2m:green:user5";
347 gpios = <&v2m_led_gpios 4 0>;
348 linux,default-trigger = "cpu2";
349 };
350
351 user6 {
352 label = "v2m:green:user6";
353 gpios = <&v2m_led_gpios 5 0>;
354 linux,default-trigger = "cpu3";
355 };
356
357 user7 {
358 label = "v2m:green:user7";
359 gpios = <&v2m_led_gpios 6 0>;
360 linux,default-trigger = "cpu4";
361 };
362
363 user8 {
364 label = "v2m:green:user8";
365 gpios = <&v2m_led_gpios 7 0>;
366 linux,default-trigger = "cpu5";
367 };
368 };
369
370 mcc {
371 compatible = "arm,vexpress,config-bus";
372 arm,vexpress,config-bridge = <&v2m_sysreg>;
373
374 oscclk0 {
375 /* MCC static memory clock */
376 compatible = "arm,vexpress-osc";
377 arm,vexpress-sysreg,func = <1 0>;
378 freq-range = <25000000 60000000>;
379 #clock-cells = <0>;
380 clock-output-names = "v2m:oscclk0";
381 };
382
383 v2m_oscclk1: oscclk1 {
384 /* CLCD clock */
385 compatible = "arm,vexpress-osc";
386 arm,vexpress-sysreg,func = <1 1>;
387 freq-range = <23750000 65000000>;
388 #clock-cells = <0>;
389 clock-output-names = "v2m:oscclk1";
390 };
391
392 v2m_oscclk2: oscclk2 {
393 /* IO FPGA peripheral clock */
394 compatible = "arm,vexpress-osc";
395 arm,vexpress-sysreg,func = <1 2>;
396 freq-range = <24000000 24000000>;
397 #clock-cells = <0>;
398 clock-output-names = "v2m:oscclk2";
399 };
400
401 volt-vio {
402 /* Logic level voltage */
403 compatible = "arm,vexpress-volt";
404 arm,vexpress-sysreg,func = <2 0>;
405 regulator-name = "VIO";
406 regulator-always-on;
407 label = "VIO";
408 };
409
410 temp-mcc {
411 /* MCC internal operating temperature */
412 compatible = "arm,vexpress-temp";
413 arm,vexpress-sysreg,func = <4 0>;
414 label = "MCC";
415 };
416
417 reset {
418 compatible = "arm,vexpress-reset";
419 arm,vexpress-sysreg,func = <5 0>;
420 };
421
422 muxfpga {
423 compatible = "arm,vexpress-muxfpga";
424 arm,vexpress-sysreg,func = <7 0>;
425 };
426
427 shutdown {
428 compatible = "arm,vexpress-shutdown";
429 arm,vexpress-sysreg,func = <8 0>;
430 };
431
432 reboot {
433 compatible = "arm,vexpress-reboot";
434 arm,vexpress-sysreg,func = <9 0>;
435 };
436
437 dvimode {
438 compatible = "arm,vexpress-dvimode";
439 arm,vexpress-sysreg,func = <11 0>;
440 };
441 };
442 };
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ARM Ltd. Versatile Express
4 *
5 * Motherboard Express uATX
6 * V2M-P1
7 *
8 * HBI-0190D
9 *
10 * Original memory map ("Legacy memory map" in the board's
11 * Technical Reference Manual)
12 *
13 * WARNING! The hardware described in this file is independent from the
14 * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
15 * correspondence between the two configurations.
16 *
17 * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
18 * CHANGES TO vexpress-v2m-rs1.dtsi!
19 */
20#include <dt-bindings/interrupt-controller/arm-gic.h>
21
22/ {
23 bus@40000000 {
24 compatible = "simple-bus";
25 #address-cells = <1>;
26 #size-cells = <1>;
27 ranges = <0x40000000 0x40000000 0x10000000>,
28 <0x10000000 0x10000000 0x00020000>;
29
30 #interrupt-cells = <1>;
31 interrupt-map-mask = <0 63>;
32 interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
33 <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
34 <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
35 <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
36 <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
37 <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
38 <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
39 <0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
40 <0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
41 <0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
42 <0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
43 <0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
44 <0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
45 <0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
46 <0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
47 <0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
48 <0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
49 <0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
50 <0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
51 <0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
52 <0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
53 <0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
54 <0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
55 <0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
56 <0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
57 <0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
58 <0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
59 <0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
60 <0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
61 <0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
62 <0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
63 <0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
64 <0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
65 <0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
66 <0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
67 <0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
68 <0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
69 <0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
70 <0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
71 <0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
72 <0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
73 <0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
74 <0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
75
76 motherboard-bus@40000000 {
77 arm,hbi = <0x190>;
78 arm,vexpress,site = <0>;
79 compatible = "arm,vexpress,v2m-p1", "simple-bus";
80 #address-cells = <2>; /* SMB chipselect number and offset */
81 #size-cells = <1>;
82 ranges = <0 0 0x40000000 0x04000000>,
83 <1 0 0x44000000 0x04000000>,
84 <2 0 0x48000000 0x04000000>,
85 <3 0 0x4c000000 0x04000000>,
86 <7 0 0x10000000 0x00020000>;
87
88 flash@0,00000000 {
89 compatible = "arm,vexpress-flash", "cfi-flash";
90 reg = <0 0x00000000 0x04000000>,
91 <1 0x00000000 0x04000000>;
92 bank-width = <4>;
93 partitions {
94 compatible = "arm,arm-firmware-suite";
95 };
96 };
97
98 psram@2,00000000 {
99 compatible = "arm,vexpress-psram", "mtd-ram";
100 reg = <2 0x00000000 0x02000000>;
101 bank-width = <4>;
102 };
103
104 ethernet@3,02000000 {
105 compatible = "smsc,lan9118", "smsc,lan9115";
106 reg = <3 0x02000000 0x10000>;
107 interrupts = <15>;
108 phy-mode = "mii";
109 reg-io-width = <4>;
110 smsc,irq-active-high;
111 smsc,irq-push-pull;
112 vdd33a-supply = <&v2m_fixed_3v3>;
113 vddvario-supply = <&v2m_fixed_3v3>;
114 };
115
116 usb@3,03000000 {
117 compatible = "nxp,usb-isp1761";
118 reg = <3 0x03000000 0x20000>;
119 interrupts = <16>;
120 dr_mode = "peripheral";
121 };
122
123 iofpga@7,00000000 {
124 compatible = "simple-bus";
125 #address-cells = <1>;
126 #size-cells = <1>;
127 ranges = <0 7 0 0x20000>;
128
129 v2m_sysreg: sysreg@0 {
130 compatible = "arm,vexpress-sysreg";
131 reg = <0x00000 0x1000>;
132 #address-cells = <1>;
133 #size-cells = <1>;
134 ranges = <0 0 0x1000>;
135
136 v2m_led_gpios: gpio@8 {
137 compatible = "arm,vexpress-sysreg,sys_led";
138 reg = <0x008 4>;
139 gpio-controller;
140 #gpio-cells = <2>;
141 };
142
143 v2m_mmc_gpios: gpio@48 {
144 compatible = "arm,vexpress-sysreg,sys_mci";
145 reg = <0x048 4>;
146 gpio-controller;
147 #gpio-cells = <2>;
148 };
149
150 v2m_flash_gpios: gpio@4c {
151 compatible = "arm,vexpress-sysreg,sys_flash";
152 reg = <0x04c 4>;
153 gpio-controller;
154 #gpio-cells = <2>;
155 };
156 };
157
158 v2m_sysctl: sysctl@1000 {
159 compatible = "arm,sp810", "arm,primecell";
160 reg = <0x01000 0x1000>;
161 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
162 clock-names = "refclk", "timclk", "apb_pclk";
163 #clock-cells = <1>;
164 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
165 assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
166 assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
167 };
168
169 /* PCI-E I2C bus */
170 v2m_i2c_pcie: i2c@2000 {
171 compatible = "arm,versatile-i2c";
172 reg = <0x02000 0x1000>;
173
174 #address-cells = <1>;
175 #size-cells = <0>;
176
177 pcie-switch@60 {
178 compatible = "idt,89hpes32h8";
179 reg = <0x60>;
180 };
181 };
182
183 aaci@4000 {
184 compatible = "arm,pl041", "arm,primecell";
185 reg = <0x04000 0x1000>;
186 interrupts = <11>;
187 clocks = <&smbclk>;
188 clock-names = "apb_pclk";
189 };
190
191 mmci@5000 {
192 compatible = "arm,pl180", "arm,primecell";
193 reg = <0x05000 0x1000>;
194 interrupts = <9>, <10>;
195 cd-gpios = <&v2m_mmc_gpios 0 0>;
196 wp-gpios = <&v2m_mmc_gpios 1 0>;
197 max-frequency = <12000000>;
198 vmmc-supply = <&v2m_fixed_3v3>;
199 clocks = <&v2m_clk24mhz>, <&smbclk>;
200 clock-names = "mclk", "apb_pclk";
201 };
202
203 kmi@6000 {
204 compatible = "arm,pl050", "arm,primecell";
205 reg = <0x06000 0x1000>;
206 interrupts = <12>;
207 clocks = <&v2m_clk24mhz>, <&smbclk>;
208 clock-names = "KMIREFCLK", "apb_pclk";
209 };
210
211 kmi@7000 {
212 compatible = "arm,pl050", "arm,primecell";
213 reg = <0x07000 0x1000>;
214 interrupts = <13>;
215 clocks = <&v2m_clk24mhz>, <&smbclk>;
216 clock-names = "KMIREFCLK", "apb_pclk";
217 };
218
219 v2m_serial0: uart@9000 {
220 compatible = "arm,pl011", "arm,primecell";
221 reg = <0x09000 0x1000>;
222 interrupts = <5>;
223 clocks = <&v2m_oscclk2>, <&smbclk>;
224 clock-names = "uartclk", "apb_pclk";
225 };
226
227 v2m_serial1: uart@a000 {
228 compatible = "arm,pl011", "arm,primecell";
229 reg = <0x0a000 0x1000>;
230 interrupts = <6>;
231 clocks = <&v2m_oscclk2>, <&smbclk>;
232 clock-names = "uartclk", "apb_pclk";
233 };
234
235 v2m_serial2: uart@b000 {
236 compatible = "arm,pl011", "arm,primecell";
237 reg = <0x0b000 0x1000>;
238 interrupts = <7>;
239 clocks = <&v2m_oscclk2>, <&smbclk>;
240 clock-names = "uartclk", "apb_pclk";
241 };
242
243 v2m_serial3: uart@c000 {
244 compatible = "arm,pl011", "arm,primecell";
245 reg = <0x0c000 0x1000>;
246 interrupts = <8>;
247 clocks = <&v2m_oscclk2>, <&smbclk>;
248 clock-names = "uartclk", "apb_pclk";
249 };
250
251 wdt@f000 {
252 compatible = "arm,sp805", "arm,primecell";
253 reg = <0x0f000 0x1000>;
254 interrupts = <0>;
255 clocks = <&v2m_refclk32khz>, <&smbclk>;
256 clock-names = "wdog_clk", "apb_pclk";
257 };
258
259 v2m_timer01: timer@11000 {
260 compatible = "arm,sp804", "arm,primecell";
261 reg = <0x11000 0x1000>;
262 interrupts = <2>;
263 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
264 clock-names = "timclken1", "timclken2", "apb_pclk";
265 };
266
267 v2m_timer23: timer@12000 {
268 compatible = "arm,sp804", "arm,primecell";
269 reg = <0x12000 0x1000>;
270 interrupts = <3>;
271 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
272 clock-names = "timclken1", "timclken2", "apb_pclk";
273 };
274
275 /* DVI I2C bus */
276 v2m_i2c_dvi: i2c@16000 {
277 compatible = "arm,versatile-i2c";
278 reg = <0x16000 0x1000>;
279 #address-cells = <1>;
280 #size-cells = <0>;
281
282 dvi-transmitter@39 {
283 compatible = "sil,sii9022-tpi", "sil,sii9022";
284 reg = <0x39>;
285
286 ports {
287 #address-cells = <1>;
288 #size-cells = <0>;
289
290 /*
291 * Both the core tile and the motherboard routes their output
292 * pads to this transmitter. The motherboard system controller
293 * can select one of them as input using a mux register in
294 * "arm,vexpress-muxfpga". The Vexpress with the CA9 core tile is
295 * the only platform with this specific set-up.
296 */
297 port@0 {
298 reg = <0>;
299 dvi_bridge_in_ct: endpoint {
300 remote-endpoint = <&clcd_pads_ct>;
301 };
302 };
303 port@1 {
304 reg = <1>;
305 dvi_bridge_in_mb: endpoint {
306 remote-endpoint = <&clcd_pads_mb>;
307 };
308 };
309 };
310 };
311
312 dvi-transmitter@60 {
313 compatible = "sil,sii9022-cpi", "sil,sii9022";
314 reg = <0x60>;
315 };
316 };
317
318 rtc@17000 {
319 compatible = "arm,pl031", "arm,primecell";
320 reg = <0x17000 0x1000>;
321 interrupts = <4>;
322 clocks = <&smbclk>;
323 clock-names = "apb_pclk";
324 };
325
326 compact-flash@1a000 {
327 compatible = "arm,vexpress-cf", "ata-generic";
328 reg = <0x1a000 0x100
329 0x1a100 0xf00>;
330 reg-shift = <2>;
331 };
332
333
334 clcd@1f000 {
335 compatible = "arm,pl111", "arm,primecell";
336 reg = <0x1f000 0x1000>;
337 interrupt-names = "combined";
338 interrupts = <14>;
339 clocks = <&v2m_oscclk1>, <&smbclk>;
340 clock-names = "clcdclk", "apb_pclk";
341 /* 800x600 16bpp @36MHz works fine */
342 max-memory-bandwidth = <54000000>;
343 memory-region = <&vram>;
344
345 port {
346 clcd_pads_mb: endpoint {
347 remote-endpoint = <&dvi_bridge_in_mb>;
348 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
349 };
350 };
351 };
352 };
353
354 v2m_fixed_3v3: fixed-regulator-0 {
355 compatible = "regulator-fixed";
356 regulator-name = "3V3";
357 regulator-min-microvolt = <3300000>;
358 regulator-max-microvolt = <3300000>;
359 regulator-always-on;
360 };
361
362 v2m_clk24mhz: clk24mhz {
363 compatible = "fixed-clock";
364 #clock-cells = <0>;
365 clock-frequency = <24000000>;
366 clock-output-names = "v2m:clk24mhz";
367 };
368
369 v2m_refclk1mhz: refclk1mhz {
370 compatible = "fixed-clock";
371 #clock-cells = <0>;
372 clock-frequency = <1000000>;
373 clock-output-names = "v2m:refclk1mhz";
374 };
375
376 v2m_refclk32khz: refclk32khz {
377 compatible = "fixed-clock";
378 #clock-cells = <0>;
379 clock-frequency = <32768>;
380 clock-output-names = "v2m:refclk32khz";
381 };
382
383 leds {
384 compatible = "gpio-leds";
385
386 led-user1 {
387 label = "v2m:green:user1";
388 gpios = <&v2m_led_gpios 0 0>;
389 linux,default-trigger = "heartbeat";
390 };
391
392 led-user2 {
393 label = "v2m:green:user2";
394 gpios = <&v2m_led_gpios 1 0>;
395 linux,default-trigger = "mmc0";
396 };
397
398 led-user3 {
399 label = "v2m:green:user3";
400 gpios = <&v2m_led_gpios 2 0>;
401 linux,default-trigger = "cpu0";
402 };
403
404 led-user4 {
405 label = "v2m:green:user4";
406 gpios = <&v2m_led_gpios 3 0>;
407 linux,default-trigger = "cpu1";
408 };
409
410 led-user5 {
411 label = "v2m:green:user5";
412 gpios = <&v2m_led_gpios 4 0>;
413 linux,default-trigger = "cpu2";
414 };
415
416 led-user6 {
417 label = "v2m:green:user6";
418 gpios = <&v2m_led_gpios 5 0>;
419 linux,default-trigger = "cpu3";
420 };
421
422 led-user7 {
423 label = "v2m:green:user7";
424 gpios = <&v2m_led_gpios 6 0>;
425 linux,default-trigger = "cpu4";
426 };
427
428 led-user8 {
429 label = "v2m:green:user8";
430 gpios = <&v2m_led_gpios 7 0>;
431 linux,default-trigger = "cpu5";
432 };
433 };
434
435 mcc {
436 compatible = "arm,vexpress,config-bus";
437 arm,vexpress,config-bridge = <&v2m_sysreg>;
438
439 oscclk0 {
440 /* MCC static memory clock */
441 compatible = "arm,vexpress-osc";
442 arm,vexpress-sysreg,func = <1 0>;
443 freq-range = <25000000 60000000>;
444 #clock-cells = <0>;
445 clock-output-names = "v2m:oscclk0";
446 };
447
448 v2m_oscclk1: oscclk1 {
449 /* CLCD clock */
450 compatible = "arm,vexpress-osc";
451 arm,vexpress-sysreg,func = <1 1>;
452 freq-range = <23750000 65000000>;
453 #clock-cells = <0>;
454 clock-output-names = "v2m:oscclk1";
455 };
456
457 v2m_oscclk2: oscclk2 {
458 /* IO FPGA peripheral clock */
459 compatible = "arm,vexpress-osc";
460 arm,vexpress-sysreg,func = <1 2>;
461 freq-range = <24000000 24000000>;
462 #clock-cells = <0>;
463 clock-output-names = "v2m:oscclk2";
464 };
465
466 volt-vio {
467 /* Logic level voltage */
468 compatible = "arm,vexpress-volt";
469 arm,vexpress-sysreg,func = <2 0>;
470 regulator-name = "VIO";
471 regulator-always-on;
472 label = "VIO";
473 };
474
475 temp-mcc {
476 /* MCC internal operating temperature */
477 compatible = "arm,vexpress-temp";
478 arm,vexpress-sysreg,func = <4 0>;
479 label = "MCC";
480 };
481
482 reset {
483 compatible = "arm,vexpress-reset";
484 arm,vexpress-sysreg,func = <5 0>;
485 };
486
487 muxfpga {
488 compatible = "arm,vexpress-muxfpga";
489 arm,vexpress-sysreg,func = <7 0>;
490 };
491
492 shutdown {
493 compatible = "arm,vexpress-shutdown";
494 arm,vexpress-sysreg,func = <8 0>;
495 };
496
497 reboot {
498 compatible = "arm,vexpress-reboot";
499 arm,vexpress-sysreg,func = <9 0>;
500 };
501
502 dvimode {
503 compatible = "arm,vexpress-dvimode";
504 arm,vexpress-sysreg,func = <11 0>;
505 };
506 };
507 };
508 };
509};