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1/*
2 * Copyright 2012 Linaro Ltd
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/mfd/dbx500-prcmu.h>
15#include <dt-bindings/arm/ux500_pm_domains.h>
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/clock/ste-ab8500.h>
18#include "skeleton.dtsi"
19
20/ {
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "ste,dbx500-smp";
25
26 cpu-map {
27 cluster0 {
28 core0 {
29 cpu = <&CPU0>;
30 };
31 core1 {
32 cpu = <&CPU1>;
33 };
34 };
35 };
36 CPU0: cpu@300 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a9";
39 reg = <0x300>;
40 /* cpufreq controls */
41 operating-points = <998400 0
42 800000 0
43 400000 0
44 200000 0>;
45 clocks = <&prcmu_clk PRCMU_ARMSS>;
46 clock-names = "cpu";
47 clock-latency = <20000>;
48 };
49 CPU1: cpu@301 {
50 device_type = "cpu";
51 compatible = "arm,cortex-a9";
52 reg = <0x301>;
53 };
54 };
55
56 soc {
57 #address-cells = <1>;
58 #size-cells = <1>;
59 compatible = "stericsson,db8500";
60 interrupt-parent = <&intc>;
61 ranges;
62
63 ptm@801ae000 {
64 compatible = "arm,coresight-etm3x", "arm,primecell";
65 reg = <0x801ae000 0x1000>;
66
67 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
68 clock-names = "apb_pclk", "atclk";
69 cpu = <&CPU0>;
70 port {
71 ptm0_out_port: endpoint {
72 remote-endpoint = <&funnel_in_port0>;
73 };
74 };
75 };
76
77 ptm@801af000 {
78 compatible = "arm,coresight-etm3x", "arm,primecell";
79 reg = <0x801af000 0x1000>;
80
81 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
82 clock-names = "apb_pclk", "atclk";
83 cpu = <&CPU1>;
84 port {
85 ptm1_out_port: endpoint {
86 remote-endpoint = <&funnel_in_port1>;
87 };
88 };
89 };
90
91 funnel@801a6000 {
92 compatible = "arm,coresight-funnel", "arm,primecell";
93 reg = <0x801a6000 0x1000>;
94
95 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
96 clock-names = "apb_pclk", "atclk";
97 ports {
98 #address-cells = <1>;
99 #size-cells = <0>;
100
101 /* funnel output ports */
102 port@0 {
103 reg = <0>;
104 funnel_out_port: endpoint {
105 remote-endpoint =
106 <&replicator_in_port0>;
107 };
108 };
109
110 /* funnel input ports */
111 port@1 {
112 reg = <0>;
113 funnel_in_port0: endpoint {
114 slave-mode;
115 remote-endpoint = <&ptm0_out_port>;
116 };
117 };
118
119 port@2 {
120 reg = <1>;
121 funnel_in_port1: endpoint {
122 slave-mode;
123 remote-endpoint = <&ptm1_out_port>;
124 };
125 };
126 };
127 };
128
129 replicator {
130 compatible = "arm,coresight-replicator";
131 clocks = <&prcmu_clk PRCMU_APEATCLK>;
132 clock-names = "atclk";
133
134 ports {
135 #address-cells = <1>;
136 #size-cells = <0>;
137
138 /* replicator output ports */
139 port@0 {
140 reg = <0>;
141 replicator_out_port0: endpoint {
142 remote-endpoint = <&tpiu_in_port>;
143 };
144 };
145 port@1 {
146 reg = <1>;
147 replicator_out_port1: endpoint {
148 remote-endpoint = <&etb_in_port>;
149 };
150 };
151
152 /* replicator input port */
153 port@2 {
154 reg = <0>;
155 replicator_in_port0: endpoint {
156 slave-mode;
157 remote-endpoint = <&funnel_out_port>;
158 };
159 };
160 };
161 };
162
163 tpiu@80190000 {
164 compatible = "arm,coresight-tpiu", "arm,primecell";
165 reg = <0x80190000 0x1000>;
166
167 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
168 clock-names = "apb_pclk", "atclk";
169 port {
170 tpiu_in_port: endpoint {
171 slave-mode;
172 remote-endpoint = <&replicator_out_port0>;
173 };
174 };
175 };
176
177 etb@801a4000 {
178 compatible = "arm,coresight-etb10", "arm,primecell";
179 reg = <0x801a4000 0x1000>;
180
181 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
182 clock-names = "apb_pclk", "atclk";
183 port {
184 etb_in_port: endpoint {
185 slave-mode;
186 remote-endpoint = <&replicator_out_port1>;
187 };
188 };
189 };
190
191 intc: interrupt-controller@a0411000 {
192 compatible = "arm,cortex-a9-gic";
193 #interrupt-cells = <3>;
194 #address-cells = <1>;
195 interrupt-controller;
196 reg = <0xa0411000 0x1000>,
197 <0xa0410100 0x100>;
198 };
199
200 scu@a04100000 {
201 compatible = "arm,cortex-a9-scu";
202 reg = <0xa0410000 0x100>;
203 };
204
205 /*
206 * The backup RAM is used for retention during sleep
207 * and various things like spin tables
208 */
209 backupram@80150000 {
210 compatible = "ste,dbx500-backupram";
211 reg = <0x80150000 0x2000>;
212 };
213
214 L2: l2-cache {
215 compatible = "arm,pl310-cache";
216 reg = <0xa0412000 0x1000>;
217 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
218 cache-unified;
219 cache-level = <2>;
220 };
221
222 pmu {
223 compatible = "arm,cortex-a9-pmu";
224 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
225 };
226
227 pm_domains: pm_domains0 {
228 compatible = "stericsson,ux500-pm-domains";
229 #power-domain-cells = <1>;
230 };
231
232 clocks {
233 compatible = "stericsson,u8500-clks";
234 /*
235 * Registers for the CLKRST block on peripheral
236 * groups 1, 2, 3, 5, 6,
237 */
238 reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
239 <0x8000f000 0x1000>, <0xa03ff000 0x1000>,
240 <0xa03cf000 0x1000>;
241
242 prcmu_clk: prcmu-clock {
243 #clock-cells = <1>;
244 };
245
246 prcc_pclk: prcc-periph-clock {
247 #clock-cells = <2>;
248 };
249
250 prcc_kclk: prcc-kernel-clock {
251 #clock-cells = <2>;
252 };
253
254 rtc_clk: rtc32k-clock {
255 #clock-cells = <0>;
256 };
257
258 smp_twd_clk: smp-twd-clock {
259 #clock-cells = <0>;
260 };
261 };
262
263 mtu@a03c6000 {
264 /* Nomadik System Timer */
265 compatible = "st,nomadik-mtu";
266 reg = <0xa03c6000 0x1000>;
267 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
268
269 clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>;
270 clock-names = "timclk", "apb_pclk";
271 };
272
273 timer@a0410600 {
274 compatible = "arm,cortex-a9-twd-timer";
275 reg = <0xa0410600 0x20>;
276 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
277
278 clocks = <&smp_twd_clk>;
279 };
280
281 watchdog@a0410620 {
282 compatible = "arm,cortex-a9-twd-wdt";
283 reg = <0xa0410620 0x20>;
284 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
285 clocks = <&smp_twd_clk>;
286 };
287
288 rtc@80154000 {
289 compatible = "arm,rtc-pl031", "arm,primecell";
290 reg = <0x80154000 0x1000>;
291 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
292
293 clocks = <&rtc_clk>;
294 clock-names = "apb_pclk";
295 };
296
297 gpio0: gpio@8012e000 {
298 compatible = "stericsson,db8500-gpio",
299 "st,nomadik-gpio";
300 reg = <0x8012e000 0x80>;
301 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
302 interrupt-controller;
303 #interrupt-cells = <2>;
304 st,supports-sleepmode;
305 gpio-controller;
306 #gpio-cells = <2>;
307 gpio-bank = <0>;
308 gpio-ranges = <&pinctrl 0 0 32>;
309 clocks = <&prcc_pclk 1 9>;
310 };
311
312 gpio1: gpio@8012e080 {
313 compatible = "stericsson,db8500-gpio",
314 "st,nomadik-gpio";
315 reg = <0x8012e080 0x80>;
316 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
317 interrupt-controller;
318 #interrupt-cells = <2>;
319 st,supports-sleepmode;
320 gpio-controller;
321 #gpio-cells = <2>;
322 gpio-bank = <1>;
323 gpio-ranges = <&pinctrl 0 32 5>;
324 clocks = <&prcc_pclk 1 9>;
325 };
326
327 gpio2: gpio@8000e000 {
328 compatible = "stericsson,db8500-gpio",
329 "st,nomadik-gpio";
330 reg = <0x8000e000 0x80>;
331 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
332 interrupt-controller;
333 #interrupt-cells = <2>;
334 st,supports-sleepmode;
335 gpio-controller;
336 #gpio-cells = <2>;
337 gpio-bank = <2>;
338 gpio-ranges = <&pinctrl 0 64 32>;
339 clocks = <&prcc_pclk 3 8>;
340 };
341
342 gpio3: gpio@8000e080 {
343 compatible = "stericsson,db8500-gpio",
344 "st,nomadik-gpio";
345 reg = <0x8000e080 0x80>;
346 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
347 interrupt-controller;
348 #interrupt-cells = <2>;
349 st,supports-sleepmode;
350 gpio-controller;
351 #gpio-cells = <2>;
352 gpio-bank = <3>;
353 gpio-ranges = <&pinctrl 0 96 2>;
354 clocks = <&prcc_pclk 3 8>;
355 };
356
357 gpio4: gpio@8000e100 {
358 compatible = "stericsson,db8500-gpio",
359 "st,nomadik-gpio";
360 reg = <0x8000e100 0x80>;
361 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
362 interrupt-controller;
363 #interrupt-cells = <2>;
364 st,supports-sleepmode;
365 gpio-controller;
366 #gpio-cells = <2>;
367 gpio-bank = <4>;
368 gpio-ranges = <&pinctrl 0 128 32>;
369 clocks = <&prcc_pclk 3 8>;
370 };
371
372 gpio5: gpio@8000e180 {
373 compatible = "stericsson,db8500-gpio",
374 "st,nomadik-gpio";
375 reg = <0x8000e180 0x80>;
376 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
377 interrupt-controller;
378 #interrupt-cells = <2>;
379 st,supports-sleepmode;
380 gpio-controller;
381 #gpio-cells = <2>;
382 gpio-bank = <5>;
383 gpio-ranges = <&pinctrl 0 160 12>;
384 clocks = <&prcc_pclk 3 8>;
385 };
386
387 gpio6: gpio@8011e000 {
388 compatible = "stericsson,db8500-gpio",
389 "st,nomadik-gpio";
390 reg = <0x8011e000 0x80>;
391 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
392 interrupt-controller;
393 #interrupt-cells = <2>;
394 st,supports-sleepmode;
395 gpio-controller;
396 #gpio-cells = <2>;
397 gpio-bank = <6>;
398 gpio-ranges = <&pinctrl 0 192 32>;
399 clocks = <&prcc_pclk 2 11>;
400 };
401
402 gpio7: gpio@8011e080 {
403 compatible = "stericsson,db8500-gpio",
404 "st,nomadik-gpio";
405 reg = <0x8011e080 0x80>;
406 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
407 interrupt-controller;
408 #interrupt-cells = <2>;
409 st,supports-sleepmode;
410 gpio-controller;
411 #gpio-cells = <2>;
412 gpio-bank = <7>;
413 gpio-ranges = <&pinctrl 0 224 7>;
414 clocks = <&prcc_pclk 2 11>;
415 };
416
417 gpio8: gpio@a03fe000 {
418 compatible = "stericsson,db8500-gpio",
419 "st,nomadik-gpio";
420 reg = <0xa03fe000 0x80>;
421 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
422 interrupt-controller;
423 #interrupt-cells = <2>;
424 st,supports-sleepmode;
425 gpio-controller;
426 #gpio-cells = <2>;
427 gpio-bank = <8>;
428 gpio-ranges = <&pinctrl 0 256 12>;
429 clocks = <&prcc_pclk 5 1>;
430 };
431
432 pinctrl: pinctrl {
433 compatible = "stericsson,db8500-pinctrl";
434 nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>,
435 <&gpio4>, <&gpio5>, <&gpio6>, <&gpio7>,
436 <&gpio8>;
437 prcm = <&prcmu>;
438 };
439
440 usb_per5@a03e0000 {
441 compatible = "stericsson,db8500-musb";
442 reg = <0xa03e0000 0x10000>;
443 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
444 interrupt-names = "mc";
445
446 dr_mode = "otg";
447
448 dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
449 <&dma 38 0 0x0>, /* Logical - MemToDev */
450 <&dma 37 0 0x2>, /* Logical - DevToMem */
451 <&dma 37 0 0x0>, /* Logical - MemToDev */
452 <&dma 36 0 0x2>, /* Logical - DevToMem */
453 <&dma 36 0 0x0>, /* Logical - MemToDev */
454 <&dma 19 0 0x2>, /* Logical - DevToMem */
455 <&dma 19 0 0x0>, /* Logical - MemToDev */
456 <&dma 18 0 0x2>, /* Logical - DevToMem */
457 <&dma 18 0 0x0>, /* Logical - MemToDev */
458 <&dma 17 0 0x2>, /* Logical - DevToMem */
459 <&dma 17 0 0x0>, /* Logical - MemToDev */
460 <&dma 16 0 0x2>, /* Logical - DevToMem */
461 <&dma 16 0 0x0>, /* Logical - MemToDev */
462 <&dma 39 0 0x2>, /* Logical - DevToMem */
463 <&dma 39 0 0x0>; /* Logical - MemToDev */
464
465 dma-names = "iep_1_9", "oep_1_9",
466 "iep_2_10", "oep_2_10",
467 "iep_3_11", "oep_3_11",
468 "iep_4_12", "oep_4_12",
469 "iep_5_13", "oep_5_13",
470 "iep_6_14", "oep_6_14",
471 "iep_7_15", "oep_7_15",
472 "iep_8", "oep_8";
473
474 clocks = <&prcc_pclk 5 0>;
475 };
476
477 dma: dma-controller@801C0000 {
478 compatible = "stericsson,db8500-dma40", "stericsson,dma40";
479 reg = <0x801C0000 0x1000 0x40010000 0x800>;
480 reg-names = "base", "lcpa";
481 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
482
483 #dma-cells = <3>;
484 memcpy-channels = <56 57 58 59 60>;
485
486 clocks = <&prcmu_clk PRCMU_DMACLK>;
487 };
488
489 prcmu: prcmu@80157000 {
490 compatible = "stericsson,db8500-prcmu";
491 reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
492 reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
493 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
494 #address-cells = <1>;
495 #size-cells = <1>;
496 interrupt-controller;
497 #interrupt-cells = <2>;
498 ranges;
499
500 prcmu-timer-4@80157450 {
501 compatible = "stericsson,db8500-prcmu-timer-4";
502 reg = <0x80157450 0xC>;
503 };
504
505 thermal@801573c0 {
506 compatible = "stericsson,db8500-thermal";
507 reg = <0x801573c0 0x40>;
508 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>,
509 <22 IRQ_TYPE_LEVEL_HIGH>;
510 interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
511 status = "disabled";
512 };
513
514 db8500-prcmu-regulators {
515 compatible = "stericsson,db8500-prcmu-regulator";
516
517 // DB8500_REGULATOR_VAPE
518 db8500_vape_reg: db8500_vape {
519 regulator-always-on;
520 };
521
522 // DB8500_REGULATOR_VARM
523 db8500_varm_reg: db8500_varm {
524 };
525
526 // DB8500_REGULATOR_VMODEM
527 db8500_vmodem_reg: db8500_vmodem {
528 };
529
530 // DB8500_REGULATOR_VPLL
531 db8500_vpll_reg: db8500_vpll {
532 };
533
534 // DB8500_REGULATOR_VSMPS1
535 db8500_vsmps1_reg: db8500_vsmps1 {
536 };
537
538 // DB8500_REGULATOR_VSMPS2
539 db8500_vsmps2_reg: db8500_vsmps2 {
540 };
541
542 // DB8500_REGULATOR_VSMPS3
543 db8500_vsmps3_reg: db8500_vsmps3 {
544 };
545
546 // DB8500_REGULATOR_VRF1
547 db8500_vrf1_reg: db8500_vrf1 {
548 };
549
550 // DB8500_REGULATOR_SWITCH_SVAMMDSP
551 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
552 };
553
554 // DB8500_REGULATOR_SWITCH_SVAMMDSPRET
555 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
556 };
557
558 // DB8500_REGULATOR_SWITCH_SVAPIPE
559 db8500_sva_pipe_reg: db8500_sva_pipe {
560 };
561
562 // DB8500_REGULATOR_SWITCH_SIAMMDSP
563 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
564 };
565
566 // DB8500_REGULATOR_SWITCH_SIAMMDSPRET
567 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
568 };
569
570 // DB8500_REGULATOR_SWITCH_SIAPIPE
571 db8500_sia_pipe_reg: db8500_sia_pipe {
572 };
573
574 // DB8500_REGULATOR_SWITCH_SGA
575 db8500_sga_reg: db8500_sga {
576 vin-supply = <&db8500_vape_reg>;
577 };
578
579 // DB8500_REGULATOR_SWITCH_B2R2_MCDE
580 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
581 vin-supply = <&db8500_vape_reg>;
582 };
583
584 // DB8500_REGULATOR_SWITCH_ESRAM12
585 db8500_esram12_reg: db8500_esram12 {
586 };
587
588 // DB8500_REGULATOR_SWITCH_ESRAM12RET
589 db8500_esram12_ret_reg: db8500_esram12_ret {
590 };
591
592 // DB8500_REGULATOR_SWITCH_ESRAM34
593 db8500_esram34_reg: db8500_esram34 {
594 };
595
596 // DB8500_REGULATOR_SWITCH_ESRAM34RET
597 db8500_esram34_ret_reg: db8500_esram34_ret {
598 };
599 };
600
601 ab8500 {
602 compatible = "stericsson,ab8500";
603 interrupt-parent = <&intc>;
604 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
605 interrupt-controller;
606 #interrupt-cells = <2>;
607
608 ab8500_clock: clock-controller {
609 compatible = "stericsson,ab8500-clk";
610 #clock-cells = <1>;
611 };
612
613 ab8500_gpio: ab8500-gpio {
614 compatible = "stericsson,ab8500-gpio";
615 gpio-controller;
616 #gpio-cells = <2>;
617 };
618
619 ab8500-rtc {
620 compatible = "stericsson,ab8500-rtc";
621 interrupts = <17 IRQ_TYPE_LEVEL_HIGH
622 18 IRQ_TYPE_LEVEL_HIGH>;
623 interrupt-names = "60S", "ALARM";
624 };
625
626 ab8500-gpadc {
627 compatible = "stericsson,ab8500-gpadc";
628 interrupts = <32 IRQ_TYPE_LEVEL_HIGH
629 39 IRQ_TYPE_LEVEL_HIGH>;
630 interrupt-names = "HW_CONV_END", "SW_CONV_END";
631 vddadc-supply = <&ab8500_ldo_tvout_reg>;
632 };
633
634 ab8500_battery: ab8500_battery {
635 stericsson,battery-type = "LIPO";
636 thermistor-on-batctrl;
637 };
638
639 ab8500_fg {
640 compatible = "stericsson,ab8500-fg";
641 battery = <&ab8500_battery>;
642 };
643
644 ab8500_btemp {
645 compatible = "stericsson,ab8500-btemp";
646 battery = <&ab8500_battery>;
647 };
648
649 ab8500_charger {
650 compatible = "stericsson,ab8500-charger";
651 battery = <&ab8500_battery>;
652 vddadc-supply = <&ab8500_ldo_tvout_reg>;
653 };
654
655 ab8500_chargalg {
656 compatible = "stericsson,ab8500-chargalg";
657 battery = <&ab8500_battery>;
658 };
659
660 ab8500_usb {
661 compatible = "stericsson,ab8500-usb";
662 interrupts = < 90 IRQ_TYPE_LEVEL_HIGH
663 96 IRQ_TYPE_LEVEL_HIGH
664 14 IRQ_TYPE_LEVEL_HIGH
665 15 IRQ_TYPE_LEVEL_HIGH
666 79 IRQ_TYPE_LEVEL_HIGH
667 74 IRQ_TYPE_LEVEL_HIGH
668 75 IRQ_TYPE_LEVEL_HIGH>;
669 interrupt-names = "ID_WAKEUP_R",
670 "ID_WAKEUP_F",
671 "VBUS_DET_F",
672 "VBUS_DET_R",
673 "USB_LINK_STATUS",
674 "USB_ADP_PROBE_PLUG",
675 "USB_ADP_PROBE_UNPLUG";
676 vddulpivio18-supply = <&ab8500_ldo_intcore_reg>;
677 v-ape-supply = <&db8500_vape_reg>;
678 musb_1v8-supply = <&db8500_vsmps2_reg>;
679 clocks = <&prcmu_clk PRCMU_SYSCLK>;
680 clock-names = "sysclk";
681 };
682
683 ab8500-ponkey {
684 compatible = "stericsson,ab8500-poweron-key";
685 interrupts = <6 IRQ_TYPE_LEVEL_HIGH
686 7 IRQ_TYPE_LEVEL_HIGH>;
687 interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
688 };
689
690 ab8500-sysctrl {
691 compatible = "stericsson,ab8500-sysctrl";
692 };
693
694 ab8500-pwm {
695 compatible = "stericsson,ab8500-pwm";
696 clocks = <&ab8500_clock AB8500_SYSCLK_INT>;
697 clock-names = "intclk";
698 };
699
700 ab8500-debugfs {
701 compatible = "stericsson,ab8500-debug";
702 };
703
704 codec: ab8500-codec {
705 compatible = "stericsson,ab8500-codec";
706
707 V-AUD-supply = <&ab8500_ldo_audio_reg>;
708 V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>;
709 V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>;
710 V-DMIC-supply = <&ab8500_ldo_dmic_reg>;
711
712 clocks = <&ab8500_clock AB8500_SYSCLK_AUDIO>;
713 clock-names = "audioclk";
714
715 stericsson,earpeice-cmv = <950>; /* Units in mV. */
716 };
717
718 ext_regulators: ab8500-ext-regulators {
719 compatible = "stericsson,ab8500-ext-regulator";
720
721 ab8500_ext1_reg: ab8500_ext1 {
722 regulator-min-microvolt = <1800000>;
723 regulator-max-microvolt = <1800000>;
724 regulator-boot-on;
725 regulator-always-on;
726 };
727
728 ab8500_ext2_reg: ab8500_ext2 {
729 regulator-min-microvolt = <1360000>;
730 regulator-max-microvolt = <1360000>;
731 regulator-boot-on;
732 regulator-always-on;
733 };
734
735 ab8500_ext3_reg: ab8500_ext3 {
736 regulator-min-microvolt = <3400000>;
737 regulator-max-microvolt = <3400000>;
738 regulator-boot-on;
739 };
740 };
741
742 ab8500-regulators {
743 compatible = "stericsson,ab8500-regulator";
744 vin-supply = <&ab8500_ext3_reg>;
745
746 // supplies to the display/camera
747 ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
748 regulator-min-microvolt = <2500000>;
749 regulator-max-microvolt = <2900000>;
750 regulator-boot-on;
751 /* BUG: If turned off MMC will be affected. */
752 regulator-always-on;
753 };
754
755 // supplies to the on-board eMMC
756 ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
757 regulator-min-microvolt = <1100000>;
758 regulator-max-microvolt = <3300000>;
759 };
760
761 // supply for VAUX3; SDcard slots
762 ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
763 regulator-min-microvolt = <1100000>;
764 regulator-max-microvolt = <3300000>;
765 };
766
767 // supply for v-intcore12; VINTCORE12 LDO
768 ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
769 };
770
771 // supply for tvout; gpadc; TVOUT LDO
772 ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
773 };
774
775 // supply for ab8500-usb; USB LDO
776 ab8500_ldo_usb_reg: ab8500_ldo_usb {
777 };
778
779 // supply for ab8500-vaudio; VAUDIO LDO
780 ab8500_ldo_audio_reg: ab8500_ldo_audio {
781 };
782
783 // supply for v-anamic1 VAMIC1 LDO
784 ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
785 };
786
787 // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
788 ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
789 };
790
791 // supply for v-dmic; VDMIC LDO
792 ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
793 };
794
795 // supply for U8500 CSI/DSI; VANA LDO
796 ab8500_ldo_ana_reg: ab8500_ldo_ana {
797 };
798 };
799 };
800 };
801
802 i2c@80004000 {
803 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
804 reg = <0x80004000 0x1000>;
805 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
806
807 #address-cells = <1>;
808 #size-cells = <0>;
809 v-i2c-supply = <&db8500_vape_reg>;
810
811 clock-frequency = <400000>;
812 clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>;
813 clock-names = "i2cclk", "apb_pclk";
814 power-domains = <&pm_domains DOMAIN_VAPE>;
815 };
816
817 i2c@80122000 {
818 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
819 reg = <0x80122000 0x1000>;
820 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
821
822 #address-cells = <1>;
823 #size-cells = <0>;
824 v-i2c-supply = <&db8500_vape_reg>;
825
826 clock-frequency = <400000>;
827
828 clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>;
829 clock-names = "i2cclk", "apb_pclk";
830 power-domains = <&pm_domains DOMAIN_VAPE>;
831 };
832
833 i2c@80128000 {
834 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
835 reg = <0x80128000 0x1000>;
836 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
837
838 #address-cells = <1>;
839 #size-cells = <0>;
840 v-i2c-supply = <&db8500_vape_reg>;
841
842 clock-frequency = <400000>;
843
844 clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>;
845 clock-names = "i2cclk", "apb_pclk";
846 power-domains = <&pm_domains DOMAIN_VAPE>;
847 };
848
849 i2c@80110000 {
850 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
851 reg = <0x80110000 0x1000>;
852 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
853
854 #address-cells = <1>;
855 #size-cells = <0>;
856 v-i2c-supply = <&db8500_vape_reg>;
857
858 clock-frequency = <400000>;
859
860 clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>;
861 clock-names = "i2cclk", "apb_pclk";
862 power-domains = <&pm_domains DOMAIN_VAPE>;
863 };
864
865 i2c@8012a000 {
866 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
867 reg = <0x8012a000 0x1000>;
868 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
869
870 #address-cells = <1>;
871 #size-cells = <0>;
872 v-i2c-supply = <&db8500_vape_reg>;
873
874 clock-frequency = <400000>;
875
876 clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>;
877 clock-names = "i2cclk", "apb_pclk";
878 power-domains = <&pm_domains DOMAIN_VAPE>;
879 };
880
881 ssp@80002000 {
882 compatible = "arm,pl022", "arm,primecell";
883 reg = <0x80002000 0x1000>;
884 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
885 #address-cells = <1>;
886 #size-cells = <0>;
887 clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;
888 clock-names = "SSPCLK", "apb_pclk";
889 dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
890 <&dma 8 0 0x0>; /* Logical - MemToDev */
891 dma-names = "rx", "tx";
892 power-domains = <&pm_domains DOMAIN_VAPE>;
893 };
894
895 ssp@80003000 {
896 compatible = "arm,pl022", "arm,primecell";
897 reg = <0x80003000 0x1000>;
898 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
899 #address-cells = <1>;
900 #size-cells = <0>;
901 clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;
902 clock-names = "SSPCLK", "apb_pclk";
903 dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
904 <&dma 9 0 0x0>; /* Logical - MemToDev */
905 dma-names = "rx", "tx";
906 power-domains = <&pm_domains DOMAIN_VAPE>;
907 };
908
909 spi@8011a000 {
910 compatible = "arm,pl022", "arm,primecell";
911 reg = <0x8011a000 0x1000>;
912 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
913 #address-cells = <1>;
914 #size-cells = <0>;
915 /* Same clock wired to kernel and pclk */
916 clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;
917 clock-names = "SSPCLK", "apb_pclk";
918 dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
919 <&dma 0 0 0x0>; /* Logical - MemToDev */
920 dma-names = "rx", "tx";
921 power-domains = <&pm_domains DOMAIN_VAPE>;
922 };
923
924 spi@80112000 {
925 compatible = "arm,pl022", "arm,primecell";
926 reg = <0x80112000 0x1000>;
927 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
928 #address-cells = <1>;
929 #size-cells = <0>;
930 /* Same clock wired to kernel and pclk */
931 clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;
932 clock-names = "SSPCLK", "apb_pclk";
933 dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
934 <&dma 35 0 0x0>; /* Logical - MemToDev */
935 dma-names = "rx", "tx";
936 power-domains = <&pm_domains DOMAIN_VAPE>;
937 };
938
939 spi@80111000 {
940 compatible = "arm,pl022", "arm,primecell";
941 reg = <0x80111000 0x1000>;
942 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
943 #address-cells = <1>;
944 #size-cells = <0>;
945 /* Same clock wired to kernel and pclk */
946 clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;
947 clock-names = "SSPCLK", "apb_pclk";
948 dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
949 <&dma 33 0 0x0>; /* Logical - MemToDev */
950 dma-names = "rx", "tx";
951 power-domains = <&pm_domains DOMAIN_VAPE>;
952 };
953
954 spi@80129000 {
955 compatible = "arm,pl022", "arm,primecell";
956 reg = <0x80129000 0x1000>;
957 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
958 #address-cells = <1>;
959 #size-cells = <0>;
960 /* Same clock wired to kernel and pclk */
961 clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;
962 clock-names = "SSPCLK", "apb_pclk";
963 dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
964 <&dma 40 0 0x0>; /* Logical - MemToDev */
965 dma-names = "rx", "tx";
966 power-domains = <&pm_domains DOMAIN_VAPE>;
967 };
968
969 ux500_serial0: uart@80120000 {
970 compatible = "arm,pl011", "arm,primecell";
971 reg = <0x80120000 0x1000>;
972 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
973
974 dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
975 <&dma 13 0 0x0>; /* Logical - MemToDev */
976 dma-names = "rx", "tx";
977
978 clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>;
979 clock-names = "uart", "apb_pclk";
980
981 status = "disabled";
982 };
983
984 ux500_serial1: uart@80121000 {
985 compatible = "arm,pl011", "arm,primecell";
986 reg = <0x80121000 0x1000>;
987 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
988
989 dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
990 <&dma 12 0 0x0>; /* Logical - MemToDev */
991 dma-names = "rx", "tx";
992
993 clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>;
994 clock-names = "uart", "apb_pclk";
995
996 status = "disabled";
997 };
998
999 ux500_serial2: uart@80007000 {
1000 compatible = "arm,pl011", "arm,primecell";
1001 reg = <0x80007000 0x1000>;
1002 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1003
1004 dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
1005 <&dma 11 0 0x0>; /* Logical - MemToDev */
1006 dma-names = "rx", "tx";
1007
1008 clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>;
1009 clock-names = "uart", "apb_pclk";
1010
1011 status = "disabled";
1012 };
1013
1014 sdi0_per1@80126000 {
1015 compatible = "arm,pl18x", "arm,primecell";
1016 reg = <0x80126000 0x1000>;
1017 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1018
1019 dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
1020 <&dma 29 0 0x0>; /* Logical - MemToDev */
1021 dma-names = "rx", "tx";
1022
1023 clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
1024 clock-names = "sdi", "apb_pclk";
1025 power-domains = <&pm_domains DOMAIN_VAPE>;
1026
1027 status = "disabled";
1028 };
1029
1030 sdi1_per2@80118000 {
1031 compatible = "arm,pl18x", "arm,primecell";
1032 reg = <0x80118000 0x1000>;
1033 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1034
1035 dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
1036 <&dma 32 0 0x0>; /* Logical - MemToDev */
1037 dma-names = "rx", "tx";
1038
1039 clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>;
1040 clock-names = "sdi", "apb_pclk";
1041 power-domains = <&pm_domains DOMAIN_VAPE>;
1042
1043 status = "disabled";
1044 };
1045
1046 sdi2_per3@80005000 {
1047 compatible = "arm,pl18x", "arm,primecell";
1048 reg = <0x80005000 0x1000>;
1049 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1050
1051 dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
1052 <&dma 28 0 0x0>; /* Logical - MemToDev */
1053 dma-names = "rx", "tx";
1054
1055 clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>;
1056 clock-names = "sdi", "apb_pclk";
1057 power-domains = <&pm_domains DOMAIN_VAPE>;
1058
1059 status = "disabled";
1060 };
1061
1062 sdi3_per2@80119000 {
1063 compatible = "arm,pl18x", "arm,primecell";
1064 reg = <0x80119000 0x1000>;
1065 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1066
1067 dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */
1068 <&dma 41 0 0x0>; /* Logical - MemToDev */
1069 dma-names = "rx", "tx";
1070
1071 clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>;
1072 clock-names = "sdi", "apb_pclk";
1073 power-domains = <&pm_domains DOMAIN_VAPE>;
1074
1075 status = "disabled";
1076 };
1077
1078 sdi4_per2@80114000 {
1079 compatible = "arm,pl18x", "arm,primecell";
1080 reg = <0x80114000 0x1000>;
1081 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1082
1083 dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
1084 <&dma 42 0 0x0>; /* Logical - MemToDev */
1085 dma-names = "rx", "tx";
1086
1087 clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>;
1088 clock-names = "sdi", "apb_pclk";
1089 power-domains = <&pm_domains DOMAIN_VAPE>;
1090
1091 status = "disabled";
1092 };
1093
1094 sdi5_per3@80008000 {
1095 compatible = "arm,pl18x", "arm,primecell";
1096 reg = <0x80008000 0x1000>;
1097 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1098
1099 dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */
1100 <&dma 43 0 0x0>; /* Logical - MemToDev */
1101 dma-names = "rx", "tx";
1102
1103 clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>;
1104 clock-names = "sdi", "apb_pclk";
1105 power-domains = <&pm_domains DOMAIN_VAPE>;
1106
1107 status = "disabled";
1108 };
1109
1110 sound {
1111 compatible = "stericsson,snd-soc-mop500";
1112 stericsson,cpu-dai = <&msp1 &msp3>;
1113 stericsson,audio-codec = <&codec>;
1114 clocks = <&prcmu_clk PRCMU_SYSCLK>, <&ab8500_clock AB8500_SYSCLK_ULP>, <&ab8500_clock AB8500_SYSCLK_INT>;
1115 clock-names = "sysclk", "ulpclk", "intclk";
1116 };
1117
1118 msp0: msp@80123000 {
1119 compatible = "stericsson,ux500-msp-i2s";
1120 reg = <0x80123000 0x1000>;
1121 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1122 v-ape-supply = <&db8500_vape_reg>;
1123
1124 dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */
1125 <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */
1126 dma-names = "rx", "tx";
1127
1128 clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>;
1129 clock-names = "msp", "apb_pclk";
1130
1131 status = "disabled";
1132 };
1133
1134 msp1: msp@80124000 {
1135 compatible = "stericsson,ux500-msp-i2s";
1136 reg = <0x80124000 0x1000>;
1137 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1138 v-ape-supply = <&db8500_vape_reg>;
1139
1140 /* This DMA channel only exist on DB8500 v1 */
1141 dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */
1142 dma-names = "tx";
1143
1144 clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>;
1145 clock-names = "msp", "apb_pclk";
1146
1147 status = "disabled";
1148 };
1149
1150 // HDMI sound
1151 msp2: msp@80117000 {
1152 compatible = "stericsson,ux500-msp-i2s";
1153 reg = <0x80117000 0x1000>;
1154 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1155 v-ape-supply = <&db8500_vape_reg>;
1156
1157 dmas = <&dma 14 0 0x12>, /* Logical - DevToMem - HighPrio */
1158 <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev
1159 HighPrio - Fixed */
1160 dma-names = "rx", "tx";
1161
1162 clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>;
1163 clock-names = "msp", "apb_pclk";
1164
1165 status = "disabled";
1166 };
1167
1168 msp3: msp@80125000 {
1169 compatible = "stericsson,ux500-msp-i2s";
1170 reg = <0x80125000 0x1000>;
1171 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1172 v-ape-supply = <&db8500_vape_reg>;
1173
1174 /* This DMA channel only exist on DB8500 v2 */
1175 dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */
1176 dma-names = "rx";
1177
1178 clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>;
1179 clock-names = "msp", "apb_pclk";
1180
1181 status = "disabled";
1182 };
1183
1184 external-bus@50000000 {
1185 compatible = "simple-bus";
1186 reg = <0x50000000 0x4000000>;
1187 #address-cells = <1>;
1188 #size-cells = <1>;
1189 ranges = <0 0x50000000 0x4000000>;
1190 status = "disabled";
1191 };
1192
1193 mcde@a0350000 {
1194 compatible = "stericsson,mcde";
1195 reg = <0xa0350000 0x1000>, /* MCDE */
1196 <0xa0351000 0x1000>, /* DSI link 1 */
1197 <0xa0352000 0x1000>, /* DSI link 2 */
1198 <0xa0353000 0x1000>; /* DSI link 3 */
1199 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1200 clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */
1201 <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */
1202 <&prcmu_clk PRCMU_PLLDSI>, /* HDMI clock */
1203 <&prcmu_clk PRCMU_DSI0CLK>, /* DSI 0 */
1204 <&prcmu_clk PRCMU_DSI1CLK>, /* DSI 1 */
1205 <&prcmu_clk PRCMU_DSI0ESCCLK>, /* TVout clock 0 */
1206 <&prcmu_clk PRCMU_DSI1ESCCLK>, /* TVout clock 1 */
1207 <&prcmu_clk PRCMU_DSI2ESCCLK>; /* TVout clock 2 */
1208 };
1209
1210 cryp@a03cb000 {
1211 compatible = "stericsson,ux500-cryp";
1212 reg = <0xa03cb000 0x1000>;
1213 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1214
1215 v-ape-supply = <&db8500_vape_reg>;
1216 clocks = <&prcc_pclk 6 1>;
1217 };
1218
1219 hash@a03c2000 {
1220 compatible = "stericsson,ux500-hash";
1221 reg = <0xa03c2000 0x1000>;
1222
1223 v-ape-supply = <&db8500_vape_reg>;
1224 clocks = <&prcc_pclk 6 2>;
1225 };
1226 };
1227};
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2012 Linaro Ltd
4 */
5
6#include <dt-bindings/interrupt-controller/irq.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/reset/stericsson,db8500-prcc-reset.h>
9#include <dt-bindings/mfd/dbx500-prcmu.h>
10#include <dt-bindings/arm/ux500_pm_domains.h>
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/thermal/thermal.h>
13
14/ {
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 /* This stablilizes the device enumeration */
19 aliases {
20 i2c0 = &i2c0;
21 i2c1 = &i2c1;
22 i2c2 = &i2c2;
23 i2c3 = &i2c3;
24 i2c4 = &i2c4;
25 spi0 = &spi0;
26 spi1 = &spi1;
27 spi2 = &spi2;
28 spi3 = &spi3;
29 serial0 = &serial0;
30 serial1 = &serial1;
31 serial2 = &serial2;
32 };
33
34 chosen {
35 };
36
37 cpus {
38 #address-cells = <1>;
39 #size-cells = <0>;
40 enable-method = "ste,dbx500-smp";
41
42 cpu-map {
43 cluster0 {
44 core0 {
45 cpu = <&CPU0>;
46 };
47 core1 {
48 cpu = <&CPU1>;
49 };
50 };
51 };
52 CPU0: cpu@300 {
53 device_type = "cpu";
54 compatible = "arm,cortex-a9";
55 reg = <0x300>;
56 clocks = <&prcmu_clk PRCMU_ARMSS>;
57 clock-names = "cpu";
58 clock-latency = <20000>;
59 #cooling-cells = <2>;
60 };
61 CPU1: cpu@301 {
62 device_type = "cpu";
63 compatible = "arm,cortex-a9";
64 reg = <0x301>;
65 };
66 };
67
68 thermal-zones {
69 /*
70 * Thermal zone for the SoC, using the thermal sensor in the
71 * PRCMU for temperature and the cpufreq driver for passive
72 * cooling.
73 */
74 cpu_thermal: cpu-thermal {
75 polling-delay-passive = <250>;
76 /*
77 * This sensor fires interrupts to update the thermal
78 * zone, so no polling is needed.
79 */
80 polling-delay = <0>;
81
82 thermal-sensors = <&thermal>;
83
84 trips {
85 cpu_alert: cpu-alert {
86 temperature = <70000>;
87 hysteresis = <2000>;
88 type = "passive";
89 };
90 cpu-crit {
91 temperature = <85000>;
92 hysteresis = <0>;
93 type = "critical";
94 };
95 };
96
97 cooling-maps {
98 trip = <&cpu_alert>;
99 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
100 contribution = <100>;
101 };
102 };
103 };
104
105 soc {
106 #address-cells = <1>;
107 #size-cells = <1>;
108 compatible = "stericsson,db8500", "simple-bus";
109 interrupt-parent = <&intc>;
110 ranges;
111
112 ptm@801ae000 {
113 compatible = "arm,coresight-etm3x", "arm,primecell";
114 reg = <0x801ae000 0x1000>;
115
116 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
117 clock-names = "apb_pclk", "atclk";
118 cpu = <&CPU0>;
119 out-ports {
120 port {
121 ptm0_out_port: endpoint {
122 remote-endpoint = <&funnel_in_port0>;
123 };
124 };
125 };
126 };
127
128 ptm@801af000 {
129 compatible = "arm,coresight-etm3x", "arm,primecell";
130 reg = <0x801af000 0x1000>;
131
132 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
133 clock-names = "apb_pclk", "atclk";
134 cpu = <&CPU1>;
135 out-ports {
136 port {
137 ptm1_out_port: endpoint {
138 remote-endpoint = <&funnel_in_port1>;
139 };
140 };
141 };
142 };
143
144 funnel@801a6000 {
145 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
146 reg = <0x801a6000 0x1000>;
147
148 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
149 clock-names = "apb_pclk", "atclk";
150 out-ports {
151 port {
152 funnel_out_port: endpoint {
153 remote-endpoint =
154 <&replicator_in_port0>;
155 };
156 };
157 };
158
159 in-ports {
160 #address-cells = <1>;
161 #size-cells = <0>;
162
163 port@0 {
164 reg = <0>;
165 funnel_in_port0: endpoint {
166 remote-endpoint = <&ptm0_out_port>;
167 };
168 };
169
170 port@1 {
171 reg = <1>;
172 funnel_in_port1: endpoint {
173 remote-endpoint = <&ptm1_out_port>;
174 };
175 };
176 };
177 };
178
179 replicator {
180 compatible = "arm,coresight-static-replicator";
181 clocks = <&prcmu_clk PRCMU_APEATCLK>;
182 clock-names = "atclk";
183
184 out-ports {
185 #address-cells = <1>;
186 #size-cells = <0>;
187
188 port@0 {
189 reg = <0>;
190 replicator_out_port0: endpoint {
191 remote-endpoint = <&tpiu_in_port>;
192 };
193 };
194 port@1 {
195 reg = <1>;
196 replicator_out_port1: endpoint {
197 remote-endpoint = <&etb_in_port>;
198 };
199 };
200 };
201
202 in-ports {
203 port {
204 replicator_in_port0: endpoint {
205 remote-endpoint = <&funnel_out_port>;
206 };
207 };
208 };
209 };
210
211 tpiu@80190000 {
212 compatible = "arm,coresight-tpiu", "arm,primecell";
213 reg = <0x80190000 0x1000>;
214
215 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
216 clock-names = "apb_pclk", "atclk";
217 in-ports {
218 port {
219 tpiu_in_port: endpoint {
220 remote-endpoint = <&replicator_out_port0>;
221 };
222 };
223 };
224 };
225
226 etb@801a4000 {
227 compatible = "arm,coresight-etb10", "arm,primecell";
228 reg = <0x801a4000 0x1000>;
229
230 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
231 clock-names = "apb_pclk", "atclk";
232 in-ports {
233 port {
234 etb_in_port: endpoint {
235 remote-endpoint = <&replicator_out_port1>;
236 };
237 };
238 };
239 };
240
241 intc: interrupt-controller@a0411000 {
242 compatible = "arm,cortex-a9-gic";
243 #interrupt-cells = <3>;
244 #address-cells = <1>;
245 interrupt-controller;
246 reg = <0xa0411000 0x1000>,
247 <0xa0410100 0x100>;
248 };
249
250 scu@a0410000 {
251 compatible = "arm,cortex-a9-scu";
252 reg = <0xa0410000 0x100>;
253 };
254
255 /*
256 * The backup RAM is used for retention during sleep
257 * and various things like spin tables
258 */
259 backupram@80150000 {
260 compatible = "ste,dbx500-backupram";
261 reg = <0x80150000 0x2000>;
262 };
263
264 L2: cache-controller {
265 compatible = "arm,pl310-cache";
266 reg = <0xa0412000 0x1000>;
267 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
268 cache-unified;
269 cache-level = <2>;
270 };
271
272 pmu {
273 compatible = "arm,cortex-a9-pmu";
274 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
275 };
276
277 pm_domains: pm_domains0 {
278 compatible = "stericsson,ux500-pm-domains";
279 #power-domain-cells = <1>;
280 };
281
282 clocks {
283 compatible = "stericsson,u8500-clks";
284 /*
285 * Registers for the CLKRST block on peripheral
286 * groups 1, 2, 3, 5, 6,
287 */
288 reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
289 <0x8000f000 0x1000>, <0xa03ff000 0x1000>,
290 <0xa03cf000 0x1000>;
291
292 prcmu_clk: prcmu-clock {
293 #clock-cells = <1>;
294 };
295
296 prcc_pclk: prcc-periph-clock {
297 #clock-cells = <2>;
298 };
299
300 prcc_kclk: prcc-kernel-clock {
301 #clock-cells = <2>;
302 };
303
304 prcc_reset: prcc-reset-controller {
305 #reset-cells = <2>;
306 };
307
308 rtc_clk: rtc32k-clock {
309 #clock-cells = <0>;
310 };
311
312 smp_twd_clk: smp-twd-clock {
313 #clock-cells = <0>;
314 };
315 };
316
317 mtu@a03c6000 {
318 /* Nomadik System Timer */
319 compatible = "st,nomadik-mtu";
320 reg = <0xa03c6000 0x1000>;
321 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
322
323 clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>;
324 clock-names = "timclk", "apb_pclk";
325 };
326
327 timer@a0410600 {
328 compatible = "arm,cortex-a9-twd-timer";
329 reg = <0xa0410600 0x20>;
330 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
331
332 clocks = <&smp_twd_clk>;
333 };
334
335 watchdog@a0410620 {
336 compatible = "arm,cortex-a9-twd-wdt";
337 reg = <0xa0410620 0x20>;
338 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
339 clocks = <&smp_twd_clk>;
340 };
341
342 rtc@80154000 {
343 compatible = "arm,pl031", "arm,primecell";
344 reg = <0x80154000 0x1000>;
345 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
346
347 clocks = <&rtc_clk>;
348 clock-names = "apb_pclk";
349 };
350
351 gpio0: gpio@8012e000 {
352 compatible = "stericsson,db8500-gpio",
353 "st,nomadik-gpio";
354 reg = <0x8012e000 0x80>;
355 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
356 interrupt-controller;
357 #interrupt-cells = <2>;
358 st,supports-sleepmode;
359 gpio-controller;
360 #gpio-cells = <2>;
361 gpio-bank = <0>;
362 gpio-ranges = <&pinctrl 0 0 32>;
363 clocks = <&prcc_pclk 1 9>;
364 };
365
366 gpio1: gpio@8012e080 {
367 compatible = "stericsson,db8500-gpio",
368 "st,nomadik-gpio";
369 reg = <0x8012e080 0x80>;
370 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
371 interrupt-controller;
372 #interrupt-cells = <2>;
373 st,supports-sleepmode;
374 gpio-controller;
375 #gpio-cells = <2>;
376 gpio-bank = <1>;
377 gpio-ranges = <&pinctrl 0 32 5>;
378 clocks = <&prcc_pclk 1 9>;
379 };
380
381 gpio2: gpio@8000e000 {
382 compatible = "stericsson,db8500-gpio",
383 "st,nomadik-gpio";
384 reg = <0x8000e000 0x80>;
385 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
386 interrupt-controller;
387 #interrupt-cells = <2>;
388 st,supports-sleepmode;
389 gpio-controller;
390 #gpio-cells = <2>;
391 gpio-bank = <2>;
392 gpio-ranges = <&pinctrl 0 64 32>;
393 clocks = <&prcc_pclk 3 8>;
394 };
395
396 gpio3: gpio@8000e080 {
397 compatible = "stericsson,db8500-gpio",
398 "st,nomadik-gpio";
399 reg = <0x8000e080 0x80>;
400 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
401 interrupt-controller;
402 #interrupt-cells = <2>;
403 st,supports-sleepmode;
404 gpio-controller;
405 #gpio-cells = <2>;
406 gpio-bank = <3>;
407 gpio-ranges = <&pinctrl 0 96 2>;
408 clocks = <&prcc_pclk 3 8>;
409 };
410
411 gpio4: gpio@8000e100 {
412 compatible = "stericsson,db8500-gpio",
413 "st,nomadik-gpio";
414 reg = <0x8000e100 0x80>;
415 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
416 interrupt-controller;
417 #interrupt-cells = <2>;
418 st,supports-sleepmode;
419 gpio-controller;
420 #gpio-cells = <2>;
421 gpio-bank = <4>;
422 gpio-ranges = <&pinctrl 0 128 32>;
423 clocks = <&prcc_pclk 3 8>;
424 };
425
426 gpio5: gpio@8000e180 {
427 compatible = "stericsson,db8500-gpio",
428 "st,nomadik-gpio";
429 reg = <0x8000e180 0x80>;
430 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
431 interrupt-controller;
432 #interrupt-cells = <2>;
433 st,supports-sleepmode;
434 gpio-controller;
435 #gpio-cells = <2>;
436 gpio-bank = <5>;
437 gpio-ranges = <&pinctrl 0 160 12>;
438 clocks = <&prcc_pclk 3 8>;
439 };
440
441 gpio6: gpio@8011e000 {
442 compatible = "stericsson,db8500-gpio",
443 "st,nomadik-gpio";
444 reg = <0x8011e000 0x80>;
445 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
446 interrupt-controller;
447 #interrupt-cells = <2>;
448 st,supports-sleepmode;
449 gpio-controller;
450 #gpio-cells = <2>;
451 gpio-bank = <6>;
452 gpio-ranges = <&pinctrl 0 192 32>;
453 clocks = <&prcc_pclk 2 11>;
454 };
455
456 gpio7: gpio@8011e080 {
457 compatible = "stericsson,db8500-gpio",
458 "st,nomadik-gpio";
459 reg = <0x8011e080 0x80>;
460 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
461 interrupt-controller;
462 #interrupt-cells = <2>;
463 st,supports-sleepmode;
464 gpio-controller;
465 #gpio-cells = <2>;
466 gpio-bank = <7>;
467 gpio-ranges = <&pinctrl 0 224 7>;
468 clocks = <&prcc_pclk 2 11>;
469 };
470
471 gpio8: gpio@a03fe000 {
472 compatible = "stericsson,db8500-gpio",
473 "st,nomadik-gpio";
474 reg = <0xa03fe000 0x80>;
475 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
476 interrupt-controller;
477 #interrupt-cells = <2>;
478 st,supports-sleepmode;
479 gpio-controller;
480 #gpio-cells = <2>;
481 gpio-bank = <8>;
482 gpio-ranges = <&pinctrl 0 256 12>;
483 clocks = <&prcc_pclk 5 1>;
484 };
485
486 pinctrl: pinctrl {
487 compatible = "stericsson,db8500-pinctrl";
488 nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>,
489 <&gpio4>, <&gpio5>, <&gpio6>, <&gpio7>,
490 <&gpio8>;
491 prcm = <&prcmu>;
492 };
493
494 usb_per5@a03e0000 {
495 compatible = "stericsson,db8500-musb";
496 reg = <0xa03e0000 0x10000>;
497 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
498 interrupt-names = "mc";
499
500 dr_mode = "otg";
501
502 dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
503 <&dma 38 0 0x0>, /* Logical - MemToDev */
504 <&dma 37 0 0x2>, /* Logical - DevToMem */
505 <&dma 37 0 0x0>, /* Logical - MemToDev */
506 <&dma 36 0 0x2>, /* Logical - DevToMem */
507 <&dma 36 0 0x0>, /* Logical - MemToDev */
508 <&dma 19 0 0x2>, /* Logical - DevToMem */
509 <&dma 19 0 0x0>, /* Logical - MemToDev */
510 <&dma 18 0 0x2>, /* Logical - DevToMem */
511 <&dma 18 0 0x0>, /* Logical - MemToDev */
512 <&dma 17 0 0x2>, /* Logical - DevToMem */
513 <&dma 17 0 0x0>, /* Logical - MemToDev */
514 <&dma 16 0 0x2>, /* Logical - DevToMem */
515 <&dma 16 0 0x0>, /* Logical - MemToDev */
516 <&dma 39 0 0x2>, /* Logical - DevToMem */
517 <&dma 39 0 0x0>; /* Logical - MemToDev */
518
519 dma-names = "iep_1_9", "oep_1_9",
520 "iep_2_10", "oep_2_10",
521 "iep_3_11", "oep_3_11",
522 "iep_4_12", "oep_4_12",
523 "iep_5_13", "oep_5_13",
524 "iep_6_14", "oep_6_14",
525 "iep_7_15", "oep_7_15",
526 "iep_8", "oep_8";
527
528 clocks = <&prcc_pclk 5 0>;
529 };
530
531 dma: dma-controller@801C0000 {
532 compatible = "stericsson,db8500-dma40", "stericsson,dma40";
533 reg = <0x801C0000 0x1000 0x40010000 0x800>;
534 reg-names = "base", "lcpa";
535 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
536
537 #dma-cells = <3>;
538 memcpy-channels = <56 57 58 59 60>;
539
540 clocks = <&prcmu_clk PRCMU_DMACLK>;
541 };
542
543 prcmu: prcmu@80157000 {
544 compatible = "stericsson,db8500-prcmu", "syscon";
545 reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
546 reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
547 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
548 #address-cells = <1>;
549 #size-cells = <1>;
550 interrupt-controller;
551 #interrupt-cells = <2>;
552 ranges;
553
554 prcmu-timer-4@80157450 {
555 compatible = "stericsson,db8500-prcmu-timer-4";
556 reg = <0x80157450 0xC>;
557 };
558
559 thermal: thermal@801573c0 {
560 compatible = "stericsson,db8500-thermal";
561 reg = <0x801573c0 0x40>;
562 interrupt-parent = <&prcmu>;
563 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>,
564 <22 IRQ_TYPE_LEVEL_HIGH>;
565 interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
566 #thermal-sensor-cells = <0>;
567 };
568
569 db8500-prcmu-regulators {
570 compatible = "stericsson,db8500-prcmu-regulator";
571
572 // DB8500_REGULATOR_VAPE
573 db8500_vape_reg: db8500_vape {
574 regulator-always-on;
575 };
576
577 // DB8500_REGULATOR_VARM
578 db8500_varm_reg: db8500_varm {
579 };
580
581 // DB8500_REGULATOR_VMODEM
582 db8500_vmodem_reg: db8500_vmodem {
583 };
584
585 // DB8500_REGULATOR_VPLL
586 db8500_vpll_reg: db8500_vpll {
587 };
588
589 // DB8500_REGULATOR_VSMPS1
590 db8500_vsmps1_reg: db8500_vsmps1 {
591 };
592
593 // DB8500_REGULATOR_VSMPS2
594 db8500_vsmps2_reg: db8500_vsmps2 {
595 };
596
597 // DB8500_REGULATOR_VSMPS3
598 db8500_vsmps3_reg: db8500_vsmps3 {
599 };
600
601 // DB8500_REGULATOR_VRF1
602 db8500_vrf1_reg: db8500_vrf1 {
603 };
604
605 // DB8500_REGULATOR_SWITCH_SVAMMDSP
606 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
607 };
608
609 // DB8500_REGULATOR_SWITCH_SVAMMDSPRET
610 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
611 };
612
613 // DB8500_REGULATOR_SWITCH_SVAPIPE
614 db8500_sva_pipe_reg: db8500_sva_pipe {
615 };
616
617 // DB8500_REGULATOR_SWITCH_SIAMMDSP
618 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
619 };
620
621 // DB8500_REGULATOR_SWITCH_SIAMMDSPRET
622 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
623 };
624
625 // DB8500_REGULATOR_SWITCH_SIAPIPE
626 db8500_sia_pipe_reg: db8500_sia_pipe {
627 };
628
629 // DB8500_REGULATOR_SWITCH_SGA
630 db8500_sga_reg: db8500_sga {
631 vin-supply = <&db8500_vape_reg>;
632 };
633
634 // DB8500_REGULATOR_SWITCH_B2R2_MCDE
635 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
636 vin-supply = <&db8500_vape_reg>;
637 };
638
639 // DB8500_REGULATOR_SWITCH_ESRAM12
640 db8500_esram12_reg: db8500_esram12 {
641 };
642
643 // DB8500_REGULATOR_SWITCH_ESRAM12RET
644 db8500_esram12_ret_reg: db8500_esram12_ret {
645 };
646
647 // DB8500_REGULATOR_SWITCH_ESRAM34
648 db8500_esram34_reg: db8500_esram34 {
649 };
650
651 // DB8500_REGULATOR_SWITCH_ESRAM34RET
652 db8500_esram34_ret_reg: db8500_esram34_ret {
653 };
654 };
655 };
656
657 i2c0: i2c@80004000 {
658 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
659 reg = <0x80004000 0x1000>;
660 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
661
662 #address-cells = <1>;
663 #size-cells = <0>;
664
665 clock-frequency = <400000>;
666 clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>;
667 clock-names = "i2cclk", "apb_pclk";
668 power-domains = <&pm_domains DOMAIN_VAPE>;
669 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_I2C0>;
670
671 status = "disabled";
672 };
673
674 i2c1: i2c@80122000 {
675 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
676 reg = <0x80122000 0x1000>;
677 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
678
679 #address-cells = <1>;
680 #size-cells = <0>;
681
682 clock-frequency = <400000>;
683
684 clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>;
685 clock-names = "i2cclk", "apb_pclk";
686 power-domains = <&pm_domains DOMAIN_VAPE>;
687 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C1>;
688
689 status = "disabled";
690 };
691
692 i2c2: i2c@80128000 {
693 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
694 reg = <0x80128000 0x1000>;
695 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
696
697 #address-cells = <1>;
698 #size-cells = <0>;
699
700 clock-frequency = <400000>;
701
702 clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>;
703 clock-names = "i2cclk", "apb_pclk";
704 power-domains = <&pm_domains DOMAIN_VAPE>;
705 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C2>;
706
707 status = "disabled";
708 };
709
710 i2c3: i2c@80110000 {
711 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
712 reg = <0x80110000 0x1000>;
713 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
714
715 #address-cells = <1>;
716 #size-cells = <0>;
717
718 clock-frequency = <400000>;
719
720 clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>;
721 clock-names = "i2cclk", "apb_pclk";
722 power-domains = <&pm_domains DOMAIN_VAPE>;
723 resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_I2C3>;
724
725 status = "disabled";
726 };
727
728 i2c4: i2c@8012a000 {
729 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
730 reg = <0x8012a000 0x1000>;
731 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
732
733 #address-cells = <1>;
734 #size-cells = <0>;
735
736 clock-frequency = <400000>;
737
738 clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>;
739 clock-names = "i2cclk", "apb_pclk";
740 power-domains = <&pm_domains DOMAIN_VAPE>;
741 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C4>;
742
743 status = "disabled";
744 };
745
746 ssp0: spi@80002000 {
747 compatible = "arm,pl022", "arm,primecell";
748 reg = <0x80002000 0x1000>;
749 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
750 #address-cells = <1>;
751 #size-cells = <0>;
752 clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;
753 clock-names = "sspclk", "apb_pclk";
754 dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
755 <&dma 8 0 0x0>; /* Logical - MemToDev */
756 dma-names = "rx", "tx";
757 power-domains = <&pm_domains DOMAIN_VAPE>;
758 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SSP0>;
759
760 status = "disabled";
761 };
762
763 ssp1: spi@80003000 {
764 compatible = "arm,pl022", "arm,primecell";
765 reg = <0x80003000 0x1000>;
766 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
767 #address-cells = <1>;
768 #size-cells = <0>;
769 clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;
770 clock-names = "sspclk", "apb_pclk";
771 dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
772 <&dma 9 0 0x0>; /* Logical - MemToDev */
773 dma-names = "rx", "tx";
774 power-domains = <&pm_domains DOMAIN_VAPE>;
775 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SSP1>;
776
777 status = "disabled";
778 };
779
780 spi0: spi@8011a000 {
781 compatible = "arm,pl022", "arm,primecell";
782 reg = <0x8011a000 0x1000>;
783 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
784 #address-cells = <1>;
785 #size-cells = <0>;
786 /* Same clock wired to kernel and pclk */
787 clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;
788 clock-names = "sspclk", "apb_pclk";
789 dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
790 <&dma 0 0 0x0>; /* Logical - MemToDev */
791 dma-names = "rx", "tx";
792 power-domains = <&pm_domains DOMAIN_VAPE>;
793
794 status = "disabled";
795 };
796
797 spi1: spi@80112000 {
798 compatible = "arm,pl022", "arm,primecell";
799 reg = <0x80112000 0x1000>;
800 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
801 #address-cells = <1>;
802 #size-cells = <0>;
803 /* Same clock wired to kernel and pclk */
804 clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;
805 clock-names = "sspclk", "apb_pclk";
806 dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
807 <&dma 35 0 0x0>; /* Logical - MemToDev */
808 dma-names = "rx", "tx";
809 power-domains = <&pm_domains DOMAIN_VAPE>;
810
811 status = "disabled";
812 };
813
814 spi2: spi@80111000 {
815 compatible = "arm,pl022", "arm,primecell";
816 reg = <0x80111000 0x1000>;
817 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
818 #address-cells = <1>;
819 #size-cells = <0>;
820 /* Same clock wired to kernel and pclk */
821 clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;
822 clock-names = "sspclk", "apb_pclk";
823 dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
824 <&dma 33 0 0x0>; /* Logical - MemToDev */
825 dma-names = "rx", "tx";
826 power-domains = <&pm_domains DOMAIN_VAPE>;
827
828 status = "disabled";
829 };
830
831 spi3: spi@80129000 {
832 compatible = "arm,pl022", "arm,primecell";
833 reg = <0x80129000 0x1000>;
834 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
835 #address-cells = <1>;
836 #size-cells = <0>;
837 /* Same clock wired to kernel and pclk */
838 clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;
839 clock-names = "sspclk", "apb_pclk";
840 dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
841 <&dma 40 0 0x0>; /* Logical - MemToDev */
842 dma-names = "rx", "tx";
843 power-domains = <&pm_domains DOMAIN_VAPE>;
844 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_SPI3>;
845
846 status = "disabled";
847 };
848
849 serial0: uart@80120000 {
850 compatible = "arm,pl011", "arm,primecell";
851 reg = <0x80120000 0x1000>;
852 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
853
854 dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
855 <&dma 13 0 0x0>; /* Logical - MemToDev */
856 dma-names = "rx", "tx";
857
858 clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>;
859 clock-names = "uart", "apb_pclk";
860 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_UART0>;
861
862 status = "disabled";
863 };
864
865 serial1: uart@80121000 {
866 compatible = "arm,pl011", "arm,primecell";
867 reg = <0x80121000 0x1000>;
868 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
869
870 dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
871 <&dma 12 0 0x0>; /* Logical - MemToDev */
872 dma-names = "rx", "tx";
873
874 clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>;
875 clock-names = "uart", "apb_pclk";
876 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_UART1>;
877
878 status = "disabled";
879 };
880
881 serial2: uart@80007000 {
882 compatible = "arm,pl011", "arm,primecell";
883 reg = <0x80007000 0x1000>;
884 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
885
886 dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
887 <&dma 11 0 0x0>; /* Logical - MemToDev */
888 dma-names = "rx", "tx";
889
890 clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>;
891 clock-names = "uart", "apb_pclk";
892 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_UART2>;
893
894 status = "disabled";
895 };
896
897 mmc@80126000 {
898 compatible = "arm,pl18x", "arm,primecell";
899 reg = <0x80126000 0x1000>;
900 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
901
902 dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
903 <&dma 29 0 0x0>; /* Logical - MemToDev */
904 dma-names = "rx", "tx";
905
906 clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
907 clock-names = "sdi", "apb_pclk";
908 power-domains = <&pm_domains DOMAIN_VAPE>;
909 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_SDI0>;
910
911 status = "disabled";
912 };
913
914 mmc@80118000 {
915 compatible = "arm,pl18x", "arm,primecell";
916 reg = <0x80118000 0x1000>;
917 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
918
919 dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
920 <&dma 32 0 0x0>; /* Logical - MemToDev */
921 dma-names = "rx", "tx";
922
923 clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>;
924 clock-names = "sdi", "apb_pclk";
925 power-domains = <&pm_domains DOMAIN_VAPE>;
926 resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI1>;
927
928 status = "disabled";
929 };
930
931 mmc@80005000 {
932 compatible = "arm,pl18x", "arm,primecell";
933 reg = <0x80005000 0x1000>;
934 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
935
936 dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
937 <&dma 28 0 0x0>; /* Logical - MemToDev */
938 dma-names = "rx", "tx";
939
940 clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>;
941 clock-names = "sdi", "apb_pclk";
942 power-domains = <&pm_domains DOMAIN_VAPE>;
943 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SDI2>;
944
945 status = "disabled";
946 };
947
948 mmc@80119000 {
949 compatible = "arm,pl18x", "arm,primecell";
950 reg = <0x80119000 0x1000>;
951 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
952
953 dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */
954 <&dma 41 0 0x0>; /* Logical - MemToDev */
955 dma-names = "rx", "tx";
956
957 clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>;
958 clock-names = "sdi", "apb_pclk";
959 power-domains = <&pm_domains DOMAIN_VAPE>;
960 resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI3>;
961
962 status = "disabled";
963 };
964
965 mmc@80114000 {
966 compatible = "arm,pl18x", "arm,primecell";
967 reg = <0x80114000 0x1000>;
968 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
969
970 dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
971 <&dma 42 0 0x0>; /* Logical - MemToDev */
972 dma-names = "rx", "tx";
973
974 clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>;
975 clock-names = "sdi", "apb_pclk";
976 power-domains = <&pm_domains DOMAIN_VAPE>;
977 resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI4>;
978
979 status = "disabled";
980 };
981
982 mmc@80008000 {
983 compatible = "arm,pl18x", "arm,primecell";
984 reg = <0x80008000 0x1000>;
985 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
986
987 dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */
988 <&dma 43 0 0x0>; /* Logical - MemToDev */
989 dma-names = "rx", "tx";
990
991 clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>;
992 clock-names = "sdi", "apb_pclk";
993 power-domains = <&pm_domains DOMAIN_VAPE>;
994 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SDI5>;
995
996 status = "disabled";
997 };
998
999 sound {
1000 compatible = "stericsson,snd-soc-mop500";
1001 stericsson,cpu-dai = <&msp1 &msp3>;
1002 };
1003
1004 msp0: msp@80123000 {
1005 compatible = "stericsson,ux500-msp-i2s";
1006 reg = <0x80123000 0x1000>;
1007 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1008 v-ape-supply = <&db8500_vape_reg>;
1009
1010 dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */
1011 <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */
1012 dma-names = "rx", "tx";
1013
1014 clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>;
1015 clock-names = "msp", "apb_pclk";
1016 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP0>;
1017
1018 status = "disabled";
1019 };
1020
1021 msp1: msp@80124000 {
1022 compatible = "stericsson,ux500-msp-i2s";
1023 reg = <0x80124000 0x1000>;
1024 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1025 v-ape-supply = <&db8500_vape_reg>;
1026
1027 /* This DMA channel only exist on DB8500 v1 */
1028 dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */
1029 dma-names = "tx";
1030
1031 clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>;
1032 clock-names = "msp", "apb_pclk";
1033 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP1>;
1034
1035 status = "disabled";
1036 };
1037
1038 // HDMI sound
1039 msp2: msp@80117000 {
1040 compatible = "stericsson,ux500-msp-i2s";
1041 reg = <0x80117000 0x1000>;
1042 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1043 v-ape-supply = <&db8500_vape_reg>;
1044
1045 dmas = <&dma 14 0 0x12>, /* Logical - DevToMem - HighPrio */
1046 <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev
1047 HighPrio - Fixed */
1048 dma-names = "rx", "tx";
1049
1050 clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>;
1051 clock-names = "msp", "apb_pclk";
1052 resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_MSP2>;
1053
1054 status = "disabled";
1055 };
1056
1057 msp3: msp@80125000 {
1058 compatible = "stericsson,ux500-msp-i2s";
1059 reg = <0x80125000 0x1000>;
1060 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1061 v-ape-supply = <&db8500_vape_reg>;
1062
1063 /* This DMA channel only exist on DB8500 v2 */
1064 dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */
1065 dma-names = "rx";
1066
1067 clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>;
1068 clock-names = "msp", "apb_pclk";
1069 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP3>;
1070
1071 status = "disabled";
1072 };
1073
1074 external-bus@50000000 {
1075 compatible = "simple-bus";
1076 reg = <0x50000000 0x4000000>;
1077 #address-cells = <1>;
1078 #size-cells = <1>;
1079 ranges = <0 0x50000000 0x4000000>;
1080 status = "disabled";
1081 };
1082
1083 gpu@a0300000 {
1084 /*
1085 * This block is referred to as "Smart Graphics Adapter SGA500"
1086 * in documentation but is in practice a pretty straight-forward
1087 * MALI-400 GPU block.
1088 */
1089 compatible = "stericsson,db8500-mali", "arm,mali-400";
1090 reg = <0xa0300000 0x10000>;
1091 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1092 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1093 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1094 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1095 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1096 interrupt-names = "gp",
1097 "gpmmu",
1098 "pp0",
1099 "ppmmu0",
1100 "combined";
1101 clocks = <&prcmu_clk PRCMU_ACLK>, <&prcmu_clk PRCMU_SGACLK>;
1102 clock-names = "bus", "core";
1103 mali-supply = <&db8500_sga_reg>;
1104 power-domains = <&pm_domains DOMAIN_VAPE>;
1105 };
1106
1107 mcde@a0350000 {
1108 compatible = "ste,mcde";
1109 reg = <0xa0350000 0x1000>;
1110 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1111 epod-supply = <&db8500_b2r2_mcde_reg>;
1112 clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */
1113 <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */
1114 <&prcmu_clk PRCMU_PLLDSI>; /* HDMI clock */
1115 clock-names = "mcde", "lcd", "hdmi";
1116 #address-cells = <1>;
1117 #size-cells = <1>;
1118 ranges;
1119 status = "disabled";
1120
1121 dsi0: dsi@a0351000 {
1122 compatible = "ste,mcde-dsi";
1123 reg = <0xa0351000 0x1000>;
1124 clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>;
1125 clock-names = "hs", "lp";
1126 #address-cells = <1>;
1127 #size-cells = <0>;
1128 };
1129 dsi1: dsi@a0352000 {
1130 compatible = "ste,mcde-dsi";
1131 reg = <0xa0352000 0x1000>;
1132 clocks = <&prcmu_clk PRCMU_DSI1CLK>, <&prcmu_clk PRCMU_DSI1ESCCLK>;
1133 clock-names = "hs", "lp";
1134 #address-cells = <1>;
1135 #size-cells = <0>;
1136 };
1137 dsi2: dsi@a0353000 {
1138 compatible = "ste,mcde-dsi";
1139 reg = <0xa0353000 0x1000>;
1140 /* This DSI port only has the Low Power / Energy Save clock */
1141 clocks = <&prcmu_clk PRCMU_DSI2ESCCLK>;
1142 clock-names = "lp";
1143 #address-cells = <1>;
1144 #size-cells = <0>;
1145 };
1146 };
1147
1148 cryp@a03cb000 {
1149 compatible = "stericsson,ux500-cryp";
1150 reg = <0xa03cb000 0x1000>;
1151 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1152 clocks = <&prcc_pclk 6 1>;
1153 power-domains = <&pm_domains DOMAIN_VAPE>;
1154 };
1155
1156 hash@a03c2000 {
1157 compatible = "stericsson,ux500-hash";
1158 reg = <0xa03c2000 0x1000>;
1159 clocks = <&prcc_pclk 6 2>;
1160 power-domains = <&pm_domains DOMAIN_VAPE>;
1161 };
1162 };
1163};