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1/*
2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48#include "skeleton64.dtsi"
49#include <dt-bindings/interrupt-controller/arm-gic.h>
50#include <dt-bindings/thermal/thermal.h>
51
52/ {
53 compatible = "fsl,ls1021a";
54 interrupt-parent = <&gic>;
55
56 aliases {
57 crypto = &crypto;
58 ethernet0 = &enet0;
59 ethernet1 = &enet1;
60 ethernet2 = &enet2;
61 serial0 = &lpuart0;
62 serial1 = &lpuart1;
63 serial2 = &lpuart2;
64 serial3 = &lpuart3;
65 serial4 = &lpuart4;
66 serial5 = &lpuart5;
67 sysclk = &sysclk;
68 };
69
70 cpus {
71 #address-cells = <1>;
72 #size-cells = <0>;
73
74 cpu0: cpu@f00 {
75 compatible = "arm,cortex-a7";
76 device_type = "cpu";
77 reg = <0xf00>;
78 clocks = <&clockgen 1 0>;
79 #cooling-cells = <2>;
80 };
81
82 cpu1: cpu@f01 {
83 compatible = "arm,cortex-a7";
84 device_type = "cpu";
85 reg = <0xf01>;
86 clocks = <&clockgen 1 0>;
87 };
88 };
89
90 sysclk: sysclk {
91 compatible = "fixed-clock";
92 #clock-cells = <0>;
93 clock-frequency = <100000000>;
94 clock-output-names = "sysclk";
95 };
96
97 timer {
98 compatible = "arm,armv7-timer";
99 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
100 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
101 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
102 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
103 };
104
105 pmu {
106 compatible = "arm,cortex-a7-pmu";
107 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
109 interrupt-affinity = <&cpu0>, <&cpu1>;
110 };
111
112 reboot {
113 compatible = "syscon-reboot";
114 regmap = <&dcfg>;
115 offset = <0xb0>;
116 mask = <0x02>;
117 };
118
119 soc {
120 compatible = "simple-bus";
121 #address-cells = <2>;
122 #size-cells = <2>;
123 device_type = "soc";
124 interrupt-parent = <&gic>;
125 ranges;
126
127 gic: interrupt-controller@1400000 {
128 compatible = "arm,gic-400", "arm,cortex-a7-gic";
129 #interrupt-cells = <3>;
130 interrupt-controller;
131 reg = <0x0 0x1401000 0x0 0x1000>,
132 <0x0 0x1402000 0x0 0x2000>,
133 <0x0 0x1404000 0x0 0x2000>,
134 <0x0 0x1406000 0x0 0x2000>;
135 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
136
137 };
138
139 msi1: msi-controller@1570e00 {
140 compatible = "fsl,ls1021a-msi";
141 reg = <0x0 0x1570e00 0x0 0x8>;
142 msi-controller;
143 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
144 };
145
146 msi2: msi-controller@1570e08 {
147 compatible = "fsl,ls1021a-msi";
148 reg = <0x0 0x1570e08 0x0 0x8>;
149 msi-controller;
150 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
151 };
152
153 ifc: ifc@1530000 {
154 compatible = "fsl,ifc", "simple-bus";
155 reg = <0x0 0x1530000 0x0 0x10000>;
156 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
157 };
158
159 dcfg: dcfg@1ee0000 {
160 compatible = "fsl,ls1021a-dcfg", "syscon";
161 reg = <0x0 0x1ee0000 0x0 0x10000>;
162 big-endian;
163 };
164
165 qspi: quadspi@1550000 {
166 compatible = "fsl,ls1021a-qspi";
167 #address-cells = <1>;
168 #size-cells = <0>;
169 reg = <0x0 0x1550000 0x0 0x10000>,
170 <0x0 0x40000000 0x0 0x40000000>;
171 reg-names = "QuadSPI", "QuadSPI-memory";
172 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
173 clock-names = "qspi_en", "qspi";
174 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
175 big-endian;
176 status = "disabled";
177 };
178
179 esdhc: esdhc@1560000 {
180 compatible = "fsl,ls1021a-esdhc", "fsl,esdhc";
181 reg = <0x0 0x1560000 0x0 0x10000>;
182 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
183 clock-frequency = <0>;
184 voltage-ranges = <1800 1800 3300 3300>;
185 sdhci,auto-cmd12;
186 big-endian;
187 bus-width = <4>;
188 status = "disabled";
189 };
190
191 sata: sata@3200000 {
192 compatible = "fsl,ls1021a-ahci";
193 reg = <0x0 0x3200000 0x0 0x10000>,
194 <0x0 0x20220520 0x0 0x4>;
195 reg-names = "ahci", "sata-ecc";
196 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&clockgen 4 1>;
198 dma-coherent;
199 status = "disabled";
200 };
201
202 scfg: scfg@1570000 {
203 compatible = "fsl,ls1021a-scfg", "syscon";
204 reg = <0x0 0x1570000 0x0 0x10000>;
205 big-endian;
206 };
207
208 crypto: crypto@1700000 {
209 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
210 fsl,sec-era = <7>;
211 #address-cells = <1>;
212 #size-cells = <1>;
213 reg = <0x0 0x1700000 0x0 0x100000>;
214 ranges = <0x0 0x0 0x1700000 0x100000>;
215 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
216
217 sec_jr0: jr@10000 {
218 compatible = "fsl,sec-v5.0-job-ring",
219 "fsl,sec-v4.0-job-ring";
220 reg = <0x10000 0x10000>;
221 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
222 };
223
224 sec_jr1: jr@20000 {
225 compatible = "fsl,sec-v5.0-job-ring",
226 "fsl,sec-v4.0-job-ring";
227 reg = <0x20000 0x10000>;
228 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
229 };
230
231 sec_jr2: jr@30000 {
232 compatible = "fsl,sec-v5.0-job-ring",
233 "fsl,sec-v4.0-job-ring";
234 reg = <0x30000 0x10000>;
235 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
236 };
237
238 sec_jr3: jr@40000 {
239 compatible = "fsl,sec-v5.0-job-ring",
240 "fsl,sec-v4.0-job-ring";
241 reg = <0x40000 0x10000>;
242 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
243 };
244
245 };
246
247 clockgen: clocking@1ee1000 {
248 compatible = "fsl,ls1021a-clockgen";
249 reg = <0x0 0x1ee1000 0x0 0x1000>;
250 #clock-cells = <2>;
251 clocks = <&sysclk>;
252 };
253
254 tmu: tmu@1f00000 {
255 compatible = "fsl,qoriq-tmu";
256 reg = <0x0 0x1f00000 0x0 0x10000>;
257 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
258 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x30061>;
259 fsl,tmu-calibration = <0x00000000 0x0000000f
260 0x00000001 0x00000017
261 0x00000002 0x0000001e
262 0x00000003 0x00000026
263 0x00000004 0x0000002e
264 0x00000005 0x00000035
265 0x00000006 0x0000003d
266 0x00000007 0x00000044
267 0x00000008 0x0000004c
268 0x00000009 0x00000053
269 0x0000000a 0x0000005b
270 0x0000000b 0x00000064
271
272 0x00010000 0x00000011
273 0x00010001 0x0000001c
274 0x00010002 0x00000024
275 0x00010003 0x0000002b
276 0x00010004 0x00000034
277 0x00010005 0x00000039
278 0x00010006 0x00000042
279 0x00010007 0x0000004c
280 0x00010008 0x00000051
281 0x00010009 0x0000005a
282 0x0001000a 0x00000063
283
284 0x00020000 0x00000013
285 0x00020001 0x00000019
286 0x00020002 0x00000024
287 0x00020003 0x0000002c
288 0x00020004 0x00000035
289 0x00020005 0x0000003d
290 0x00020006 0x00000046
291 0x00020007 0x00000050
292 0x00020008 0x00000059
293
294 0x00030000 0x00000002
295 0x00030001 0x0000000d
296 0x00030002 0x00000019
297 0x00030003 0x00000024>;
298 #thermal-sensor-cells = <1>;
299 };
300
301 thermal-zones {
302 cpu_thermal: cpu-thermal {
303 polling-delay-passive = <1000>;
304 polling-delay = <5000>;
305
306 thermal-sensors = <&tmu 0>;
307
308 trips {
309 cpu_alert: cpu-alert {
310 temperature = <85000>;
311 hysteresis = <2000>;
312 type = "passive";
313 };
314 cpu_crit: cpu-crit {
315 temperature = <95000>;
316 hysteresis = <2000>;
317 type = "critical";
318 };
319 };
320
321 cooling-maps {
322 map0 {
323 trip = <&cpu_alert>;
324 cooling-device =
325 <&cpu0 THERMAL_NO_LIMIT
326 THERMAL_NO_LIMIT>;
327 };
328 };
329 };
330 };
331
332 dspi0: dspi@2100000 {
333 compatible = "fsl,ls1021a-v1.0-dspi";
334 #address-cells = <1>;
335 #size-cells = <0>;
336 reg = <0x0 0x2100000 0x0 0x10000>;
337 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
338 clock-names = "dspi";
339 clocks = <&clockgen 4 1>;
340 spi-num-chipselects = <6>;
341 big-endian;
342 status = "disabled";
343 };
344
345 dspi1: dspi@2110000 {
346 compatible = "fsl,ls1021a-v1.0-dspi";
347 #address-cells = <1>;
348 #size-cells = <0>;
349 reg = <0x0 0x2110000 0x0 0x10000>;
350 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
351 clock-names = "dspi";
352 clocks = <&clockgen 4 1>;
353 spi-num-chipselects = <6>;
354 big-endian;
355 status = "disabled";
356 };
357
358 i2c0: i2c@2180000 {
359 compatible = "fsl,vf610-i2c";
360 #address-cells = <1>;
361 #size-cells = <0>;
362 reg = <0x0 0x2180000 0x0 0x10000>;
363 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
364 clock-names = "i2c";
365 clocks = <&clockgen 4 1>;
366 status = "disabled";
367 };
368
369 i2c1: i2c@2190000 {
370 compatible = "fsl,vf610-i2c";
371 #address-cells = <1>;
372 #size-cells = <0>;
373 reg = <0x0 0x2190000 0x0 0x10000>;
374 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
375 clock-names = "i2c";
376 clocks = <&clockgen 4 1>;
377 status = "disabled";
378 };
379
380 i2c2: i2c@21a0000 {
381 compatible = "fsl,vf610-i2c";
382 #address-cells = <1>;
383 #size-cells = <0>;
384 reg = <0x0 0x21a0000 0x0 0x10000>;
385 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
386 clock-names = "i2c";
387 clocks = <&clockgen 4 1>;
388 status = "disabled";
389 };
390
391 uart0: serial@21c0500 {
392 compatible = "fsl,16550-FIFO64", "ns16550a";
393 reg = <0x0 0x21c0500 0x0 0x100>;
394 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
395 clock-frequency = <0>;
396 fifo-size = <15>;
397 status = "disabled";
398 };
399
400 uart1: serial@21c0600 {
401 compatible = "fsl,16550-FIFO64", "ns16550a";
402 reg = <0x0 0x21c0600 0x0 0x100>;
403 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
404 clock-frequency = <0>;
405 fifo-size = <15>;
406 status = "disabled";
407 };
408
409 uart2: serial@21d0500 {
410 compatible = "fsl,16550-FIFO64", "ns16550a";
411 reg = <0x0 0x21d0500 0x0 0x100>;
412 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
413 clock-frequency = <0>;
414 fifo-size = <15>;
415 status = "disabled";
416 };
417
418 uart3: serial@21d0600 {
419 compatible = "fsl,16550-FIFO64", "ns16550a";
420 reg = <0x0 0x21d0600 0x0 0x100>;
421 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
422 clock-frequency = <0>;
423 fifo-size = <15>;
424 status = "disabled";
425 };
426
427 gpio0: gpio@2300000 {
428 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
429 reg = <0x0 0x2300000 0x0 0x10000>;
430 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
431 gpio-controller;
432 #gpio-cells = <2>;
433 interrupt-controller;
434 #interrupt-cells = <2>;
435 };
436
437 gpio1: gpio@2310000 {
438 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
439 reg = <0x0 0x2310000 0x0 0x10000>;
440 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
441 gpio-controller;
442 #gpio-cells = <2>;
443 interrupt-controller;
444 #interrupt-cells = <2>;
445 };
446
447 gpio2: gpio@2320000 {
448 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
449 reg = <0x0 0x2320000 0x0 0x10000>;
450 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
451 gpio-controller;
452 #gpio-cells = <2>;
453 interrupt-controller;
454 #interrupt-cells = <2>;
455 };
456
457 gpio3: gpio@2330000 {
458 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
459 reg = <0x0 0x2330000 0x0 0x10000>;
460 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
461 gpio-controller;
462 #gpio-cells = <2>;
463 interrupt-controller;
464 #interrupt-cells = <2>;
465 };
466
467 lpuart0: serial@2950000 {
468 compatible = "fsl,ls1021a-lpuart";
469 reg = <0x0 0x2950000 0x0 0x1000>;
470 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
471 clocks = <&sysclk>;
472 clock-names = "ipg";
473 status = "disabled";
474 };
475
476 lpuart1: serial@2960000 {
477 compatible = "fsl,ls1021a-lpuart";
478 reg = <0x0 0x2960000 0x0 0x1000>;
479 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
480 clocks = <&clockgen 4 1>;
481 clock-names = "ipg";
482 status = "disabled";
483 };
484
485 lpuart2: serial@2970000 {
486 compatible = "fsl,ls1021a-lpuart";
487 reg = <0x0 0x2970000 0x0 0x1000>;
488 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
489 clocks = <&clockgen 4 1>;
490 clock-names = "ipg";
491 status = "disabled";
492 };
493
494 lpuart3: serial@2980000 {
495 compatible = "fsl,ls1021a-lpuart";
496 reg = <0x0 0x2980000 0x0 0x1000>;
497 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&clockgen 4 1>;
499 clock-names = "ipg";
500 status = "disabled";
501 };
502
503 lpuart4: serial@2990000 {
504 compatible = "fsl,ls1021a-lpuart";
505 reg = <0x0 0x2990000 0x0 0x1000>;
506 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
507 clocks = <&clockgen 4 1>;
508 clock-names = "ipg";
509 status = "disabled";
510 };
511
512 lpuart5: serial@29a0000 {
513 compatible = "fsl,ls1021a-lpuart";
514 reg = <0x0 0x29a0000 0x0 0x1000>;
515 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
516 clocks = <&clockgen 4 1>;
517 clock-names = "ipg";
518 status = "disabled";
519 };
520
521 wdog0: watchdog@2ad0000 {
522 compatible = "fsl,imx21-wdt";
523 reg = <0x0 0x2ad0000 0x0 0x10000>;
524 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&clockgen 4 1>;
526 clock-names = "wdog-en";
527 big-endian;
528 };
529
530 sai1: sai@2b50000 {
531 #sound-dai-cells = <0>;
532 compatible = "fsl,vf610-sai";
533 reg = <0x0 0x2b50000 0x0 0x10000>;
534 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
535 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
536 <&clockgen 4 1>, <&clockgen 4 1>;
537 clock-names = "bus", "mclk1", "mclk2", "mclk3";
538 dma-names = "tx", "rx";
539 dmas = <&edma0 1 47>,
540 <&edma0 1 46>;
541 status = "disabled";
542 };
543
544 sai2: sai@2b60000 {
545 #sound-dai-cells = <0>;
546 compatible = "fsl,vf610-sai";
547 reg = <0x0 0x2b60000 0x0 0x10000>;
548 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
549 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
550 <&clockgen 4 1>, <&clockgen 4 1>;
551 clock-names = "bus", "mclk1", "mclk2", "mclk3";
552 dma-names = "tx", "rx";
553 dmas = <&edma0 1 45>,
554 <&edma0 1 44>;
555 status = "disabled";
556 };
557
558 edma0: edma@2c00000 {
559 #dma-cells = <2>;
560 compatible = "fsl,vf610-edma";
561 reg = <0x0 0x2c00000 0x0 0x10000>,
562 <0x0 0x2c10000 0x0 0x10000>,
563 <0x0 0x2c20000 0x0 0x10000>;
564 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
566 interrupt-names = "edma-tx", "edma-err";
567 dma-channels = <32>;
568 big-endian;
569 clock-names = "dmamux0", "dmamux1";
570 clocks = <&clockgen 4 1>,
571 <&clockgen 4 1>;
572 };
573
574 dcu: dcu@2ce0000 {
575 compatible = "fsl,ls1021a-dcu";
576 reg = <0x0 0x2ce0000 0x0 0x10000>;
577 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
578 clocks = <&clockgen 4 0>,
579 <&clockgen 4 0>;
580 clock-names = "dcu", "pix";
581 big-endian;
582 status = "disabled";
583 };
584
585 mdio0: mdio@2d24000 {
586 compatible = "gianfar";
587 device_type = "mdio";
588 #address-cells = <1>;
589 #size-cells = <0>;
590 reg = <0x0 0x2d24000 0x0 0x4000>,
591 <0x0 0x2d10030 0x0 0x4>;
592 };
593
594 ptp_clock@2d10e00 {
595 compatible = "fsl,etsec-ptp";
596 reg = <0x0 0x2d10e00 0x0 0xb0>;
597 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
598 fsl,tclk-period = <5>;
599 fsl,tmr-prsc = <2>;
600 fsl,tmr-add = <0xaaaaaaab>;
601 fsl,tmr-fiper1 = <999999995>;
602 fsl,tmr-fiper2 = <99990>;
603 fsl,max-adj = <499999999>;
604 };
605
606 enet0: ethernet@2d10000 {
607 compatible = "fsl,etsec2";
608 device_type = "network";
609 #address-cells = <2>;
610 #size-cells = <2>;
611 interrupt-parent = <&gic>;
612 model = "eTSEC";
613 fsl,magic-packet;
614 ranges;
615 dma-coherent;
616
617 queue-group@2d10000 {
618 #address-cells = <2>;
619 #size-cells = <2>;
620 reg = <0x0 0x2d10000 0x0 0x1000>;
621 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
622 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
623 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
624 };
625
626 queue-group@2d14000 {
627 #address-cells = <2>;
628 #size-cells = <2>;
629 reg = <0x0 0x2d14000 0x0 0x1000>;
630 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
631 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
632 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
633 };
634 };
635
636 enet1: ethernet@2d50000 {
637 compatible = "fsl,etsec2";
638 device_type = "network";
639 #address-cells = <2>;
640 #size-cells = <2>;
641 interrupt-parent = <&gic>;
642 model = "eTSEC";
643 ranges;
644 dma-coherent;
645
646 queue-group@2d50000 {
647 #address-cells = <2>;
648 #size-cells = <2>;
649 reg = <0x0 0x2d50000 0x0 0x1000>;
650 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
651 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
652 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
653 };
654
655 queue-group@2d54000 {
656 #address-cells = <2>;
657 #size-cells = <2>;
658 reg = <0x0 0x2d54000 0x0 0x1000>;
659 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
660 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
661 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
662 };
663 };
664
665 enet2: ethernet@2d90000 {
666 compatible = "fsl,etsec2";
667 device_type = "network";
668 #address-cells = <2>;
669 #size-cells = <2>;
670 interrupt-parent = <&gic>;
671 model = "eTSEC";
672 ranges;
673 dma-coherent;
674
675 queue-group@2d90000 {
676 #address-cells = <2>;
677 #size-cells = <2>;
678 reg = <0x0 0x2d90000 0x0 0x1000>;
679 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
680 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
681 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
682 };
683
684 queue-group@2d94000 {
685 #address-cells = <2>;
686 #size-cells = <2>;
687 reg = <0x0 0x2d94000 0x0 0x1000>;
688 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
689 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
690 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
691 };
692 };
693
694 usb2: usb@8600000 {
695 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
696 reg = <0x0 0x8600000 0x0 0x1000>;
697 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
698 dr_mode = "host";
699 phy_type = "ulpi";
700 };
701
702 usb3: usb3@3100000 {
703 compatible = "snps,dwc3";
704 reg = <0x0 0x3100000 0x0 0x10000>;
705 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
706 dr_mode = "host";
707 snps,quirk-frame-length-adjustment = <0x20>;
708 snps,dis_rxdet_inp3_quirk;
709 };
710
711 pcie@3400000 {
712 compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
713 reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
714 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
715 reg-names = "regs", "config";
716 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
717 fsl,pcie-scfg = <&scfg 0>;
718 #address-cells = <3>;
719 #size-cells = <2>;
720 device_type = "pci";
721 num-lanes = <4>;
722 bus-range = <0x0 0xff>;
723 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
724 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
725 msi-parent = <&msi1>, <&msi2>;
726 #interrupt-cells = <1>;
727 interrupt-map-mask = <0 0 0 7>;
728 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
729 <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
730 <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
731 <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
732 };
733
734 pcie@3500000 {
735 compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
736 reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */
737 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
738 reg-names = "regs", "config";
739 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
740 fsl,pcie-scfg = <&scfg 1>;
741 #address-cells = <3>;
742 #size-cells = <2>;
743 device_type = "pci";
744 num-lanes = <4>;
745 bus-range = <0x0 0xff>;
746 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
747 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
748 msi-parent = <&msi1>, <&msi2>;
749 #interrupt-cells = <1>;
750 interrupt-map-mask = <0 0 0 7>;
751 interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
752 <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
753 <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
754 <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
755 };
756
757 can0: can@2a70000 {
758 compatible = "fsl,ls1021ar2-flexcan";
759 reg = <0x0 0x2a70000 0x0 0x1000>;
760 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
761 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
762 clock-names = "ipg", "per";
763 big-endian;
764 };
765
766 can1: can@2a80000 {
767 compatible = "fsl,ls1021ar2-flexcan";
768 reg = <0x0 0x2a80000 0x0 0x1000>;
769 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
770 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
771 clock-names = "ipg", "per";
772 big-endian;
773 };
774
775 can2: can@2a90000 {
776 compatible = "fsl,ls1021ar2-flexcan";
777 reg = <0x0 0x2a90000 0x0 0x1000>;
778 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
779 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
780 clock-names = "ipg", "per";
781 big-endian;
782 };
783
784 can3: can@2aa0000 {
785 compatible = "fsl,ls1021ar2-flexcan";
786 reg = <0x0 0x2aa0000 0x0 0x1000>;
787 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
788 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
789 clock-names = "ipg", "per";
790 big-endian;
791 };
792
793 ocram1: sram@10000000 {
794 compatible = "mmio-sram";
795 reg = <0x0 0x10000000 0x0 0x10000>;
796 #address-cells = <1>;
797 #size-cells = <1>;
798 ranges = <0x0 0x0 0x10000000 0x10000>;
799 };
800
801 ocram2: sram@10010000 {
802 compatible = "mmio-sram";
803 reg = <0x0 0x10010000 0x0 0x10000>;
804 #address-cells = <1>;
805 #size-cells = <1>;
806 ranges = <0x0 0x0 0x10010000 0x10000>;
807 };
808 };
809};
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
4 */
5
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/thermal/thermal.h>
8
9/ {
10 #address-cells = <2>;
11 #size-cells = <2>;
12 interrupt-parent = <&gic>;
13
14 aliases {
15 crypto = &crypto;
16 ethernet0 = &enet0;
17 ethernet1 = &enet1;
18 ethernet2 = &enet2;
19 rtc1 = &ftm_alarm0;
20 serial0 = &lpuart0;
21 serial1 = &lpuart1;
22 serial2 = &lpuart2;
23 serial3 = &lpuart3;
24 serial4 = &lpuart4;
25 serial5 = &lpuart5;
26 sysclk = &sysclk;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 cpu0: cpu@f00 {
34 compatible = "arm,cortex-a7";
35 device_type = "cpu";
36 reg = <0xf00>;
37 clocks = <&clockgen 1 0>;
38 #cooling-cells = <2>;
39 };
40
41 cpu1: cpu@f01 {
42 compatible = "arm,cortex-a7";
43 device_type = "cpu";
44 reg = <0xf01>;
45 clocks = <&clockgen 1 0>;
46 #cooling-cells = <2>;
47 };
48 };
49
50 memory@0 {
51 device_type = "memory";
52 reg = <0x0 0x0 0x0 0x0>;
53 };
54
55 sysclk: sysclk {
56 compatible = "fixed-clock";
57 #clock-cells = <0>;
58 clock-frequency = <100000000>;
59 clock-output-names = "sysclk";
60 };
61
62 timer {
63 compatible = "arm,armv7-timer";
64 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
65 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
66 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
67 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
68 };
69
70 pmu {
71 compatible = "arm,cortex-a7-pmu";
72 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
73 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
74 interrupt-affinity = <&cpu0>, <&cpu1>;
75 };
76
77 reboot {
78 compatible = "syscon-reboot";
79 regmap = <&dcfg>;
80 offset = <0xb0>;
81 mask = <0x02>;
82 };
83
84 soc {
85 compatible = "simple-bus";
86 #address-cells = <2>;
87 #size-cells = <2>;
88 device_type = "soc";
89 interrupt-parent = <&gic>;
90 ranges;
91
92 ddr: memory-controller@1080000 {
93 compatible = "fsl,qoriq-memory-controller";
94 reg = <0x0 0x1080000 0x0 0x1000>;
95 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
96 big-endian;
97 };
98
99 gic: interrupt-controller@1400000 {
100 compatible = "arm,gic-400", "arm,cortex-a7-gic";
101 #interrupt-cells = <3>;
102 interrupt-controller;
103 reg = <0x0 0x1401000 0x0 0x1000>,
104 <0x0 0x1402000 0x0 0x2000>,
105 <0x0 0x1404000 0x0 0x2000>,
106 <0x0 0x1406000 0x0 0x2000>;
107 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
108
109 };
110
111 msi1: msi-controller@1570e00 {
112 compatible = "fsl,ls1021a-msi";
113 reg = <0x0 0x1570e00 0x0 0x8>;
114 msi-controller;
115 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
116 };
117
118 msi2: msi-controller@1570e08 {
119 compatible = "fsl,ls1021a-msi";
120 reg = <0x0 0x1570e08 0x0 0x8>;
121 msi-controller;
122 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
123 };
124
125 ifc: memory-controller@1530000 {
126 compatible = "fsl,ifc";
127 reg = <0x0 0x1530000 0x0 0x10000>;
128 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
129 status = "disabled";
130 };
131
132 sfp: efuse@1e80000 {
133 compatible = "fsl,ls1021a-sfp";
134 reg = <0x0 0x1e80000 0x0 0x10000>;
135 clocks = <&clockgen 4 3>;
136 clock-names = "sfp";
137 };
138
139 dcfg: dcfg@1ee0000 {
140 compatible = "fsl,ls1021a-dcfg", "syscon";
141 reg = <0x0 0x1ee0000 0x0 0x1000>;
142 big-endian;
143 };
144
145 qspi: spi@1550000 {
146 compatible = "fsl,ls1021a-qspi";
147 #address-cells = <1>;
148 #size-cells = <0>;
149 reg = <0x0 0x1550000 0x0 0x10000>,
150 <0x0 0x40000000 0x0 0x20000000>;
151 reg-names = "QuadSPI", "QuadSPI-memory";
152 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
153 clock-names = "qspi_en", "qspi";
154 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
155 status = "disabled";
156 };
157
158 esdhc: esdhc@1560000 {
159 compatible = "fsl,ls1021a-esdhc", "fsl,esdhc";
160 reg = <0x0 0x1560000 0x0 0x10000>;
161 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
162 clock-frequency = <0>;
163 voltage-ranges = <1800 1800 3300 3300>;
164 sdhci,auto-cmd12;
165 big-endian;
166 bus-width = <4>;
167 status = "disabled";
168 };
169
170 sata: sata@3200000 {
171 compatible = "fsl,ls1021a-ahci";
172 reg = <0x0 0x3200000 0x0 0x10000>,
173 <0x0 0x20220520 0x0 0x4>;
174 reg-names = "ahci", "sata-ecc";
175 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&clockgen 4 1>;
177 dma-coherent;
178 status = "disabled";
179 };
180
181 scfg: scfg@1570000 {
182 compatible = "fsl,ls1021a-scfg", "syscon";
183 reg = <0x0 0x1570000 0x0 0x10000>;
184 big-endian;
185 #address-cells = <1>;
186 #size-cells = <1>;
187 ranges = <0x0 0x0 0x1570000 0x10000>;
188
189 extirq: interrupt-controller@1ac {
190 compatible = "fsl,ls1021a-extirq";
191 #interrupt-cells = <2>;
192 #address-cells = <0>;
193 interrupt-controller;
194 reg = <0x1ac 4>;
195 interrupt-map =
196 <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
197 <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
198 <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
199 <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
200 <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
201 <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
202 interrupt-map-mask = <0x7 0x0>;
203 };
204 };
205
206 crypto: crypto@1700000 {
207 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
208 fsl,sec-era = <7>;
209 #address-cells = <1>;
210 #size-cells = <1>;
211 reg = <0x0 0x1700000 0x0 0x100000>;
212 ranges = <0x0 0x0 0x1700000 0x100000>;
213 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
214 dma-coherent;
215
216 sec_jr0: jr@10000 {
217 compatible = "fsl,sec-v5.0-job-ring",
218 "fsl,sec-v4.0-job-ring";
219 reg = <0x10000 0x10000>;
220 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
221 };
222
223 sec_jr1: jr@20000 {
224 compatible = "fsl,sec-v5.0-job-ring",
225 "fsl,sec-v4.0-job-ring";
226 reg = <0x20000 0x10000>;
227 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
228 };
229
230 sec_jr2: jr@30000 {
231 compatible = "fsl,sec-v5.0-job-ring",
232 "fsl,sec-v4.0-job-ring";
233 reg = <0x30000 0x10000>;
234 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
235 };
236
237 sec_jr3: jr@40000 {
238 compatible = "fsl,sec-v5.0-job-ring",
239 "fsl,sec-v4.0-job-ring";
240 reg = <0x40000 0x10000>;
241 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
242 };
243
244 };
245
246 clockgen: clocking@1ee1000 {
247 compatible = "fsl,ls1021a-clockgen";
248 reg = <0x0 0x1ee1000 0x0 0x1000>;
249 #clock-cells = <2>;
250 clocks = <&sysclk>;
251 };
252
253 tmu: tmu@1f00000 {
254 compatible = "fsl,qoriq-tmu";
255 reg = <0x0 0x1f00000 0x0 0x10000>;
256 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
257 fsl,tmu-range = <0xb0000 0x9002c 0x6004e 0x30066>;
258 fsl,tmu-calibration = <0x00000000 0x00000020>,
259 <0x00000001 0x00000024>,
260 <0x00000002 0x0000002a>,
261 <0x00000003 0x00000032>,
262 <0x00000004 0x00000038>,
263 <0x00000005 0x0000003e>,
264 <0x00000006 0x00000043>,
265 <0x00000007 0x0000004a>,
266 <0x00000008 0x00000050>,
267 <0x00000009 0x00000059>,
268 <0x0000000a 0x0000005f>,
269 <0x0000000b 0x00000066>,
270
271 <0x00010000 0x00000023>,
272 <0x00010001 0x0000002b>,
273 <0x00010002 0x00000033>,
274 <0x00010003 0x0000003a>,
275 <0x00010004 0x00000042>,
276 <0x00010005 0x0000004a>,
277 <0x00010006 0x00000054>,
278 <0x00010007 0x0000005c>,
279 <0x00010008 0x00000065>,
280 <0x00010009 0x0000006f>,
281
282 <0x00020000 0x00000029>,
283 <0x00020001 0x00000033>,
284 <0x00020002 0x0000003d>,
285 <0x00020003 0x00000048>,
286 <0x00020004 0x00000054>,
287 <0x00020005 0x00000060>,
288 <0x00020006 0x0000006c>,
289
290 <0x00030000 0x00000025>,
291 <0x00030001 0x00000033>,
292 <0x00030002 0x00000043>,
293 <0x00030003 0x00000055>;
294 #thermal-sensor-cells = <1>;
295 };
296
297 dspi0: spi@2100000 {
298 compatible = "fsl,ls1021a-v1.0-dspi";
299 #address-cells = <1>;
300 #size-cells = <0>;
301 reg = <0x0 0x2100000 0x0 0x10000>;
302 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
303 clock-names = "dspi";
304 clocks = <&clockgen 4 1>;
305 spi-num-chipselects = <6>;
306 big-endian;
307 status = "disabled";
308 };
309
310 dspi1: spi@2110000 {
311 compatible = "fsl,ls1021a-v1.0-dspi";
312 #address-cells = <1>;
313 #size-cells = <0>;
314 reg = <0x0 0x2110000 0x0 0x10000>;
315 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
316 clock-names = "dspi";
317 clocks = <&clockgen 4 1>;
318 spi-num-chipselects = <6>;
319 big-endian;
320 status = "disabled";
321 };
322
323 i2c0: i2c@2180000 {
324 compatible = "fsl,vf610-i2c";
325 #address-cells = <1>;
326 #size-cells = <0>;
327 reg = <0x0 0x2180000 0x0 0x10000>;
328 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
329 clocks = <&clockgen 4 1>;
330 dma-names = "rx", "tx";
331 dmas = <&edma0 1 38>, <&edma0 1 39>;
332 status = "disabled";
333 };
334
335 i2c1: i2c@2190000 {
336 compatible = "fsl,vf610-i2c";
337 #address-cells = <1>;
338 #size-cells = <0>;
339 reg = <0x0 0x2190000 0x0 0x10000>;
340 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&clockgen 4 1>;
342 dma-names = "rx", "tx";
343 dmas = <&edma0 1 36>, <&edma0 1 37>;
344 status = "disabled";
345 };
346
347 i2c2: i2c@21a0000 {
348 compatible = "fsl,vf610-i2c";
349 #address-cells = <1>;
350 #size-cells = <0>;
351 reg = <0x0 0x21a0000 0x0 0x10000>;
352 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&clockgen 4 1>;
354 dma-names = "rx", "tx";
355 dmas = <&edma0 1 34>, <&edma0 1 35>;
356 status = "disabled";
357 };
358
359 uart0: serial@21c0500 {
360 compatible = "fsl,16550-FIFO64", "ns16550a";
361 reg = <0x0 0x21c0500 0x0 0x100>;
362 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
363 clock-frequency = <0>;
364 fifo-size = <15>;
365 status = "disabled";
366 };
367
368 uart1: serial@21c0600 {
369 compatible = "fsl,16550-FIFO64", "ns16550a";
370 reg = <0x0 0x21c0600 0x0 0x100>;
371 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
372 clock-frequency = <0>;
373 fifo-size = <15>;
374 status = "disabled";
375 };
376
377 uart2: serial@21d0500 {
378 compatible = "fsl,16550-FIFO64", "ns16550a";
379 reg = <0x0 0x21d0500 0x0 0x100>;
380 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
381 clock-frequency = <0>;
382 fifo-size = <15>;
383 status = "disabled";
384 };
385
386 uart3: serial@21d0600 {
387 compatible = "fsl,16550-FIFO64", "ns16550a";
388 reg = <0x0 0x21d0600 0x0 0x100>;
389 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
390 clock-frequency = <0>;
391 fifo-size = <15>;
392 status = "disabled";
393 };
394
395 counter0: counter@29d0000 {
396 compatible = "fsl,ftm-quaddec";
397 reg = <0x0 0x29d0000 0x0 0x10000>;
398 big-endian;
399 status = "disabled";
400 };
401
402 counter1: counter@29e0000 {
403 compatible = "fsl,ftm-quaddec";
404 reg = <0x0 0x29e0000 0x0 0x10000>;
405 big-endian;
406 status = "disabled";
407 };
408
409 counter2: counter@29f0000 {
410 compatible = "fsl,ftm-quaddec";
411 reg = <0x0 0x29f0000 0x0 0x10000>;
412 big-endian;
413 status = "disabled";
414 };
415
416 counter3: counter@2a00000 {
417 compatible = "fsl,ftm-quaddec";
418 reg = <0x0 0x2a00000 0x0 0x10000>;
419 big-endian;
420 status = "disabled";
421 };
422
423 gpio0: gpio@2300000 {
424 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
425 reg = <0x0 0x2300000 0x0 0x10000>;
426 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
427 gpio-controller;
428 #gpio-cells = <2>;
429 interrupt-controller;
430 #interrupt-cells = <2>;
431 };
432
433 gpio1: gpio@2310000 {
434 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
435 reg = <0x0 0x2310000 0x0 0x10000>;
436 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
437 gpio-controller;
438 #gpio-cells = <2>;
439 interrupt-controller;
440 #interrupt-cells = <2>;
441 };
442
443 gpio2: gpio@2320000 {
444 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
445 reg = <0x0 0x2320000 0x0 0x10000>;
446 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
447 gpio-controller;
448 #gpio-cells = <2>;
449 interrupt-controller;
450 #interrupt-cells = <2>;
451 };
452
453 gpio3: gpio@2330000 {
454 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
455 reg = <0x0 0x2330000 0x0 0x10000>;
456 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
457 gpio-controller;
458 #gpio-cells = <2>;
459 interrupt-controller;
460 #interrupt-cells = <2>;
461 };
462
463 lpuart0: serial@2950000 {
464 compatible = "fsl,ls1021a-lpuart";
465 reg = <0x0 0x2950000 0x0 0x1000>;
466 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
467 clocks = <&sysclk>;
468 clock-names = "ipg";
469 status = "disabled";
470 };
471
472 lpuart1: serial@2960000 {
473 compatible = "fsl,ls1021a-lpuart";
474 reg = <0x0 0x2960000 0x0 0x1000>;
475 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
476 clocks = <&clockgen 4 1>;
477 clock-names = "ipg";
478 status = "disabled";
479 };
480
481 lpuart2: serial@2970000 {
482 compatible = "fsl,ls1021a-lpuart";
483 reg = <0x0 0x2970000 0x0 0x1000>;
484 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&clockgen 4 1>;
486 clock-names = "ipg";
487 status = "disabled";
488 };
489
490 lpuart3: serial@2980000 {
491 compatible = "fsl,ls1021a-lpuart";
492 reg = <0x0 0x2980000 0x0 0x1000>;
493 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&clockgen 4 1>;
495 clock-names = "ipg";
496 status = "disabled";
497 };
498
499 lpuart4: serial@2990000 {
500 compatible = "fsl,ls1021a-lpuart";
501 reg = <0x0 0x2990000 0x0 0x1000>;
502 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&clockgen 4 1>;
504 clock-names = "ipg";
505 status = "disabled";
506 };
507
508 lpuart5: serial@29a0000 {
509 compatible = "fsl,ls1021a-lpuart";
510 reg = <0x0 0x29a0000 0x0 0x1000>;
511 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&clockgen 4 1>;
513 clock-names = "ipg";
514 status = "disabled";
515 };
516
517 pwm0: pwm@29d0000 {
518 compatible = "fsl,vf610-ftm-pwm";
519 #pwm-cells = <3>;
520 reg = <0x0 0x29d0000 0x0 0x10000>;
521 clock-names = "ftm_sys", "ftm_ext",
522 "ftm_fix", "ftm_cnt_clk_en";
523 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
524 <&clockgen 4 1>, <&clockgen 4 1>;
525 big-endian;
526 status = "disabled";
527 };
528
529 pwm1: pwm@29e0000 {
530 compatible = "fsl,vf610-ftm-pwm";
531 #pwm-cells = <3>;
532 reg = <0x0 0x29e0000 0x0 0x10000>;
533 clock-names = "ftm_sys", "ftm_ext",
534 "ftm_fix", "ftm_cnt_clk_en";
535 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
536 <&clockgen 4 1>, <&clockgen 4 1>;
537 big-endian;
538 status = "disabled";
539 };
540
541 pwm2: pwm@29f0000 {
542 compatible = "fsl,vf610-ftm-pwm";
543 #pwm-cells = <3>;
544 reg = <0x0 0x29f0000 0x0 0x10000>;
545 clock-names = "ftm_sys", "ftm_ext",
546 "ftm_fix", "ftm_cnt_clk_en";
547 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
548 <&clockgen 4 1>, <&clockgen 4 1>;
549 big-endian;
550 status = "disabled";
551 };
552
553 pwm3: pwm@2a00000 {
554 compatible = "fsl,vf610-ftm-pwm";
555 #pwm-cells = <3>;
556 reg = <0x0 0x2a00000 0x0 0x10000>;
557 clock-names = "ftm_sys", "ftm_ext",
558 "ftm_fix", "ftm_cnt_clk_en";
559 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
560 <&clockgen 4 1>, <&clockgen 4 1>;
561 big-endian;
562 status = "disabled";
563 };
564
565 pwm4: pwm@2a10000 {
566 compatible = "fsl,vf610-ftm-pwm";
567 #pwm-cells = <3>;
568 reg = <0x0 0x2a10000 0x0 0x10000>;
569 clock-names = "ftm_sys", "ftm_ext",
570 "ftm_fix", "ftm_cnt_clk_en";
571 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
572 <&clockgen 4 1>, <&clockgen 4 1>;
573 big-endian;
574 status = "disabled";
575 };
576
577 pwm5: pwm@2a20000 {
578 compatible = "fsl,vf610-ftm-pwm";
579 #pwm-cells = <3>;
580 reg = <0x0 0x2a20000 0x0 0x10000>;
581 clock-names = "ftm_sys", "ftm_ext",
582 "ftm_fix", "ftm_cnt_clk_en";
583 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
584 <&clockgen 4 1>, <&clockgen 4 1>;
585 big-endian;
586 status = "disabled";
587 };
588
589 pwm6: pwm@2a30000 {
590 compatible = "fsl,vf610-ftm-pwm";
591 #pwm-cells = <3>;
592 reg = <0x0 0x2a30000 0x0 0x10000>;
593 clock-names = "ftm_sys", "ftm_ext",
594 "ftm_fix", "ftm_cnt_clk_en";
595 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
596 <&clockgen 4 1>, <&clockgen 4 1>;
597 big-endian;
598 status = "disabled";
599 };
600
601 pwm7: pwm@2a40000 {
602 compatible = "fsl,vf610-ftm-pwm";
603 #pwm-cells = <3>;
604 reg = <0x0 0x2a40000 0x0 0x10000>;
605 clock-names = "ftm_sys", "ftm_ext",
606 "ftm_fix", "ftm_cnt_clk_en";
607 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
608 <&clockgen 4 1>, <&clockgen 4 1>;
609 big-endian;
610 status = "disabled";
611 };
612
613 wdog0: watchdog@2ad0000 {
614 compatible = "fsl,imx21-wdt";
615 reg = <0x0 0x2ad0000 0x0 0x10000>;
616 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
617 clocks = <&clockgen 4 1>;
618 clock-names = "wdog-en";
619 big-endian;
620 };
621
622 sai1: sai@2b50000 {
623 #sound-dai-cells = <0>;
624 compatible = "fsl,vf610-sai";
625 reg = <0x0 0x2b50000 0x0 0x10000>;
626 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
627 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
628 <&clockgen 4 1>, <&clockgen 4 1>;
629 clock-names = "bus", "mclk1", "mclk2", "mclk3";
630 dma-names = "tx", "rx";
631 dmas = <&edma0 1 47>,
632 <&edma0 1 46>;
633 status = "disabled";
634 };
635
636 sai2: sai@2b60000 {
637 #sound-dai-cells = <0>;
638 compatible = "fsl,vf610-sai";
639 reg = <0x0 0x2b60000 0x0 0x10000>;
640 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
641 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
642 <&clockgen 4 1>, <&clockgen 4 1>;
643 clock-names = "bus", "mclk1", "mclk2", "mclk3";
644 dma-names = "tx", "rx";
645 dmas = <&edma0 1 45>,
646 <&edma0 1 44>;
647 status = "disabled";
648 };
649
650 edma0: dma-controller@2c00000 {
651 #dma-cells = <2>;
652 compatible = "fsl,vf610-edma";
653 reg = <0x0 0x2c00000 0x0 0x10000>,
654 <0x0 0x2c10000 0x0 0x10000>,
655 <0x0 0x2c20000 0x0 0x10000>;
656 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
657 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
658 interrupt-names = "edma-tx", "edma-err";
659 dma-channels = <32>;
660 big-endian;
661 clock-names = "dmamux0", "dmamux1";
662 clocks = <&clockgen 4 1>,
663 <&clockgen 4 1>;
664 };
665
666 dcu: dcu@2ce0000 {
667 compatible = "fsl,ls1021a-dcu";
668 reg = <0x0 0x2ce0000 0x0 0x10000>;
669 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
670 clocks = <&clockgen 4 0>,
671 <&clockgen 4 0>;
672 clock-names = "dcu", "pix";
673 big-endian;
674 status = "disabled";
675 };
676
677 mdio0: mdio@2d24000 {
678 compatible = "gianfar";
679 device_type = "mdio";
680 #address-cells = <1>;
681 #size-cells = <0>;
682 reg = <0x0 0x2d24000 0x0 0x4000>,
683 <0x0 0x2d10030 0x0 0x4>;
684 };
685
686 mdio1: mdio@2d64000 {
687 compatible = "gianfar";
688 device_type = "mdio";
689 #address-cells = <1>;
690 #size-cells = <0>;
691 reg = <0x0 0x2d64000 0x0 0x4000>,
692 <0x0 0x2d50030 0x0 0x4>;
693 };
694
695 ptp_clock@2d10e00 {
696 compatible = "fsl,etsec-ptp";
697 reg = <0x0 0x2d10e00 0x0 0xb0>;
698 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
699 fsl,tclk-period = <5>;
700 fsl,tmr-prsc = <2>;
701 fsl,tmr-add = <0xaaaaaaab>;
702 fsl,tmr-fiper1 = <999999995>;
703 fsl,tmr-fiper2 = <999999995>;
704 fsl,max-adj = <499999999>;
705 fsl,extts-fifo;
706 };
707
708 enet0: ethernet@2d10000 {
709 compatible = "fsl,etsec2";
710 device_type = "network";
711 #address-cells = <2>;
712 #size-cells = <2>;
713 interrupt-parent = <&gic>;
714 model = "eTSEC";
715 fsl,magic-packet;
716 ranges;
717 dma-coherent;
718
719 queue-group@2d10000 {
720 #address-cells = <2>;
721 #size-cells = <2>;
722 reg = <0x0 0x2d10000 0x0 0x1000>;
723 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
724 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
725 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
726 };
727
728 queue-group@2d14000 {
729 #address-cells = <2>;
730 #size-cells = <2>;
731 reg = <0x0 0x2d14000 0x0 0x1000>;
732 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
733 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
734 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
735 };
736 };
737
738 enet1: ethernet@2d50000 {
739 compatible = "fsl,etsec2";
740 device_type = "network";
741 #address-cells = <2>;
742 #size-cells = <2>;
743 interrupt-parent = <&gic>;
744 model = "eTSEC";
745 ranges;
746 dma-coherent;
747
748 queue-group@2d50000 {
749 #address-cells = <2>;
750 #size-cells = <2>;
751 reg = <0x0 0x2d50000 0x0 0x1000>;
752 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
753 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
754 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
755 };
756
757 queue-group@2d54000 {
758 #address-cells = <2>;
759 #size-cells = <2>;
760 reg = <0x0 0x2d54000 0x0 0x1000>;
761 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
762 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
763 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
764 };
765 };
766
767 enet2: ethernet@2d90000 {
768 compatible = "fsl,etsec2";
769 device_type = "network";
770 #address-cells = <2>;
771 #size-cells = <2>;
772 interrupt-parent = <&gic>;
773 model = "eTSEC";
774 ranges;
775 dma-coherent;
776
777 queue-group@2d90000 {
778 #address-cells = <2>;
779 #size-cells = <2>;
780 reg = <0x0 0x2d90000 0x0 0x1000>;
781 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
784 };
785
786 queue-group@2d94000 {
787 #address-cells = <2>;
788 #size-cells = <2>;
789 reg = <0x0 0x2d94000 0x0 0x1000>;
790 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
791 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
792 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
793 };
794 };
795
796 usb2: usb@8600000 {
797 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
798 reg = <0x0 0x8600000 0x0 0x1000>;
799 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
800 dr_mode = "host";
801 phy_type = "ulpi";
802 };
803
804 usb3: usb@3100000 {
805 compatible = "snps,dwc3";
806 reg = <0x0 0x3100000 0x0 0x10000>;
807 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
808 dr_mode = "host";
809 snps,quirk-frame-length-adjustment = <0x20>;
810 snps,dis_rxdet_inp3_quirk;
811 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
812 };
813
814 pcie@3400000 {
815 compatible = "fsl,ls1021a-pcie";
816 reg = <0x00 0x03400000 0x0 0x00010000>, /* controller registers */
817 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
818 reg-names = "regs", "config";
819 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
820 fsl,pcie-scfg = <&scfg 0>;
821 #address-cells = <3>;
822 #size-cells = <2>;
823 device_type = "pci";
824 num-viewport = <6>;
825 bus-range = <0x0 0xff>;
826 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000>, /* downstream I/O */
827 <0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
828 msi-parent = <&msi1>, <&msi2>;
829 #interrupt-cells = <1>;
830 interrupt-map-mask = <0 0 0 7>;
831 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
832 <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
833 <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
834 <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
835 status = "disabled";
836 };
837
838 pcie@3500000 {
839 compatible = "fsl,ls1021a-pcie";
840 reg = <0x00 0x03500000 0x0 0x00010000>, /* controller registers */
841 <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
842 reg-names = "regs", "config";
843 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
844 fsl,pcie-scfg = <&scfg 1>;
845 #address-cells = <3>;
846 #size-cells = <2>;
847 device_type = "pci";
848 num-viewport = <6>;
849 bus-range = <0x0 0xff>;
850 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000>, /* downstream I/O */
851 <0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
852 msi-parent = <&msi1>, <&msi2>;
853 #interrupt-cells = <1>;
854 interrupt-map-mask = <0 0 0 7>;
855 interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
856 <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
857 <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
858 <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
859 status = "disabled";
860 };
861
862 can0: can@2a70000 {
863 compatible = "fsl,ls1021ar2-flexcan";
864 reg = <0x0 0x2a70000 0x0 0x1000>;
865 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
866 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
867 clock-names = "ipg", "per";
868 big-endian;
869 };
870
871 can1: can@2a80000 {
872 compatible = "fsl,ls1021ar2-flexcan";
873 reg = <0x0 0x2a80000 0x0 0x1000>;
874 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
875 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
876 clock-names = "ipg", "per";
877 big-endian;
878 };
879
880 can2: can@2a90000 {
881 compatible = "fsl,ls1021ar2-flexcan";
882 reg = <0x0 0x2a90000 0x0 0x1000>;
883 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
884 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
885 clock-names = "ipg", "per";
886 big-endian;
887 };
888
889 can3: can@2aa0000 {
890 compatible = "fsl,ls1021ar2-flexcan";
891 reg = <0x0 0x2aa0000 0x0 0x1000>;
892 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
893 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
894 clock-names = "ipg", "per";
895 big-endian;
896 };
897
898 ocram1: sram@10000000 {
899 compatible = "mmio-sram";
900 reg = <0x0 0x10000000 0x0 0x10000>;
901 #address-cells = <1>;
902 #size-cells = <1>;
903 ranges = <0x0 0x0 0x10000000 0x10000>;
904 };
905
906 ocram2: sram@10010000 {
907 compatible = "mmio-sram";
908 reg = <0x0 0x10010000 0x0 0x10000>;
909 #address-cells = <1>;
910 #size-cells = <1>;
911 ranges = <0x0 0x0 0x10010000 0x10000>;
912 };
913
914 qdma: dma-controller@8390000 {
915 compatible = "fsl,ls1021a-qdma";
916 reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
917 <0x0 0x8389000 0x0 0x1000>, /* Status regs */
918 <0x0 0x838a000 0x0 0x2000>; /* Block regs */
919 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
920 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
921 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
922 interrupt-names = "qdma-error",
923 "qdma-queue0", "qdma-queue1";
924 #dma-cells = <2>;
925 dma-channels = <8>;
926 block-number = <1>;
927 block-offset = <0x1000>;
928 fsl,dma-queues = <2>;
929 status-sizes = <64>;
930 queue-sizes = <64 64>;
931 big-endian;
932 };
933
934 rcpm: power-controller@1ee2140 {
935 compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+";
936 reg = <0x0 0x1ee2140 0x0 0x8>;
937 #fsl,rcpm-wakeup-cells = <2>;
938 #power-domain-cells = <0>;
939 };
940
941 ftm_alarm0: timer0@29d0000 {
942 compatible = "fsl,ls1021a-ftm-alarm";
943 reg = <0x0 0x29d0000 0x0 0x10000>;
944 reg-names = "ftm";
945 fsl,rcpm-wakeup = <&rcpm 0x0 0x20000000>;
946 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
947 big-endian;
948 };
949 };
950
951 thermal-zones {
952 cpu_thermal: cpu-thermal {
953 polling-delay-passive = <1000>;
954 polling-delay = <5000>;
955
956 thermal-sensors = <&tmu 0>;
957
958 trips {
959 cpu_alert: cpu-alert {
960 temperature = <85000>;
961 hysteresis = <2000>;
962 type = "passive";
963 };
964 cpu_crit: cpu-crit {
965 temperature = <95000>;
966 hysteresis = <2000>;
967 type = "critical";
968 };
969 };
970
971 cooling-maps {
972 map0 {
973 trip = <&cpu_alert>;
974 cooling-device =
975 <&cpu0 THERMAL_NO_LIMIT
976 THERMAL_NO_LIMIT>,
977 <&cpu1 THERMAL_NO_LIMIT
978 THERMAL_NO_LIMIT>;
979 };
980 };
981 };
982 };
983};