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1/*
2 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l.
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43/dts-v1/;
44
45#include <dt-bindings/gpio/gpio.h>
46#include <dt-bindings/input/input.h>
47#include "imx6ul.dtsi"
48
49/ {
50 model = "Engicam GEAM6UL Starter Kit";
51 compatible = "engicam,imx6ul-geam", "fsl,imx6ul";
52
53 memory@80000000 {
54 reg = <0x80000000 0x08000000>;
55 };
56
57 backlight {
58 compatible = "pwm-backlight";
59 pwms = <&pwm8 0 100000>;
60 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
61 10 11 12 13 14 15 16 17 18 19
62 20 21 22 23 24 25 26 27 28 29
63 30 31 32 33 34 35 36 37 38 39
64 40 41 42 43 44 45 46 47 48 49
65 50 51 52 53 54 55 56 57 58 59
66 60 61 62 63 64 65 66 67 68 69
67 70 71 72 73 74 75 76 77 78 79
68 80 81 82 83 84 85 86 87 88 89
69 90 91 92 93 94 95 96 97 98 99
70 100>;
71 default-brightness-level = <100>;
72 };
73
74 chosen {
75 stdout-path = &uart1;
76 };
77
78 reg_1p8v: regulator-1p8v {
79 compatible = "regulator-fixed";
80 regulator-name = "1P8V";
81 regulator-min-microvolt = <1800000>;
82 regulator-max-microvolt = <1800000>;
83 regulator-always-on;
84 regulator-boot-on;
85 };
86
87 reg_3p3v: regulator-3p3v {
88 compatible = "regulator-fixed";
89 regulator-name = "3P3V";
90 regulator-min-microvolt = <3300000>;
91 regulator-max-microvolt = <3300000>;
92 regulator-always-on;
93 regulator-boot-on;
94 };
95
96 sound {
97 compatible = "simple-audio-card";
98 simple-audio-card,name = "imx6ul-geam-sgtl5000";
99 simple-audio-card,format = "i2s";
100 simple-audio-card,bitclock-master = <&dailink_master>;
101 simple-audio-card,frame-master = <&dailink_master>;
102 simple-audio-card,widgets =
103 "Microphone", "Mic Jack",
104 "Line", "Line In",
105 "Line", "Line Out",
106 "Headphone", "Headphone Jack";
107 simple-audio-card,routing =
108 "MIC_IN", "Mic Jack",
109 "Mic Jack", "Mic Bias",
110 "Headphone Jack", "HP_OUT";
111
112 simple-audio-card,cpu {
113 sound-dai = <&sai2>;
114 };
115
116 dailink_master: simple-audio-card,codec {
117 sound-dai = <&sgtl5000>;
118 clocks = <&clks IMX6UL_CLK_SAI2>;
119 };
120 };
121};
122
123&can1 {
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_flexcan1>;
126 xceiver-supply = <®_3p3v>;
127 status = "okay";
128};
129
130&can2 {
131 pinctrl-names = "default";
132 pinctrl-0 = <&pinctrl_flexcan2>;
133 xceiver-supply = <®_3p3v>;
134 status = "okay";
135};
136
137&fec1 {
138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_enet1>;
140 phy-mode = "rmii";
141 phy-handle = <ðphy0>;
142 status = "okay";
143};
144
145&fec2 {
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_enet2>;
148 phy-mode = "rmii";
149 phy-handle = <ðphy1>;
150 status = "okay";
151
152 mdio {
153 #address-cells = <1>;
154 #size-cells = <0>;
155
156 ethphy0: ethernet-phy@0 {
157 compatible = "ethernet-phy-ieee802.3-c22";
158 reg = <0>;
159 };
160
161 ethphy1: ethernet-phy@1 {
162 compatible = "ethernet-phy-ieee802.3-c22";
163 reg = <1>;
164 };
165 };
166};
167
168&gpmi {
169 pinctrl-names = "default";
170 pinctrl-0 = <&pinctrl_gpmi_nand>;
171 nand-on-flash-bbt;
172 status = "okay";
173};
174
175&i2c1 {
176 clock-frequency = <100000>;
177 pinctrl-names = "default";
178 pinctrl-0 = <&pinctrl_i2c1>;
179 status = "okay";
180
181 sgtl5000: codec@a {
182 compatible = "fsl,sgtl5000";
183 reg = <0x0a>;
184 #sound-dai-cells = <0>;
185 clocks = <&clks IMX6UL_CLK_OSC>;
186 clock-names = "mclk";
187 VDDA-supply = <®_3p3v>;
188 VDDIO-supply = <®_3p3v>;
189 VDDD-supply = <®_1p8v>;
190 };
191};
192
193&i2c2 {
194 clock_frequency = <100000>;
195 pinctrl-names = "default";
196 pinctrl-0 = <&pinctrl_i2c2>;
197 status = "okay";
198};
199
200&lcdif {
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_lcdif_dat
203 &pinctrl_lcdif_ctrl>;
204 display = <&display0>;
205 status = "okay";
206
207 display0: display {
208 bits-per-pixel = <16>;
209 bus-width = <18>;
210
211 display-timings {
212 native-mode = <&timing0>;
213 timing0: timing0 {
214 clock-frequency = <28000000>;
215 hactive = <800>;
216 vactive = <480>;
217 hfront-porch = <30>;
218 hback-porch = <30>;
219 hsync-len = <64>;
220 vback-porch = <5>;
221 vfront-porch = <5>;
222 vsync-len = <20>;
223 hsync-active = <0>;
224 vsync-active = <0>;
225 de-active = <1>;
226 pixelclk-active = <0>;
227 };
228 };
229 };
230};
231
232&pwm8 {
233 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_pwm8>;
235 status = "okay";
236};
237
238&tsc {
239 pinctrl-names = "default";
240 pinctrl-0 = <&pinctrl_tsc>;
241 xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
242};
243
244&sai2 {
245 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_sai2>;
247 status = "okay";
248};
249
250&tsc {
251 measure-delay-time = <0x1ffff>;
252 pre-charge-time = <0x1fff>;
253 status = "okay";
254};
255
256&uart1 {
257 pinctrl-names = "default";
258 pinctrl-0 = <&pinctrl_uart1>;
259 status = "okay";
260};
261
262&uart2 {
263 pinctrl-names = "default";
264 pinctrl-0 = <&pinctrl_uart2>;
265 status = "okay";
266};
267
268&usbotg1 {
269 dr_mode = "peripheral";
270 status = "okay";
271};
272
273&usbotg2 {
274 dr_mode = "host";
275 status = "okay";
276};
277
278&usdhc1 {
279 pinctrl-names = "default", "state_100mhz", "state_200mhz";
280 pinctrl-0 = <&pinctrl_usdhc1>;
281 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
282 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
283 bus-width = <4>;
284 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
285 no-1-8-v;
286 status = "okay";
287};
288
289&iomuxc {
290 pinctrl_enet1: enet1grp {
291 fsl,pins = <
292 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
293 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
294 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
295 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
296 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
297 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
298 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
299 >;
300 };
301
302 pinctrl_enet2: enet2grp {
303 fsl,pins = <
304 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
305 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
306 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
307 MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* ENET_nRST */
308 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
309 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
310 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
311 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
312 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
313 MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 0x4001b031
314 >;
315 };
316
317 pinctrl_flexcan1: flexcan1grp {
318 fsl,pins = <
319 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
320 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
321 >;
322 };
323
324 pinctrl_flexcan2: flexcan2grp {
325 fsl,pins = <
326 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
327 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
328 >;
329 };
330
331 pinctrl_gpmi_nand: gpmi-nand {
332 fsl,pins = <
333 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
334 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
335 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
336 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
337 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
338 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
339 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
340 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
341 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
342 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
343 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
344 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
345 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
346 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
347 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
348 >;
349 };
350
351 pinctrl_i2c1: i2c1grp {
352 fsl,pins = <
353 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
354 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
355 >;
356 };
357
358 pinctrl_i2c2: i2c2grp {
359 fsl,pins = <
360 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
361 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
362 >;
363 };
364
365 pinctrl_lcdif_ctrl: lcdifctrlgrp {
366 fsl,pins = <
367 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
368 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
369 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
370 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
371 >;
372 };
373
374 pinctrl_lcdif_dat: lcdifdatgrp {
375 fsl,pins = <
376 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
377 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
378 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
379 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
380 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
381 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
382 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
383 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
384 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
385 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
386 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
387 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
388 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
389 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
390 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
391 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
392 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
393 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
394 >;
395 };
396
397 pinctrl_pwm8: pwm8grp {
398 fsl,pins = <
399 MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0
400 >;
401 };
402
403 pinctrl_tsc: tscgrp {
404 fsl,pin = <
405 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
406 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
407 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
408 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
409 >;
410 };
411
412 pinctrl_sai2: sai2grp {
413 fsl,pins = <
414 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0
415 MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x4001b031
416 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
417 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
418 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0
419 >;
420 };
421
422 pinctrl_uart1: uart1grp {
423 fsl,pins = <
424 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
425 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
426 >;
427 };
428
429 pinctrl_uart2: uart2grp {
430 fsl,pins = <
431 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
432 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
433 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
434 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
435 >;
436 };
437
438 pinctrl_usdhc1: usdhc1grp {
439 fsl,pins = <
440 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
441 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
442 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
443 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
444 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
445 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
446 >;
447 };
448
449 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
450 fsl,pins = <
451 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
452 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
453 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
454 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
455 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
456 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
457 >;
458 };
459
460 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
461 fsl,pins = <
462 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
463 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
464 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
465 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
466 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
467 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
468 >;
469 };
470
471 pinctrl_usdhc2: usdhc2grp {
472 fsl,pins = <
473 MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17070
474 MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x10070
475 MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17070
476 MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17070
477 MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17070
478 MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17070
479 >;
480 };
481};
1// SPDX-License-Identifier: GPL-2.0 OR X11
2/*
3 * Copyright (C) 2016 Amarula Solutions B.V.
4 * Copyright (C) 2016 Engicam S.r.l.
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/input/input.h>
11#include "imx6ul.dtsi"
12
13/ {
14 model = "Engicam GEAM6UL Starter Kit";
15 compatible = "engicam,imx6ul-geam", "fsl,imx6ul";
16
17 memory@80000000 {
18 device_type = "memory";
19 reg = <0x80000000 0x08000000>;
20 };
21
22 backlight {
23 compatible = "pwm-backlight";
24 pwms = <&pwm8 0 100000>;
25 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
26 10 11 12 13 14 15 16 17 18 19
27 20 21 22 23 24 25 26 27 28 29
28 30 31 32 33 34 35 36 37 38 39
29 40 41 42 43 44 45 46 47 48 49
30 50 51 52 53 54 55 56 57 58 59
31 60 61 62 63 64 65 66 67 68 69
32 70 71 72 73 74 75 76 77 78 79
33 80 81 82 83 84 85 86 87 88 89
34 90 91 92 93 94 95 96 97 98 99
35 100>;
36 default-brightness-level = <100>;
37 };
38
39 chosen {
40 stdout-path = &uart1;
41 };
42
43 reg_1p8v: regulator-1p8v {
44 compatible = "regulator-fixed";
45 regulator-name = "1P8V";
46 regulator-min-microvolt = <1800000>;
47 regulator-max-microvolt = <1800000>;
48 regulator-always-on;
49 regulator-boot-on;
50 };
51
52 reg_3p3v: regulator-3p3v {
53 compatible = "regulator-fixed";
54 regulator-name = "3P3V";
55 regulator-min-microvolt = <3300000>;
56 regulator-max-microvolt = <3300000>;
57 regulator-always-on;
58 regulator-boot-on;
59 };
60
61 sound {
62 compatible = "simple-audio-card";
63 simple-audio-card,name = "imx6ul-geam-sgtl5000";
64 simple-audio-card,format = "i2s";
65 simple-audio-card,bitclock-master = <&dailink_master>;
66 simple-audio-card,frame-master = <&dailink_master>;
67 simple-audio-card,widgets =
68 "Microphone", "Mic Jack",
69 "Line", "Line In",
70 "Line", "Line Out",
71 "Headphone", "Headphone Jack";
72 simple-audio-card,routing =
73 "MIC_IN", "Mic Jack",
74 "Mic Jack", "Mic Bias",
75 "Headphone Jack", "HP_OUT";
76
77 simple-audio-card,cpu {
78 sound-dai = <&sai2>;
79 };
80
81 dailink_master: simple-audio-card,codec {
82 sound-dai = <&sgtl5000>;
83 clocks = <&clks IMX6UL_CLK_SAI2>;
84 };
85 };
86};
87
88&can1 {
89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_flexcan1>;
91 xceiver-supply = <®_3p3v>;
92 status = "okay";
93};
94
95&can2 {
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_flexcan2>;
98 xceiver-supply = <®_3p3v>;
99 status = "okay";
100};
101
102&fec1 {
103 pinctrl-names = "default";
104 pinctrl-0 = <&pinctrl_enet1>;
105 phy-mode = "rmii";
106 phy-handle = <ðphy0>;
107 status = "okay";
108};
109
110&fec2 {
111 pinctrl-names = "default";
112 pinctrl-0 = <&pinctrl_enet2>;
113 phy-mode = "rmii";
114 phy-handle = <ðphy1>;
115 status = "okay";
116
117 mdio {
118 #address-cells = <1>;
119 #size-cells = <0>;
120
121 ethphy0: ethernet-phy@0 {
122 compatible = "ethernet-phy-ieee802.3-c22";
123 reg = <0>;
124 };
125
126 ethphy1: ethernet-phy@1 {
127 compatible = "ethernet-phy-ieee802.3-c22";
128 reg = <1>;
129 };
130 };
131};
132
133&gpmi {
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_gpmi_nand>;
136 nand-on-flash-bbt;
137 status = "okay";
138};
139
140&i2c1 {
141 clock-frequency = <100000>;
142 pinctrl-names = "default";
143 pinctrl-0 = <&pinctrl_i2c1>;
144 status = "okay";
145
146 sgtl5000: codec@a {
147 compatible = "fsl,sgtl5000";
148 reg = <0x0a>;
149 #sound-dai-cells = <0>;
150 clocks = <&clks IMX6UL_CLK_OSC>;
151 clock-names = "mclk";
152 VDDA-supply = <®_3p3v>;
153 VDDIO-supply = <®_3p3v>;
154 VDDD-supply = <®_1p8v>;
155 };
156};
157
158&i2c2 {
159 clock-frequency = <100000>;
160 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_i2c2>;
162 status = "okay";
163};
164
165&lcdif {
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_lcdif_dat
168 &pinctrl_lcdif_ctrl>;
169 display = <&display0>;
170 status = "okay";
171
172 display0: display0 {
173 bits-per-pixel = <16>;
174 bus-width = <18>;
175
176 display-timings {
177 native-mode = <&timing0>;
178 timing0: timing0 {
179 clock-frequency = <28000000>;
180 hactive = <800>;
181 vactive = <480>;
182 hfront-porch = <30>;
183 hback-porch = <30>;
184 hsync-len = <64>;
185 vback-porch = <5>;
186 vfront-porch = <5>;
187 vsync-len = <20>;
188 hsync-active = <0>;
189 vsync-active = <0>;
190 de-active = <1>;
191 pixelclk-active = <0>;
192 };
193 };
194 };
195};
196
197&pwm8 {
198 #pwm-cells = <2>;
199 pinctrl-names = "default";
200 pinctrl-0 = <&pinctrl_pwm8>;
201 status = "okay";
202};
203
204&tsc {
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_tsc>;
207 xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
208};
209
210&sai2 {
211 pinctrl-names = "default";
212 pinctrl-0 = <&pinctrl_sai2>;
213 status = "okay";
214};
215
216&tsc {
217 measure-delay-time = <0x1ffff>;
218 pre-charge-time = <0x1fff>;
219 status = "okay";
220};
221
222&uart1 {
223 pinctrl-names = "default";
224 pinctrl-0 = <&pinctrl_uart1>;
225 status = "okay";
226};
227
228&uart2 {
229 pinctrl-names = "default";
230 pinctrl-0 = <&pinctrl_uart2>;
231 status = "okay";
232};
233
234&usbotg1 {
235 dr_mode = "peripheral";
236 status = "okay";
237};
238
239&usbotg2 {
240 dr_mode = "host";
241 status = "okay";
242};
243
244&usdhc1 {
245 pinctrl-names = "default", "state_100mhz", "state_200mhz";
246 pinctrl-0 = <&pinctrl_usdhc1>;
247 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
248 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
249 bus-width = <4>;
250 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
251 no-1-8-v;
252 status = "okay";
253};
254
255&iomuxc {
256 pinctrl_enet1: enet1grp {
257 fsl,pins = <
258 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
259 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
260 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
261 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
262 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
263 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
264 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
265 >;
266 };
267
268 pinctrl_enet2: enet2grp {
269 fsl,pins = <
270 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
271 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
272 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
273 MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* ENET_nRST */
274 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
275 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
276 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
277 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
278 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
279 MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 0x4001b031
280 >;
281 };
282
283 pinctrl_flexcan1: flexcan1grp {
284 fsl,pins = <
285 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
286 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
287 >;
288 };
289
290 pinctrl_flexcan2: flexcan2grp {
291 fsl,pins = <
292 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
293 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
294 >;
295 };
296
297 pinctrl_gpmi_nand: gpminandgrp {
298 fsl,pins = <
299 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
300 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
301 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
302 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
303 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
304 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
305 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
306 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
307 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
308 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
309 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
310 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
311 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
312 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
313 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
314 >;
315 };
316
317 pinctrl_i2c1: i2c1grp {
318 fsl,pins = <
319 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
320 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
321 >;
322 };
323
324 pinctrl_i2c2: i2c2grp {
325 fsl,pins = <
326 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
327 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
328 >;
329 };
330
331 pinctrl_lcdif_ctrl: lcdifctrlgrp {
332 fsl,pins = <
333 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
334 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
335 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
336 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
337 >;
338 };
339
340 pinctrl_lcdif_dat: lcdifdatgrp {
341 fsl,pins = <
342 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
343 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
344 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
345 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
346 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
347 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
348 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
349 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
350 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
351 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
352 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
353 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
354 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
355 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
356 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
357 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
358 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
359 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
360 >;
361 };
362
363 pinctrl_pwm8: pwm8grp {
364 fsl,pins = <
365 MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0
366 >;
367 };
368
369 pinctrl_tsc: tscgrp {
370 fsl,pin = <
371 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
372 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
373 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
374 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
375 >;
376 };
377
378 pinctrl_sai2: sai2grp {
379 fsl,pins = <
380 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0
381 MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x4001b031
382 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
383 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
384 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0
385 >;
386 };
387
388 pinctrl_uart1: uart1grp {
389 fsl,pins = <
390 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
391 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
392 >;
393 };
394
395 pinctrl_uart2: uart2grp {
396 fsl,pins = <
397 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
398 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
399 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
400 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
401 >;
402 };
403
404 pinctrl_usdhc1: usdhc1grp {
405 fsl,pins = <
406 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
407 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
408 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
409 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
410 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
411 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
412 >;
413 };
414
415 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
416 fsl,pins = <
417 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
418 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
419 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
420 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
421 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
422 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
423 >;
424 };
425
426 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
427 fsl,pins = <
428 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
429 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
430 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
431 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
432 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
433 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
434 >;
435 };
436
437 pinctrl_usdhc2: usdhc2grp {
438 fsl,pins = <
439 MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17070
440 MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x10070
441 MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17070
442 MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17070
443 MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17070
444 MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17070
445 >;
446 };
447};