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1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
5 */
6
7&pllss {
8 /*
9 * See TRM "2.6.10 Connected outputso DPLLS" and
10 * "2.6.11 Connected Outputs of DPLLJ". Only clkout is
11 * connected except for hdmi and usb.
12 */
13 adpll_mpu_ck: adpll@40 {
14 #clock-cells = <1>;
15 compatible = "ti,dm814-adpll-s-clock";
16 reg = <0x40 0x40>;
17 clocks = <&devosc_ck &devosc_ck &devosc_ck>;
18 clock-names = "clkinp", "clkinpulow", "clkinphif";
19 clock-output-names = "481c5040.adpll.dcoclkldo",
20 "481c5040.adpll.clkout",
21 "481c5040.adpll.clkoutx2",
22 "481c5040.adpll.clkouthif";
23 };
24
25 adpll_dsp_ck: adpll@80 {
26 #clock-cells = <1>;
27 compatible = "ti,dm814-adpll-lj-clock";
28 reg = <0x80 0x30>;
29 clocks = <&devosc_ck &devosc_ck>;
30 clock-names = "clkinp", "clkinpulow";
31 clock-output-names = "481c5080.adpll.dcoclkldo",
32 "481c5080.adpll.clkout",
33 "481c5080.adpll.clkoutldo";
34 };
35
36 adpll_sgx_ck: adpll@b0 {
37 #clock-cells = <1>;
38 compatible = "ti,dm814-adpll-lj-clock";
39 reg = <0xb0 0x30>;
40 clocks = <&devosc_ck &devosc_ck>;
41 clock-names = "clkinp", "clkinpulow";
42 clock-output-names = "481c50b0.adpll.dcoclkldo",
43 "481c50b0.adpll.clkout",
44 "481c50b0.adpll.clkoutldo";
45 };
46
47 adpll_hdvic_ck: adpll@e0 {
48 #clock-cells = <1>;
49 compatible = "ti,dm814-adpll-lj-clock";
50 reg = <0xe0 0x30>;
51 clocks = <&devosc_ck &devosc_ck>;
52 clock-names = "clkinp", "clkinpulow";
53 clock-output-names = "481c50e0.adpll.dcoclkldo",
54 "481c50e0.adpll.clkout",
55 "481c50e0.adpll.clkoutldo";
56 };
57
58 adpll_l3_ck: adpll@110 {
59 #clock-cells = <1>;
60 compatible = "ti,dm814-adpll-lj-clock";
61 reg = <0x110 0x30>;
62 clocks = <&devosc_ck &devosc_ck>;
63 clock-names = "clkinp", "clkinpulow";
64 clock-output-names = "481c5110.adpll.dcoclkldo",
65 "481c5110.adpll.clkout",
66 "481c5110.adpll.clkoutldo";
67 };
68
69 adpll_isp_ck: adpll@140 {
70 #clock-cells = <1>;
71 compatible = "ti,dm814-adpll-lj-clock";
72 reg = <0x140 0x30>;
73 clocks = <&devosc_ck &devosc_ck>;
74 clock-names = "clkinp", "clkinpulow";
75 clock-output-names = "481c5140.adpll.dcoclkldo",
76 "481c5140.adpll.clkout",
77 "481c5140.adpll.clkoutldo";
78 };
79
80 adpll_dss_ck: adpll@170 {
81 #clock-cells = <1>;
82 compatible = "ti,dm814-adpll-lj-clock";
83 reg = <0x170 0x30>;
84 clocks = <&devosc_ck &devosc_ck>;
85 clock-names = "clkinp", "clkinpulow";
86 clock-output-names = "481c5170.adpll.dcoclkldo",
87 "481c5170.adpll.clkout",
88 "481c5170.adpll.clkoutldo";
89 };
90
91 adpll_video0_ck: adpll@1a0 {
92 #clock-cells = <1>;
93 compatible = "ti,dm814-adpll-lj-clock";
94 reg = <0x1a0 0x30>;
95 clocks = <&devosc_ck &devosc_ck>;
96 clock-names = "clkinp", "clkinpulow";
97 clock-output-names = "481c51a0.adpll.dcoclkldo",
98 "481c51a0.adpll.clkout",
99 "481c51a0.adpll.clkoutldo";
100 };
101
102 adpll_video1_ck: adpll@1d0 {
103 #clock-cells = <1>;
104 compatible = "ti,dm814-adpll-lj-clock";
105 reg = <0x1d0 0x30>;
106 clocks = <&devosc_ck &devosc_ck>;
107 clock-names = "clkinp", "clkinpulow";
108 clock-output-names = "481c51d0.adpll.dcoclkldo",
109 "481c51d0.adpll.clkout",
110 "481c51d0.adpll.clkoutldo";
111 };
112
113 adpll_hdmi_ck: adpll@200 {
114 #clock-cells = <1>;
115 compatible = "ti,dm814-adpll-lj-clock";
116 reg = <0x200 0x30>;
117 clocks = <&devosc_ck &devosc_ck>;
118 clock-names = "clkinp", "clkinpulow";
119 clock-output-names = "481c5200.adpll.dcoclkldo",
120 "481c5200.adpll.clkout",
121 "481c5200.adpll.clkoutldo";
122 };
123
124 adpll_audio_ck: adpll@230 {
125 #clock-cells = <1>;
126 compatible = "ti,dm814-adpll-lj-clock";
127 reg = <0x230 0x30>;
128 clocks = <&devosc_ck &devosc_ck>;
129 clock-names = "clkinp", "clkinpulow";
130 clock-output-names = "481c5230.adpll.dcoclkldo",
131 "481c5230.adpll.clkout",
132 "481c5230.adpll.clkoutldo";
133 };
134
135 adpll_usb_ck: adpll@260 {
136 #clock-cells = <1>;
137 compatible = "ti,dm814-adpll-lj-clock";
138 reg = <0x260 0x30>;
139 clocks = <&devosc_ck &devosc_ck>;
140 clock-names = "clkinp", "clkinpulow";
141 clock-output-names = "481c5260.adpll.dcoclkldo",
142 "481c5260.adpll.clkout",
143 "481c5260.adpll.clkoutldo";
144 };
145
146 adpll_ddr_ck: adpll@290 {
147 #clock-cells = <1>;
148 compatible = "ti,dm814-adpll-lj-clock";
149 reg = <0x290 0x30>;
150 clocks = <&devosc_ck &devosc_ck>;
151 clock-names = "clkinp", "clkinpulow";
152 clock-output-names = "481c5290.adpll.dcoclkldo",
153 "481c5290.adpll.clkout",
154 "481c5290.adpll.clkoutldo";
155 };
156};
157
158&pllss_clocks {
159 timer1_fck: timer1_fck@2e0 {
160 #clock-cells = <0>;
161 compatible = "ti,mux-clock";
162 clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
163 &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
164 ti,bit-shift = <3>;
165 reg = <0x2e0>;
166 };
167
168 timer2_fck: timer2_fck@2e0 {
169 #clock-cells = <0>;
170 compatible = "ti,mux-clock";
171 clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
172 &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
173 ti,bit-shift = <6>;
174 reg = <0x2e0>;
175 };
176
177 /* CPTS_RFT_CLK in RMII_REFCLK_SRC, usually sourced from auiod */
178 cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
179 #clock-cells = <0>;
180 compatible = "ti,mux-clock";
181 clocks = <&adpll_video0_ck 1
182 &adpll_video1_ck 1
183 &adpll_audio_ck 1>;
184 ti,bit-shift = <1>;
185 reg = <0x2e8>;
186 };
187
188 /* REVISIT: Set up with a proper mux using RMII_REFCLK_SRC */
189 cpsw_125mhz_gclk: cpsw_125mhz_gclk {
190 #clock-cells = <0>;
191 compatible = "fixed-clock";
192 clock-frequency = <125000000>;
193 };
194
195 sysclk18_ck: sysclk18_ck@2f0 {
196 #clock-cells = <0>;
197 compatible = "ti,mux-clock";
198 clocks = <&rtcosc_ck>, <&rtcdivider_ck>;
199 ti,bit-shift = <0>;
200 reg = <0x02f0>;
201 };
202};
203
204&scm_clocks {
205 devosc_ck: devosc_ck@40 {
206 #clock-cells = <0>;
207 compatible = "ti,mux-clock";
208 clocks = <&virt_20000000_ck>, <&virt_19200000_ck>;
209 ti,bit-shift = <21>;
210 reg = <0x0040>;
211 };
212
213 /* Optional auxosc, 20 - 30 MHz range, assume 22.5729 MHz by default */
214 auxosc_ck: auxosc_ck {
215 #clock-cells = <0>;
216 compatible = "fixed-clock";
217 clock-frequency = <22572900>;
218 };
219
220 /* Optional 32768Hz crystal or clock on RTCOSC pins */
221 rtcosc_ck: rtcosc_ck {
222 #clock-cells = <0>;
223 compatible = "fixed-clock";
224 clock-frequency = <32768>;
225 };
226
227 /* Optional external clock on TCLKIN pin, set rate in baord dts file */
228 tclkin_ck: tclkin_ck {
229 #clock-cells = <0>;
230 compatible = "fixed-clock";
231 clock-frequency = <0>;
232 };
233
234 virt_20000000_ck: virt_20000000_ck {
235 #clock-cells = <0>;
236 compatible = "fixed-clock";
237 clock-frequency = <20000000>;
238 };
239
240 virt_19200000_ck: virt_19200000_ck {
241 #clock-cells = <0>;
242 compatible = "fixed-clock";
243 clock-frequency = <19200000>;
244 };
245
246 mpu_ck: mpu_ck {
247 #clock-cells = <0>;
248 compatible = "fixed-clock";
249 clock-frequency = <1000000000>;
250 };
251};
252
253&prcm_clocks {
254 osc_src_ck: osc_src_ck {
255 #clock-cells = <0>;
256 compatible = "fixed-factor-clock";
257 clocks = <&devosc_ck>;
258 clock-mult = <1>;
259 clock-div = <1>;
260 };
261
262 mpu_clksrc_ck: mpu_clksrc_ck@40 {
263 #clock-cells = <0>;
264 compatible = "ti,mux-clock";
265 clocks = <&devosc_ck>, <&rtcdivider_ck>;
266 ti,bit-shift = <0>;
267 reg = <0x0040>;
268 };
269
270 /* Fixed divider clock 0.0016384 * devosc */
271 rtcdivider_ck: rtcdivider_ck {
272 #clock-cells = <0>;
273 compatible = "fixed-factor-clock";
274 clocks = <&devosc_ck>;
275 clock-mult = <128>;
276 clock-div = <78125>;
277 };
278
279 /* L4_HS 220 MHz*/
280 sysclk4_ck: sysclk4_ck {
281 #clock-cells = <0>;
282 compatible = "ti,fixed-factor-clock";
283 clocks = <&adpll_l3_ck 1>;
284 ti,clock-mult = <1>;
285 ti,clock-div = <1>;
286 };
287
288 /* L4_FWCFG */
289 sysclk5_ck: sysclk5_ck {
290 #clock-cells = <0>;
291 compatible = "ti,fixed-factor-clock";
292 clocks = <&adpll_l3_ck 1>;
293 ti,clock-mult = <1>;
294 ti,clock-div = <2>;
295 };
296
297 /* L4_LS 110 MHz */
298 sysclk6_ck: sysclk6_ck {
299 #clock-cells = <0>;
300 compatible = "ti,fixed-factor-clock";
301 clocks = <&adpll_l3_ck 1>;
302 ti,clock-mult = <1>;
303 ti,clock-div = <2>;
304 };
305
306 sysclk8_ck: sysclk8_ck {
307 #clock-cells = <0>;
308 compatible = "ti,fixed-factor-clock";
309 clocks = <&adpll_usb_ck 1>;
310 ti,clock-mult = <1>;
311 ti,clock-div = <1>;
312 };
313
314 sysclk10_ck: sysclk10_ck {
315 compatible = "ti,divider-clock";
316 reg = <0x324>;
317 ti,max-div = <7>;
318 #clock-cells = <0>;
319 clocks = <&adpll_usb_ck 1>;
320 };
321
322 aud_clkin0_ck: aud_clkin0_ck {
323 #clock-cells = <0>;
324 compatible = "fixed-clock";
325 clock-frequency = <20000000>;
326 };
327
328 aud_clkin1_ck: aud_clkin1_ck {
329 #clock-cells = <0>;
330 compatible = "fixed-clock";
331 clock-frequency = <20000000>;
332 };
333
334 aud_clkin2_ck: aud_clkin2_ck {
335 #clock-cells = <0>;
336 compatible = "fixed-clock";
337 clock-frequency = <20000000>;
338 };
339};
340
341&prcm {
342 default_cm: default_cm@500 {
343 compatible = "ti,omap4-cm";
344 reg = <0x500 0x100>;
345 #address-cells = <1>;
346 #size-cells = <1>;
347 ranges = <0 0x500 0x100>;
348
349 default_clkctrl: clk@0 {
350 compatible = "ti,clkctrl";
351 reg = <0x0 0x5c>;
352 #clock-cells = <2>;
353 };
354 };
355
356 alwon_cm: alwon_cm@1400 {
357 compatible = "ti,omap4-cm";
358 reg = <0x1400 0x300>;
359 #address-cells = <1>;
360 #size-cells = <1>;
361 ranges = <0 0x1400 0x300>;
362
363 alwon_clkctrl: clk@0 {
364 compatible = "ti,clkctrl";
365 reg = <0x0 0x228>;
366 #clock-cells = <2>;
367 };
368 };
369};
1// SPDX-License-Identifier: GPL-2.0-only
2
3&pllss {
4 /*
5 * See TRM "2.6.10 Connected outputso DPLLS" and
6 * "2.6.11 Connected Outputs of DPLLJ". Only clkout is
7 * connected except for hdmi and usb.
8 */
9 adpll_mpu_ck: adpll@40 {
10 #clock-cells = <1>;
11 compatible = "ti,dm814-adpll-s-clock";
12 reg = <0x40 0x40>;
13 clocks = <&devosc_ck &devosc_ck &devosc_ck>;
14 clock-names = "clkinp", "clkinpulow", "clkinphif";
15 clock-output-names = "481c5040.adpll.dcoclkldo",
16 "481c5040.adpll.clkout",
17 "481c5040.adpll.clkoutx2",
18 "481c5040.adpll.clkouthif";
19 };
20
21 adpll_dsp_ck: adpll@80 {
22 #clock-cells = <1>;
23 compatible = "ti,dm814-adpll-lj-clock";
24 reg = <0x80 0x30>;
25 clocks = <&devosc_ck &devosc_ck>;
26 clock-names = "clkinp", "clkinpulow";
27 clock-output-names = "481c5080.adpll.dcoclkldo",
28 "481c5080.adpll.clkout",
29 "481c5080.adpll.clkoutldo";
30 };
31
32 adpll_sgx_ck: adpll@b0 {
33 #clock-cells = <1>;
34 compatible = "ti,dm814-adpll-lj-clock";
35 reg = <0xb0 0x30>;
36 clocks = <&devosc_ck &devosc_ck>;
37 clock-names = "clkinp", "clkinpulow";
38 clock-output-names = "481c50b0.adpll.dcoclkldo",
39 "481c50b0.adpll.clkout",
40 "481c50b0.adpll.clkoutldo";
41 };
42
43 adpll_hdvic_ck: adpll@e0 {
44 #clock-cells = <1>;
45 compatible = "ti,dm814-adpll-lj-clock";
46 reg = <0xe0 0x30>;
47 clocks = <&devosc_ck &devosc_ck>;
48 clock-names = "clkinp", "clkinpulow";
49 clock-output-names = "481c50e0.adpll.dcoclkldo",
50 "481c50e0.adpll.clkout",
51 "481c50e0.adpll.clkoutldo";
52 };
53
54 adpll_l3_ck: adpll@110 {
55 #clock-cells = <1>;
56 compatible = "ti,dm814-adpll-lj-clock";
57 reg = <0x110 0x30>;
58 clocks = <&devosc_ck &devosc_ck>;
59 clock-names = "clkinp", "clkinpulow";
60 clock-output-names = "481c5110.adpll.dcoclkldo",
61 "481c5110.adpll.clkout",
62 "481c5110.adpll.clkoutldo";
63 };
64
65 adpll_isp_ck: adpll@140 {
66 #clock-cells = <1>;
67 compatible = "ti,dm814-adpll-lj-clock";
68 reg = <0x140 0x30>;
69 clocks = <&devosc_ck &devosc_ck>;
70 clock-names = "clkinp", "clkinpulow";
71 clock-output-names = "481c5140.adpll.dcoclkldo",
72 "481c5140.adpll.clkout",
73 "481c5140.adpll.clkoutldo";
74 };
75
76 adpll_dss_ck: adpll@170 {
77 #clock-cells = <1>;
78 compatible = "ti,dm814-adpll-lj-clock";
79 reg = <0x170 0x30>;
80 clocks = <&devosc_ck &devosc_ck>;
81 clock-names = "clkinp", "clkinpulow";
82 clock-output-names = "481c5170.adpll.dcoclkldo",
83 "481c5170.adpll.clkout",
84 "481c5170.adpll.clkoutldo";
85 };
86
87 adpll_video0_ck: adpll@1a0 {
88 #clock-cells = <1>;
89 compatible = "ti,dm814-adpll-lj-clock";
90 reg = <0x1a0 0x30>;
91 clocks = <&devosc_ck &devosc_ck>;
92 clock-names = "clkinp", "clkinpulow";
93 clock-output-names = "481c51a0.adpll.dcoclkldo",
94 "481c51a0.adpll.clkout",
95 "481c51a0.adpll.clkoutldo";
96 };
97
98 adpll_video1_ck: adpll@1d0 {
99 #clock-cells = <1>;
100 compatible = "ti,dm814-adpll-lj-clock";
101 reg = <0x1d0 0x30>;
102 clocks = <&devosc_ck &devosc_ck>;
103 clock-names = "clkinp", "clkinpulow";
104 clock-output-names = "481c51d0.adpll.dcoclkldo",
105 "481c51d0.adpll.clkout",
106 "481c51d0.adpll.clkoutldo";
107 };
108
109 adpll_hdmi_ck: adpll@200 {
110 #clock-cells = <1>;
111 compatible = "ti,dm814-adpll-lj-clock";
112 reg = <0x200 0x30>;
113 clocks = <&devosc_ck &devosc_ck>;
114 clock-names = "clkinp", "clkinpulow";
115 clock-output-names = "481c5200.adpll.dcoclkldo",
116 "481c5200.adpll.clkout",
117 "481c5200.adpll.clkoutldo";
118 };
119
120 adpll_audio_ck: adpll@230 {
121 #clock-cells = <1>;
122 compatible = "ti,dm814-adpll-lj-clock";
123 reg = <0x230 0x30>;
124 clocks = <&devosc_ck &devosc_ck>;
125 clock-names = "clkinp", "clkinpulow";
126 clock-output-names = "481c5230.adpll.dcoclkldo",
127 "481c5230.adpll.clkout",
128 "481c5230.adpll.clkoutldo";
129 };
130
131 adpll_usb_ck: adpll@260 {
132 #clock-cells = <1>;
133 compatible = "ti,dm814-adpll-lj-clock";
134 reg = <0x260 0x30>;
135 clocks = <&devosc_ck &devosc_ck>;
136 clock-names = "clkinp", "clkinpulow";
137 clock-output-names = "481c5260.adpll.dcoclkldo",
138 "481c5260.adpll.clkout",
139 "481c5260.adpll.clkoutldo";
140 };
141
142 adpll_ddr_ck: adpll@290 {
143 #clock-cells = <1>;
144 compatible = "ti,dm814-adpll-lj-clock";
145 reg = <0x290 0x30>;
146 clocks = <&devosc_ck &devosc_ck>;
147 clock-names = "clkinp", "clkinpulow";
148 clock-output-names = "481c5290.adpll.dcoclkldo",
149 "481c5290.adpll.clkout",
150 "481c5290.adpll.clkoutldo";
151 };
152};
153
154&pllss_clocks {
155 timer1_fck: timer1_fck@2e0 {
156 #clock-cells = <0>;
157 compatible = "ti,mux-clock";
158 clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
159 &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
160 ti,bit-shift = <3>;
161 reg = <0x2e0>;
162 };
163
164 timer2_fck: timer2_fck@2e0 {
165 #clock-cells = <0>;
166 compatible = "ti,mux-clock";
167 clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
168 &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
169 ti,bit-shift = <6>;
170 reg = <0x2e0>;
171 };
172
173 /* CPTS_RFT_CLK in RMII_REFCLK_SRC, usually sourced from auiod */
174 cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
175 #clock-cells = <0>;
176 compatible = "ti,mux-clock";
177 clocks = <&adpll_video0_ck 1
178 &adpll_video1_ck 1
179 &adpll_audio_ck 1>;
180 ti,bit-shift = <1>;
181 reg = <0x2e8>;
182 };
183
184 /* REVISIT: Set up with a proper mux using RMII_REFCLK_SRC */
185 cpsw_125mhz_gclk: cpsw_125mhz_gclk {
186 #clock-cells = <0>;
187 compatible = "fixed-clock";
188 clock-frequency = <125000000>;
189 };
190
191 sysclk18_ck: sysclk18_ck@2f0 {
192 #clock-cells = <0>;
193 compatible = "ti,mux-clock";
194 clocks = <&rtcosc_ck>, <&rtcdivider_ck>;
195 ti,bit-shift = <0>;
196 reg = <0x02f0>;
197 };
198};
199
200&scm_clocks {
201 devosc_ck: devosc_ck@40 {
202 #clock-cells = <0>;
203 compatible = "ti,mux-clock";
204 clocks = <&virt_20000000_ck>, <&virt_19200000_ck>;
205 ti,bit-shift = <21>;
206 reg = <0x0040>;
207 };
208
209 /* Optional auxosc, 20 - 30 MHz range, assume 22.5729 MHz by default */
210 auxosc_ck: auxosc_ck {
211 #clock-cells = <0>;
212 compatible = "fixed-clock";
213 clock-frequency = <22572900>;
214 };
215
216 /* Optional 32768Hz crystal or clock on RTCOSC pins */
217 rtcosc_ck: rtcosc_ck {
218 #clock-cells = <0>;
219 compatible = "fixed-clock";
220 clock-frequency = <32768>;
221 };
222
223 /* Optional external clock on TCLKIN pin, set rate in baord dts file */
224 tclkin_ck: tclkin_ck {
225 #clock-cells = <0>;
226 compatible = "fixed-clock";
227 clock-frequency = <0>;
228 };
229
230 virt_20000000_ck: virt_20000000_ck {
231 #clock-cells = <0>;
232 compatible = "fixed-clock";
233 clock-frequency = <20000000>;
234 };
235
236 virt_19200000_ck: virt_19200000_ck {
237 #clock-cells = <0>;
238 compatible = "fixed-clock";
239 clock-frequency = <19200000>;
240 };
241
242 mpu_ck: mpu_ck {
243 #clock-cells = <0>;
244 compatible = "fixed-clock";
245 clock-frequency = <1000000000>;
246 };
247};
248
249&prcm_clocks {
250 osc_src_ck: osc_src_ck {
251 #clock-cells = <0>;
252 compatible = "fixed-factor-clock";
253 clocks = <&devosc_ck>;
254 clock-mult = <1>;
255 clock-div = <1>;
256 };
257
258 mpu_clksrc_ck: mpu_clksrc_ck@40 {
259 #clock-cells = <0>;
260 compatible = "ti,mux-clock";
261 clocks = <&devosc_ck>, <&rtcdivider_ck>;
262 ti,bit-shift = <0>;
263 reg = <0x0040>;
264 };
265
266 /* Fixed divider clock 0.0016384 * devosc */
267 rtcdivider_ck: rtcdivider_ck {
268 #clock-cells = <0>;
269 compatible = "fixed-factor-clock";
270 clocks = <&devosc_ck>;
271 clock-mult = <128>;
272 clock-div = <78125>;
273 };
274
275 /* L4_HS 220 MHz*/
276 sysclk4_ck: sysclk4_ck {
277 #clock-cells = <0>;
278 compatible = "ti,fixed-factor-clock";
279 clocks = <&adpll_l3_ck 1>;
280 ti,clock-mult = <1>;
281 ti,clock-div = <1>;
282 };
283
284 /* L4_FWCFG */
285 sysclk5_ck: sysclk5_ck {
286 #clock-cells = <0>;
287 compatible = "ti,fixed-factor-clock";
288 clocks = <&adpll_l3_ck 1>;
289 ti,clock-mult = <1>;
290 ti,clock-div = <2>;
291 };
292
293 /* L4_LS 110 MHz */
294 sysclk6_ck: sysclk6_ck {
295 #clock-cells = <0>;
296 compatible = "ti,fixed-factor-clock";
297 clocks = <&adpll_l3_ck 1>;
298 ti,clock-mult = <1>;
299 ti,clock-div = <2>;
300 };
301
302 sysclk8_ck: sysclk8_ck {
303 #clock-cells = <0>;
304 compatible = "ti,fixed-factor-clock";
305 clocks = <&adpll_usb_ck 1>;
306 ti,clock-mult = <1>;
307 ti,clock-div = <1>;
308 };
309
310 sysclk10_ck: sysclk10_ck {
311 compatible = "ti,divider-clock";
312 reg = <0x324>;
313 ti,max-div = <7>;
314 #clock-cells = <0>;
315 clocks = <&adpll_usb_ck 1>;
316 };
317
318 aud_clkin0_ck: aud_clkin0_ck {
319 #clock-cells = <0>;
320 compatible = "fixed-clock";
321 clock-frequency = <20000000>;
322 };
323
324 aud_clkin1_ck: aud_clkin1_ck {
325 #clock-cells = <0>;
326 compatible = "fixed-clock";
327 clock-frequency = <20000000>;
328 };
329
330 aud_clkin2_ck: aud_clkin2_ck {
331 #clock-cells = <0>;
332 compatible = "fixed-clock";
333 clock-frequency = <20000000>;
334 };
335};
336
337&prcm {
338 default_cm: default_cm@500 {
339 compatible = "ti,omap4-cm";
340 reg = <0x500 0x100>;
341 #address-cells = <1>;
342 #size-cells = <1>;
343 ranges = <0 0x500 0x100>;
344
345 default_clkctrl: clk@0 {
346 compatible = "ti,clkctrl";
347 reg = <0x0 0x5c>;
348 #clock-cells = <2>;
349 };
350 };
351
352 alwon_cm: alwon_cm@1400 {
353 compatible = "ti,omap4-cm";
354 reg = <0x1400 0x300>;
355 #address-cells = <1>;
356 #size-cells = <1>;
357 ranges = <0 0x1400 0x300>;
358
359 alwon_clkctrl: clk@0 {
360 compatible = "ti,clkctrl";
361 reg = <0x0 0x228>;
362 #clock-cells = <2>;
363 };
364 };
365
366 alwon_ethernet_cm: alwon_ethernet_cm@15d4 {
367 compatible = "ti,omap4-cm";
368 reg = <0x15d4 0x4>;
369 #address-cells = <1>;
370 #size-cells = <1>;
371 ranges = <0 0x15d4 0x4>;
372
373 alwon_ethernet_clkctrl: clk@0 {
374 compatible = "ti,clkctrl";
375 reg = <0 0x4>;
376 #clock-cells = <2>;
377 };
378 };
379};