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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * xHCI host controller driver PCI Bus Glue.
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 */
10
11#include <linux/pci.h>
12#include <linux/slab.h>
13#include <linux/module.h>
14#include <linux/acpi.h>
15
16#include "xhci.h"
17#include "xhci-trace.h"
18
19#define SSIC_PORT_NUM 2
20#define SSIC_PORT_CFG2 0x880c
21#define SSIC_PORT_CFG2_OFFSET 0x30
22#define PROG_DONE (1 << 30)
23#define SSIC_PORT_UNUSED (1 << 31)
24
25/* Device for a quirk */
26#define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
27#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
28#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009
29#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
30
31#define PCI_VENDOR_ID_ETRON 0x1b6f
32#define PCI_DEVICE_ID_EJ168 0x7023
33
34#define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
35#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
36#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1
37#define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
38#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
39#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
40#define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8
41#define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8
42#define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
43#define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0
44
45#define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9
46#define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba
47#define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb
48#define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc
49#define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142
50
51static const char hcd_name[] = "xhci_hcd";
52
53static struct hc_driver __read_mostly xhci_pci_hc_driver;
54
55static int xhci_pci_setup(struct usb_hcd *hcd);
56
57static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
58 .reset = xhci_pci_setup,
59};
60
61/* called after powerup, by probe or system-pm "wakeup" */
62static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
63{
64 /*
65 * TODO: Implement finding debug ports later.
66 * TODO: see if there are any quirks that need to be added to handle
67 * new extended capabilities.
68 */
69
70 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
71 if (!pci_set_mwi(pdev))
72 xhci_dbg(xhci, "MWI active\n");
73
74 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
75 return 0;
76}
77
78static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
79{
80 struct pci_dev *pdev = to_pci_dev(dev);
81
82 /* Look for vendor-specific quirks */
83 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
84 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
85 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
86 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
87 pdev->revision == 0x0) {
88 xhci->quirks |= XHCI_RESET_EP_QUIRK;
89 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
90 "QUIRK: Fresco Logic xHC needs configure"
91 " endpoint cmd after reset endpoint");
92 }
93 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
94 pdev->revision == 0x4) {
95 xhci->quirks |= XHCI_SLOW_SUSPEND;
96 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
97 "QUIRK: Fresco Logic xHC revision %u"
98 "must be suspended extra slowly",
99 pdev->revision);
100 }
101 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
102 xhci->quirks |= XHCI_BROKEN_STREAMS;
103 /* Fresco Logic confirms: all revisions of this chip do not
104 * support MSI, even though some of them claim to in their PCI
105 * capabilities.
106 */
107 xhci->quirks |= XHCI_BROKEN_MSI;
108 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
109 "QUIRK: Fresco Logic revision %u "
110 "has broken MSI implementation",
111 pdev->revision);
112 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
113 }
114
115 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
116 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
117 xhci->quirks |= XHCI_BROKEN_STREAMS;
118
119 if (pdev->vendor == PCI_VENDOR_ID_NEC)
120 xhci->quirks |= XHCI_NEC_HOST;
121
122 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
123 xhci->quirks |= XHCI_AMD_0x96_HOST;
124
125 /* AMD PLL quirk */
126 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
127 xhci->quirks |= XHCI_AMD_PLL_FIX;
128
129 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
130 (pdev->device == 0x15e0 ||
131 pdev->device == 0x15e1 ||
132 pdev->device == 0x43bb))
133 xhci->quirks |= XHCI_SUSPEND_DELAY;
134
135 if (pdev->vendor == PCI_VENDOR_ID_AMD)
136 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
137
138 if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
139 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
140 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
141 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
142 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
143 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
144
145 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
146 xhci->quirks |= XHCI_LPM_SUPPORT;
147 xhci->quirks |= XHCI_INTEL_HOST;
148 xhci->quirks |= XHCI_AVOID_BEI;
149 }
150 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
151 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
152 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
153 xhci->limit_active_eps = 64;
154 xhci->quirks |= XHCI_SW_BW_CHECKING;
155 /*
156 * PPT desktop boards DH77EB and DH77DF will power back on after
157 * a few seconds of being shutdown. The fix for this is to
158 * switch the ports from xHCI to EHCI on shutdown. We can't use
159 * DMI information to find those particular boards (since each
160 * vendor will change the board name), so we have to key off all
161 * PPT chipsets.
162 */
163 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
164 }
165 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
166 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
167 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
168 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
169 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
170 }
171 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
172 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
173 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
174 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
175 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
176 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
177 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
178 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) {
179 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
180 }
181 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
182 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
183 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
184 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
185 }
186 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
187 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
188 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
189 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
190 xhci->quirks |= XHCI_MISSING_CAS;
191
192 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
193 pdev->device == PCI_DEVICE_ID_EJ168) {
194 xhci->quirks |= XHCI_RESET_ON_RESUME;
195 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
196 xhci->quirks |= XHCI_BROKEN_STREAMS;
197 }
198 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
199 pdev->device == 0x0014)
200 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
201 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
202 pdev->device == 0x0015)
203 xhci->quirks |= XHCI_RESET_ON_RESUME;
204 if (pdev->vendor == PCI_VENDOR_ID_VIA)
205 xhci->quirks |= XHCI_RESET_ON_RESUME;
206
207 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
208 if (pdev->vendor == PCI_VENDOR_ID_VIA &&
209 pdev->device == 0x3432)
210 xhci->quirks |= XHCI_BROKEN_STREAMS;
211
212 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
213 pdev->device == 0x1042)
214 xhci->quirks |= XHCI_BROKEN_STREAMS;
215 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
216 pdev->device == 0x1142)
217 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
218
219 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
220 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
221 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
222
223 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
224 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
225
226 if (xhci->quirks & XHCI_RESET_ON_RESUME)
227 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
228 "QUIRK: Resetting on resume");
229}
230
231#ifdef CONFIG_ACPI
232static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
233{
234 static const guid_t intel_dsm_guid =
235 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
236 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
237 union acpi_object *obj;
238
239 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
240 NULL);
241 ACPI_FREE(obj);
242}
243#else
244static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
245#endif /* CONFIG_ACPI */
246
247/* called during probe() after chip reset completes */
248static int xhci_pci_setup(struct usb_hcd *hcd)
249{
250 struct xhci_hcd *xhci;
251 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
252 int retval;
253
254 xhci = hcd_to_xhci(hcd);
255 if (!xhci->sbrn)
256 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
257
258 /* imod_interval is the interrupt moderation value in nanoseconds. */
259 xhci->imod_interval = 40000;
260
261 retval = xhci_gen_setup(hcd, xhci_pci_quirks);
262 if (retval)
263 return retval;
264
265 if (!usb_hcd_is_primary_hcd(hcd))
266 return 0;
267
268 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
269
270 /* Find any debug ports */
271 return xhci_pci_reinit(xhci, pdev);
272}
273
274/*
275 * We need to register our own PCI probe function (instead of the USB core's
276 * function) in order to create a second roothub under xHCI.
277 */
278static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
279{
280 int retval;
281 struct xhci_hcd *xhci;
282 struct hc_driver *driver;
283 struct usb_hcd *hcd;
284
285 driver = (struct hc_driver *)id->driver_data;
286
287 /* For some HW implementation, a XHCI reset is just not enough... */
288 if (usb_xhci_needs_pci_reset(dev)) {
289 dev_info(&dev->dev, "Resetting\n");
290 if (pci_reset_function_locked(dev))
291 dev_warn(&dev->dev, "Reset failed");
292 }
293
294 /* Prevent runtime suspending between USB-2 and USB-3 initialization */
295 pm_runtime_get_noresume(&dev->dev);
296
297 /* Register the USB 2.0 roothub.
298 * FIXME: USB core must know to register the USB 2.0 roothub first.
299 * This is sort of silly, because we could just set the HCD driver flags
300 * to say USB 2.0, but I'm not sure what the implications would be in
301 * the other parts of the HCD code.
302 */
303 retval = usb_hcd_pci_probe(dev, id);
304
305 if (retval)
306 goto put_runtime_pm;
307
308 /* USB 2.0 roothub is stored in the PCI device now. */
309 hcd = dev_get_drvdata(&dev->dev);
310 xhci = hcd_to_xhci(hcd);
311 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
312 pci_name(dev), hcd);
313 if (!xhci->shared_hcd) {
314 retval = -ENOMEM;
315 goto dealloc_usb2_hcd;
316 }
317
318 retval = xhci_ext_cap_init(xhci);
319 if (retval)
320 goto put_usb3_hcd;
321
322 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
323 IRQF_SHARED);
324 if (retval)
325 goto put_usb3_hcd;
326 /* Roothub already marked as USB 3.0 speed */
327
328 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
329 HCC_MAX_PSA(xhci->hcc_params) >= 4)
330 xhci->shared_hcd->can_do_streams = 1;
331
332 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
333 xhci_pme_acpi_rtd3_enable(dev);
334
335 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
336 pm_runtime_put_noidle(&dev->dev);
337
338 return 0;
339
340put_usb3_hcd:
341 usb_put_hcd(xhci->shared_hcd);
342dealloc_usb2_hcd:
343 usb_hcd_pci_remove(dev);
344put_runtime_pm:
345 pm_runtime_put_noidle(&dev->dev);
346 return retval;
347}
348
349static void xhci_pci_remove(struct pci_dev *dev)
350{
351 struct xhci_hcd *xhci;
352
353 xhci = hcd_to_xhci(pci_get_drvdata(dev));
354 xhci->xhc_state |= XHCI_STATE_REMOVING;
355 if (xhci->shared_hcd) {
356 usb_remove_hcd(xhci->shared_hcd);
357 usb_put_hcd(xhci->shared_hcd);
358 }
359
360 /* Workaround for spurious wakeups at shutdown with HSW */
361 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
362 pci_set_power_state(dev, PCI_D3hot);
363
364 usb_hcd_pci_remove(dev);
365}
366
367#ifdef CONFIG_PM
368/*
369 * In some Intel xHCI controllers, in order to get D3 working,
370 * through a vendor specific SSIC CONFIG register at offset 0x883c,
371 * SSIC PORT need to be marked as "unused" before putting xHCI
372 * into D3. After D3 exit, the SSIC port need to be marked as "used".
373 * Without this change, xHCI might not enter D3 state.
374 */
375static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
376{
377 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
378 u32 val;
379 void __iomem *reg;
380 int i;
381
382 for (i = 0; i < SSIC_PORT_NUM; i++) {
383 reg = (void __iomem *) xhci->cap_regs +
384 SSIC_PORT_CFG2 +
385 i * SSIC_PORT_CFG2_OFFSET;
386
387 /* Notify SSIC that SSIC profile programming is not done. */
388 val = readl(reg) & ~PROG_DONE;
389 writel(val, reg);
390
391 /* Mark SSIC port as unused(suspend) or used(resume) */
392 val = readl(reg);
393 if (suspend)
394 val |= SSIC_PORT_UNUSED;
395 else
396 val &= ~SSIC_PORT_UNUSED;
397 writel(val, reg);
398
399 /* Notify SSIC that SSIC profile programming is done */
400 val = readl(reg) | PROG_DONE;
401 writel(val, reg);
402 readl(reg);
403 }
404}
405
406/*
407 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
408 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
409 */
410static void xhci_pme_quirk(struct usb_hcd *hcd)
411{
412 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
413 void __iomem *reg;
414 u32 val;
415
416 reg = (void __iomem *) xhci->cap_regs + 0x80a4;
417 val = readl(reg);
418 writel(val | BIT(28), reg);
419 readl(reg);
420}
421
422static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
423{
424 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
425 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
426 int ret;
427
428 /*
429 * Systems with the TI redriver that loses port status change events
430 * need to have the registers polled during D3, so avoid D3cold.
431 */
432 if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
433 pci_d3cold_disable(pdev);
434
435 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
436 xhci_pme_quirk(hcd);
437
438 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
439 xhci_ssic_port_unused_quirk(hcd, true);
440
441 ret = xhci_suspend(xhci, do_wakeup);
442 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
443 xhci_ssic_port_unused_quirk(hcd, false);
444
445 return ret;
446}
447
448static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
449{
450 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
451 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
452 int retval = 0;
453
454 /* The BIOS on systems with the Intel Panther Point chipset may or may
455 * not support xHCI natively. That means that during system resume, it
456 * may switch the ports back to EHCI so that users can use their
457 * keyboard to select a kernel from GRUB after resume from hibernate.
458 *
459 * The BIOS is supposed to remember whether the OS had xHCI ports
460 * enabled before resume, and switch the ports back to xHCI when the
461 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
462 * writers.
463 *
464 * Unconditionally switch the ports back to xHCI after a system resume.
465 * It should not matter whether the EHCI or xHCI controller is
466 * resumed first. It's enough to do the switchover in xHCI because
467 * USB core won't notice anything as the hub driver doesn't start
468 * running again until after all the devices (including both EHCI and
469 * xHCI host controllers) have been resumed.
470 */
471
472 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
473 usb_enable_intel_xhci_ports(pdev);
474
475 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
476 xhci_ssic_port_unused_quirk(hcd, false);
477
478 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
479 xhci_pme_quirk(hcd);
480
481 retval = xhci_resume(xhci, hibernated);
482 return retval;
483}
484#endif /* CONFIG_PM */
485
486/*-------------------------------------------------------------------------*/
487
488/* PCI driver selection metadata; PCI hotplugging uses this */
489static const struct pci_device_id pci_ids[] = { {
490 /* handle any USB 3.0 xHCI controller */
491 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
492 .driver_data = (unsigned long) &xhci_pci_hc_driver,
493 },
494 { /* end: all zeroes */ }
495};
496MODULE_DEVICE_TABLE(pci, pci_ids);
497
498/* pci driver glue; this is a "new style" PCI driver module */
499static struct pci_driver xhci_pci_driver = {
500 .name = (char *) hcd_name,
501 .id_table = pci_ids,
502
503 .probe = xhci_pci_probe,
504 .remove = xhci_pci_remove,
505 /* suspend and resume implemented later */
506
507 .shutdown = usb_hcd_pci_shutdown,
508#ifdef CONFIG_PM
509 .driver = {
510 .pm = &usb_hcd_pci_pm_ops
511 },
512#endif
513};
514
515static int __init xhci_pci_init(void)
516{
517 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
518#ifdef CONFIG_PM
519 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
520 xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
521#endif
522 return pci_register_driver(&xhci_pci_driver);
523}
524module_init(xhci_pci_init);
525
526static void __exit xhci_pci_exit(void)
527{
528 pci_unregister_driver(&xhci_pci_driver);
529}
530module_exit(xhci_pci_exit);
531
532MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
533MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * xHCI host controller driver PCI Bus Glue.
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 */
10
11#include <linux/pci.h>
12#include <linux/slab.h>
13#include <linux/module.h>
14#include <linux/acpi.h>
15#include <linux/reset.h>
16
17#include "xhci.h"
18#include "xhci-trace.h"
19#include "xhci-pci.h"
20
21#define SSIC_PORT_NUM 2
22#define SSIC_PORT_CFG2 0x880c
23#define SSIC_PORT_CFG2_OFFSET 0x30
24#define PROG_DONE (1 << 30)
25#define SSIC_PORT_UNUSED (1 << 31)
26#define SPARSE_DISABLE_BIT 17
27#define SPARSE_CNTL_ENABLE 0xC12C
28
29/* Device for a quirk */
30#define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
31#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
32#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009
33#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 0x1100
34#define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
35
36#define PCI_VENDOR_ID_ETRON 0x1b6f
37#define PCI_DEVICE_ID_EJ168 0x7023
38
39#define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
40#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
41#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1
42#define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
43#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
44#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
45#define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8
46#define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8
47#define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
48#define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0
49#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5
50#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6
51#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1
52#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db
53#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4
54#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9
55#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec
56#define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0
57#define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13
58#define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af
59#define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13
60#define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138
61#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI 0x51ed
62#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI 0x54ed
63
64#define PCI_DEVICE_ID_AMD_RENOIR_XHCI 0x1639
65#define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9
66#define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba
67#define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb
68#define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc
69
70#define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042
71#define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142
72#define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242
73#define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142
74#define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242
75
76static const char hcd_name[] = "xhci_hcd";
77
78static struct hc_driver __read_mostly xhci_pci_hc_driver;
79
80static int xhci_pci_setup(struct usb_hcd *hcd);
81static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
82 struct usb_tt *tt, gfp_t mem_flags);
83
84static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
85 .reset = xhci_pci_setup,
86 .update_hub_device = xhci_pci_update_hub_device,
87};
88
89/* called after powerup, by probe or system-pm "wakeup" */
90static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
91{
92 /*
93 * TODO: Implement finding debug ports later.
94 * TODO: see if there are any quirks that need to be added to handle
95 * new extended capabilities.
96 */
97
98 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
99 if (!pci_set_mwi(pdev))
100 xhci_dbg(xhci, "MWI active\n");
101
102 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
103 return 0;
104}
105
106static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
107{
108 struct pci_dev *pdev = to_pci_dev(dev);
109 struct xhci_driver_data *driver_data;
110 const struct pci_device_id *id;
111
112 id = pci_match_id(to_pci_driver(pdev->dev.driver)->id_table, pdev);
113
114 if (id && id->driver_data) {
115 driver_data = (struct xhci_driver_data *)id->driver_data;
116 xhci->quirks |= driver_data->quirks;
117 }
118
119 /* Look for vendor-specific quirks */
120 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
121 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
122 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
123 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
124 pdev->revision == 0x0) {
125 xhci->quirks |= XHCI_RESET_EP_QUIRK;
126 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
127 "XHCI_RESET_EP_QUIRK for this evaluation HW is deprecated");
128 }
129 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
130 pdev->revision == 0x4) {
131 xhci->quirks |= XHCI_SLOW_SUSPEND;
132 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
133 "QUIRK: Fresco Logic xHC revision %u"
134 "must be suspended extra slowly",
135 pdev->revision);
136 }
137 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
138 xhci->quirks |= XHCI_BROKEN_STREAMS;
139 /* Fresco Logic confirms: all revisions of this chip do not
140 * support MSI, even though some of them claim to in their PCI
141 * capabilities.
142 */
143 xhci->quirks |= XHCI_BROKEN_MSI;
144 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
145 "QUIRK: Fresco Logic revision %u "
146 "has broken MSI implementation",
147 pdev->revision);
148 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
149 }
150
151 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
152 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
153 xhci->quirks |= XHCI_BROKEN_STREAMS;
154
155 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
156 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1100)
157 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
158
159 if (pdev->vendor == PCI_VENDOR_ID_NEC)
160 xhci->quirks |= XHCI_NEC_HOST;
161
162 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
163 xhci->quirks |= XHCI_AMD_0x96_HOST;
164
165 /* AMD PLL quirk */
166 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check())
167 xhci->quirks |= XHCI_AMD_PLL_FIX;
168
169 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
170 (pdev->device == 0x145c ||
171 pdev->device == 0x15e0 ||
172 pdev->device == 0x15e1 ||
173 pdev->device == 0x43bb))
174 xhci->quirks |= XHCI_SUSPEND_DELAY;
175
176 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
177 (pdev->device == 0x15e0 || pdev->device == 0x15e1))
178 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
179
180 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) {
181 xhci->quirks |= XHCI_DISABLE_SPARSE;
182 xhci->quirks |= XHCI_RESET_ON_RESUME;
183 }
184
185 if (pdev->vendor == PCI_VENDOR_ID_AMD)
186 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
187
188 if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
189 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
190 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
191 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
192 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
193 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
194
195 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
196 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI)
197 xhci->quirks |= XHCI_BROKEN_D3COLD;
198
199 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
200 xhci->quirks |= XHCI_LPM_SUPPORT;
201 xhci->quirks |= XHCI_INTEL_HOST;
202 xhci->quirks |= XHCI_AVOID_BEI;
203 }
204 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
205 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
206 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
207 xhci->limit_active_eps = 64;
208 xhci->quirks |= XHCI_SW_BW_CHECKING;
209 /*
210 * PPT desktop boards DH77EB and DH77DF will power back on after
211 * a few seconds of being shutdown. The fix for this is to
212 * switch the ports from xHCI to EHCI on shutdown. We can't use
213 * DMI information to find those particular boards (since each
214 * vendor will change the board name), so we have to key off all
215 * PPT chipsets.
216 */
217 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
218 }
219 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
220 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
221 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
222 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
223 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
224 }
225 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
226 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
227 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
228 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
229 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
230 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
231 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
232 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
233 pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
234 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
235 }
236 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
237 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
238 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
239 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
240 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
241 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
242 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
243 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
244 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
245 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
246 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
247 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
248 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
249 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
250 xhci->quirks |= XHCI_MISSING_CAS;
251
252 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
253 (pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_PCH_XHCI ||
254 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_N_PCH_XHCI))
255 xhci->quirks |= XHCI_RESET_TO_DEFAULT;
256
257 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
258 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI ||
259 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI ||
260 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI ||
261 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI ||
262 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI ||
263 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI ||
264 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI ||
265 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI ||
266 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI ||
267 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI ||
268 pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI))
269 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
270
271 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
272 pdev->device == PCI_DEVICE_ID_EJ168) {
273 xhci->quirks |= XHCI_RESET_ON_RESUME;
274 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
275 xhci->quirks |= XHCI_BROKEN_STREAMS;
276 }
277 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
278 pdev->device == 0x0014) {
279 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
280 xhci->quirks |= XHCI_ZERO_64B_REGS;
281 }
282 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
283 pdev->device == 0x0015) {
284 xhci->quirks |= XHCI_RESET_ON_RESUME;
285 xhci->quirks |= XHCI_ZERO_64B_REGS;
286 }
287 if (pdev->vendor == PCI_VENDOR_ID_VIA)
288 xhci->quirks |= XHCI_RESET_ON_RESUME;
289
290 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
291 if (pdev->vendor == PCI_VENDOR_ID_VIA &&
292 pdev->device == 0x3432)
293 xhci->quirks |= XHCI_BROKEN_STREAMS;
294
295 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) {
296 xhci->quirks |= XHCI_LPM_SUPPORT;
297 xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS;
298 }
299
300 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
301 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI) {
302 /*
303 * try to tame the ASMedia 1042 controller which reports 0.96
304 * but appears to behave more like 1.0
305 */
306 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
307 xhci->quirks |= XHCI_BROKEN_STREAMS;
308 }
309 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
310 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) {
311 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
312 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
313 }
314 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
315 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI ||
316 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI ||
317 pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI))
318 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
319
320 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
321 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
322 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
323
324 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
325 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
326
327 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
328 pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
329 pdev->device == 0x9026)
330 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
331
332 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
333 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 ||
334 pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4))
335 xhci->quirks |= XHCI_NO_SOFT_RETRY;
336
337 /* xHC spec requires PCI devices to support D3hot and D3cold */
338 if (xhci->hci_version >= 0x120)
339 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
340
341 if (xhci->quirks & XHCI_RESET_ON_RESUME)
342 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
343 "QUIRK: Resetting on resume");
344}
345
346#ifdef CONFIG_ACPI
347static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
348{
349 static const guid_t intel_dsm_guid =
350 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
351 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
352 union acpi_object *obj;
353
354 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
355 NULL);
356 ACPI_FREE(obj);
357}
358
359static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev)
360{
361 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
362 struct xhci_hub *rhub = &xhci->usb3_rhub;
363 int ret;
364 int i;
365
366 /* This is not the usb3 roothub we are looking for */
367 if (hcd != rhub->hcd)
368 return;
369
370 if (hdev->maxchild > rhub->num_ports) {
371 dev_err(&hdev->dev, "USB3 roothub port number mismatch\n");
372 return;
373 }
374
375 for (i = 0; i < hdev->maxchild; i++) {
376 ret = usb_acpi_port_lpm_incapable(hdev, i);
377
378 dev_dbg(&hdev->dev, "port-%d disable U1/U2 _DSM: %d\n", i + 1, ret);
379
380 if (ret >= 0) {
381 rhub->ports[i]->lpm_incapable = ret;
382 continue;
383 }
384 }
385}
386
387#else
388static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
389static void xhci_find_lpm_incapable_ports(struct usb_hcd *hcd, struct usb_device *hdev) { }
390#endif /* CONFIG_ACPI */
391
392/* called during probe() after chip reset completes */
393static int xhci_pci_setup(struct usb_hcd *hcd)
394{
395 struct xhci_hcd *xhci;
396 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
397 int retval;
398
399 xhci = hcd_to_xhci(hcd);
400 if (!xhci->sbrn)
401 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
402
403 /* imod_interval is the interrupt moderation value in nanoseconds. */
404 xhci->imod_interval = 40000;
405
406 retval = xhci_gen_setup(hcd, xhci_pci_quirks);
407 if (retval)
408 return retval;
409
410 if (!usb_hcd_is_primary_hcd(hcd))
411 return 0;
412
413 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
414 xhci_pme_acpi_rtd3_enable(pdev);
415
416 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
417
418 /* Find any debug ports */
419 return xhci_pci_reinit(xhci, pdev);
420}
421
422static int xhci_pci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
423 struct usb_tt *tt, gfp_t mem_flags)
424{
425 /* Check if acpi claims some USB3 roothub ports are lpm incapable */
426 if (!hdev->parent)
427 xhci_find_lpm_incapable_ports(hcd, hdev);
428
429 return xhci_update_hub_device(hcd, hdev, tt, mem_flags);
430}
431
432/*
433 * We need to register our own PCI probe function (instead of the USB core's
434 * function) in order to create a second roothub under xHCI.
435 */
436static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
437{
438 int retval;
439 struct xhci_hcd *xhci;
440 struct usb_hcd *hcd;
441 struct xhci_driver_data *driver_data;
442 struct reset_control *reset;
443
444 driver_data = (struct xhci_driver_data *)id->driver_data;
445 if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) {
446 retval = renesas_xhci_check_request_fw(dev, id);
447 if (retval)
448 return retval;
449 }
450
451 reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
452 if (IS_ERR(reset))
453 return PTR_ERR(reset);
454 reset_control_reset(reset);
455
456 /* Prevent runtime suspending between USB-2 and USB-3 initialization */
457 pm_runtime_get_noresume(&dev->dev);
458
459 /* Register the USB 2.0 roothub.
460 * FIXME: USB core must know to register the USB 2.0 roothub first.
461 * This is sort of silly, because we could just set the HCD driver flags
462 * to say USB 2.0, but I'm not sure what the implications would be in
463 * the other parts of the HCD code.
464 */
465 retval = usb_hcd_pci_probe(dev, &xhci_pci_hc_driver);
466
467 if (retval)
468 goto put_runtime_pm;
469
470 /* USB 2.0 roothub is stored in the PCI device now. */
471 hcd = dev_get_drvdata(&dev->dev);
472 xhci = hcd_to_xhci(hcd);
473 xhci->reset = reset;
474 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev,
475 pci_name(dev), hcd);
476 if (!xhci->shared_hcd) {
477 retval = -ENOMEM;
478 goto dealloc_usb2_hcd;
479 }
480
481 retval = xhci_ext_cap_init(xhci);
482 if (retval)
483 goto put_usb3_hcd;
484
485 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
486 IRQF_SHARED);
487 if (retval)
488 goto put_usb3_hcd;
489 /* Roothub already marked as USB 3.0 speed */
490
491 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
492 HCC_MAX_PSA(xhci->hcc_params) >= 4)
493 xhci->shared_hcd->can_do_streams = 1;
494
495 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
496 pm_runtime_put_noidle(&dev->dev);
497
498 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
499 pm_runtime_allow(&dev->dev);
500
501 dma_set_max_seg_size(&dev->dev, UINT_MAX);
502
503 return 0;
504
505put_usb3_hcd:
506 usb_put_hcd(xhci->shared_hcd);
507dealloc_usb2_hcd:
508 usb_hcd_pci_remove(dev);
509put_runtime_pm:
510 pm_runtime_put_noidle(&dev->dev);
511 return retval;
512}
513
514static void xhci_pci_remove(struct pci_dev *dev)
515{
516 struct xhci_hcd *xhci;
517
518 xhci = hcd_to_xhci(pci_get_drvdata(dev));
519
520 xhci->xhc_state |= XHCI_STATE_REMOVING;
521
522 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
523 pm_runtime_forbid(&dev->dev);
524
525 if (xhci->shared_hcd) {
526 usb_remove_hcd(xhci->shared_hcd);
527 usb_put_hcd(xhci->shared_hcd);
528 xhci->shared_hcd = NULL;
529 }
530
531 /* Workaround for spurious wakeups at shutdown with HSW */
532 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
533 pci_set_power_state(dev, PCI_D3hot);
534
535 usb_hcd_pci_remove(dev);
536}
537
538#ifdef CONFIG_PM
539/*
540 * In some Intel xHCI controllers, in order to get D3 working,
541 * through a vendor specific SSIC CONFIG register at offset 0x883c,
542 * SSIC PORT need to be marked as "unused" before putting xHCI
543 * into D3. After D3 exit, the SSIC port need to be marked as "used".
544 * Without this change, xHCI might not enter D3 state.
545 */
546static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
547{
548 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
549 u32 val;
550 void __iomem *reg;
551 int i;
552
553 for (i = 0; i < SSIC_PORT_NUM; i++) {
554 reg = (void __iomem *) xhci->cap_regs +
555 SSIC_PORT_CFG2 +
556 i * SSIC_PORT_CFG2_OFFSET;
557
558 /* Notify SSIC that SSIC profile programming is not done. */
559 val = readl(reg) & ~PROG_DONE;
560 writel(val, reg);
561
562 /* Mark SSIC port as unused(suspend) or used(resume) */
563 val = readl(reg);
564 if (suspend)
565 val |= SSIC_PORT_UNUSED;
566 else
567 val &= ~SSIC_PORT_UNUSED;
568 writel(val, reg);
569
570 /* Notify SSIC that SSIC profile programming is done */
571 val = readl(reg) | PROG_DONE;
572 writel(val, reg);
573 readl(reg);
574 }
575}
576
577/*
578 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
579 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
580 */
581static void xhci_pme_quirk(struct usb_hcd *hcd)
582{
583 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
584 void __iomem *reg;
585 u32 val;
586
587 reg = (void __iomem *) xhci->cap_regs + 0x80a4;
588 val = readl(reg);
589 writel(val | BIT(28), reg);
590 readl(reg);
591}
592
593static void xhci_sparse_control_quirk(struct usb_hcd *hcd)
594{
595 u32 reg;
596
597 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE);
598 reg &= ~BIT(SPARSE_DISABLE_BIT);
599 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE);
600}
601
602static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
603{
604 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
605 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
606 int ret;
607
608 /*
609 * Systems with the TI redriver that loses port status change events
610 * need to have the registers polled during D3, so avoid D3cold.
611 */
612 if (xhci->quirks & (XHCI_COMP_MODE_QUIRK | XHCI_BROKEN_D3COLD))
613 pci_d3cold_disable(pdev);
614
615 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
616 xhci_pme_quirk(hcd);
617
618 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
619 xhci_ssic_port_unused_quirk(hcd, true);
620
621 if (xhci->quirks & XHCI_DISABLE_SPARSE)
622 xhci_sparse_control_quirk(hcd);
623
624 ret = xhci_suspend(xhci, do_wakeup);
625 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
626 xhci_ssic_port_unused_quirk(hcd, false);
627
628 return ret;
629}
630
631static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
632{
633 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
634 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
635 int retval = 0;
636
637 reset_control_reset(xhci->reset);
638
639 /* The BIOS on systems with the Intel Panther Point chipset may or may
640 * not support xHCI natively. That means that during system resume, it
641 * may switch the ports back to EHCI so that users can use their
642 * keyboard to select a kernel from GRUB after resume from hibernate.
643 *
644 * The BIOS is supposed to remember whether the OS had xHCI ports
645 * enabled before resume, and switch the ports back to xHCI when the
646 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
647 * writers.
648 *
649 * Unconditionally switch the ports back to xHCI after a system resume.
650 * It should not matter whether the EHCI or xHCI controller is
651 * resumed first. It's enough to do the switchover in xHCI because
652 * USB core won't notice anything as the hub driver doesn't start
653 * running again until after all the devices (including both EHCI and
654 * xHCI host controllers) have been resumed.
655 */
656
657 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
658 usb_enable_intel_xhci_ports(pdev);
659
660 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
661 xhci_ssic_port_unused_quirk(hcd, false);
662
663 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
664 xhci_pme_quirk(hcd);
665
666 retval = xhci_resume(xhci, hibernated);
667 return retval;
668}
669
670static int xhci_pci_poweroff_late(struct usb_hcd *hcd, bool do_wakeup)
671{
672 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
673 struct xhci_port *port;
674 struct usb_device *udev;
675 unsigned int slot_id;
676 u32 portsc;
677 int i;
678
679 /*
680 * Systems with XHCI_RESET_TO_DEFAULT quirk have boot firmware that
681 * cause significant boot delay if usb ports are in suspended U3 state
682 * during boot. Some USB devices survive in U3 state over S4 hibernate
683 *
684 * Disable ports that are in U3 if remote wake is not enabled for either
685 * host controller or connected device
686 */
687
688 if (!(xhci->quirks & XHCI_RESET_TO_DEFAULT))
689 return 0;
690
691 for (i = 0; i < HCS_MAX_PORTS(xhci->hcs_params1); i++) {
692 port = &xhci->hw_ports[i];
693 portsc = readl(port->addr);
694
695 if ((portsc & PORT_PLS_MASK) != XDEV_U3)
696 continue;
697
698 slot_id = xhci_find_slot_id_by_port(port->rhub->hcd, xhci,
699 port->hcd_portnum + 1);
700 if (!slot_id || !xhci->devs[slot_id]) {
701 xhci_err(xhci, "No dev for slot_id %d for port %d-%d in U3\n",
702 slot_id, port->rhub->hcd->self.busnum, port->hcd_portnum + 1);
703 continue;
704 }
705
706 udev = xhci->devs[slot_id]->udev;
707
708 /* if wakeup is enabled then don't disable the port */
709 if (udev->do_remote_wakeup && do_wakeup)
710 continue;
711
712 xhci_dbg(xhci, "port %d-%d in U3 without wakeup, disable it\n",
713 port->rhub->hcd->self.busnum, port->hcd_portnum + 1);
714 portsc = xhci_port_state_to_neutral(portsc);
715 writel(portsc | PORT_PE, port->addr);
716 }
717
718 return 0;
719}
720
721static void xhci_pci_shutdown(struct usb_hcd *hcd)
722{
723 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
724 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
725
726 xhci_shutdown(hcd);
727
728 /* Yet another workaround for spurious wakeups at shutdown with HSW */
729 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
730 pci_set_power_state(pdev, PCI_D3hot);
731}
732#endif /* CONFIG_PM */
733
734/*-------------------------------------------------------------------------*/
735
736static const struct xhci_driver_data reneses_data = {
737 .quirks = XHCI_RENESAS_FW_QUIRK,
738 .firmware = "renesas_usb_fw.mem",
739};
740
741/* PCI driver selection metadata; PCI hotplugging uses this */
742static const struct pci_device_id pci_ids[] = {
743 { PCI_DEVICE(0x1912, 0x0014),
744 .driver_data = (unsigned long)&reneses_data,
745 },
746 { PCI_DEVICE(0x1912, 0x0015),
747 .driver_data = (unsigned long)&reneses_data,
748 },
749 /* handle any USB 3.0 xHCI controller */
750 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
751 },
752 { /* end: all zeroes */ }
753};
754MODULE_DEVICE_TABLE(pci, pci_ids);
755
756/*
757 * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't
758 * load firmware, so don't encumber the xhci-pci driver with it.
759 */
760#if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS)
761MODULE_FIRMWARE("renesas_usb_fw.mem");
762#endif
763
764/* pci driver glue; this is a "new style" PCI driver module */
765static struct pci_driver xhci_pci_driver = {
766 .name = hcd_name,
767 .id_table = pci_ids,
768
769 .probe = xhci_pci_probe,
770 .remove = xhci_pci_remove,
771 /* suspend and resume implemented later */
772
773 .shutdown = usb_hcd_pci_shutdown,
774 .driver = {
775#ifdef CONFIG_PM
776 .pm = &usb_hcd_pci_pm_ops,
777#endif
778 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
779 },
780};
781
782static int __init xhci_pci_init(void)
783{
784 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
785#ifdef CONFIG_PM
786 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
787 xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
788 xhci_pci_hc_driver.pci_poweroff_late = xhci_pci_poweroff_late;
789 xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
790#endif
791 return pci_register_driver(&xhci_pci_driver);
792}
793module_init(xhci_pci_init);
794
795static void __exit xhci_pci_exit(void)
796{
797 pci_unregister_driver(&xhci_pci_driver);
798}
799module_exit(xhci_pci_exit);
800
801MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
802MODULE_LICENSE("GPL");