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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#include <linux/kernel.h>
12#include <linux/slab.h>
13#include <linux/spinlock.h>
14#include <linux/platform_device.h>
15#include <linux/pm_runtime.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/list.h>
19#include <linux/dma-mapping.h>
20
21#include <linux/usb/ch9.h>
22#include <linux/usb/gadget.h>
23#include <linux/usb/composite.h>
24
25#include "core.h"
26#include "debug.h"
27#include "gadget.h"
28#include "io.h"
29
30static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
31static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
32 struct dwc3_ep *dep, struct dwc3_request *req);
33
34static void dwc3_ep0_prepare_one_trb(struct dwc3_ep *dep,
35 dma_addr_t buf_dma, u32 len, u32 type, bool chain)
36{
37 struct dwc3_trb *trb;
38 struct dwc3 *dwc;
39
40 dwc = dep->dwc;
41 trb = &dwc->ep0_trb[dep->trb_enqueue];
42
43 if (chain)
44 dep->trb_enqueue++;
45
46 trb->bpl = lower_32_bits(buf_dma);
47 trb->bph = upper_32_bits(buf_dma);
48 trb->size = len;
49 trb->ctrl = type;
50
51 trb->ctrl |= (DWC3_TRB_CTRL_HWO
52 | DWC3_TRB_CTRL_ISP_IMI);
53
54 if (chain)
55 trb->ctrl |= DWC3_TRB_CTRL_CHN;
56 else
57 trb->ctrl |= (DWC3_TRB_CTRL_IOC
58 | DWC3_TRB_CTRL_LST);
59
60 trace_dwc3_prepare_trb(dep, trb);
61}
62
63static int dwc3_ep0_start_trans(struct dwc3_ep *dep)
64{
65 struct dwc3_gadget_ep_cmd_params params;
66 struct dwc3 *dwc;
67 int ret;
68
69 if (dep->flags & DWC3_EP_BUSY)
70 return 0;
71
72 dwc = dep->dwc;
73
74 memset(¶ms, 0, sizeof(params));
75 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
76 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
77
78 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, ¶ms);
79 if (ret < 0)
80 return ret;
81
82 dep->flags |= DWC3_EP_BUSY;
83 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
84 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
85
86 return 0;
87}
88
89static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
90 struct dwc3_request *req)
91{
92 struct dwc3 *dwc = dep->dwc;
93
94 req->request.actual = 0;
95 req->request.status = -EINPROGRESS;
96 req->epnum = dep->number;
97
98 list_add_tail(&req->list, &dep->pending_list);
99
100 /*
101 * Gadget driver might not be quick enough to queue a request
102 * before we get a Transfer Not Ready event on this endpoint.
103 *
104 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
105 * flag is set, it's telling us that as soon as Gadget queues the
106 * required request, we should kick the transfer here because the
107 * IRQ we were waiting for is long gone.
108 */
109 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
110 unsigned direction;
111
112 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
113
114 if (dwc->ep0state != EP0_DATA_PHASE) {
115 dev_WARN(dwc->dev, "Unexpected pending request\n");
116 return 0;
117 }
118
119 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
120
121 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
122 DWC3_EP0_DIR_IN);
123
124 return 0;
125 }
126
127 /*
128 * In case gadget driver asked us to delay the STATUS phase,
129 * handle it here.
130 */
131 if (dwc->delayed_status) {
132 unsigned direction;
133
134 direction = !dwc->ep0_expect_in;
135 dwc->delayed_status = false;
136 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
137
138 if (dwc->ep0state == EP0_STATUS_PHASE)
139 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
140
141 return 0;
142 }
143
144 /*
145 * Unfortunately we have uncovered a limitation wrt the Data Phase.
146 *
147 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
148 * come before issueing Start Transfer command, but if we do, we will
149 * miss situations where the host starts another SETUP phase instead of
150 * the DATA phase. Such cases happen at least on TD.7.6 of the Link
151 * Layer Compliance Suite.
152 *
153 * The problem surfaces due to the fact that in case of back-to-back
154 * SETUP packets there will be no XferNotReady(DATA) generated and we
155 * will be stuck waiting for XferNotReady(DATA) forever.
156 *
157 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
158 * it tells us to start Data Phase right away. It also mentions that if
159 * we receive a SETUP phase instead of the DATA phase, core will issue
160 * XferComplete for the DATA phase, before actually initiating it in
161 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
162 * can only be used to print some debugging logs, as the core expects
163 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
164 * just so it completes right away, without transferring anything and,
165 * only then, we can go back to the SETUP phase.
166 *
167 * Because of this scenario, SNPS decided to change the programming
168 * model of control transfers and support on-demand transfers only for
169 * the STATUS phase. To fix the issue we have now, we will always wait
170 * for gadget driver to queue the DATA phase's struct usb_request, then
171 * start it right away.
172 *
173 * If we're actually in a 2-stage transfer, we will wait for
174 * XferNotReady(STATUS).
175 */
176 if (dwc->three_stage_setup) {
177 unsigned direction;
178
179 direction = dwc->ep0_expect_in;
180 dwc->ep0state = EP0_DATA_PHASE;
181
182 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
183
184 dep->flags &= ~DWC3_EP0_DIR_IN;
185 }
186
187 return 0;
188}
189
190int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
191 gfp_t gfp_flags)
192{
193 struct dwc3_request *req = to_dwc3_request(request);
194 struct dwc3_ep *dep = to_dwc3_ep(ep);
195 struct dwc3 *dwc = dep->dwc;
196
197 unsigned long flags;
198
199 int ret;
200
201 spin_lock_irqsave(&dwc->lock, flags);
202 if (!dep->endpoint.desc) {
203 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
204 dep->name);
205 ret = -ESHUTDOWN;
206 goto out;
207 }
208
209 /* we share one TRB for ep0/1 */
210 if (!list_empty(&dep->pending_list)) {
211 ret = -EBUSY;
212 goto out;
213 }
214
215 ret = __dwc3_gadget_ep0_queue(dep, req);
216
217out:
218 spin_unlock_irqrestore(&dwc->lock, flags);
219
220 return ret;
221}
222
223static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
224{
225 struct dwc3_ep *dep;
226
227 /* reinitialize physical ep1 */
228 dep = dwc->eps[1];
229 dep->flags = DWC3_EP_ENABLED;
230
231 /* stall is always issued on EP0 */
232 dep = dwc->eps[0];
233 __dwc3_gadget_ep_set_halt(dep, 1, false);
234 dep->flags = DWC3_EP_ENABLED;
235 dwc->delayed_status = false;
236
237 if (!list_empty(&dep->pending_list)) {
238 struct dwc3_request *req;
239
240 req = next_request(&dep->pending_list);
241 dwc3_gadget_giveback(dep, req, -ECONNRESET);
242 }
243
244 dwc->ep0state = EP0_SETUP_PHASE;
245 dwc3_ep0_out_start(dwc);
246}
247
248int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
249{
250 struct dwc3_ep *dep = to_dwc3_ep(ep);
251 struct dwc3 *dwc = dep->dwc;
252
253 dwc3_ep0_stall_and_restart(dwc);
254
255 return 0;
256}
257
258int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
259{
260 struct dwc3_ep *dep = to_dwc3_ep(ep);
261 struct dwc3 *dwc = dep->dwc;
262 unsigned long flags;
263 int ret;
264
265 spin_lock_irqsave(&dwc->lock, flags);
266 ret = __dwc3_gadget_ep0_set_halt(ep, value);
267 spin_unlock_irqrestore(&dwc->lock, flags);
268
269 return ret;
270}
271
272void dwc3_ep0_out_start(struct dwc3 *dwc)
273{
274 struct dwc3_ep *dep;
275 int ret;
276
277 complete(&dwc->ep0_in_setup);
278
279 dep = dwc->eps[0];
280 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 8,
281 DWC3_TRBCTL_CONTROL_SETUP, false);
282 ret = dwc3_ep0_start_trans(dep);
283 WARN_ON(ret < 0);
284}
285
286static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
287{
288 struct dwc3_ep *dep;
289 u32 windex = le16_to_cpu(wIndex_le);
290 u32 epnum;
291
292 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
293 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
294 epnum |= 1;
295
296 dep = dwc->eps[epnum];
297 if (dep->flags & DWC3_EP_ENABLED)
298 return dep;
299
300 return NULL;
301}
302
303static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
304{
305}
306/*
307 * ch 9.4.5
308 */
309static int dwc3_ep0_handle_status(struct dwc3 *dwc,
310 struct usb_ctrlrequest *ctrl)
311{
312 struct dwc3_ep *dep;
313 u32 recip;
314 u32 value;
315 u32 reg;
316 u16 usb_status = 0;
317 __le16 *response_pkt;
318
319 /* We don't support PTM_STATUS */
320 value = le16_to_cpu(ctrl->wValue);
321 if (value != 0)
322 return -EINVAL;
323
324 recip = ctrl->bRequestType & USB_RECIP_MASK;
325 switch (recip) {
326 case USB_RECIP_DEVICE:
327 /*
328 * LTM will be set once we know how to set this in HW.
329 */
330 usb_status |= dwc->gadget.is_selfpowered;
331
332 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
333 (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
334 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
335 if (reg & DWC3_DCTL_INITU1ENA)
336 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
337 if (reg & DWC3_DCTL_INITU2ENA)
338 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
339 }
340
341 break;
342
343 case USB_RECIP_INTERFACE:
344 /*
345 * Function Remote Wake Capable D0
346 * Function Remote Wakeup D1
347 */
348 break;
349
350 case USB_RECIP_ENDPOINT:
351 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
352 if (!dep)
353 return -EINVAL;
354
355 if (dep->flags & DWC3_EP_STALL)
356 usb_status = 1 << USB_ENDPOINT_HALT;
357 break;
358 default:
359 return -EINVAL;
360 }
361
362 response_pkt = (__le16 *) dwc->setup_buf;
363 *response_pkt = cpu_to_le16(usb_status);
364
365 dep = dwc->eps[0];
366 dwc->ep0_usb_req.dep = dep;
367 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
368 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
369 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
370
371 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
372}
373
374static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state,
375 int set)
376{
377 u32 reg;
378
379 if (state != USB_STATE_CONFIGURED)
380 return -EINVAL;
381 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
382 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
383 return -EINVAL;
384
385 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
386 if (set)
387 reg |= DWC3_DCTL_INITU1ENA;
388 else
389 reg &= ~DWC3_DCTL_INITU1ENA;
390 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
391
392 return 0;
393}
394
395static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state,
396 int set)
397{
398 u32 reg;
399
400
401 if (state != USB_STATE_CONFIGURED)
402 return -EINVAL;
403 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
404 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
405 return -EINVAL;
406
407 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
408 if (set)
409 reg |= DWC3_DCTL_INITU2ENA;
410 else
411 reg &= ~DWC3_DCTL_INITU2ENA;
412 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
413
414 return 0;
415}
416
417static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state,
418 u32 wIndex, int set)
419{
420 if ((wIndex & 0xff) != 0)
421 return -EINVAL;
422 if (!set)
423 return -EINVAL;
424
425 switch (wIndex >> 8) {
426 case TEST_J:
427 case TEST_K:
428 case TEST_SE0_NAK:
429 case TEST_PACKET:
430 case TEST_FORCE_EN:
431 dwc->test_mode_nr = wIndex >> 8;
432 dwc->test_mode = true;
433 break;
434 default:
435 return -EINVAL;
436 }
437
438 return 0;
439}
440
441static int dwc3_ep0_handle_device(struct dwc3 *dwc,
442 struct usb_ctrlrequest *ctrl, int set)
443{
444 enum usb_device_state state;
445 u32 wValue;
446 u32 wIndex;
447 int ret = 0;
448
449 wValue = le16_to_cpu(ctrl->wValue);
450 wIndex = le16_to_cpu(ctrl->wIndex);
451 state = dwc->gadget.state;
452
453 switch (wValue) {
454 case USB_DEVICE_REMOTE_WAKEUP:
455 break;
456 /*
457 * 9.4.1 says only only for SS, in AddressState only for
458 * default control pipe
459 */
460 case USB_DEVICE_U1_ENABLE:
461 ret = dwc3_ep0_handle_u1(dwc, state, set);
462 break;
463 case USB_DEVICE_U2_ENABLE:
464 ret = dwc3_ep0_handle_u2(dwc, state, set);
465 break;
466 case USB_DEVICE_LTM_ENABLE:
467 ret = -EINVAL;
468 break;
469 case USB_DEVICE_TEST_MODE:
470 ret = dwc3_ep0_handle_test(dwc, state, wIndex, set);
471 break;
472 default:
473 ret = -EINVAL;
474 }
475
476 return ret;
477}
478
479static int dwc3_ep0_handle_intf(struct dwc3 *dwc,
480 struct usb_ctrlrequest *ctrl, int set)
481{
482 u32 wValue;
483 int ret = 0;
484
485 wValue = le16_to_cpu(ctrl->wValue);
486
487 switch (wValue) {
488 case USB_INTRF_FUNC_SUSPEND:
489 /*
490 * REVISIT: Ideally we would enable some low power mode here,
491 * however it's unclear what we should be doing here.
492 *
493 * For now, we're not doing anything, just making sure we return
494 * 0 so USB Command Verifier tests pass without any errors.
495 */
496 break;
497 default:
498 ret = -EINVAL;
499 }
500
501 return ret;
502}
503
504static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc,
505 struct usb_ctrlrequest *ctrl, int set)
506{
507 struct dwc3_ep *dep;
508 u32 wValue;
509 int ret;
510
511 wValue = le16_to_cpu(ctrl->wValue);
512
513 switch (wValue) {
514 case USB_ENDPOINT_HALT:
515 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
516 if (!dep)
517 return -EINVAL;
518
519 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
520 break;
521
522 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
523 if (ret)
524 return -EINVAL;
525 break;
526 default:
527 return -EINVAL;
528 }
529
530 return 0;
531}
532
533static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
534 struct usb_ctrlrequest *ctrl, int set)
535{
536 u32 recip;
537 int ret;
538
539 recip = ctrl->bRequestType & USB_RECIP_MASK;
540
541 switch (recip) {
542 case USB_RECIP_DEVICE:
543 ret = dwc3_ep0_handle_device(dwc, ctrl, set);
544 break;
545 case USB_RECIP_INTERFACE:
546 ret = dwc3_ep0_handle_intf(dwc, ctrl, set);
547 break;
548 case USB_RECIP_ENDPOINT:
549 ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set);
550 break;
551 default:
552 ret = -EINVAL;
553 }
554
555 return ret;
556}
557
558static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
559{
560 enum usb_device_state state = dwc->gadget.state;
561 u32 addr;
562 u32 reg;
563
564 addr = le16_to_cpu(ctrl->wValue);
565 if (addr > 127) {
566 dev_err(dwc->dev, "invalid device address %d\n", addr);
567 return -EINVAL;
568 }
569
570 if (state == USB_STATE_CONFIGURED) {
571 dev_err(dwc->dev, "can't SetAddress() from Configured State\n");
572 return -EINVAL;
573 }
574
575 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
576 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
577 reg |= DWC3_DCFG_DEVADDR(addr);
578 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
579
580 if (addr)
581 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
582 else
583 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
584
585 return 0;
586}
587
588static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
589{
590 int ret;
591
592 spin_unlock(&dwc->lock);
593 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
594 spin_lock(&dwc->lock);
595 return ret;
596}
597
598static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
599{
600 enum usb_device_state state = dwc->gadget.state;
601 u32 cfg;
602 int ret;
603 u32 reg;
604
605 cfg = le16_to_cpu(ctrl->wValue);
606
607 switch (state) {
608 case USB_STATE_DEFAULT:
609 return -EINVAL;
610
611 case USB_STATE_ADDRESS:
612 ret = dwc3_ep0_delegate_req(dwc, ctrl);
613 /* if the cfg matches and the cfg is non zero */
614 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
615
616 /*
617 * only change state if set_config has already
618 * been processed. If gadget driver returns
619 * USB_GADGET_DELAYED_STATUS, we will wait
620 * to change the state on the next usb_ep_queue()
621 */
622 if (ret == 0)
623 usb_gadget_set_state(&dwc->gadget,
624 USB_STATE_CONFIGURED);
625
626 /*
627 * Enable transition to U1/U2 state when
628 * nothing is pending from application.
629 */
630 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
631 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
632 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
633 }
634 break;
635
636 case USB_STATE_CONFIGURED:
637 ret = dwc3_ep0_delegate_req(dwc, ctrl);
638 if (!cfg && !ret)
639 usb_gadget_set_state(&dwc->gadget,
640 USB_STATE_ADDRESS);
641 break;
642 default:
643 ret = -EINVAL;
644 }
645 return ret;
646}
647
648static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
649{
650 struct dwc3_ep *dep = to_dwc3_ep(ep);
651 struct dwc3 *dwc = dep->dwc;
652
653 u32 param = 0;
654 u32 reg;
655
656 struct timing {
657 u8 u1sel;
658 u8 u1pel;
659 __le16 u2sel;
660 __le16 u2pel;
661 } __packed timing;
662
663 int ret;
664
665 memcpy(&timing, req->buf, sizeof(timing));
666
667 dwc->u1sel = timing.u1sel;
668 dwc->u1pel = timing.u1pel;
669 dwc->u2sel = le16_to_cpu(timing.u2sel);
670 dwc->u2pel = le16_to_cpu(timing.u2pel);
671
672 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
673 if (reg & DWC3_DCTL_INITU2ENA)
674 param = dwc->u2pel;
675 if (reg & DWC3_DCTL_INITU1ENA)
676 param = dwc->u1pel;
677
678 /*
679 * According to Synopsys Databook, if parameter is
680 * greater than 125, a value of zero should be
681 * programmed in the register.
682 */
683 if (param > 125)
684 param = 0;
685
686 /* now that we have the time, issue DGCMD Set Sel */
687 ret = dwc3_send_gadget_generic_command(dwc,
688 DWC3_DGCMD_SET_PERIODIC_PAR, param);
689 WARN_ON(ret < 0);
690}
691
692static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
693{
694 struct dwc3_ep *dep;
695 enum usb_device_state state = dwc->gadget.state;
696 u16 wLength;
697
698 if (state == USB_STATE_DEFAULT)
699 return -EINVAL;
700
701 wLength = le16_to_cpu(ctrl->wLength);
702
703 if (wLength != 6) {
704 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
705 wLength);
706 return -EINVAL;
707 }
708
709 /*
710 * To handle Set SEL we need to receive 6 bytes from Host. So let's
711 * queue a usb_request for 6 bytes.
712 *
713 * Remember, though, this controller can't handle non-wMaxPacketSize
714 * aligned transfers on the OUT direction, so we queue a request for
715 * wMaxPacketSize instead.
716 */
717 dep = dwc->eps[0];
718 dwc->ep0_usb_req.dep = dep;
719 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
720 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
721 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
722
723 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
724}
725
726static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
727{
728 u16 wLength;
729 u16 wValue;
730 u16 wIndex;
731
732 wValue = le16_to_cpu(ctrl->wValue);
733 wLength = le16_to_cpu(ctrl->wLength);
734 wIndex = le16_to_cpu(ctrl->wIndex);
735
736 if (wIndex || wLength)
737 return -EINVAL;
738
739 dwc->gadget.isoch_delay = wValue;
740
741 return 0;
742}
743
744static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
745{
746 int ret;
747
748 switch (ctrl->bRequest) {
749 case USB_REQ_GET_STATUS:
750 ret = dwc3_ep0_handle_status(dwc, ctrl);
751 break;
752 case USB_REQ_CLEAR_FEATURE:
753 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
754 break;
755 case USB_REQ_SET_FEATURE:
756 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
757 break;
758 case USB_REQ_SET_ADDRESS:
759 ret = dwc3_ep0_set_address(dwc, ctrl);
760 break;
761 case USB_REQ_SET_CONFIGURATION:
762 ret = dwc3_ep0_set_config(dwc, ctrl);
763 break;
764 case USB_REQ_SET_SEL:
765 ret = dwc3_ep0_set_sel(dwc, ctrl);
766 break;
767 case USB_REQ_SET_ISOCH_DELAY:
768 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
769 break;
770 default:
771 ret = dwc3_ep0_delegate_req(dwc, ctrl);
772 break;
773 }
774
775 return ret;
776}
777
778static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
779 const struct dwc3_event_depevt *event)
780{
781 struct usb_ctrlrequest *ctrl = (void *) dwc->ep0_trb;
782 int ret = -EINVAL;
783 u32 len;
784
785 if (!dwc->gadget_driver)
786 goto out;
787
788 trace_dwc3_ctrl_req(ctrl);
789
790 len = le16_to_cpu(ctrl->wLength);
791 if (!len) {
792 dwc->three_stage_setup = false;
793 dwc->ep0_expect_in = false;
794 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
795 } else {
796 dwc->three_stage_setup = true;
797 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
798 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
799 }
800
801 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
802 ret = dwc3_ep0_std_request(dwc, ctrl);
803 else
804 ret = dwc3_ep0_delegate_req(dwc, ctrl);
805
806 if (ret == USB_GADGET_DELAYED_STATUS)
807 dwc->delayed_status = true;
808
809out:
810 if (ret < 0)
811 dwc3_ep0_stall_and_restart(dwc);
812}
813
814static void dwc3_ep0_complete_data(struct dwc3 *dwc,
815 const struct dwc3_event_depevt *event)
816{
817 struct dwc3_request *r;
818 struct usb_request *ur;
819 struct dwc3_trb *trb;
820 struct dwc3_ep *ep0;
821 u32 transferred = 0;
822 u32 status;
823 u32 length;
824 u8 epnum;
825
826 epnum = event->endpoint_number;
827 ep0 = dwc->eps[0];
828
829 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
830 trb = dwc->ep0_trb;
831 trace_dwc3_complete_trb(ep0, trb);
832
833 r = next_request(&ep0->pending_list);
834 if (!r)
835 return;
836
837 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
838 if (status == DWC3_TRBSTS_SETUP_PENDING) {
839 dwc->setup_packet_pending = true;
840 if (r)
841 dwc3_gadget_giveback(ep0, r, -ECONNRESET);
842
843 return;
844 }
845
846 ur = &r->request;
847
848 length = trb->size & DWC3_TRB_SIZE_MASK;
849 transferred = ur->length - length;
850 ur->actual += transferred;
851
852 if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
853 ur->length && ur->zero) || dwc->ep0_bounced) {
854 trb++;
855 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
856 trace_dwc3_complete_trb(ep0, trb);
857
858 if (r->direction)
859 dwc->eps[1]->trb_enqueue = 0;
860 else
861 dwc->eps[0]->trb_enqueue = 0;
862
863 dwc->ep0_bounced = false;
864 }
865
866 if ((epnum & 1) && ur->actual < ur->length)
867 dwc3_ep0_stall_and_restart(dwc);
868 else
869 dwc3_gadget_giveback(ep0, r, 0);
870}
871
872static void dwc3_ep0_complete_status(struct dwc3 *dwc,
873 const struct dwc3_event_depevt *event)
874{
875 struct dwc3_request *r;
876 struct dwc3_ep *dep;
877 struct dwc3_trb *trb;
878 u32 status;
879
880 dep = dwc->eps[0];
881 trb = dwc->ep0_trb;
882
883 trace_dwc3_complete_trb(dep, trb);
884
885 if (!list_empty(&dep->pending_list)) {
886 r = next_request(&dep->pending_list);
887
888 dwc3_gadget_giveback(dep, r, 0);
889 }
890
891 if (dwc->test_mode) {
892 int ret;
893
894 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
895 if (ret < 0) {
896 dev_err(dwc->dev, "invalid test #%d\n",
897 dwc->test_mode_nr);
898 dwc3_ep0_stall_and_restart(dwc);
899 return;
900 }
901 }
902
903 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
904 if (status == DWC3_TRBSTS_SETUP_PENDING)
905 dwc->setup_packet_pending = true;
906
907 dwc->ep0state = EP0_SETUP_PHASE;
908 dwc3_ep0_out_start(dwc);
909}
910
911static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
912 const struct dwc3_event_depevt *event)
913{
914 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
915
916 dep->flags &= ~DWC3_EP_BUSY;
917 dep->resource_index = 0;
918 dwc->setup_packet_pending = false;
919
920 switch (dwc->ep0state) {
921 case EP0_SETUP_PHASE:
922 dwc3_ep0_inspect_setup(dwc, event);
923 break;
924
925 case EP0_DATA_PHASE:
926 dwc3_ep0_complete_data(dwc, event);
927 break;
928
929 case EP0_STATUS_PHASE:
930 dwc3_ep0_complete_status(dwc, event);
931 break;
932 default:
933 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
934 }
935}
936
937static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
938 struct dwc3_ep *dep, struct dwc3_request *req)
939{
940 int ret;
941
942 req->direction = !!dep->number;
943
944 if (req->request.length == 0) {
945 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0,
946 DWC3_TRBCTL_CONTROL_DATA, false);
947 ret = dwc3_ep0_start_trans(dep);
948 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
949 && (dep->number == 0)) {
950 u32 maxpacket;
951 u32 rem;
952
953 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
954 &req->request, dep->number);
955 if (ret)
956 return;
957
958 maxpacket = dep->endpoint.maxpacket;
959 rem = req->request.length % maxpacket;
960 dwc->ep0_bounced = true;
961
962 /* prepare normal TRB */
963 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
964 req->request.length,
965 DWC3_TRBCTL_CONTROL_DATA,
966 true);
967
968 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
969
970 /* Now prepare one extra TRB to align transfer size */
971 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
972 maxpacket - rem,
973 DWC3_TRBCTL_CONTROL_DATA,
974 false);
975 ret = dwc3_ep0_start_trans(dep);
976 } else if (IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) &&
977 req->request.length && req->request.zero) {
978 u32 maxpacket;
979
980 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
981 &req->request, dep->number);
982 if (ret)
983 return;
984
985 maxpacket = dep->endpoint.maxpacket;
986
987 /* prepare normal TRB */
988 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
989 req->request.length,
990 DWC3_TRBCTL_CONTROL_DATA,
991 true);
992
993 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
994
995 /* Now prepare one extra TRB to align transfer size */
996 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
997 0, DWC3_TRBCTL_CONTROL_DATA,
998 false);
999 ret = dwc3_ep0_start_trans(dep);
1000 } else {
1001 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1002 &req->request, dep->number);
1003 if (ret)
1004 return;
1005
1006 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1007 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1008 false);
1009
1010 req->trb = &dwc->ep0_trb[dep->trb_enqueue];
1011
1012 ret = dwc3_ep0_start_trans(dep);
1013 }
1014
1015 WARN_ON(ret < 0);
1016}
1017
1018static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1019{
1020 struct dwc3 *dwc = dep->dwc;
1021 u32 type;
1022
1023 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1024 : DWC3_TRBCTL_CONTROL_STATUS2;
1025
1026 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0, type, false);
1027 return dwc3_ep0_start_trans(dep);
1028}
1029
1030static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1031{
1032 WARN_ON(dwc3_ep0_start_control_status(dep));
1033}
1034
1035static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1036 const struct dwc3_event_depevt *event)
1037{
1038 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
1039
1040 __dwc3_ep0_do_control_status(dwc, dep);
1041}
1042
1043static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1044{
1045 struct dwc3_gadget_ep_cmd_params params;
1046 u32 cmd;
1047 int ret;
1048
1049 if (!dep->resource_index)
1050 return;
1051
1052 cmd = DWC3_DEPCMD_ENDTRANSFER;
1053 cmd |= DWC3_DEPCMD_CMDIOC;
1054 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1055 memset(¶ms, 0, sizeof(params));
1056 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1057 WARN_ON_ONCE(ret);
1058 dep->resource_index = 0;
1059}
1060
1061static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1062 const struct dwc3_event_depevt *event)
1063{
1064 switch (event->status) {
1065 case DEPEVT_STATUS_CONTROL_DATA:
1066 /*
1067 * We already have a DATA transfer in the controller's cache,
1068 * if we receive a XferNotReady(DATA) we will ignore it, unless
1069 * it's for the wrong direction.
1070 *
1071 * In that case, we must issue END_TRANSFER command to the Data
1072 * Phase we already have started and issue SetStall on the
1073 * control endpoint.
1074 */
1075 if (dwc->ep0_expect_in != event->endpoint_number) {
1076 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
1077
1078 dev_err(dwc->dev, "unexpected direction for Data Phase\n");
1079 dwc3_ep0_end_control_data(dwc, dep);
1080 dwc3_ep0_stall_and_restart(dwc);
1081 return;
1082 }
1083
1084 break;
1085
1086 case DEPEVT_STATUS_CONTROL_STATUS:
1087 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1088 return;
1089
1090 dwc->ep0state = EP0_STATUS_PHASE;
1091
1092 if (dwc->delayed_status) {
1093 struct dwc3_ep *dep = dwc->eps[0];
1094
1095 WARN_ON_ONCE(event->endpoint_number != 1);
1096 /*
1097 * We should handle the delay STATUS phase here if the
1098 * request for handling delay STATUS has been queued
1099 * into the list.
1100 */
1101 if (!list_empty(&dep->pending_list)) {
1102 dwc->delayed_status = false;
1103 usb_gadget_set_state(&dwc->gadget,
1104 USB_STATE_CONFIGURED);
1105 dwc3_ep0_do_control_status(dwc, event);
1106 }
1107
1108 return;
1109 }
1110
1111 dwc3_ep0_do_control_status(dwc, event);
1112 }
1113}
1114
1115void dwc3_ep0_interrupt(struct dwc3 *dwc,
1116 const struct dwc3_event_depevt *event)
1117{
1118 switch (event->endpoint_event) {
1119 case DWC3_DEPEVT_XFERCOMPLETE:
1120 dwc3_ep0_xfer_complete(dwc, event);
1121 break;
1122
1123 case DWC3_DEPEVT_XFERNOTREADY:
1124 dwc3_ep0_xfernotready(dwc, event);
1125 break;
1126
1127 case DWC3_DEPEVT_XFERINPROGRESS:
1128 case DWC3_DEPEVT_RXTXFIFOEVT:
1129 case DWC3_DEPEVT_STREAMEVT:
1130 case DWC3_DEPEVT_EPCMDCMPLT:
1131 break;
1132 }
1133}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#include <linux/kernel.h>
12#include <linux/slab.h>
13#include <linux/spinlock.h>
14#include <linux/platform_device.h>
15#include <linux/pm_runtime.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/list.h>
19#include <linux/dma-mapping.h>
20
21#include <linux/usb/ch9.h>
22#include <linux/usb/gadget.h>
23#include <linux/usb/composite.h>
24
25#include "core.h"
26#include "debug.h"
27#include "gadget.h"
28#include "io.h"
29
30static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
31static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
32 struct dwc3_ep *dep, struct dwc3_request *req);
33
34static void dwc3_ep0_prepare_one_trb(struct dwc3_ep *dep,
35 dma_addr_t buf_dma, u32 len, u32 type, bool chain)
36{
37 struct dwc3_trb *trb;
38 struct dwc3 *dwc;
39
40 dwc = dep->dwc;
41 trb = &dwc->ep0_trb[dep->trb_enqueue];
42
43 if (chain)
44 dep->trb_enqueue++;
45
46 trb->bpl = lower_32_bits(buf_dma);
47 trb->bph = upper_32_bits(buf_dma);
48 trb->size = len;
49 trb->ctrl = type;
50
51 trb->ctrl |= (DWC3_TRB_CTRL_HWO
52 | DWC3_TRB_CTRL_ISP_IMI);
53
54 if (chain)
55 trb->ctrl |= DWC3_TRB_CTRL_CHN;
56 else
57 trb->ctrl |= (DWC3_TRB_CTRL_IOC
58 | DWC3_TRB_CTRL_LST);
59
60 trace_dwc3_prepare_trb(dep, trb);
61}
62
63static int dwc3_ep0_start_trans(struct dwc3_ep *dep)
64{
65 struct dwc3_gadget_ep_cmd_params params;
66 struct dwc3 *dwc;
67 int ret;
68
69 if (dep->flags & DWC3_EP_TRANSFER_STARTED)
70 return 0;
71
72 dwc = dep->dwc;
73
74 memset(¶ms, 0, sizeof(params));
75 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
76 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
77
78 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, ¶ms);
79 if (ret < 0)
80 return ret;
81
82 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
83
84 return 0;
85}
86
87static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
88 struct dwc3_request *req)
89{
90 struct dwc3 *dwc = dep->dwc;
91
92 req->request.actual = 0;
93 req->request.status = -EINPROGRESS;
94 req->epnum = dep->number;
95
96 list_add_tail(&req->list, &dep->pending_list);
97
98 /*
99 * Gadget driver might not be quick enough to queue a request
100 * before we get a Transfer Not Ready event on this endpoint.
101 *
102 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
103 * flag is set, it's telling us that as soon as Gadget queues the
104 * required request, we should kick the transfer here because the
105 * IRQ we were waiting for is long gone.
106 */
107 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
108 unsigned int direction;
109
110 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
111
112 if (dwc->ep0state != EP0_DATA_PHASE) {
113 dev_WARN(dwc->dev, "Unexpected pending request\n");
114 return 0;
115 }
116
117 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
118
119 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
120 DWC3_EP0_DIR_IN);
121
122 return 0;
123 }
124
125 /*
126 * In case gadget driver asked us to delay the STATUS phase,
127 * handle it here.
128 */
129 if (dwc->delayed_status) {
130 unsigned int direction;
131
132 direction = !dwc->ep0_expect_in;
133 dwc->delayed_status = false;
134 usb_gadget_set_state(dwc->gadget, USB_STATE_CONFIGURED);
135
136 if (dwc->ep0state == EP0_STATUS_PHASE)
137 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
138
139 return 0;
140 }
141
142 /*
143 * Unfortunately we have uncovered a limitation wrt the Data Phase.
144 *
145 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
146 * come before issueing Start Transfer command, but if we do, we will
147 * miss situations where the host starts another SETUP phase instead of
148 * the DATA phase. Such cases happen at least on TD.7.6 of the Link
149 * Layer Compliance Suite.
150 *
151 * The problem surfaces due to the fact that in case of back-to-back
152 * SETUP packets there will be no XferNotReady(DATA) generated and we
153 * will be stuck waiting for XferNotReady(DATA) forever.
154 *
155 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
156 * it tells us to start Data Phase right away. It also mentions that if
157 * we receive a SETUP phase instead of the DATA phase, core will issue
158 * XferComplete for the DATA phase, before actually initiating it in
159 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
160 * can only be used to print some debugging logs, as the core expects
161 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
162 * just so it completes right away, without transferring anything and,
163 * only then, we can go back to the SETUP phase.
164 *
165 * Because of this scenario, SNPS decided to change the programming
166 * model of control transfers and support on-demand transfers only for
167 * the STATUS phase. To fix the issue we have now, we will always wait
168 * for gadget driver to queue the DATA phase's struct usb_request, then
169 * start it right away.
170 *
171 * If we're actually in a 2-stage transfer, we will wait for
172 * XferNotReady(STATUS).
173 */
174 if (dwc->three_stage_setup) {
175 unsigned int direction;
176
177 direction = dwc->ep0_expect_in;
178 dwc->ep0state = EP0_DATA_PHASE;
179
180 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
181
182 dep->flags &= ~DWC3_EP0_DIR_IN;
183 }
184
185 return 0;
186}
187
188int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
189 gfp_t gfp_flags)
190{
191 struct dwc3_request *req = to_dwc3_request(request);
192 struct dwc3_ep *dep = to_dwc3_ep(ep);
193 struct dwc3 *dwc = dep->dwc;
194
195 unsigned long flags;
196
197 int ret;
198
199 spin_lock_irqsave(&dwc->lock, flags);
200 if (!dep->endpoint.desc || !dwc->pullups_connected || !dwc->connected) {
201 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
202 dep->name);
203 ret = -ESHUTDOWN;
204 goto out;
205 }
206
207 /* we share one TRB for ep0/1 */
208 if (!list_empty(&dep->pending_list)) {
209 ret = -EBUSY;
210 goto out;
211 }
212
213 ret = __dwc3_gadget_ep0_queue(dep, req);
214
215out:
216 spin_unlock_irqrestore(&dwc->lock, flags);
217
218 return ret;
219}
220
221void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
222{
223 struct dwc3_ep *dep;
224
225 /* reinitialize physical ep1 */
226 dep = dwc->eps[1];
227 dep->flags = DWC3_EP_ENABLED;
228
229 /* stall is always issued on EP0 */
230 dep = dwc->eps[0];
231 __dwc3_gadget_ep_set_halt(dep, 1, false);
232 dep->flags = DWC3_EP_ENABLED;
233 dwc->delayed_status = false;
234
235 if (!list_empty(&dep->pending_list)) {
236 struct dwc3_request *req;
237
238 req = next_request(&dep->pending_list);
239 dwc3_gadget_giveback(dep, req, -ECONNRESET);
240 }
241
242 dwc->eps[0]->trb_enqueue = 0;
243 dwc->eps[1]->trb_enqueue = 0;
244 dwc->ep0state = EP0_SETUP_PHASE;
245 dwc3_ep0_out_start(dwc);
246}
247
248int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
249{
250 struct dwc3_ep *dep = to_dwc3_ep(ep);
251 struct dwc3 *dwc = dep->dwc;
252
253 dwc3_ep0_stall_and_restart(dwc);
254
255 return 0;
256}
257
258int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
259{
260 struct dwc3_ep *dep = to_dwc3_ep(ep);
261 struct dwc3 *dwc = dep->dwc;
262 unsigned long flags;
263 int ret;
264
265 spin_lock_irqsave(&dwc->lock, flags);
266 ret = __dwc3_gadget_ep0_set_halt(ep, value);
267 spin_unlock_irqrestore(&dwc->lock, flags);
268
269 return ret;
270}
271
272void dwc3_ep0_out_start(struct dwc3 *dwc)
273{
274 struct dwc3_ep *dep;
275 int ret;
276 int i;
277
278 complete(&dwc->ep0_in_setup);
279
280 dep = dwc->eps[0];
281 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 8,
282 DWC3_TRBCTL_CONTROL_SETUP, false);
283 ret = dwc3_ep0_start_trans(dep);
284 WARN_ON(ret < 0);
285 for (i = 2; i < DWC3_ENDPOINTS_NUM; i++) {
286 struct dwc3_ep *dwc3_ep;
287
288 dwc3_ep = dwc->eps[i];
289 if (!dwc3_ep)
290 continue;
291
292 if (!(dwc3_ep->flags & DWC3_EP_DELAY_STOP))
293 continue;
294
295 dwc3_ep->flags &= ~DWC3_EP_DELAY_STOP;
296 if (dwc->connected)
297 dwc3_stop_active_transfer(dwc3_ep, true, true);
298 else
299 dwc3_remove_requests(dwc, dwc3_ep, -ESHUTDOWN);
300 }
301}
302
303static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
304{
305 struct dwc3_ep *dep;
306 u32 windex = le16_to_cpu(wIndex_le);
307 u32 epnum;
308
309 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
310 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
311 epnum |= 1;
312
313 dep = dwc->eps[epnum];
314 if (dep == NULL)
315 return NULL;
316
317 if (dep->flags & DWC3_EP_ENABLED)
318 return dep;
319
320 return NULL;
321}
322
323static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
324{
325}
326/*
327 * ch 9.4.5
328 */
329static int dwc3_ep0_handle_status(struct dwc3 *dwc,
330 struct usb_ctrlrequest *ctrl)
331{
332 struct dwc3_ep *dep;
333 u32 recip;
334 u32 value;
335 u32 reg;
336 u16 usb_status = 0;
337 __le16 *response_pkt;
338
339 /* We don't support PTM_STATUS */
340 value = le16_to_cpu(ctrl->wValue);
341 if (value != 0)
342 return -EINVAL;
343
344 recip = ctrl->bRequestType & USB_RECIP_MASK;
345 switch (recip) {
346 case USB_RECIP_DEVICE:
347 /*
348 * LTM will be set once we know how to set this in HW.
349 */
350 usb_status |= dwc->gadget->is_selfpowered;
351
352 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
353 (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
354 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
355 if (reg & DWC3_DCTL_INITU1ENA)
356 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
357 if (reg & DWC3_DCTL_INITU2ENA)
358 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
359 }
360
361 break;
362
363 case USB_RECIP_INTERFACE:
364 /*
365 * Function Remote Wake Capable D0
366 * Function Remote Wakeup D1
367 */
368 break;
369
370 case USB_RECIP_ENDPOINT:
371 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
372 if (!dep)
373 return -EINVAL;
374
375 if (dep->flags & DWC3_EP_STALL)
376 usb_status = 1 << USB_ENDPOINT_HALT;
377 break;
378 default:
379 return -EINVAL;
380 }
381
382 response_pkt = (__le16 *) dwc->setup_buf;
383 *response_pkt = cpu_to_le16(usb_status);
384
385 dep = dwc->eps[0];
386 dwc->ep0_usb_req.dep = dep;
387 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
388 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
389 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
390
391 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
392}
393
394static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state,
395 int set)
396{
397 u32 reg;
398
399 if (state != USB_STATE_CONFIGURED)
400 return -EINVAL;
401 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
402 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
403 return -EINVAL;
404 if (set && dwc->dis_u1_entry_quirk)
405 return -EINVAL;
406
407 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
408 if (set)
409 reg |= DWC3_DCTL_INITU1ENA;
410 else
411 reg &= ~DWC3_DCTL_INITU1ENA;
412 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
413
414 return 0;
415}
416
417static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state,
418 int set)
419{
420 u32 reg;
421
422
423 if (state != USB_STATE_CONFIGURED)
424 return -EINVAL;
425 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
426 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
427 return -EINVAL;
428 if (set && dwc->dis_u2_entry_quirk)
429 return -EINVAL;
430
431 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
432 if (set)
433 reg |= DWC3_DCTL_INITU2ENA;
434 else
435 reg &= ~DWC3_DCTL_INITU2ENA;
436 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
437
438 return 0;
439}
440
441static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state,
442 u32 wIndex, int set)
443{
444 if ((wIndex & 0xff) != 0)
445 return -EINVAL;
446 if (!set)
447 return -EINVAL;
448
449 switch (wIndex >> 8) {
450 case USB_TEST_J:
451 case USB_TEST_K:
452 case USB_TEST_SE0_NAK:
453 case USB_TEST_PACKET:
454 case USB_TEST_FORCE_ENABLE:
455 dwc->test_mode_nr = wIndex >> 8;
456 dwc->test_mode = true;
457 break;
458 default:
459 return -EINVAL;
460 }
461
462 return 0;
463}
464
465static int dwc3_ep0_handle_device(struct dwc3 *dwc,
466 struct usb_ctrlrequest *ctrl, int set)
467{
468 enum usb_device_state state;
469 u32 wValue;
470 u32 wIndex;
471 int ret = 0;
472
473 wValue = le16_to_cpu(ctrl->wValue);
474 wIndex = le16_to_cpu(ctrl->wIndex);
475 state = dwc->gadget->state;
476
477 switch (wValue) {
478 case USB_DEVICE_REMOTE_WAKEUP:
479 break;
480 /*
481 * 9.4.1 says only for SS, in AddressState only for
482 * default control pipe
483 */
484 case USB_DEVICE_U1_ENABLE:
485 ret = dwc3_ep0_handle_u1(dwc, state, set);
486 break;
487 case USB_DEVICE_U2_ENABLE:
488 ret = dwc3_ep0_handle_u2(dwc, state, set);
489 break;
490 case USB_DEVICE_LTM_ENABLE:
491 ret = -EINVAL;
492 break;
493 case USB_DEVICE_TEST_MODE:
494 ret = dwc3_ep0_handle_test(dwc, state, wIndex, set);
495 break;
496 default:
497 ret = -EINVAL;
498 }
499
500 return ret;
501}
502
503static int dwc3_ep0_handle_intf(struct dwc3 *dwc,
504 struct usb_ctrlrequest *ctrl, int set)
505{
506 u32 wValue;
507 int ret = 0;
508
509 wValue = le16_to_cpu(ctrl->wValue);
510
511 switch (wValue) {
512 case USB_INTRF_FUNC_SUSPEND:
513 /*
514 * REVISIT: Ideally we would enable some low power mode here,
515 * however it's unclear what we should be doing here.
516 *
517 * For now, we're not doing anything, just making sure we return
518 * 0 so USB Command Verifier tests pass without any errors.
519 */
520 break;
521 default:
522 ret = -EINVAL;
523 }
524
525 return ret;
526}
527
528static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc,
529 struct usb_ctrlrequest *ctrl, int set)
530{
531 struct dwc3_ep *dep;
532 u32 wValue;
533 int ret;
534
535 wValue = le16_to_cpu(ctrl->wValue);
536
537 switch (wValue) {
538 case USB_ENDPOINT_HALT:
539 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
540 if (!dep)
541 return -EINVAL;
542
543 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
544 break;
545
546 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
547 if (ret)
548 return -EINVAL;
549
550 /* ClearFeature(Halt) may need delayed status */
551 if (!set && (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
552 return USB_GADGET_DELAYED_STATUS;
553
554 break;
555 default:
556 return -EINVAL;
557 }
558
559 return 0;
560}
561
562static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
563 struct usb_ctrlrequest *ctrl, int set)
564{
565 u32 recip;
566 int ret;
567
568 recip = ctrl->bRequestType & USB_RECIP_MASK;
569
570 switch (recip) {
571 case USB_RECIP_DEVICE:
572 ret = dwc3_ep0_handle_device(dwc, ctrl, set);
573 break;
574 case USB_RECIP_INTERFACE:
575 ret = dwc3_ep0_handle_intf(dwc, ctrl, set);
576 break;
577 case USB_RECIP_ENDPOINT:
578 ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set);
579 break;
580 default:
581 ret = -EINVAL;
582 }
583
584 return ret;
585}
586
587static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
588{
589 enum usb_device_state state = dwc->gadget->state;
590 u32 addr;
591 u32 reg;
592
593 addr = le16_to_cpu(ctrl->wValue);
594 if (addr > 127) {
595 dev_err(dwc->dev, "invalid device address %d\n", addr);
596 return -EINVAL;
597 }
598
599 if (state == USB_STATE_CONFIGURED) {
600 dev_err(dwc->dev, "can't SetAddress() from Configured State\n");
601 return -EINVAL;
602 }
603
604 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
605 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
606 reg |= DWC3_DCFG_DEVADDR(addr);
607 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
608
609 if (addr)
610 usb_gadget_set_state(dwc->gadget, USB_STATE_ADDRESS);
611 else
612 usb_gadget_set_state(dwc->gadget, USB_STATE_DEFAULT);
613
614 return 0;
615}
616
617static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
618{
619 int ret = -EINVAL;
620
621 if (dwc->async_callbacks) {
622 spin_unlock(&dwc->lock);
623 ret = dwc->gadget_driver->setup(dwc->gadget, ctrl);
624 spin_lock(&dwc->lock);
625 }
626 return ret;
627}
628
629static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
630{
631 enum usb_device_state state = dwc->gadget->state;
632 u32 cfg;
633 int ret;
634 u32 reg;
635
636 cfg = le16_to_cpu(ctrl->wValue);
637
638 switch (state) {
639 case USB_STATE_DEFAULT:
640 return -EINVAL;
641
642 case USB_STATE_ADDRESS:
643 dwc3_gadget_clear_tx_fifos(dwc);
644
645 ret = dwc3_ep0_delegate_req(dwc, ctrl);
646 /* if the cfg matches and the cfg is non zero */
647 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
648
649 /*
650 * only change state if set_config has already
651 * been processed. If gadget driver returns
652 * USB_GADGET_DELAYED_STATUS, we will wait
653 * to change the state on the next usb_ep_queue()
654 */
655 if (ret == 0)
656 usb_gadget_set_state(dwc->gadget,
657 USB_STATE_CONFIGURED);
658
659 /*
660 * Enable transition to U1/U2 state when
661 * nothing is pending from application.
662 */
663 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
664 if (!dwc->dis_u1_entry_quirk)
665 reg |= DWC3_DCTL_ACCEPTU1ENA;
666 if (!dwc->dis_u2_entry_quirk)
667 reg |= DWC3_DCTL_ACCEPTU2ENA;
668 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
669 }
670 break;
671
672 case USB_STATE_CONFIGURED:
673 ret = dwc3_ep0_delegate_req(dwc, ctrl);
674 if (!cfg && !ret)
675 usb_gadget_set_state(dwc->gadget,
676 USB_STATE_ADDRESS);
677 break;
678 default:
679 ret = -EINVAL;
680 }
681 return ret;
682}
683
684static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
685{
686 struct dwc3_ep *dep = to_dwc3_ep(ep);
687 struct dwc3 *dwc = dep->dwc;
688
689 u32 param = 0;
690 u32 reg;
691
692 struct timing {
693 u8 u1sel;
694 u8 u1pel;
695 __le16 u2sel;
696 __le16 u2pel;
697 } __packed timing;
698
699 int ret;
700
701 memcpy(&timing, req->buf, sizeof(timing));
702
703 dwc->u1sel = timing.u1sel;
704 dwc->u1pel = timing.u1pel;
705 dwc->u2sel = le16_to_cpu(timing.u2sel);
706 dwc->u2pel = le16_to_cpu(timing.u2pel);
707
708 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
709 if (reg & DWC3_DCTL_INITU2ENA)
710 param = dwc->u2pel;
711 if (reg & DWC3_DCTL_INITU1ENA)
712 param = dwc->u1pel;
713
714 /*
715 * According to Synopsys Databook, if parameter is
716 * greater than 125, a value of zero should be
717 * programmed in the register.
718 */
719 if (param > 125)
720 param = 0;
721
722 /* now that we have the time, issue DGCMD Set Sel */
723 ret = dwc3_send_gadget_generic_command(dwc,
724 DWC3_DGCMD_SET_PERIODIC_PAR, param);
725 WARN_ON(ret < 0);
726}
727
728static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
729{
730 struct dwc3_ep *dep;
731 enum usb_device_state state = dwc->gadget->state;
732 u16 wLength;
733
734 if (state == USB_STATE_DEFAULT)
735 return -EINVAL;
736
737 wLength = le16_to_cpu(ctrl->wLength);
738
739 if (wLength != 6) {
740 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
741 wLength);
742 return -EINVAL;
743 }
744
745 /*
746 * To handle Set SEL we need to receive 6 bytes from Host. So let's
747 * queue a usb_request for 6 bytes.
748 *
749 * Remember, though, this controller can't handle non-wMaxPacketSize
750 * aligned transfers on the OUT direction, so we queue a request for
751 * wMaxPacketSize instead.
752 */
753 dep = dwc->eps[0];
754 dwc->ep0_usb_req.dep = dep;
755 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
756 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
757 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
758
759 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
760}
761
762static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
763{
764 u16 wLength;
765 u16 wValue;
766 u16 wIndex;
767
768 wValue = le16_to_cpu(ctrl->wValue);
769 wLength = le16_to_cpu(ctrl->wLength);
770 wIndex = le16_to_cpu(ctrl->wIndex);
771
772 if (wIndex || wLength)
773 return -EINVAL;
774
775 dwc->gadget->isoch_delay = wValue;
776
777 return 0;
778}
779
780static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
781{
782 int ret;
783
784 switch (ctrl->bRequest) {
785 case USB_REQ_GET_STATUS:
786 ret = dwc3_ep0_handle_status(dwc, ctrl);
787 break;
788 case USB_REQ_CLEAR_FEATURE:
789 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
790 break;
791 case USB_REQ_SET_FEATURE:
792 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
793 break;
794 case USB_REQ_SET_ADDRESS:
795 ret = dwc3_ep0_set_address(dwc, ctrl);
796 break;
797 case USB_REQ_SET_CONFIGURATION:
798 ret = dwc3_ep0_set_config(dwc, ctrl);
799 break;
800 case USB_REQ_SET_SEL:
801 ret = dwc3_ep0_set_sel(dwc, ctrl);
802 break;
803 case USB_REQ_SET_ISOCH_DELAY:
804 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
805 break;
806 default:
807 ret = dwc3_ep0_delegate_req(dwc, ctrl);
808 break;
809 }
810
811 return ret;
812}
813
814static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
815 const struct dwc3_event_depevt *event)
816{
817 struct usb_ctrlrequest *ctrl = (void *) dwc->ep0_trb;
818 int ret = -EINVAL;
819 u32 len;
820
821 if (!dwc->gadget_driver || !dwc->softconnect || !dwc->connected)
822 goto out;
823
824 trace_dwc3_ctrl_req(ctrl);
825
826 len = le16_to_cpu(ctrl->wLength);
827 if (!len) {
828 dwc->three_stage_setup = false;
829 dwc->ep0_expect_in = false;
830 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
831 } else {
832 dwc->three_stage_setup = true;
833 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
834 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
835 }
836
837 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
838 ret = dwc3_ep0_std_request(dwc, ctrl);
839 else
840 ret = dwc3_ep0_delegate_req(dwc, ctrl);
841
842 if (ret == USB_GADGET_DELAYED_STATUS)
843 dwc->delayed_status = true;
844
845out:
846 if (ret < 0)
847 dwc3_ep0_stall_and_restart(dwc);
848}
849
850static void dwc3_ep0_complete_data(struct dwc3 *dwc,
851 const struct dwc3_event_depevt *event)
852{
853 struct dwc3_request *r;
854 struct usb_request *ur;
855 struct dwc3_trb *trb;
856 struct dwc3_ep *ep0;
857 u32 transferred = 0;
858 u32 status;
859 u32 length;
860 u8 epnum;
861
862 epnum = event->endpoint_number;
863 ep0 = dwc->eps[0];
864
865 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
866 trb = dwc->ep0_trb;
867 trace_dwc3_complete_trb(ep0, trb);
868
869 r = next_request(&ep0->pending_list);
870 if (!r)
871 return;
872
873 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
874 if (status == DWC3_TRBSTS_SETUP_PENDING) {
875 dwc->setup_packet_pending = true;
876 if (r)
877 dwc3_gadget_giveback(ep0, r, -ECONNRESET);
878
879 return;
880 }
881
882 ur = &r->request;
883
884 length = trb->size & DWC3_TRB_SIZE_MASK;
885 transferred = ur->length - length;
886 ur->actual += transferred;
887
888 if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
889 ur->length && ur->zero) || dwc->ep0_bounced) {
890 trb++;
891 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
892 trace_dwc3_complete_trb(ep0, trb);
893
894 if (r->direction)
895 dwc->eps[1]->trb_enqueue = 0;
896 else
897 dwc->eps[0]->trb_enqueue = 0;
898
899 dwc->ep0_bounced = false;
900 }
901
902 if ((epnum & 1) && ur->actual < ur->length)
903 dwc3_ep0_stall_and_restart(dwc);
904 else
905 dwc3_gadget_giveback(ep0, r, 0);
906}
907
908static void dwc3_ep0_complete_status(struct dwc3 *dwc,
909 const struct dwc3_event_depevt *event)
910{
911 struct dwc3_request *r;
912 struct dwc3_ep *dep;
913 struct dwc3_trb *trb;
914 u32 status;
915
916 dep = dwc->eps[0];
917 trb = dwc->ep0_trb;
918
919 trace_dwc3_complete_trb(dep, trb);
920
921 if (!list_empty(&dep->pending_list)) {
922 r = next_request(&dep->pending_list);
923
924 dwc3_gadget_giveback(dep, r, 0);
925 }
926
927 if (dwc->test_mode) {
928 int ret;
929
930 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
931 if (ret < 0) {
932 dev_err(dwc->dev, "invalid test #%d\n",
933 dwc->test_mode_nr);
934 dwc3_ep0_stall_and_restart(dwc);
935 return;
936 }
937 }
938
939 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
940 if (status == DWC3_TRBSTS_SETUP_PENDING)
941 dwc->setup_packet_pending = true;
942
943 dwc->ep0state = EP0_SETUP_PHASE;
944 dwc3_ep0_out_start(dwc);
945}
946
947static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
948 const struct dwc3_event_depevt *event)
949{
950 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
951
952 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
953 dep->resource_index = 0;
954 dwc->setup_packet_pending = false;
955
956 switch (dwc->ep0state) {
957 case EP0_SETUP_PHASE:
958 dwc3_ep0_inspect_setup(dwc, event);
959 break;
960
961 case EP0_DATA_PHASE:
962 dwc3_ep0_complete_data(dwc, event);
963 break;
964
965 case EP0_STATUS_PHASE:
966 dwc3_ep0_complete_status(dwc, event);
967 break;
968 default:
969 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
970 }
971}
972
973static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
974 struct dwc3_ep *dep, struct dwc3_request *req)
975{
976 unsigned int trb_length = 0;
977 int ret;
978
979 req->direction = !!dep->number;
980
981 if (req->request.length == 0) {
982 if (!req->direction)
983 trb_length = dep->endpoint.maxpacket;
984
985 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, trb_length,
986 DWC3_TRBCTL_CONTROL_DATA, false);
987 ret = dwc3_ep0_start_trans(dep);
988 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
989 && (dep->number == 0)) {
990 u32 maxpacket;
991 u32 rem;
992
993 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
994 &req->request, dep->number);
995 if (ret)
996 return;
997
998 maxpacket = dep->endpoint.maxpacket;
999 rem = req->request.length % maxpacket;
1000 dwc->ep0_bounced = true;
1001
1002 /* prepare normal TRB */
1003 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1004 req->request.length,
1005 DWC3_TRBCTL_CONTROL_DATA,
1006 true);
1007
1008 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
1009
1010 /* Now prepare one extra TRB to align transfer size */
1011 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
1012 maxpacket - rem,
1013 DWC3_TRBCTL_CONTROL_DATA,
1014 false);
1015 ret = dwc3_ep0_start_trans(dep);
1016 } else if (IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) &&
1017 req->request.length && req->request.zero) {
1018
1019 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1020 &req->request, dep->number);
1021 if (ret)
1022 return;
1023
1024 /* prepare normal TRB */
1025 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1026 req->request.length,
1027 DWC3_TRBCTL_CONTROL_DATA,
1028 true);
1029
1030 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
1031
1032 if (!req->direction)
1033 trb_length = dep->endpoint.maxpacket;
1034
1035 /* Now prepare one extra TRB to align transfer size */
1036 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
1037 trb_length, DWC3_TRBCTL_CONTROL_DATA,
1038 false);
1039 ret = dwc3_ep0_start_trans(dep);
1040 } else {
1041 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1042 &req->request, dep->number);
1043 if (ret)
1044 return;
1045
1046 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1047 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1048 false);
1049
1050 req->trb = &dwc->ep0_trb[dep->trb_enqueue];
1051
1052 ret = dwc3_ep0_start_trans(dep);
1053 }
1054
1055 WARN_ON(ret < 0);
1056}
1057
1058static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1059{
1060 struct dwc3 *dwc = dep->dwc;
1061 u32 type;
1062
1063 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1064 : DWC3_TRBCTL_CONTROL_STATUS2;
1065
1066 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0, type, false);
1067 return dwc3_ep0_start_trans(dep);
1068}
1069
1070static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1071{
1072 WARN_ON(dwc3_ep0_start_control_status(dep));
1073}
1074
1075static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1076 const struct dwc3_event_depevt *event)
1077{
1078 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
1079
1080 __dwc3_ep0_do_control_status(dwc, dep);
1081}
1082
1083void dwc3_ep0_send_delayed_status(struct dwc3 *dwc)
1084{
1085 unsigned int direction = !dwc->ep0_expect_in;
1086
1087 dwc->delayed_status = false;
1088 dwc->clear_stall_protocol = 0;
1089
1090 if (dwc->ep0state != EP0_STATUS_PHASE)
1091 return;
1092
1093 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
1094}
1095
1096void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1097{
1098 struct dwc3_gadget_ep_cmd_params params;
1099 u32 cmd;
1100 int ret;
1101
1102 /*
1103 * For status/DATA OUT stage, TRB will be queued on ep0 out
1104 * endpoint for which resource index is zero. Hence allow
1105 * queuing ENDXFER command for ep0 out endpoint.
1106 */
1107 if (!dep->resource_index && dep->number)
1108 return;
1109
1110 cmd = DWC3_DEPCMD_ENDTRANSFER;
1111 cmd |= DWC3_DEPCMD_CMDIOC;
1112 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1113 memset(¶ms, 0, sizeof(params));
1114 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1115 WARN_ON_ONCE(ret);
1116 dep->resource_index = 0;
1117}
1118
1119static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1120 const struct dwc3_event_depevt *event)
1121{
1122 switch (event->status) {
1123 case DEPEVT_STATUS_CONTROL_DATA:
1124 if (!dwc->softconnect || !dwc->connected)
1125 return;
1126 /*
1127 * We already have a DATA transfer in the controller's cache,
1128 * if we receive a XferNotReady(DATA) we will ignore it, unless
1129 * it's for the wrong direction.
1130 *
1131 * In that case, we must issue END_TRANSFER command to the Data
1132 * Phase we already have started and issue SetStall on the
1133 * control endpoint.
1134 */
1135 if (dwc->ep0_expect_in != event->endpoint_number) {
1136 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
1137
1138 dev_err(dwc->dev, "unexpected direction for Data Phase\n");
1139 dwc3_ep0_end_control_data(dwc, dep);
1140 dwc3_ep0_stall_and_restart(dwc);
1141 return;
1142 }
1143
1144 break;
1145
1146 case DEPEVT_STATUS_CONTROL_STATUS:
1147 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1148 return;
1149
1150 if (dwc->setup_packet_pending) {
1151 dwc3_ep0_stall_and_restart(dwc);
1152 return;
1153 }
1154
1155 dwc->ep0state = EP0_STATUS_PHASE;
1156
1157 if (dwc->delayed_status) {
1158 struct dwc3_ep *dep = dwc->eps[0];
1159
1160 WARN_ON_ONCE(event->endpoint_number != 1);
1161 /*
1162 * We should handle the delay STATUS phase here if the
1163 * request for handling delay STATUS has been queued
1164 * into the list.
1165 */
1166 if (!list_empty(&dep->pending_list)) {
1167 dwc->delayed_status = false;
1168 usb_gadget_set_state(dwc->gadget,
1169 USB_STATE_CONFIGURED);
1170 dwc3_ep0_do_control_status(dwc, event);
1171 }
1172
1173 return;
1174 }
1175
1176 dwc3_ep0_do_control_status(dwc, event);
1177 }
1178}
1179
1180void dwc3_ep0_interrupt(struct dwc3 *dwc,
1181 const struct dwc3_event_depevt *event)
1182{
1183 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
1184 u8 cmd;
1185
1186 switch (event->endpoint_event) {
1187 case DWC3_DEPEVT_XFERCOMPLETE:
1188 dwc3_ep0_xfer_complete(dwc, event);
1189 break;
1190
1191 case DWC3_DEPEVT_XFERNOTREADY:
1192 dwc3_ep0_xfernotready(dwc, event);
1193 break;
1194
1195 case DWC3_DEPEVT_XFERINPROGRESS:
1196 case DWC3_DEPEVT_RXTXFIFOEVT:
1197 case DWC3_DEPEVT_STREAMEVT:
1198 break;
1199 case DWC3_DEPEVT_EPCMDCMPLT:
1200 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
1201
1202 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
1203 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
1204 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
1205 }
1206 break;
1207 }
1208}