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1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/* Copyright 2020 NXP
3 * Lynx PCS MDIO helpers
4 */
5
6#include <linux/mdio.h>
7#include <linux/phylink.h>
8#include <linux/pcs-lynx.h>
9
10#define SGMII_CLOCK_PERIOD_NS 8 /* PCS is clocked at 125 MHz */
11#define LINK_TIMER_VAL(ns) ((u32)((ns) / SGMII_CLOCK_PERIOD_NS))
12
13#define SGMII_AN_LINK_TIMER_NS 1600000 /* defined by SGMII spec */
14#define IEEE8023_LINK_TIMER_NS 10000000
15
16#define LINK_TIMER_LO 0x12
17#define LINK_TIMER_HI 0x13
18#define IF_MODE 0x14
19#define IF_MODE_SGMII_EN BIT(0)
20#define IF_MODE_USE_SGMII_AN BIT(1)
21#define IF_MODE_SPEED(x) (((x) << 2) & GENMASK(3, 2))
22#define IF_MODE_SPEED_MSK GENMASK(3, 2)
23#define IF_MODE_HALF_DUPLEX BIT(4)
24
25struct lynx_pcs {
26 struct phylink_pcs pcs;
27 struct mdio_device *mdio;
28};
29
30enum sgmii_speed {
31 SGMII_SPEED_10 = 0,
32 SGMII_SPEED_100 = 1,
33 SGMII_SPEED_1000 = 2,
34 SGMII_SPEED_2500 = 2,
35};
36
37#define phylink_pcs_to_lynx(pl_pcs) container_of((pl_pcs), struct lynx_pcs, pcs)
38#define lynx_to_phylink_pcs(lynx) (&(lynx)->pcs)
39
40struct mdio_device *lynx_get_mdio_device(struct phylink_pcs *pcs)
41{
42 struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs);
43
44 return lynx->mdio;
45}
46EXPORT_SYMBOL(lynx_get_mdio_device);
47
48static void lynx_pcs_get_state_usxgmii(struct mdio_device *pcs,
49 struct phylink_link_state *state)
50{
51 struct mii_bus *bus = pcs->bus;
52 int addr = pcs->addr;
53 int status, lpa;
54
55 status = mdiobus_c45_read(bus, addr, MDIO_MMD_VEND2, MII_BMSR);
56 if (status < 0)
57 return;
58
59 state->link = !!(status & MDIO_STAT1_LSTATUS);
60 state->an_complete = !!(status & MDIO_AN_STAT1_COMPLETE);
61 if (!state->link || !state->an_complete)
62 return;
63
64 lpa = mdiobus_c45_read(bus, addr, MDIO_MMD_VEND2, MII_LPA);
65 if (lpa < 0)
66 return;
67
68 phylink_decode_usxgmii_word(state, lpa);
69}
70
71static void lynx_pcs_get_state_2500basex(struct mdio_device *pcs,
72 struct phylink_link_state *state)
73{
74 int bmsr, lpa;
75
76 bmsr = mdiodev_read(pcs, MII_BMSR);
77 lpa = mdiodev_read(pcs, MII_LPA);
78 if (bmsr < 0 || lpa < 0) {
79 state->link = false;
80 return;
81 }
82
83 state->link = !!(bmsr & BMSR_LSTATUS);
84 state->an_complete = !!(bmsr & BMSR_ANEGCOMPLETE);
85 if (!state->link)
86 return;
87
88 state->speed = SPEED_2500;
89 state->pause |= MLO_PAUSE_TX | MLO_PAUSE_RX;
90 state->duplex = DUPLEX_FULL;
91}
92
93static void lynx_pcs_get_state(struct phylink_pcs *pcs,
94 struct phylink_link_state *state)
95{
96 struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs);
97
98 switch (state->interface) {
99 case PHY_INTERFACE_MODE_1000BASEX:
100 case PHY_INTERFACE_MODE_SGMII:
101 case PHY_INTERFACE_MODE_QSGMII:
102 phylink_mii_c22_pcs_get_state(lynx->mdio, state);
103 break;
104 case PHY_INTERFACE_MODE_2500BASEX:
105 lynx_pcs_get_state_2500basex(lynx->mdio, state);
106 break;
107 case PHY_INTERFACE_MODE_USXGMII:
108 lynx_pcs_get_state_usxgmii(lynx->mdio, state);
109 break;
110 case PHY_INTERFACE_MODE_10GBASER:
111 phylink_mii_c45_pcs_get_state(lynx->mdio, state);
112 break;
113 default:
114 break;
115 }
116
117 dev_dbg(&lynx->mdio->dev,
118 "mode=%s/%s/%s link=%u an_enabled=%u an_complete=%u\n",
119 phy_modes(state->interface),
120 phy_speed_to_str(state->speed),
121 phy_duplex_to_str(state->duplex),
122 state->link, state->an_enabled, state->an_complete);
123}
124
125static int lynx_pcs_config_giga(struct mdio_device *pcs, unsigned int mode,
126 phy_interface_t interface,
127 const unsigned long *advertising)
128{
129 u32 link_timer;
130 u16 if_mode;
131 int err;
132
133 if (interface == PHY_INTERFACE_MODE_1000BASEX) {
134 link_timer = LINK_TIMER_VAL(IEEE8023_LINK_TIMER_NS);
135 mdiodev_write(pcs, LINK_TIMER_LO, link_timer & 0xffff);
136 mdiodev_write(pcs, LINK_TIMER_HI, link_timer >> 16);
137
138 if_mode = 0;
139 } else {
140 if_mode = IF_MODE_SGMII_EN;
141 if (mode == MLO_AN_INBAND) {
142 if_mode |= IF_MODE_USE_SGMII_AN;
143
144 /* Adjust link timer for SGMII */
145 link_timer = LINK_TIMER_VAL(SGMII_AN_LINK_TIMER_NS);
146 mdiodev_write(pcs, LINK_TIMER_LO, link_timer & 0xffff);
147 mdiodev_write(pcs, LINK_TIMER_HI, link_timer >> 16);
148 }
149 }
150
151 err = mdiodev_modify(pcs, IF_MODE,
152 IF_MODE_SGMII_EN | IF_MODE_USE_SGMII_AN,
153 if_mode);
154 if (err)
155 return err;
156
157 return phylink_mii_c22_pcs_config(pcs, mode, interface, advertising);
158}
159
160static int lynx_pcs_config_usxgmii(struct mdio_device *pcs, unsigned int mode,
161 const unsigned long *advertising)
162{
163 struct mii_bus *bus = pcs->bus;
164 int addr = pcs->addr;
165
166 if (!phylink_autoneg_inband(mode)) {
167 dev_err(&pcs->dev, "USXGMII only supports in-band AN for now\n");
168 return -EOPNOTSUPP;
169 }
170
171 /* Configure device ability for the USXGMII Replicator */
172 return mdiobus_c45_write(bus, addr, MDIO_MMD_VEND2, MII_ADVERTISE,
173 MDIO_USXGMII_10G | MDIO_USXGMII_LINK |
174 MDIO_USXGMII_FULL_DUPLEX |
175 ADVERTISE_SGMII | ADVERTISE_LPACK);
176}
177
178static int lynx_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
179 phy_interface_t ifmode,
180 const unsigned long *advertising,
181 bool permit)
182{
183 struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs);
184
185 switch (ifmode) {
186 case PHY_INTERFACE_MODE_1000BASEX:
187 case PHY_INTERFACE_MODE_SGMII:
188 case PHY_INTERFACE_MODE_QSGMII:
189 return lynx_pcs_config_giga(lynx->mdio, mode, ifmode,
190 advertising);
191 case PHY_INTERFACE_MODE_2500BASEX:
192 if (phylink_autoneg_inband(mode)) {
193 dev_err(&lynx->mdio->dev,
194 "AN not supported on 3.125GHz SerDes lane\n");
195 return -EOPNOTSUPP;
196 }
197 break;
198 case PHY_INTERFACE_MODE_USXGMII:
199 return lynx_pcs_config_usxgmii(lynx->mdio, mode, advertising);
200 case PHY_INTERFACE_MODE_10GBASER:
201 /* Nothing to do here for 10GBASER */
202 break;
203 default:
204 return -EOPNOTSUPP;
205 }
206
207 return 0;
208}
209
210static void lynx_pcs_an_restart(struct phylink_pcs *pcs)
211{
212 struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs);
213
214 phylink_mii_c22_pcs_an_restart(lynx->mdio);
215}
216
217static void lynx_pcs_link_up_sgmii(struct mdio_device *pcs, unsigned int mode,
218 int speed, int duplex)
219{
220 u16 if_mode = 0, sgmii_speed;
221
222 /* The PCS needs to be configured manually only
223 * when not operating on in-band mode
224 */
225 if (mode == MLO_AN_INBAND)
226 return;
227
228 if (duplex == DUPLEX_HALF)
229 if_mode |= IF_MODE_HALF_DUPLEX;
230
231 switch (speed) {
232 case SPEED_1000:
233 sgmii_speed = SGMII_SPEED_1000;
234 break;
235 case SPEED_100:
236 sgmii_speed = SGMII_SPEED_100;
237 break;
238 case SPEED_10:
239 sgmii_speed = SGMII_SPEED_10;
240 break;
241 case SPEED_UNKNOWN:
242 /* Silently don't do anything */
243 return;
244 default:
245 dev_err(&pcs->dev, "Invalid PCS speed %d\n", speed);
246 return;
247 }
248 if_mode |= IF_MODE_SPEED(sgmii_speed);
249
250 mdiodev_modify(pcs, IF_MODE,
251 IF_MODE_HALF_DUPLEX | IF_MODE_SPEED_MSK,
252 if_mode);
253}
254
255/* 2500Base-X is SerDes protocol 7 on Felix and 6 on ENETC. It is a SerDes lane
256 * clocked at 3.125 GHz which encodes symbols with 8b/10b and does not have
257 * auto-negotiation of any link parameters. Electrically it is compatible with
258 * a single lane of XAUI.
259 * The hardware reference manual wants to call this mode SGMII, but it isn't
260 * really, since the fundamental features of SGMII:
261 * - Downgrading the link speed by duplicating symbols
262 * - Auto-negotiation
263 * are not there.
264 * The speed is configured at 1000 in the IF_MODE because the clock frequency
265 * is actually given by a PLL configured in the Reset Configuration Word (RCW).
266 * Since there is no difference between fixed speed SGMII w/o AN and 802.3z w/o
267 * AN, we call this PHY interface type 2500Base-X. In case a PHY negotiates a
268 * lower link speed on line side, the system-side interface remains fixed at
269 * 2500 Mbps and we do rate adaptation through pause frames.
270 */
271static void lynx_pcs_link_up_2500basex(struct mdio_device *pcs,
272 unsigned int mode,
273 int speed, int duplex)
274{
275 u16 if_mode = 0;
276
277 if (mode == MLO_AN_INBAND) {
278 dev_err(&pcs->dev, "AN not supported for 2500BaseX\n");
279 return;
280 }
281
282 if (duplex == DUPLEX_HALF)
283 if_mode |= IF_MODE_HALF_DUPLEX;
284 if_mode |= IF_MODE_SPEED(SGMII_SPEED_2500);
285
286 mdiodev_modify(pcs, IF_MODE,
287 IF_MODE_HALF_DUPLEX | IF_MODE_SPEED_MSK,
288 if_mode);
289}
290
291static void lynx_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
292 phy_interface_t interface,
293 int speed, int duplex)
294{
295 struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs);
296
297 switch (interface) {
298 case PHY_INTERFACE_MODE_SGMII:
299 case PHY_INTERFACE_MODE_QSGMII:
300 lynx_pcs_link_up_sgmii(lynx->mdio, mode, speed, duplex);
301 break;
302 case PHY_INTERFACE_MODE_2500BASEX:
303 lynx_pcs_link_up_2500basex(lynx->mdio, mode, speed, duplex);
304 break;
305 case PHY_INTERFACE_MODE_USXGMII:
306 /* At the moment, only in-band AN is supported for USXGMII
307 * so nothing to do in link_up
308 */
309 break;
310 default:
311 break;
312 }
313}
314
315static const struct phylink_pcs_ops lynx_pcs_phylink_ops = {
316 .pcs_get_state = lynx_pcs_get_state,
317 .pcs_config = lynx_pcs_config,
318 .pcs_an_restart = lynx_pcs_an_restart,
319 .pcs_link_up = lynx_pcs_link_up,
320};
321
322struct phylink_pcs *lynx_pcs_create(struct mdio_device *mdio)
323{
324 struct lynx_pcs *lynx;
325
326 lynx = kzalloc(sizeof(*lynx), GFP_KERNEL);
327 if (!lynx)
328 return NULL;
329
330 lynx->mdio = mdio;
331 lynx->pcs.ops = &lynx_pcs_phylink_ops;
332 lynx->pcs.poll = true;
333
334 return lynx_to_phylink_pcs(lynx);
335}
336EXPORT_SYMBOL(lynx_pcs_create);
337
338void lynx_pcs_destroy(struct phylink_pcs *pcs)
339{
340 struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs);
341
342 kfree(lynx);
343}
344EXPORT_SYMBOL(lynx_pcs_destroy);
345
346MODULE_LICENSE("Dual BSD/GPL");