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1/*
2 * Copyright (c) 2015 MediaTek Inc.
3 * Author: YT SHEN <yt.shen@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <drm/drmP.h>
16#include <drm/drm_atomic.h>
17#include <drm/drm_atomic_helper.h>
18#include <drm/drm_crtc_helper.h>
19#include <drm/drm_gem.h>
20#include <drm/drm_gem_cma_helper.h>
21#include <drm/drm_of.h>
22#include <linux/component.h>
23#include <linux/iommu.h>
24#include <linux/of_address.h>
25#include <linux/of_platform.h>
26#include <linux/pm_runtime.h>
27
28#include "mtk_drm_crtc.h"
29#include "mtk_drm_ddp.h"
30#include "mtk_drm_ddp_comp.h"
31#include "mtk_drm_drv.h"
32#include "mtk_drm_fb.h"
33#include "mtk_drm_gem.h"
34
35#define DRIVER_NAME "mediatek"
36#define DRIVER_DESC "Mediatek SoC DRM"
37#define DRIVER_DATE "20150513"
38#define DRIVER_MAJOR 1
39#define DRIVER_MINOR 0
40
41static void mtk_atomic_schedule(struct mtk_drm_private *private,
42 struct drm_atomic_state *state)
43{
44 private->commit.state = state;
45 schedule_work(&private->commit.work);
46}
47
48static void mtk_atomic_wait_for_fences(struct drm_atomic_state *state)
49{
50 struct drm_plane *plane;
51 struct drm_plane_state *new_plane_state;
52 int i;
53
54 for_each_new_plane_in_state(state, plane, new_plane_state, i)
55 mtk_fb_wait(new_plane_state->fb);
56}
57
58static void mtk_atomic_complete(struct mtk_drm_private *private,
59 struct drm_atomic_state *state)
60{
61 struct drm_device *drm = private->drm;
62
63 mtk_atomic_wait_for_fences(state);
64
65 /*
66 * Mediatek drm supports runtime PM, so plane registers cannot be
67 * written when their crtc is disabled.
68 *
69 * The comment for drm_atomic_helper_commit states:
70 * For drivers supporting runtime PM the recommended sequence is
71 *
72 * drm_atomic_helper_commit_modeset_disables(dev, state);
73 * drm_atomic_helper_commit_modeset_enables(dev, state);
74 * drm_atomic_helper_commit_planes(dev, state,
75 * DRM_PLANE_COMMIT_ACTIVE_ONLY);
76 *
77 * See the kerneldoc entries for these three functions for more details.
78 */
79 drm_atomic_helper_commit_modeset_disables(drm, state);
80 drm_atomic_helper_commit_modeset_enables(drm, state);
81 drm_atomic_helper_commit_planes(drm, state,
82 DRM_PLANE_COMMIT_ACTIVE_ONLY);
83
84 drm_atomic_helper_wait_for_vblanks(drm, state);
85
86 drm_atomic_helper_cleanup_planes(drm, state);
87 drm_atomic_state_put(state);
88}
89
90static void mtk_atomic_work(struct work_struct *work)
91{
92 struct mtk_drm_private *private = container_of(work,
93 struct mtk_drm_private, commit.work);
94
95 mtk_atomic_complete(private, private->commit.state);
96}
97
98static int mtk_atomic_commit(struct drm_device *drm,
99 struct drm_atomic_state *state,
100 bool async)
101{
102 struct mtk_drm_private *private = drm->dev_private;
103 int ret;
104
105 ret = drm_atomic_helper_prepare_planes(drm, state);
106 if (ret)
107 return ret;
108
109 mutex_lock(&private->commit.lock);
110 flush_work(&private->commit.work);
111
112 ret = drm_atomic_helper_swap_state(state, true);
113 if (ret) {
114 mutex_unlock(&private->commit.lock);
115 drm_atomic_helper_cleanup_planes(drm, state);
116 return ret;
117 }
118
119 drm_atomic_state_get(state);
120 if (async)
121 mtk_atomic_schedule(private, state);
122 else
123 mtk_atomic_complete(private, state);
124
125 mutex_unlock(&private->commit.lock);
126
127 return 0;
128}
129
130static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = {
131 .fb_create = mtk_drm_mode_fb_create,
132 .atomic_check = drm_atomic_helper_check,
133 .atomic_commit = mtk_atomic_commit,
134};
135
136static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
137 DDP_COMPONENT_OVL0,
138 DDP_COMPONENT_RDMA0,
139 DDP_COMPONENT_COLOR0,
140 DDP_COMPONENT_BLS,
141 DDP_COMPONENT_DSI0,
142};
143
144static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
145 DDP_COMPONENT_RDMA1,
146 DDP_COMPONENT_DPI0,
147};
148
149static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
150 DDP_COMPONENT_OVL0,
151 DDP_COMPONENT_COLOR0,
152 DDP_COMPONENT_AAL,
153 DDP_COMPONENT_OD,
154 DDP_COMPONENT_RDMA0,
155 DDP_COMPONENT_UFOE,
156 DDP_COMPONENT_DSI0,
157 DDP_COMPONENT_PWM0,
158};
159
160static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = {
161 DDP_COMPONENT_OVL1,
162 DDP_COMPONENT_COLOR1,
163 DDP_COMPONENT_GAMMA,
164 DDP_COMPONENT_RDMA1,
165 DDP_COMPONENT_DPI0,
166};
167
168static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
169 .main_path = mt2701_mtk_ddp_main,
170 .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
171 .ext_path = mt2701_mtk_ddp_ext,
172 .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext),
173 .shadow_register = true,
174};
175
176static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
177 .main_path = mt8173_mtk_ddp_main,
178 .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
179 .ext_path = mt8173_mtk_ddp_ext,
180 .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
181};
182
183static int mtk_drm_kms_init(struct drm_device *drm)
184{
185 struct mtk_drm_private *private = drm->dev_private;
186 struct platform_device *pdev;
187 struct device_node *np;
188 int ret;
189
190 if (!iommu_present(&platform_bus_type))
191 return -EPROBE_DEFER;
192
193 pdev = of_find_device_by_node(private->mutex_node);
194 if (!pdev) {
195 dev_err(drm->dev, "Waiting for disp-mutex device %pOF\n",
196 private->mutex_node);
197 of_node_put(private->mutex_node);
198 return -EPROBE_DEFER;
199 }
200 private->mutex_dev = &pdev->dev;
201
202 drm_mode_config_init(drm);
203
204 drm->mode_config.min_width = 64;
205 drm->mode_config.min_height = 64;
206
207 /*
208 * set max width and height as default value(4096x4096).
209 * this value would be used to check framebuffer size limitation
210 * at drm_mode_addfb().
211 */
212 drm->mode_config.max_width = 4096;
213 drm->mode_config.max_height = 4096;
214 drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
215
216 ret = component_bind_all(drm->dev, drm);
217 if (ret)
218 goto err_config_cleanup;
219
220 /*
221 * We currently support two fixed data streams, each optional,
222 * and each statically assigned to a crtc:
223 * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...
224 */
225 ret = mtk_drm_crtc_create(drm, private->data->main_path,
226 private->data->main_len);
227 if (ret < 0)
228 goto err_component_unbind;
229 /* ... and OVL1 -> COLOR1 -> GAMMA -> RDMA1 -> DPI0. */
230 ret = mtk_drm_crtc_create(drm, private->data->ext_path,
231 private->data->ext_len);
232 if (ret < 0)
233 goto err_component_unbind;
234
235 /* Use OVL device for all DMA memory allocations */
236 np = private->comp_node[private->data->main_path[0]] ?:
237 private->comp_node[private->data->ext_path[0]];
238 pdev = of_find_device_by_node(np);
239 if (!pdev) {
240 ret = -ENODEV;
241 dev_err(drm->dev, "Need at least one OVL device\n");
242 goto err_component_unbind;
243 }
244
245 private->dma_dev = &pdev->dev;
246
247 /*
248 * We don't use the drm_irq_install() helpers provided by the DRM
249 * core, so we need to set this manually in order to allow the
250 * DRM_IOCTL_WAIT_VBLANK to operate correctly.
251 */
252 drm->irq_enabled = true;
253 ret = drm_vblank_init(drm, MAX_CRTC);
254 if (ret < 0)
255 goto err_component_unbind;
256
257 drm_kms_helper_poll_init(drm);
258 drm_mode_config_reset(drm);
259
260 return 0;
261
262err_component_unbind:
263 component_unbind_all(drm->dev, drm);
264err_config_cleanup:
265 drm_mode_config_cleanup(drm);
266
267 return ret;
268}
269
270static void mtk_drm_kms_deinit(struct drm_device *drm)
271{
272 drm_kms_helper_poll_fini(drm);
273
274 component_unbind_all(drm->dev, drm);
275 drm_mode_config_cleanup(drm);
276}
277
278static const struct file_operations mtk_drm_fops = {
279 .owner = THIS_MODULE,
280 .open = drm_open,
281 .release = drm_release,
282 .unlocked_ioctl = drm_ioctl,
283 .mmap = mtk_drm_gem_mmap,
284 .poll = drm_poll,
285 .read = drm_read,
286 .compat_ioctl = drm_compat_ioctl,
287};
288
289static struct drm_driver mtk_drm_driver = {
290 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
291 DRIVER_ATOMIC,
292
293 .gem_free_object_unlocked = mtk_drm_gem_free_object,
294 .gem_vm_ops = &drm_gem_cma_vm_ops,
295 .dumb_create = mtk_drm_gem_dumb_create,
296
297 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
298 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
299 .gem_prime_export = drm_gem_prime_export,
300 .gem_prime_import = drm_gem_prime_import,
301 .gem_prime_get_sg_table = mtk_gem_prime_get_sg_table,
302 .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table,
303 .gem_prime_mmap = mtk_drm_gem_mmap_buf,
304 .fops = &mtk_drm_fops,
305
306 .name = DRIVER_NAME,
307 .desc = DRIVER_DESC,
308 .date = DRIVER_DATE,
309 .major = DRIVER_MAJOR,
310 .minor = DRIVER_MINOR,
311};
312
313static int compare_of(struct device *dev, void *data)
314{
315 return dev->of_node == data;
316}
317
318static int mtk_drm_bind(struct device *dev)
319{
320 struct mtk_drm_private *private = dev_get_drvdata(dev);
321 struct drm_device *drm;
322 int ret;
323
324 drm = drm_dev_alloc(&mtk_drm_driver, dev);
325 if (IS_ERR(drm))
326 return PTR_ERR(drm);
327
328 drm->dev_private = private;
329 private->drm = drm;
330
331 ret = mtk_drm_kms_init(drm);
332 if (ret < 0)
333 goto err_free;
334
335 ret = drm_dev_register(drm, 0);
336 if (ret < 0)
337 goto err_deinit;
338
339 return 0;
340
341err_deinit:
342 mtk_drm_kms_deinit(drm);
343err_free:
344 drm_dev_unref(drm);
345 return ret;
346}
347
348static void mtk_drm_unbind(struct device *dev)
349{
350 struct mtk_drm_private *private = dev_get_drvdata(dev);
351
352 drm_dev_unregister(private->drm);
353 drm_dev_unref(private->drm);
354 private->drm = NULL;
355}
356
357static const struct component_master_ops mtk_drm_ops = {
358 .bind = mtk_drm_bind,
359 .unbind = mtk_drm_unbind,
360};
361
362static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
363 { .compatible = "mediatek,mt2701-disp-ovl", .data = (void *)MTK_DISP_OVL },
364 { .compatible = "mediatek,mt8173-disp-ovl", .data = (void *)MTK_DISP_OVL },
365 { .compatible = "mediatek,mt2701-disp-rdma", .data = (void *)MTK_DISP_RDMA },
366 { .compatible = "mediatek,mt8173-disp-rdma", .data = (void *)MTK_DISP_RDMA },
367 { .compatible = "mediatek,mt8173-disp-wdma", .data = (void *)MTK_DISP_WDMA },
368 { .compatible = "mediatek,mt2701-disp-color", .data = (void *)MTK_DISP_COLOR },
369 { .compatible = "mediatek,mt8173-disp-color", .data = (void *)MTK_DISP_COLOR },
370 { .compatible = "mediatek,mt8173-disp-aal", .data = (void *)MTK_DISP_AAL},
371 { .compatible = "mediatek,mt8173-disp-gamma", .data = (void *)MTK_DISP_GAMMA, },
372 { .compatible = "mediatek,mt8173-disp-ufoe", .data = (void *)MTK_DISP_UFOE },
373 { .compatible = "mediatek,mt2701-dsi", .data = (void *)MTK_DSI },
374 { .compatible = "mediatek,mt8173-dsi", .data = (void *)MTK_DSI },
375 { .compatible = "mediatek,mt8173-dpi", .data = (void *)MTK_DPI },
376 { .compatible = "mediatek,mt2701-disp-mutex", .data = (void *)MTK_DISP_MUTEX },
377 { .compatible = "mediatek,mt8173-disp-mutex", .data = (void *)MTK_DISP_MUTEX },
378 { .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_BLS },
379 { .compatible = "mediatek,mt8173-disp-pwm", .data = (void *)MTK_DISP_PWM },
380 { .compatible = "mediatek,mt8173-disp-od", .data = (void *)MTK_DISP_OD },
381 { }
382};
383
384static int mtk_drm_probe(struct platform_device *pdev)
385{
386 struct device *dev = &pdev->dev;
387 struct mtk_drm_private *private;
388 struct resource *mem;
389 struct device_node *node;
390 struct component_match *match = NULL;
391 int ret;
392 int i;
393
394 private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);
395 if (!private)
396 return -ENOMEM;
397
398 mutex_init(&private->commit.lock);
399 INIT_WORK(&private->commit.work, mtk_atomic_work);
400 private->data = of_device_get_match_data(dev);
401
402 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
403 private->config_regs = devm_ioremap_resource(dev, mem);
404 if (IS_ERR(private->config_regs)) {
405 ret = PTR_ERR(private->config_regs);
406 dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n",
407 ret);
408 return ret;
409 }
410
411 /* Iterate over sibling DISP function blocks */
412 for_each_child_of_node(dev->of_node->parent, node) {
413 const struct of_device_id *of_id;
414 enum mtk_ddp_comp_type comp_type;
415 int comp_id;
416
417 of_id = of_match_node(mtk_ddp_comp_dt_ids, node);
418 if (!of_id)
419 continue;
420
421 if (!of_device_is_available(node)) {
422 dev_dbg(dev, "Skipping disabled component %pOF\n",
423 node);
424 continue;
425 }
426
427 comp_type = (enum mtk_ddp_comp_type)of_id->data;
428
429 if (comp_type == MTK_DISP_MUTEX) {
430 private->mutex_node = of_node_get(node);
431 continue;
432 }
433
434 comp_id = mtk_ddp_comp_get_id(node, comp_type);
435 if (comp_id < 0) {
436 dev_warn(dev, "Skipping unknown component %pOF\n",
437 node);
438 continue;
439 }
440
441 private->comp_node[comp_id] = of_node_get(node);
442
443 /*
444 * Currently only the COLOR, OVL, RDMA, DSI, and DPI blocks have
445 * separate component platform drivers and initialize their own
446 * DDP component structure. The others are initialized here.
447 */
448 if (comp_type == MTK_DISP_COLOR ||
449 comp_type == MTK_DISP_OVL ||
450 comp_type == MTK_DISP_RDMA ||
451 comp_type == MTK_DSI ||
452 comp_type == MTK_DPI) {
453 dev_info(dev, "Adding component match for %pOF\n",
454 node);
455 drm_of_component_match_add(dev, &match, compare_of,
456 node);
457 } else {
458 struct mtk_ddp_comp *comp;
459
460 comp = devm_kzalloc(dev, sizeof(*comp), GFP_KERNEL);
461 if (!comp) {
462 ret = -ENOMEM;
463 goto err_node;
464 }
465
466 ret = mtk_ddp_comp_init(dev, node, comp, comp_id, NULL);
467 if (ret)
468 goto err_node;
469
470 private->ddp_comp[comp_id] = comp;
471 }
472 }
473
474 if (!private->mutex_node) {
475 dev_err(dev, "Failed to find disp-mutex node\n");
476 ret = -ENODEV;
477 goto err_node;
478 }
479
480 pm_runtime_enable(dev);
481
482 platform_set_drvdata(pdev, private);
483
484 ret = component_master_add_with_match(dev, &mtk_drm_ops, match);
485 if (ret)
486 goto err_pm;
487
488 return 0;
489
490err_pm:
491 pm_runtime_disable(dev);
492err_node:
493 of_node_put(private->mutex_node);
494 for (i = 0; i < DDP_COMPONENT_ID_MAX; i++)
495 of_node_put(private->comp_node[i]);
496 return ret;
497}
498
499static int mtk_drm_remove(struct platform_device *pdev)
500{
501 struct mtk_drm_private *private = platform_get_drvdata(pdev);
502 struct drm_device *drm = private->drm;
503 int i;
504
505 drm_dev_unregister(drm);
506 mtk_drm_kms_deinit(drm);
507 drm_dev_unref(drm);
508
509 component_master_del(&pdev->dev, &mtk_drm_ops);
510 pm_runtime_disable(&pdev->dev);
511 of_node_put(private->mutex_node);
512 for (i = 0; i < DDP_COMPONENT_ID_MAX; i++)
513 of_node_put(private->comp_node[i]);
514
515 return 0;
516}
517
518#ifdef CONFIG_PM_SLEEP
519static int mtk_drm_sys_suspend(struct device *dev)
520{
521 struct mtk_drm_private *private = dev_get_drvdata(dev);
522 struct drm_device *drm = private->drm;
523
524 drm_kms_helper_poll_disable(drm);
525
526 private->suspend_state = drm_atomic_helper_suspend(drm);
527 if (IS_ERR(private->suspend_state)) {
528 drm_kms_helper_poll_enable(drm);
529 return PTR_ERR(private->suspend_state);
530 }
531
532 DRM_DEBUG_DRIVER("mtk_drm_sys_suspend\n");
533 return 0;
534}
535
536static int mtk_drm_sys_resume(struct device *dev)
537{
538 struct mtk_drm_private *private = dev_get_drvdata(dev);
539 struct drm_device *drm = private->drm;
540
541 drm_atomic_helper_resume(drm, private->suspend_state);
542 drm_kms_helper_poll_enable(drm);
543
544 DRM_DEBUG_DRIVER("mtk_drm_sys_resume\n");
545 return 0;
546}
547#endif
548
549static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend,
550 mtk_drm_sys_resume);
551
552static const struct of_device_id mtk_drm_of_ids[] = {
553 { .compatible = "mediatek,mt2701-mmsys",
554 .data = &mt2701_mmsys_driver_data},
555 { .compatible = "mediatek,mt8173-mmsys",
556 .data = &mt8173_mmsys_driver_data},
557 { }
558};
559
560static struct platform_driver mtk_drm_platform_driver = {
561 .probe = mtk_drm_probe,
562 .remove = mtk_drm_remove,
563 .driver = {
564 .name = "mediatek-drm",
565 .of_match_table = mtk_drm_of_ids,
566 .pm = &mtk_drm_pm_ops,
567 },
568};
569
570static struct platform_driver * const mtk_drm_drivers[] = {
571 &mtk_ddp_driver,
572 &mtk_disp_color_driver,
573 &mtk_disp_ovl_driver,
574 &mtk_disp_rdma_driver,
575 &mtk_dpi_driver,
576 &mtk_drm_platform_driver,
577 &mtk_dsi_driver,
578 &mtk_mipi_tx_driver,
579};
580
581static int __init mtk_drm_init(void)
582{
583 return platform_register_drivers(mtk_drm_drivers,
584 ARRAY_SIZE(mtk_drm_drivers));
585}
586
587static void __exit mtk_drm_exit(void)
588{
589 platform_unregister_drivers(mtk_drm_drivers,
590 ARRAY_SIZE(mtk_drm_drivers));
591}
592
593module_init(mtk_drm_init);
594module_exit(mtk_drm_exit);
595
596MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>");
597MODULE_DESCRIPTION("Mediatek SoC DRM driver");
598MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: YT SHEN <yt.shen@mediatek.com>
5 */
6
7#include <linux/clk.h>
8#include <linux/clk-provider.h>
9#include <linux/component.h>
10#include <linux/iommu.h>
11#include <linux/module.h>
12#include <linux/of_address.h>
13#include <linux/of_platform.h>
14#include <linux/pm_runtime.h>
15#include <linux/dma-mapping.h>
16
17#include <drm/drm_atomic.h>
18#include <drm/drm_atomic_helper.h>
19#include <drm/drm_drv.h>
20#include <drm/drm_fbdev_generic.h>
21#include <drm/drm_fourcc.h>
22#include <drm/drm_gem.h>
23#include <drm/drm_gem_dma_helper.h>
24#include <drm/drm_gem_framebuffer_helper.h>
25#include <drm/drm_of.h>
26#include <drm/drm_probe_helper.h>
27#include <drm/drm_vblank.h>
28
29#include "mtk_drm_crtc.h"
30#include "mtk_drm_ddp_comp.h"
31#include "mtk_drm_drv.h"
32#include "mtk_drm_gem.h"
33
34#define DRIVER_NAME "mediatek"
35#define DRIVER_DESC "Mediatek SoC DRM"
36#define DRIVER_DATE "20150513"
37#define DRIVER_MAJOR 1
38#define DRIVER_MINOR 0
39
40static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = {
41 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
42};
43
44static struct drm_framebuffer *
45mtk_drm_mode_fb_create(struct drm_device *dev,
46 struct drm_file *file,
47 const struct drm_mode_fb_cmd2 *cmd)
48{
49 const struct drm_format_info *info = drm_get_format_info(dev, cmd);
50
51 if (info->num_planes != 1)
52 return ERR_PTR(-EINVAL);
53
54 return drm_gem_fb_create(dev, file, cmd);
55}
56
57static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = {
58 .fb_create = mtk_drm_mode_fb_create,
59 .atomic_check = drm_atomic_helper_check,
60 .atomic_commit = drm_atomic_helper_commit,
61};
62
63static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
64 DDP_COMPONENT_OVL0,
65 DDP_COMPONENT_RDMA0,
66 DDP_COMPONENT_COLOR0,
67 DDP_COMPONENT_BLS,
68 DDP_COMPONENT_DSI0,
69};
70
71static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
72 DDP_COMPONENT_RDMA1,
73 DDP_COMPONENT_DPI0,
74};
75
76static const enum mtk_ddp_comp_id mt7623_mtk_ddp_main[] = {
77 DDP_COMPONENT_OVL0,
78 DDP_COMPONENT_RDMA0,
79 DDP_COMPONENT_COLOR0,
80 DDP_COMPONENT_BLS,
81 DDP_COMPONENT_DPI0,
82};
83
84static const enum mtk_ddp_comp_id mt7623_mtk_ddp_ext[] = {
85 DDP_COMPONENT_RDMA1,
86 DDP_COMPONENT_DSI0,
87};
88
89static const enum mtk_ddp_comp_id mt2712_mtk_ddp_main[] = {
90 DDP_COMPONENT_OVL0,
91 DDP_COMPONENT_COLOR0,
92 DDP_COMPONENT_AAL0,
93 DDP_COMPONENT_OD0,
94 DDP_COMPONENT_RDMA0,
95 DDP_COMPONENT_DPI0,
96 DDP_COMPONENT_PWM0,
97};
98
99static const enum mtk_ddp_comp_id mt2712_mtk_ddp_ext[] = {
100 DDP_COMPONENT_OVL1,
101 DDP_COMPONENT_COLOR1,
102 DDP_COMPONENT_AAL1,
103 DDP_COMPONENT_OD1,
104 DDP_COMPONENT_RDMA1,
105 DDP_COMPONENT_DPI1,
106 DDP_COMPONENT_PWM1,
107};
108
109static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = {
110 DDP_COMPONENT_RDMA2,
111 DDP_COMPONENT_DSI3,
112 DDP_COMPONENT_PWM2,
113};
114
115static enum mtk_ddp_comp_id mt8167_mtk_ddp_main[] = {
116 DDP_COMPONENT_OVL0,
117 DDP_COMPONENT_COLOR0,
118 DDP_COMPONENT_CCORR,
119 DDP_COMPONENT_AAL0,
120 DDP_COMPONENT_GAMMA,
121 DDP_COMPONENT_DITHER0,
122 DDP_COMPONENT_RDMA0,
123 DDP_COMPONENT_DSI0,
124};
125
126static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
127 DDP_COMPONENT_OVL0,
128 DDP_COMPONENT_COLOR0,
129 DDP_COMPONENT_AAL0,
130 DDP_COMPONENT_OD0,
131 DDP_COMPONENT_RDMA0,
132 DDP_COMPONENT_UFOE,
133 DDP_COMPONENT_DSI0,
134 DDP_COMPONENT_PWM0,
135};
136
137static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = {
138 DDP_COMPONENT_OVL1,
139 DDP_COMPONENT_COLOR1,
140 DDP_COMPONENT_GAMMA,
141 DDP_COMPONENT_RDMA1,
142 DDP_COMPONENT_DPI0,
143};
144
145static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = {
146 DDP_COMPONENT_OVL0,
147 DDP_COMPONENT_OVL_2L0,
148 DDP_COMPONENT_RDMA0,
149 DDP_COMPONENT_COLOR0,
150 DDP_COMPONENT_CCORR,
151 DDP_COMPONENT_AAL0,
152 DDP_COMPONENT_GAMMA,
153 DDP_COMPONENT_DITHER0,
154 DDP_COMPONENT_DSI0,
155};
156
157static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = {
158 DDP_COMPONENT_OVL_2L1,
159 DDP_COMPONENT_RDMA1,
160 DDP_COMPONENT_DPI0,
161};
162
163static const enum mtk_ddp_comp_id mt8186_mtk_ddp_main[] = {
164 DDP_COMPONENT_OVL0,
165 DDP_COMPONENT_RDMA0,
166 DDP_COMPONENT_COLOR0,
167 DDP_COMPONENT_CCORR,
168 DDP_COMPONENT_AAL0,
169 DDP_COMPONENT_GAMMA,
170 DDP_COMPONENT_POSTMASK0,
171 DDP_COMPONENT_DITHER0,
172 DDP_COMPONENT_DSI0,
173};
174
175static const enum mtk_ddp_comp_id mt8186_mtk_ddp_ext[] = {
176 DDP_COMPONENT_OVL_2L0,
177 DDP_COMPONENT_RDMA1,
178 DDP_COMPONENT_DPI0,
179};
180
181static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = {
182 DDP_COMPONENT_OVL0,
183 DDP_COMPONENT_OVL_2L0,
184 DDP_COMPONENT_RDMA0,
185 DDP_COMPONENT_COLOR0,
186 DDP_COMPONENT_CCORR,
187 DDP_COMPONENT_AAL0,
188 DDP_COMPONENT_GAMMA,
189 DDP_COMPONENT_POSTMASK0,
190 DDP_COMPONENT_DITHER0,
191 DDP_COMPONENT_DSI0,
192};
193
194static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = {
195 DDP_COMPONENT_OVL_2L2,
196 DDP_COMPONENT_RDMA4,
197 DDP_COMPONENT_DPI0,
198};
199
200static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
201 DDP_COMPONENT_OVL0,
202 DDP_COMPONENT_RDMA0,
203 DDP_COMPONENT_COLOR0,
204 DDP_COMPONENT_CCORR,
205 DDP_COMPONENT_AAL0,
206 DDP_COMPONENT_GAMMA,
207 DDP_COMPONENT_DITHER0,
208 DDP_COMPONENT_DSC0,
209 DDP_COMPONENT_MERGE0,
210 DDP_COMPONENT_DP_INTF0,
211};
212
213static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
214 .main_path = mt2701_mtk_ddp_main,
215 .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
216 .ext_path = mt2701_mtk_ddp_ext,
217 .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext),
218 .shadow_register = true,
219};
220
221static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
222 .num_drv_data = 1,
223 .drv_data = {
224 &mt2701_mmsys_driver_data,
225 },
226};
227
228static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
229 .main_path = mt7623_mtk_ddp_main,
230 .main_len = ARRAY_SIZE(mt7623_mtk_ddp_main),
231 .ext_path = mt7623_mtk_ddp_ext,
232 .ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
233 .shadow_register = true,
234};
235
236static const struct mtk_mmsys_match_data mt7623_mmsys_match_data = {
237 .num_drv_data = 1,
238 .drv_data = {
239 &mt7623_mmsys_driver_data,
240 },
241};
242
243static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
244 .main_path = mt2712_mtk_ddp_main,
245 .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
246 .ext_path = mt2712_mtk_ddp_ext,
247 .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
248 .third_path = mt2712_mtk_ddp_third,
249 .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
250};
251
252static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
253 .num_drv_data = 1,
254 .drv_data = {
255 &mt2712_mmsys_driver_data,
256 },
257};
258
259static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
260 .main_path = mt8167_mtk_ddp_main,
261 .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
262};
263
264static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
265 .num_drv_data = 1,
266 .drv_data = {
267 &mt8167_mmsys_driver_data,
268 },
269};
270
271static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
272 .main_path = mt8173_mtk_ddp_main,
273 .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
274 .ext_path = mt8173_mtk_ddp_ext,
275 .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
276};
277
278static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
279 .num_drv_data = 1,
280 .drv_data = {
281 &mt8173_mmsys_driver_data,
282 },
283};
284
285static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
286 .main_path = mt8183_mtk_ddp_main,
287 .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
288 .ext_path = mt8183_mtk_ddp_ext,
289 .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
290};
291
292static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
293 .num_drv_data = 1,
294 .drv_data = {
295 &mt8183_mmsys_driver_data,
296 },
297};
298
299static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
300 .main_path = mt8186_mtk_ddp_main,
301 .main_len = ARRAY_SIZE(mt8186_mtk_ddp_main),
302 .ext_path = mt8186_mtk_ddp_ext,
303 .ext_len = ARRAY_SIZE(mt8186_mtk_ddp_ext),
304};
305
306static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = {
307 .num_drv_data = 1,
308 .drv_data = {
309 &mt8186_mmsys_driver_data,
310 },
311};
312
313static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
314 .main_path = mt8192_mtk_ddp_main,
315 .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
316 .ext_path = mt8192_mtk_ddp_ext,
317 .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
318};
319
320static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
321 .num_drv_data = 1,
322 .drv_data = {
323 &mt8192_mmsys_driver_data,
324 },
325};
326
327static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
328 .io_start = 0x1c01a000,
329 .main_path = mt8195_mtk_ddp_main,
330 .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
331};
332
333static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
334 .io_start = 0x1c100000,
335};
336
337static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
338 .num_drv_data = 1,
339 .drv_data = {
340 &mt8195_vdosys0_driver_data,
341 &mt8195_vdosys1_driver_data,
342 },
343};
344
345static int mtk_drm_kms_init(struct drm_device *drm)
346{
347 struct mtk_drm_private *private = drm->dev_private;
348 struct platform_device *pdev;
349 struct device_node *np;
350 struct device *dma_dev;
351 int ret;
352
353 if (drm_firmware_drivers_only())
354 return -ENODEV;
355
356 if (!iommu_present(&platform_bus_type))
357 return -EPROBE_DEFER;
358
359 pdev = of_find_device_by_node(private->mutex_node);
360 if (!pdev) {
361 dev_err(drm->dev, "Waiting for disp-mutex device %pOF\n",
362 private->mutex_node);
363 of_node_put(private->mutex_node);
364 return -EPROBE_DEFER;
365 }
366 private->mutex_dev = &pdev->dev;
367
368 ret = drmm_mode_config_init(drm);
369 if (ret)
370 goto put_mutex_dev;
371
372 drm->mode_config.min_width = 64;
373 drm->mode_config.min_height = 64;
374
375 /*
376 * set max width and height as default value(4096x4096).
377 * this value would be used to check framebuffer size limitation
378 * at drm_mode_addfb().
379 */
380 drm->mode_config.max_width = 4096;
381 drm->mode_config.max_height = 4096;
382 drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
383 drm->mode_config.helper_private = &mtk_drm_mode_config_helpers;
384
385 ret = component_bind_all(drm->dev, drm);
386 if (ret)
387 goto put_mutex_dev;
388
389 /*
390 * Ensure internal panels are at the top of the connector list before
391 * crtc creation.
392 */
393 drm_helper_move_panel_connectors_to_head(drm);
394
395 /*
396 * We currently support two fixed data streams, each optional,
397 * and each statically assigned to a crtc:
398 * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...
399 */
400 ret = mtk_drm_crtc_create(drm, private->data->main_path,
401 private->data->main_len);
402 if (ret < 0)
403 goto err_component_unbind;
404 /* ... and OVL1 -> COLOR1 -> GAMMA -> RDMA1 -> DPI0. */
405 ret = mtk_drm_crtc_create(drm, private->data->ext_path,
406 private->data->ext_len);
407 if (ret < 0)
408 goto err_component_unbind;
409
410 ret = mtk_drm_crtc_create(drm, private->data->third_path,
411 private->data->third_len);
412 if (ret < 0)
413 goto err_component_unbind;
414
415 /* Use OVL device for all DMA memory allocations */
416 np = private->comp_node[private->data->main_path[0]] ?:
417 private->comp_node[private->data->ext_path[0]];
418 pdev = of_find_device_by_node(np);
419 if (!pdev) {
420 ret = -ENODEV;
421 dev_err(drm->dev, "Need at least one OVL device\n");
422 goto err_component_unbind;
423 }
424
425 dma_dev = &pdev->dev;
426 private->dma_dev = dma_dev;
427
428 /*
429 * Configure the DMA segment size to make sure we get contiguous IOVA
430 * when importing PRIME buffers.
431 */
432 ret = dma_set_max_seg_size(dma_dev, UINT_MAX);
433 if (ret) {
434 dev_err(dma_dev, "Failed to set DMA segment size\n");
435 goto err_component_unbind;
436 }
437
438 ret = drm_vblank_init(drm, MAX_CRTC);
439 if (ret < 0)
440 goto err_component_unbind;
441
442 drm_kms_helper_poll_init(drm);
443 drm_mode_config_reset(drm);
444
445 return 0;
446
447err_component_unbind:
448 component_unbind_all(drm->dev, drm);
449put_mutex_dev:
450 put_device(private->mutex_dev);
451 return ret;
452}
453
454static void mtk_drm_kms_deinit(struct drm_device *drm)
455{
456 drm_kms_helper_poll_fini(drm);
457 drm_atomic_helper_shutdown(drm);
458
459 component_unbind_all(drm->dev, drm);
460}
461
462DEFINE_DRM_GEM_FOPS(mtk_drm_fops);
463
464/*
465 * We need to override this because the device used to import the memory is
466 * not dev->dev, as drm_gem_prime_import() expects.
467 */
468static struct drm_gem_object *mtk_drm_gem_prime_import(struct drm_device *dev,
469 struct dma_buf *dma_buf)
470{
471 struct mtk_drm_private *private = dev->dev_private;
472
473 return drm_gem_prime_import_dev(dev, dma_buf, private->dma_dev);
474}
475
476static const struct drm_driver mtk_drm_driver = {
477 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
478
479 .dumb_create = mtk_drm_gem_dumb_create,
480
481 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
482 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
483 .gem_prime_import = mtk_drm_gem_prime_import,
484 .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table,
485 .gem_prime_mmap = drm_gem_prime_mmap,
486 .fops = &mtk_drm_fops,
487
488 .name = DRIVER_NAME,
489 .desc = DRIVER_DESC,
490 .date = DRIVER_DATE,
491 .major = DRIVER_MAJOR,
492 .minor = DRIVER_MINOR,
493};
494
495static int mtk_drm_bind(struct device *dev)
496{
497 struct mtk_drm_private *private = dev_get_drvdata(dev);
498 struct drm_device *drm;
499 int ret;
500
501 drm = drm_dev_alloc(&mtk_drm_driver, dev);
502 if (IS_ERR(drm))
503 return PTR_ERR(drm);
504
505 drm->dev_private = private;
506 private->drm = drm;
507
508 ret = mtk_drm_kms_init(drm);
509 if (ret < 0)
510 goto err_free;
511
512 ret = drm_dev_register(drm, 0);
513 if (ret < 0)
514 goto err_deinit;
515
516 drm_fbdev_generic_setup(drm, 32);
517
518 return 0;
519
520err_deinit:
521 mtk_drm_kms_deinit(drm);
522err_free:
523 drm_dev_put(drm);
524 return ret;
525}
526
527static void mtk_drm_unbind(struct device *dev)
528{
529 struct mtk_drm_private *private = dev_get_drvdata(dev);
530
531 drm_dev_unregister(private->drm);
532 mtk_drm_kms_deinit(private->drm);
533 drm_dev_put(private->drm);
534 private->num_pipes = 0;
535 private->drm = NULL;
536}
537
538static const struct component_master_ops mtk_drm_ops = {
539 .bind = mtk_drm_bind,
540 .unbind = mtk_drm_unbind,
541};
542
543static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
544 { .compatible = "mediatek,mt8167-disp-aal",
545 .data = (void *)MTK_DISP_AAL},
546 { .compatible = "mediatek,mt8173-disp-aal",
547 .data = (void *)MTK_DISP_AAL},
548 { .compatible = "mediatek,mt8183-disp-aal",
549 .data = (void *)MTK_DISP_AAL},
550 { .compatible = "mediatek,mt8192-disp-aal",
551 .data = (void *)MTK_DISP_AAL},
552 { .compatible = "mediatek,mt8167-disp-ccorr",
553 .data = (void *)MTK_DISP_CCORR },
554 { .compatible = "mediatek,mt8183-disp-ccorr",
555 .data = (void *)MTK_DISP_CCORR },
556 { .compatible = "mediatek,mt8192-disp-ccorr",
557 .data = (void *)MTK_DISP_CCORR },
558 { .compatible = "mediatek,mt2701-disp-color",
559 .data = (void *)MTK_DISP_COLOR },
560 { .compatible = "mediatek,mt8167-disp-color",
561 .data = (void *)MTK_DISP_COLOR },
562 { .compatible = "mediatek,mt8173-disp-color",
563 .data = (void *)MTK_DISP_COLOR },
564 { .compatible = "mediatek,mt8167-disp-dither",
565 .data = (void *)MTK_DISP_DITHER },
566 { .compatible = "mediatek,mt8183-disp-dither",
567 .data = (void *)MTK_DISP_DITHER },
568 { .compatible = "mediatek,mt8195-disp-dsc",
569 .data = (void *)MTK_DISP_DSC },
570 { .compatible = "mediatek,mt8167-disp-gamma",
571 .data = (void *)MTK_DISP_GAMMA, },
572 { .compatible = "mediatek,mt8173-disp-gamma",
573 .data = (void *)MTK_DISP_GAMMA, },
574 { .compatible = "mediatek,mt8183-disp-gamma",
575 .data = (void *)MTK_DISP_GAMMA, },
576 { .compatible = "mediatek,mt8195-disp-merge",
577 .data = (void *)MTK_DISP_MERGE },
578 { .compatible = "mediatek,mt2701-disp-mutex",
579 .data = (void *)MTK_DISP_MUTEX },
580 { .compatible = "mediatek,mt2712-disp-mutex",
581 .data = (void *)MTK_DISP_MUTEX },
582 { .compatible = "mediatek,mt8167-disp-mutex",
583 .data = (void *)MTK_DISP_MUTEX },
584 { .compatible = "mediatek,mt8173-disp-mutex",
585 .data = (void *)MTK_DISP_MUTEX },
586 { .compatible = "mediatek,mt8183-disp-mutex",
587 .data = (void *)MTK_DISP_MUTEX },
588 { .compatible = "mediatek,mt8186-disp-mutex",
589 .data = (void *)MTK_DISP_MUTEX },
590 { .compatible = "mediatek,mt8192-disp-mutex",
591 .data = (void *)MTK_DISP_MUTEX },
592 { .compatible = "mediatek,mt8195-disp-mutex",
593 .data = (void *)MTK_DISP_MUTEX },
594 { .compatible = "mediatek,mt8173-disp-od",
595 .data = (void *)MTK_DISP_OD },
596 { .compatible = "mediatek,mt2701-disp-ovl",
597 .data = (void *)MTK_DISP_OVL },
598 { .compatible = "mediatek,mt8167-disp-ovl",
599 .data = (void *)MTK_DISP_OVL },
600 { .compatible = "mediatek,mt8173-disp-ovl",
601 .data = (void *)MTK_DISP_OVL },
602 { .compatible = "mediatek,mt8183-disp-ovl",
603 .data = (void *)MTK_DISP_OVL },
604 { .compatible = "mediatek,mt8192-disp-ovl",
605 .data = (void *)MTK_DISP_OVL },
606 { .compatible = "mediatek,mt8183-disp-ovl-2l",
607 .data = (void *)MTK_DISP_OVL_2L },
608 { .compatible = "mediatek,mt8192-disp-ovl-2l",
609 .data = (void *)MTK_DISP_OVL_2L },
610 { .compatible = "mediatek,mt8192-disp-postmask",
611 .data = (void *)MTK_DISP_POSTMASK },
612 { .compatible = "mediatek,mt2701-disp-pwm",
613 .data = (void *)MTK_DISP_BLS },
614 { .compatible = "mediatek,mt8167-disp-pwm",
615 .data = (void *)MTK_DISP_PWM },
616 { .compatible = "mediatek,mt8173-disp-pwm",
617 .data = (void *)MTK_DISP_PWM },
618 { .compatible = "mediatek,mt2701-disp-rdma",
619 .data = (void *)MTK_DISP_RDMA },
620 { .compatible = "mediatek,mt8167-disp-rdma",
621 .data = (void *)MTK_DISP_RDMA },
622 { .compatible = "mediatek,mt8173-disp-rdma",
623 .data = (void *)MTK_DISP_RDMA },
624 { .compatible = "mediatek,mt8183-disp-rdma",
625 .data = (void *)MTK_DISP_RDMA },
626 { .compatible = "mediatek,mt8195-disp-rdma",
627 .data = (void *)MTK_DISP_RDMA },
628 { .compatible = "mediatek,mt8173-disp-ufoe",
629 .data = (void *)MTK_DISP_UFOE },
630 { .compatible = "mediatek,mt8173-disp-wdma",
631 .data = (void *)MTK_DISP_WDMA },
632 { .compatible = "mediatek,mt2701-dpi",
633 .data = (void *)MTK_DPI },
634 { .compatible = "mediatek,mt8167-dsi",
635 .data = (void *)MTK_DSI },
636 { .compatible = "mediatek,mt8173-dpi",
637 .data = (void *)MTK_DPI },
638 { .compatible = "mediatek,mt8183-dpi",
639 .data = (void *)MTK_DPI },
640 { .compatible = "mediatek,mt8188-dp-intf",
641 .data = (void *)MTK_DP_INTF },
642 { .compatible = "mediatek,mt8192-dpi",
643 .data = (void *)MTK_DPI },
644 { .compatible = "mediatek,mt8195-dp-intf",
645 .data = (void *)MTK_DP_INTF },
646 { .compatible = "mediatek,mt2701-dsi",
647 .data = (void *)MTK_DSI },
648 { .compatible = "mediatek,mt8173-dsi",
649 .data = (void *)MTK_DSI },
650 { .compatible = "mediatek,mt8183-dsi",
651 .data = (void *)MTK_DSI },
652 { .compatible = "mediatek,mt8186-dsi",
653 .data = (void *)MTK_DSI },
654 { }
655};
656
657static const struct of_device_id mtk_drm_of_ids[] = {
658 { .compatible = "mediatek,mt2701-mmsys",
659 .data = &mt2701_mmsys_match_data},
660 { .compatible = "mediatek,mt7623-mmsys",
661 .data = &mt7623_mmsys_match_data},
662 { .compatible = "mediatek,mt2712-mmsys",
663 .data = &mt2712_mmsys_match_data},
664 { .compatible = "mediatek,mt8167-mmsys",
665 .data = &mt8167_mmsys_match_data},
666 { .compatible = "mediatek,mt8173-mmsys",
667 .data = &mt8173_mmsys_match_data},
668 { .compatible = "mediatek,mt8183-mmsys",
669 .data = &mt8183_mmsys_match_data},
670 { .compatible = "mediatek,mt8186-mmsys",
671 .data = &mt8186_mmsys_match_data},
672 { .compatible = "mediatek,mt8192-mmsys",
673 .data = &mt8192_mmsys_match_data},
674 { .compatible = "mediatek,mt8195-mmsys",
675 .data = &mt8195_mmsys_match_data},
676 { }
677};
678MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
679
680static int mtk_drm_find_match_data(struct device *dev,
681 const struct mtk_mmsys_match_data *match_data)
682{
683 int i;
684 struct platform_device *pdev = of_find_device_by_node(dev->parent->of_node);
685 struct resource *res;
686
687 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
688 if (!res) {
689 dev_err(dev, "failed to get parent resource\n");
690 return -EINVAL;
691 }
692
693 for (i = 0; i < match_data->num_drv_data; i++)
694 if (match_data->drv_data[i]->io_start == res->start)
695 return i;
696
697 return -EINVAL;
698}
699
700static int mtk_drm_probe(struct platform_device *pdev)
701{
702 struct device *dev = &pdev->dev;
703 struct device_node *phandle = dev->parent->of_node;
704 const struct of_device_id *of_id;
705 const struct mtk_mmsys_match_data *match_data;
706 struct mtk_drm_private *private;
707 struct device_node *node;
708 struct component_match *match = NULL;
709 int ret;
710 int i;
711
712 private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);
713 if (!private)
714 return -ENOMEM;
715
716 private->mmsys_dev = dev->parent;
717 if (!private->mmsys_dev) {
718 dev_err(dev, "Failed to get MMSYS device\n");
719 return -ENODEV;
720 }
721
722 of_id = of_match_node(mtk_drm_of_ids, phandle);
723 if (!of_id)
724 return -ENODEV;
725
726 match_data = of_id->data;
727 if (match_data->num_drv_data > 1) {
728 /* This SoC has multiple mmsys channels */
729 ret = mtk_drm_find_match_data(dev, match_data);
730 if (ret < 0) {
731 dev_err(dev, "Couldn't get match driver data\n");
732 return ret;
733 }
734 private->data = match_data->drv_data[ret];
735 } else {
736 dev_dbg(dev, "Using single mmsys channel\n");
737 private->data = match_data->drv_data[0];
738 }
739
740 /* Iterate over sibling DISP function blocks */
741 for_each_child_of_node(phandle->parent, node) {
742 const struct of_device_id *of_id;
743 enum mtk_ddp_comp_type comp_type;
744 int comp_id;
745
746 of_id = of_match_node(mtk_ddp_comp_dt_ids, node);
747 if (!of_id)
748 continue;
749
750 if (!of_device_is_available(node)) {
751 dev_dbg(dev, "Skipping disabled component %pOF\n",
752 node);
753 continue;
754 }
755
756 comp_type = (enum mtk_ddp_comp_type)of_id->data;
757
758 if (comp_type == MTK_DISP_MUTEX) {
759 private->mutex_node = of_node_get(node);
760 continue;
761 }
762
763 comp_id = mtk_ddp_comp_get_id(node, comp_type);
764 if (comp_id < 0) {
765 dev_warn(dev, "Skipping unknown component %pOF\n",
766 node);
767 continue;
768 }
769
770 private->comp_node[comp_id] = of_node_get(node);
771
772 /*
773 * Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI
774 * blocks have separate component platform drivers and initialize their own
775 * DDP component structure. The others are initialized here.
776 */
777 if (comp_type == MTK_DISP_AAL ||
778 comp_type == MTK_DISP_CCORR ||
779 comp_type == MTK_DISP_COLOR ||
780 comp_type == MTK_DISP_GAMMA ||
781 comp_type == MTK_DISP_MERGE ||
782 comp_type == MTK_DISP_OVL ||
783 comp_type == MTK_DISP_OVL_2L ||
784 comp_type == MTK_DISP_RDMA ||
785 comp_type == MTK_DP_INTF ||
786 comp_type == MTK_DPI ||
787 comp_type == MTK_DSI) {
788 dev_info(dev, "Adding component match for %pOF\n",
789 node);
790 drm_of_component_match_add(dev, &match, component_compare_of,
791 node);
792 }
793
794 ret = mtk_ddp_comp_init(node, &private->ddp_comp[comp_id], comp_id);
795 if (ret) {
796 of_node_put(node);
797 goto err_node;
798 }
799 }
800
801 if (!private->mutex_node) {
802 dev_err(dev, "Failed to find disp-mutex node\n");
803 ret = -ENODEV;
804 goto err_node;
805 }
806
807 pm_runtime_enable(dev);
808
809 platform_set_drvdata(pdev, private);
810
811 ret = component_master_add_with_match(dev, &mtk_drm_ops, match);
812 if (ret)
813 goto err_pm;
814
815 return 0;
816
817err_pm:
818 pm_runtime_disable(dev);
819err_node:
820 of_node_put(private->mutex_node);
821 for (i = 0; i < DDP_COMPONENT_ID_MAX; i++)
822 of_node_put(private->comp_node[i]);
823 return ret;
824}
825
826static int mtk_drm_remove(struct platform_device *pdev)
827{
828 struct mtk_drm_private *private = platform_get_drvdata(pdev);
829 int i;
830
831 component_master_del(&pdev->dev, &mtk_drm_ops);
832 pm_runtime_disable(&pdev->dev);
833 of_node_put(private->mutex_node);
834 for (i = 0; i < DDP_COMPONENT_ID_MAX; i++)
835 of_node_put(private->comp_node[i]);
836
837 return 0;
838}
839
840static int mtk_drm_sys_prepare(struct device *dev)
841{
842 struct mtk_drm_private *private = dev_get_drvdata(dev);
843 struct drm_device *drm = private->drm;
844
845 return drm_mode_config_helper_suspend(drm);
846}
847
848static void mtk_drm_sys_complete(struct device *dev)
849{
850 struct mtk_drm_private *private = dev_get_drvdata(dev);
851 struct drm_device *drm = private->drm;
852 int ret;
853
854 ret = drm_mode_config_helper_resume(drm);
855 if (ret)
856 dev_err(dev, "Failed to resume\n");
857}
858
859static const struct dev_pm_ops mtk_drm_pm_ops = {
860 .prepare = mtk_drm_sys_prepare,
861 .complete = mtk_drm_sys_complete,
862};
863
864static struct platform_driver mtk_drm_platform_driver = {
865 .probe = mtk_drm_probe,
866 .remove = mtk_drm_remove,
867 .driver = {
868 .name = "mediatek-drm",
869 .pm = &mtk_drm_pm_ops,
870 },
871};
872
873static struct platform_driver * const mtk_drm_drivers[] = {
874 &mtk_disp_aal_driver,
875 &mtk_disp_ccorr_driver,
876 &mtk_disp_color_driver,
877 &mtk_disp_gamma_driver,
878 &mtk_disp_merge_driver,
879 &mtk_disp_ovl_driver,
880 &mtk_disp_rdma_driver,
881 &mtk_dpi_driver,
882 &mtk_drm_platform_driver,
883 &mtk_dsi_driver,
884 &mtk_mdp_rdma_driver,
885};
886
887static int __init mtk_drm_init(void)
888{
889 return platform_register_drivers(mtk_drm_drivers,
890 ARRAY_SIZE(mtk_drm_drivers));
891}
892
893static void __exit mtk_drm_exit(void)
894{
895 platform_unregister_drivers(mtk_drm_drivers,
896 ARRAY_SIZE(mtk_drm_drivers));
897}
898
899module_init(mtk_drm_init);
900module_exit(mtk_drm_exit);
901
902MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>");
903MODULE_DESCRIPTION("Mediatek SoC DRM driver");
904MODULE_LICENSE("GPL v2");