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1/*
2 * Copyright 2012 ST-Ericsson AB
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 *
11 * Device Tree for the HREF+ prior to the v60 variant.
12 */
13
14#include "ste-dbx5x0.dtsi"
15#include "ste-href-ab8500.dtsi"
16#include "ste-href.dtsi"
17
18/ {
19 gpio_keys {
20 button@1 {
21 gpios = <&tc3589x_gpio 7 GPIO_ACTIVE_HIGH>;
22 };
23 };
24
25 soc {
26 /* Enable UART1 on this board */
27 uart@80121000 {
28 status = "okay";
29 };
30
31 i2c@80004000 {
32 tps61052@33 {
33 compatible = "ti,tps61052";
34 reg = <0x33>;
35 };
36
37 tc35892@42 {
38 compatible = "toshiba,tc35892";
39 reg = <0x42>;
40 interrupt-parent = <&gpio6>;
41 interrupts = <25 IRQ_TYPE_EDGE_RISING>;
42 pinctrl-names = "default";
43 pinctrl-0 = <&tc35892_hrefprev60_mode>;
44
45 interrupt-controller;
46 #interrupt-cells = <1>;
47
48 tc3589x_gpio: tc3589x_gpio {
49 compatible = "tc3589x-gpio";
50 interrupts = <0>;
51
52 interrupt-controller;
53 #interrupt-cells = <2>;
54 gpio-controller;
55 #gpio-cells = <2>;
56 };
57 };
58 };
59
60 ssp@80002000 {
61 /*
62 * On the first generation boards, this SSP/SPI port was connected
63 * to the AB8500.
64 */
65 pinctrl-names = "default";
66 pinctrl-0 = <&ssp0_hrefprev60_mode>;
67 };
68
69 // External Micro SD slot
70 sdi0_per1@80126000 {
71 cd-gpios = <&tc3589x_gpio 3 GPIO_ACTIVE_HIGH>;
72 };
73
74 vmmci: regulator-gpio {
75 gpios = <&tc3589x_gpio 18 GPIO_ACTIVE_HIGH>;
76 enable-gpio = <&tc3589x_gpio 17 GPIO_ACTIVE_HIGH>;
77 enable-active-high;
78 };
79
80 pinctrl {
81 /* Set this up using hogs */
82 pinctrl-names = "default";
83 pinctrl-0 = <&ipgpio_hrefprev60_mode>;
84
85 ssp0 {
86 ssp0_hrefprev60_mode: ssp0_hrefprev60_default {
87 hrefprev60_mux {
88 function = "ssp0";
89 groups = "ssp0_a_1";
90 };
91 hrefprev60_cfg1 {
92 pins = "GPIO145_C13"; /* RXD */
93 ste,config = <&in_pd>;
94 };
95
96 };
97 };
98 sdi0 {
99 /* This additional pin needed on early MOP500 and HREFs previous to v60 */
100 sdi0_default_mode: sdi0_default {
101 hrefprev60_mux {
102 function = "mc0";
103 groups = "mc0dat31dir_a_1";
104 };
105 hrefprev60_cfg1 {
106 pins = "GPIO21_AB3"; /* DAT31DIR */
107 ste,config = <&out_hi>;
108 };
109
110 };
111 };
112 tc35892 {
113 tc35892_hrefprev60_mode: tc35892_hrefprev60 {
114 hrefprev60_cfg {
115 pins = "GPIO217_AH12";
116 ste,config = <&gpio_in_pu>;
117 };
118 };
119 };
120 ipgpio {
121 ipgpio_hrefprev60_mode: ipgpio_hrefprev60 {
122 hrefprev60_mux {
123 function = "ipgpio";
124 groups = "ipgpio0_c_1", "ipgpio1_c_1";
125 };
126 hrefprev60_cfg1 {
127 pins = "GPIO6_AF6", "GPIO7_AG5";
128 ste,config = <&in_pu>;
129 };
130 };
131 };
132 };
133 };
134};
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2012 ST-Ericsson AB
4 *
5 * Device Tree for the HREF+ prior to the v60 variant.
6 */
7
8#include "ste-href-ab8500.dtsi"
9#include "ste-href.dtsi"
10
11/ {
12 gpio_keys {
13 button@1 {
14 gpios = <&tc3589x_gpio 7 GPIO_ACTIVE_HIGH>;
15 };
16 };
17
18 soc {
19 /* Enable UART1 on this board */
20 uart@80121000 {
21 status = "okay";
22 };
23
24 i2c@80004000 {
25 tps61052@33 {
26 compatible = "ti,tps61052";
27 reg = <0x33>;
28 };
29
30 tc35892@42 {
31 compatible = "toshiba,tc35892";
32 reg = <0x42>;
33 interrupt-parent = <&gpio6>;
34 interrupts = <25 IRQ_TYPE_EDGE_RISING>;
35 pinctrl-names = "default";
36 pinctrl-0 = <&tc35892_hrefprev60_mode>;
37
38 interrupt-controller;
39 #interrupt-cells = <1>;
40
41 tc3589x_gpio: tc3589x_gpio {
42 compatible = "tc3589x-gpio";
43 interrupts = <0>;
44
45 interrupt-controller;
46 #interrupt-cells = <2>;
47 gpio-controller;
48 #gpio-cells = <2>;
49 };
50 };
51 };
52
53 spi@80002000 {
54 /*
55 * On the first generation boards, this SSP/SPI port was connected
56 * to the AB8500.
57 */
58 pinctrl-names = "default";
59 pinctrl-0 = <&ssp0_hrefprev60_mode>;
60 status = "okay";
61 };
62
63 // External Micro SD slot
64 mmc@80126000 {
65 cd-gpios = <&tc3589x_gpio 3 GPIO_ACTIVE_HIGH>;
66 };
67
68 pinctrl {
69 /* Set this up using hogs */
70 pinctrl-names = "default";
71 pinctrl-0 = <&ipgpio_hrefprev60_mode>;
72
73 ssp0 {
74 ssp0_hrefprev60_mode: ssp0_hrefprev60_default {
75 hrefprev60_mux {
76 function = "ssp0";
77 groups = "ssp0_a_1";
78 };
79 hrefprev60_cfg1 {
80 pins = "GPIO145_C13"; /* RXD */
81 ste,config = <&in_pd>;
82 };
83
84 };
85 };
86 sdi0 {
87 /* This additional pin needed on early MOP500 and HREFs previous to v60 */
88 sdi0_default_mode: sdi0_default {
89 hrefprev60_mux {
90 function = "mc0";
91 groups = "mc0dat31dir_a_1";
92 };
93 hrefprev60_cfg1 {
94 pins = "GPIO21_AB3"; /* DAT31DIR */
95 ste,config = <&out_hi>;
96 };
97
98 };
99 };
100 tc35892 {
101 tc35892_hrefprev60_mode: tc35892_hrefprev60 {
102 hrefprev60_cfg {
103 pins = "GPIO217_AH12";
104 ste,config = <&gpio_in_pu>;
105 };
106 };
107 };
108 ipgpio {
109 ipgpio_hrefprev60_mode: ipgpio_hrefprev60 {
110 hrefprev60_mux {
111 function = "ipgpio";
112 groups = "ipgpio0_c_1", "ipgpio1_c_1";
113 };
114 hrefprev60_cfg1 {
115 pins = "GPIO6_AF6", "GPIO7_AG5";
116 ste,config = <&in_pu>;
117 };
118 };
119 };
120 };
121 };
122};