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1/*
2 * support for the bosch am335x based shc c3 board
3 *
4 * Copyright, C) 2015 Heiko Schocher <hs@denx.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10/dts-v1/;
11
12#include "am33xx.dtsi"
13#include <dt-bindings/input/input.h>
14
15/ {
16 model = "Bosch SHC";
17 compatible = "ti,am335x-shc", "ti,am335x-bone", "ti,am33xx";
18
19 aliases {
20 mmcblk0 = &mmc1;
21 mmcblk1 = &mmc2;
22 };
23
24 cpus {
25 cpu@0 {
26 /*
27 * To consider voltage drop between PMIC and SoC,
28 * tolerance value is reduced to 2% from 4% and
29 * voltage value is increased as a precaution.
30 */
31 operating-points = <
32 /* kHz uV */
33 594000 1225000
34 294000 1125000
35 >;
36 voltage-tolerance = <2>; /* 2 percentage */
37 cpu0-supply = <&dcdc2_reg>;
38 };
39 };
40
41 gpio_keys {
42 compatible = "gpio-keys";
43
44 back_button {
45 label = "Back Button";
46 gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
47 linux,code = <KEY_BACK>;
48 debounce-interval = <1000>;
49 wakeup-source;
50 };
51
52 front_button {
53 label = "Front Button";
54 gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
55 linux,code = <KEY_FRONT>;
56 debounce-interval = <1000>;
57 wakeup-source;
58 };
59 };
60
61 leds {
62 pinctrl-names = "default";
63 pinctrl-0 = <&user_leds_s0>;
64
65 compatible = "gpio-leds";
66
67 led1 {
68 label = "shc:power:red";
69 gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>;
70 default-state = "off";
71 };
72
73 led2 {
74 label = "shc:power:bl";
75 gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
76 linux,default-trigger = "timer";
77 default-state = "on";
78 };
79
80 led3 {
81 label = "shc:lan:red";
82 gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
83 default-state = "off";
84 };
85
86 led4 {
87 label = "shc:lan:bl";
88 gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
89 default-state = "off";
90 };
91
92 led5 {
93 label = "shc:cloud:red";
94 gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
95 default-state = "off";
96 };
97
98 led6 {
99 label = "shc:cloud:bl";
100 gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
101 default-state = "off";
102 };
103 };
104
105 memory@80000000 {
106 device_type = "memory";
107 reg = <0x80000000 0x20000000>; /* 512 MB */
108 };
109
110 vmmcsd_fixed: fixedregulator0 {
111 compatible = "regulator-fixed";
112 regulator-name = "vmmcsd_fixed";
113 regulator-min-microvolt = <3300000>;
114 regulator-max-microvolt = <3300000>;
115 };
116};
117
118&aes {
119 status = "okay";
120};
121
122&cppi41dma {
123 status = "okay";
124};
125
126&davinci_mdio {
127 pinctrl-names = "default", "sleep";
128 pinctrl-0 = <&davinci_mdio_default>;
129 pinctrl-1 = <&davinci_mdio_sleep>;
130 status = "okay";
131
132 ethernetphy0: ethernet-phy@0 {
133 reg = <0>;
134 smsc,disable-energy-detect;
135 };
136};
137
138&epwmss1 {
139 status = "okay";
140
141 ehrpwm1: pwm@48302200 {
142 pinctrl-names = "default";
143 pinctrl-0 = <&ehrpwm1_pins>;
144 status = "okay";
145 };
146};
147
148&gpio1 {
149 hmtc_rst {
150 gpio-hog;
151 gpios = <24 GPIO_ACTIVE_LOW>;
152 output-high;
153 line-name = "homematic_reset";
154 };
155
156 hmtc_prog {
157 gpio-hog;
158 gpios = <27 GPIO_ACTIVE_LOW>;
159 output-high;
160 line-name = "homematic_program";
161 };
162};
163
164&gpio3 {
165 zgb_rst {
166 gpio-hog;
167 gpios = <18 GPIO_ACTIVE_LOW>;
168 output-low;
169 line-name = "zigbee_reset";
170 };
171
172 zgb_boot {
173 gpio-hog;
174 gpios = <19 GPIO_ACTIVE_HIGH>;
175 output-high;
176 line-name = "zigbee_boot";
177 };
178};
179
180&i2c0 {
181 pinctrl-names = "default";
182 pinctrl-0 = <&i2c0_pins>;
183 status = "okay";
184 clock-frequency = <400000>;
185
186 tps: tps@24 {
187 reg = <0x24>;
188 };
189
190 at24@50 {
191 compatible = "atmel,24c32";
192 pagesize = <32>;
193 reg = <0x50>;
194 };
195
196 pcf8563@51 {
197 compatible = "nxp,pcf8563";
198 reg = <0x51>;
199 };
200};
201
202&mac {
203 pinctrl-names = "default", "sleep";
204 pinctrl-0 = <&cpsw_default>;
205 pinctrl-1 = <&cpsw_sleep>;
206 status = "okay";
207 slaves = <1>;
208 cpsw_emac0: slave@4a100200 {
209 phy_id = <&davinci_mdio>, <0>;
210 phy-mode = "mii";
211 phy-handle = <ðernetphy0>;
212 };
213};
214
215&mmc1 {
216 pinctrl-names = "default";
217 pinctrl-0 = <&mmc1_pins>;
218 bus-width = <0x4>;
219 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
220 cd-inverted;
221 max-frequency = <26000000>;
222 vmmc-supply = <&vmmcsd_fixed>;
223 status = "okay";
224};
225
226&mmc2 {
227 pinctrl-names = "default";
228 pinctrl-0 = <&emmc_pins>;
229 bus-width = <8>;
230 max-frequency = <26000000>;
231 sd-uhs-sdr25;
232 vmmc-supply = <&vmmcsd_fixed>;
233 status = "okay";
234};
235
236&mmc3 {
237 pinctrl-names = "default";
238 pinctrl-0 = <&mmc3_pins>;
239 bus-width = <4>;
240 cap-power-off-card;
241 max-frequency = <26000000>;
242 sd-uhs-sdr25;
243 vmmc-supply = <&vmmcsd_fixed>;
244 status = "okay";
245};
246
247&rtc {
248 ti,no-init;
249};
250
251&sham {
252 status = "okay";
253};
254
255&tps {
256 compatible = "ti,tps65217";
257 ti,pmic-shutdown-controller;
258
259 regulators {
260 #address-cells = <1>;
261 #size-cells = <0>;
262
263 dcdc1_reg: regulator@0 {
264 reg = <0>;
265 regulator-name = "vdds_dpr";
266 regulator-compatible = "dcdc1";
267 regulator-min-microvolt = <1300000>;
268 regulator-max-microvolt = <1450000>;
269 regulator-boot-on;
270 regulator-always-on;
271 };
272
273 dcdc2_reg: regulator@1 {
274 reg = <1>;
275 /*
276 * VDD_MPU voltage limits 0.95V - 1.26V with
277 * +/-4% tolerance
278 */
279 regulator-compatible = "dcdc2";
280 regulator-name = "vdd_mpu";
281 regulator-min-microvolt = <925000>;
282 regulator-max-microvolt = <1375000>;
283 regulator-boot-on;
284 regulator-always-on;
285 regulator-ramp-delay = <70000>;
286 };
287
288 dcdc3_reg: regulator@2 {
289 reg = <2>;
290 /*
291 * VDD_CORE voltage limits 0.95V - 1.1V with
292 * +/-4% tolerance
293 */
294 regulator-name = "vdd_core";
295 regulator-compatible = "dcdc3";
296 regulator-min-microvolt = <925000>;
297 regulator-max-microvolt = <1125000>;
298 regulator-boot-on;
299 regulator-always-on;
300 };
301
302 ldo1_reg: regulator@3 {
303 reg = <3>;
304 regulator-name = "vio,vrtc,vdds";
305 regulator-compatible = "ldo1";
306 regulator-min-microvolt = <1000000>;
307 regulator-max-microvolt = <1800000>;
308 regulator-always-on;
309 };
310
311 ldo2_reg: regulator@4 {
312 reg = <4>;
313 regulator-name = "vdd_3v3aux";
314 regulator-compatible = "ldo2";
315 regulator-min-microvolt = <900000>;
316 regulator-max-microvolt = <3300000>;
317 regulator-always-on;
318 };
319
320 ldo3_reg: regulator@5 {
321 reg = <5>;
322 regulator-name = "vdd_1v8";
323 regulator-compatible = "ldo3";
324 regulator-min-microvolt = <900000>;
325 regulator-max-microvolt = <1800000>;
326 regulator-always-on;
327 };
328
329 ldo4_reg: regulator@6 {
330 reg = <6>;
331 regulator-name = "vdd_3v3a";
332 regulator-compatible = "ldo4";
333 regulator-min-microvolt = <1800000>;
334 regulator-max-microvolt = <3300000>;
335 regulator-always-on;
336 };
337 };
338};
339
340&uart0 {
341 pinctrl-names = "default";
342 pinctrl-0 = <&uart0_pins>;
343 status = "okay";
344};
345
346&uart1 {
347 pinctrl-names = "default";
348 pinctrl-0 = <&uart1_pins>;
349 status = "okay";
350};
351
352&uart2 {
353 pinctrl-names = "default";
354 pinctrl-0 = <&uart2_pins>;
355 status = "okay";
356};
357
358&uart4 {
359 pinctrl-names = "default";
360 pinctrl-0 = <&uart4_pins>;
361 status = "okay";
362};
363
364&usb {
365 status = "okay";
366};
367
368&usb_ctrl_mod {
369 status = "okay";
370};
371
372&usb1_phy {
373 status = "okay";
374};
375
376&usb1 {
377 status = "okay";
378 dr_mode = "host";
379};
380
381&am33xx_pinmux {
382 pinctrl-names = "default";
383 pinctrl-0 = <&clkout2_pin>;
384
385 clkout2_pin: pinmux_clkout2_pin {
386 pinctrl-single,pins = <
387 /* xdma_event_intr1.clkout2 */
388 AM33XX_IOPAD(0x9b4, PIN_INPUT | MUX_MODE6)
389 >;
390 };
391
392 cpsw_default: cpsw_default {
393 pinctrl-single,pins = <
394 /* Slave 1 */
395 AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE0)
396 AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
397 AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE0)
398 AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
399 AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
400 AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE0)
401 AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE0)
402 AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE0)
403 AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE0)
404 AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE0)
405 AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE0)
406 AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE0)
407 AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE0)
408 >;
409 };
410
411 cpsw_sleep: cpsw_sleep {
412 pinctrl-single,pins = <
413 /* Slave 1 reset value */
414 AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
415 AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
416 AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
417 AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
418 AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
419 AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
420 AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
421 AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
422 AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
423 AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
424 AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
425 AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
426 AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
427 >;
428 };
429
430 davinci_mdio_default: davinci_mdio_default {
431 pinctrl-single,pins = <
432 /* mdio_data.mdio_data */
433 AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)
434 /* mdio_clk.mdio_clk */
435 AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)
436 >;
437 };
438
439 davinci_mdio_sleep: davinci_mdio_sleep {
440 pinctrl-single,pins = <
441 /* MDIO reset value */
442 AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
443 AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
444 >;
445 };
446
447 ehrpwm1_pins: pinmux_ehrpwm1 {
448 pinctrl-single,pins = <
449 AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE6) /* gpmc_a3.gpio1_19 */
450 >;
451 };
452
453 emmc_pins: pinmux_emmc_pins {
454 pinctrl-single,pins = <
455 AM33XX_IOPAD(0x880, PIN_INPUT | MUX_MODE2)
456 AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2)
457 AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1)
458 AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1)
459 AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1)
460 AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1)
461 AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1)
462 AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1)
463 AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1)
464 AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1)
465 >;
466 };
467
468 i2c0_pins: pinmux_i2c0_pins {
469 pinctrl-single,pins = <
470 AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0)
471 AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0)
472 >;
473 };
474
475 mmc1_pins: pinmux_mmc1_pins {
476 pinctrl-single,pins = <
477 AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE5)
478 >;
479 };
480
481 mmc3_pins: pinmux_mmc3_pins {
482 pinctrl-single,pins = <
483 AM33XX_IOPAD(0x830, PIN_INPUT | MUX_MODE3)
484 AM33XX_IOPAD(0x834, PIN_INPUT | MUX_MODE3)
485 AM33XX_IOPAD(0x838, PIN_INPUT | MUX_MODE3)
486 AM33XX_IOPAD(0x83c, PIN_INPUT | MUX_MODE3)
487 AM33XX_IOPAD(0x888, PIN_INPUT | MUX_MODE3)
488 AM33XX_IOPAD(0x88c, PIN_INPUT | MUX_MODE3)
489 >;
490 };
491
492 uart0_pins: pinmux_uart0_pins {
493 pinctrl-single,pins = <
494 AM33XX_IOPAD(0x968, PIN_INPUT_PULLDOWN | MUX_MODE0)
495 AM33XX_IOPAD(0x96c, PIN_OUTPUT | MUX_MODE0)
496 AM33XX_IOPAD(0x970, PIN_INPUT_PULLDOWN | MUX_MODE0)
497 AM33XX_IOPAD(0x974, PIN_OUTPUT | MUX_MODE0)
498 >;
499 };
500
501 uart1_pins: pinmux_uart1 {
502 pinctrl-single,pins = <
503 AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE0)
504 AM33XX_IOPAD(0x97C, PIN_OUTPUT | MUX_MODE0)
505 AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0)
506 AM33XX_IOPAD(0x984, PIN_OUTPUT | MUX_MODE0)
507 >;
508 };
509
510 uart2_pins: pinmux_uart2_pins {
511 pinctrl-single,pins = <
512 AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1)
513 AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1)
514 >;
515 };
516
517 uart4_pins: pinmux_uart4_pins {
518 pinctrl-single,pins = <
519 AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6)
520 AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE6)
521 >;
522 };
523
524 user_leds_s0: user_leds_s0 {
525 pinctrl-single,pins = <
526 AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE7)
527 AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE7)
528 AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE7)
529 AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE7)
530 AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE7)
531 AM33XX_IOPAD(0x844, PIN_OUTPUT | MUX_MODE7)
532 AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE7)
533 AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
534 AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7)
535 AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7)
536 AM33XX_IOPAD(0x85c, PIN_OUTPUT_PULLUP | MUX_MODE7)
537 AM33XX_IOPAD(0x860, PIN_INPUT | MUX_MODE7)
538 AM33XX_IOPAD(0x864, PIN_INPUT | MUX_MODE7)
539 AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE7)
540 AM33XX_IOPAD(0x86c, PIN_INPUT | MUX_MODE7)
541 AM33XX_IOPAD(0x878, PIN_OUTPUT_PULLUP | MUX_MODE7)
542 AM33XX_IOPAD(0x87c, PIN_INPUT | MUX_MODE7)
543 AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE7)
544 AM33XX_IOPAD(0x894, PIN_INPUT | MUX_MODE7)
545 AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE7)
546 AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE7)
547 AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE7)
548 AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE7)
549 AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE7)
550 AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE7)
551 AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE7)
552 AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE7)
553 AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE7)
554 AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE7)
555 AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE7)
556 AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE7)
557 AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE7)
558 AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE7)
559 AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE7)
560 AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE7)
561 AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE7)
562 AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE7)
563 AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE7)
564 AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE7)
565 AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE7)
566 AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE7)
567 AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
568 AM33XX_IOPAD(0x958, PIN_OUTPUT | MUX_MODE7)
569 AM33XX_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE7)
570 AM33XX_IOPAD(0x964, PIN_OUTPUT_PULLUP | MUX_MODE7)
571 AM33XX_IOPAD(0x9a0, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
572 AM33XX_IOPAD(0x9a4, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
573 AM33XX_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE7)
574 AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLUP | MUX_MODE7)
575 >;
576 };
577};
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * support for the bosch am335x based shc c3 board
4 *
5 * Copyright, C) 2015 Heiko Schocher <hs@denx.de>
6 *
7 */
8/dts-v1/;
9
10#include "am33xx.dtsi"
11#include <dt-bindings/input/input.h>
12
13/ {
14 model = "Bosch SHC";
15 compatible = "ti,am335x-shc", "ti,am335x-bone", "ti,am33xx";
16
17 aliases {
18 mmcblk0 = &mmc1;
19 mmcblk1 = &mmc2;
20 };
21
22 cpus {
23 cpu@0 {
24 /*
25 * To consider voltage drop between PMIC and SoC,
26 * tolerance value is reduced to 2% from 4% and
27 * voltage value is increased as a precaution.
28 */
29 operating-points = <
30 /* kHz uV */
31 594000 1225000
32 294000 1125000
33 >;
34 voltage-tolerance = <2>; /* 2 percentage */
35 cpu0-supply = <&dcdc2_reg>;
36 };
37 };
38
39 gpio-keys {
40 compatible = "gpio-keys";
41
42 back-button {
43 label = "Back Button";
44 gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
45 linux,code = <KEY_BACK>;
46 debounce-interval = <1000>;
47 wakeup-source;
48 };
49
50 front-button {
51 label = "Front Button";
52 gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
53 linux,code = <KEY_FRONT>;
54 debounce-interval = <1000>;
55 wakeup-source;
56 };
57 };
58
59 leds {
60 pinctrl-names = "default";
61 pinctrl-0 = <&user_leds_s0>;
62
63 compatible = "gpio-leds";
64
65 led1 {
66 label = "shc:power:red";
67 gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>;
68 default-state = "off";
69 };
70
71 led2 {
72 label = "shc:power:bl";
73 gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
74 linux,default-trigger = "timer";
75 default-state = "on";
76 };
77
78 led3 {
79 label = "shc:lan:red";
80 gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
81 default-state = "off";
82 };
83
84 led4 {
85 label = "shc:lan:bl";
86 gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
87 default-state = "off";
88 };
89
90 led5 {
91 label = "shc:cloud:red";
92 gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
93 default-state = "off";
94 };
95
96 led6 {
97 label = "shc:cloud:bl";
98 gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
99 default-state = "off";
100 };
101 };
102
103 memory@80000000 {
104 device_type = "memory";
105 reg = <0x80000000 0x20000000>; /* 512 MB */
106 };
107
108 vmmcsd_fixed: fixedregulator0 {
109 compatible = "regulator-fixed";
110 regulator-name = "vmmcsd_fixed";
111 regulator-min-microvolt = <3300000>;
112 regulator-max-microvolt = <3300000>;
113 };
114};
115
116&aes {
117 status = "okay";
118};
119
120&epwmss1 {
121 status = "okay";
122
123 ehrpwm1: pwm@200 {
124 pinctrl-names = "default";
125 pinctrl-0 = <&ehrpwm1_pins>;
126 status = "okay";
127 };
128};
129
130&gpio1 {
131 hmtc-rst-hog {
132 gpio-hog;
133 gpios = <24 GPIO_ACTIVE_LOW>;
134 output-high;
135 line-name = "homematic_reset";
136 };
137
138 hmtc-prog-hog {
139 gpio-hog;
140 gpios = <27 GPIO_ACTIVE_LOW>;
141 output-high;
142 line-name = "homematic_program";
143 };
144};
145
146&gpio3 {
147 zgb-rst-hog {
148 gpio-hog;
149 gpios = <18 GPIO_ACTIVE_LOW>;
150 output-low;
151 line-name = "zigbee_reset";
152 };
153
154 zgb-boot-hog {
155 gpio-hog;
156 gpios = <19 GPIO_ACTIVE_HIGH>;
157 output-high;
158 line-name = "zigbee_boot";
159 };
160};
161
162&i2c0 {
163 pinctrl-names = "default";
164 pinctrl-0 = <&i2c0_pins>;
165 status = "okay";
166 clock-frequency = <400000>;
167
168 tps: tps@24 {
169 reg = <0x24>;
170 };
171
172 at24@50 {
173 compatible = "atmel,24c32";
174 pagesize = <32>;
175 reg = <0x50>;
176 };
177
178 pcf8563@51 {
179 compatible = "nxp,pcf8563";
180 reg = <0x51>;
181 };
182};
183
184&mac_sw {
185 pinctrl-names = "default", "sleep";
186 pinctrl-0 = <&cpsw_default>;
187 pinctrl-1 = <&cpsw_sleep>;
188 status = "okay";
189};
190
191&cpsw_port1 {
192 phy-mode = "mii";
193 phy-handle = <ðernetphy0>;
194 ti,dual-emac-pvid = <1>;
195};
196
197&cpsw_port2 {
198 status = "disabled";
199};
200
201&davinci_mdio_sw {
202 pinctrl-names = "default", "sleep";
203 pinctrl-0 = <&davinci_mdio_default>;
204 pinctrl-1 = <&davinci_mdio_sleep>;
205
206 ethernetphy0: ethernet-phy@0 {
207 reg = <0>;
208 smsc,disable-energy-detect;
209 };
210};
211
212&mmc1 {
213 pinctrl-names = "default";
214 pinctrl-0 = <&mmc1_pins>;
215 bus-width = <0x4>;
216 cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
217 cd-inverted;
218 max-frequency = <26000000>;
219 vmmc-supply = <&vmmcsd_fixed>;
220 status = "okay";
221};
222
223&mmc2 {
224 pinctrl-names = "default";
225 pinctrl-0 = <&emmc_pins>;
226 bus-width = <8>;
227 max-frequency = <26000000>;
228 sd-uhs-sdr25;
229 vmmc-supply = <&vmmcsd_fixed>;
230 status = "okay";
231};
232
233&mmc3 {
234 pinctrl-names = "default";
235 pinctrl-0 = <&mmc3_pins>;
236 bus-width = <4>;
237 cap-power-off-card;
238 max-frequency = <26000000>;
239 sd-uhs-sdr25;
240 vmmc-supply = <&vmmcsd_fixed>;
241 status = "okay";
242};
243
244&rtc {
245 ti,no-init;
246};
247
248&sham {
249 status = "okay";
250};
251
252&tps {
253 compatible = "ti,tps65217";
254 ti,pmic-shutdown-controller;
255
256 regulators {
257 #address-cells = <1>;
258 #size-cells = <0>;
259
260 dcdc1_reg: regulator@0 {
261 reg = <0>;
262 regulator-name = "vdds_dpr";
263 regulator-compatible = "dcdc1";
264 regulator-min-microvolt = <1300000>;
265 regulator-max-microvolt = <1450000>;
266 regulator-boot-on;
267 regulator-always-on;
268 };
269
270 dcdc2_reg: regulator@1 {
271 reg = <1>;
272 /*
273 * VDD_MPU voltage limits 0.95V - 1.26V with
274 * +/-4% tolerance
275 */
276 regulator-compatible = "dcdc2";
277 regulator-name = "vdd_mpu";
278 regulator-min-microvolt = <925000>;
279 regulator-max-microvolt = <1375000>;
280 regulator-boot-on;
281 regulator-always-on;
282 regulator-ramp-delay = <70000>;
283 };
284
285 dcdc3_reg: regulator@2 {
286 reg = <2>;
287 /*
288 * VDD_CORE voltage limits 0.95V - 1.1V with
289 * +/-4% tolerance
290 */
291 regulator-name = "vdd_core";
292 regulator-compatible = "dcdc3";
293 regulator-min-microvolt = <925000>;
294 regulator-max-microvolt = <1125000>;
295 regulator-boot-on;
296 regulator-always-on;
297 };
298
299 ldo1_reg: regulator@3 {
300 reg = <3>;
301 regulator-name = "vio,vrtc,vdds";
302 regulator-compatible = "ldo1";
303 regulator-min-microvolt = <1000000>;
304 regulator-max-microvolt = <1800000>;
305 regulator-always-on;
306 };
307
308 ldo2_reg: regulator@4 {
309 reg = <4>;
310 regulator-name = "vdd_3v3aux";
311 regulator-compatible = "ldo2";
312 regulator-min-microvolt = <900000>;
313 regulator-max-microvolt = <3300000>;
314 regulator-always-on;
315 };
316
317 ldo3_reg: regulator@5 {
318 reg = <5>;
319 regulator-name = "vdd_1v8";
320 regulator-compatible = "ldo3";
321 regulator-min-microvolt = <900000>;
322 regulator-max-microvolt = <1800000>;
323 regulator-always-on;
324 };
325
326 ldo4_reg: regulator@6 {
327 reg = <6>;
328 regulator-name = "vdd_3v3a";
329 regulator-compatible = "ldo4";
330 regulator-min-microvolt = <1800000>;
331 regulator-max-microvolt = <3300000>;
332 regulator-always-on;
333 };
334 };
335};
336
337&uart0 {
338 pinctrl-names = "default";
339 pinctrl-0 = <&uart0_pins>;
340 status = "okay";
341};
342
343&uart1 {
344 pinctrl-names = "default";
345 pinctrl-0 = <&uart1_pins>;
346 status = "okay";
347};
348
349&uart2 {
350 pinctrl-names = "default";
351 pinctrl-0 = <&uart2_pins>;
352 status = "okay";
353};
354
355&uart4 {
356 pinctrl-names = "default";
357 pinctrl-0 = <&uart4_pins>;
358 status = "okay";
359};
360
361&usb1 {
362 dr_mode = "host";
363};
364
365&am33xx_pinmux {
366 pinctrl-names = "default";
367 pinctrl-0 = <&clkout2_pin>;
368
369 clkout2_pin: pinmux_clkout2_pin {
370 pinctrl-single,pins = <
371 /* xdma_event_intr1.clkout2 */
372 AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT, MUX_MODE6)
373 >;
374 };
375
376 cpsw_default: cpsw_default {
377 pinctrl-single,pins = <
378 /* Slave 1 */
379 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE0)
380 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
381 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE0)
382 AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
383 AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
384 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE0)
385 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE0)
386 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
387 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
388 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE0)
389 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE0)
390 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE0)
391 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE0)
392 >;
393 };
394
395 cpsw_sleep: cpsw_sleep {
396 pinctrl-single,pins = <
397 /* Slave 1 reset value */
398 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
399 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
400 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
401 AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
402 AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
403 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
404 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
405 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
406 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
407 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
408 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
409 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
410 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
411 >;
412 };
413
414 davinci_mdio_default: davinci_mdio_default {
415 pinctrl-single,pins = <
416 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
417 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
418 >;
419 };
420
421 davinci_mdio_sleep: davinci_mdio_sleep {
422 pinctrl-single,pins = <
423 /* MDIO reset value */
424 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
425 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
426 >;
427 };
428
429 ehrpwm1_pins: pinmux_ehrpwm1 {
430 pinctrl-single,pins = <
431 AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE6) /* gpmc_a3.gpio1_19 */
432 >;
433 };
434
435 emmc_pins: pinmux_emmc_pins {
436 pinctrl-single,pins = <
437 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT, MUX_MODE2)
438 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2)
439 AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1)
440 AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1)
441 AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1)
442 AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1)
443 AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1)
444 AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1)
445 AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1)
446 AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1)
447 >;
448 };
449
450 i2c0_pins: pinmux_i2c0_pins {
451 pinctrl-single,pins = <
452 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0)
453 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0)
454 >;
455 };
456
457 mmc1_pins: pinmux_mmc1_pins {
458 pinctrl-single,pins = <
459 AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE5)
460 >;
461 };
462
463 mmc3_pins: pinmux_mmc3_pins {
464 pinctrl-single,pins = <
465 AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT, MUX_MODE3)
466 AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT, MUX_MODE3)
467 AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT, MUX_MODE3)
468 AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT, MUX_MODE3)
469 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT, MUX_MODE3)
470 AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT, MUX_MODE3)
471 >;
472 };
473
474 uart0_pins: pinmux_uart0_pins {
475 pinctrl-single,pins = <
476 AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0)
477 AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE0)
478 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLDOWN, MUX_MODE0)
479 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT, MUX_MODE0)
480 >;
481 };
482
483 uart1_pins: pinmux_uart1 {
484 pinctrl-single,pins = <
485 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0)
486 AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT, MUX_MODE0)
487 AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0)
488 AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0)
489 >;
490 };
491
492 uart2_pins: pinmux_uart2_pins {
493 pinctrl-single,pins = <
494 AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1)
495 AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1)
496 >;
497 };
498
499 uart4_pins: pinmux_uart4_pins {
500 pinctrl-single,pins = <
501 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6)
502 AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLUP, MUX_MODE6)
503 >;
504 };
505
506 user_leds_s0: user_leds_s0 {
507 pinctrl-single,pins = <
508 AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE7)
509 AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE7)
510 AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7)
511 AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7)
512 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE7)
513 AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_OUTPUT, MUX_MODE7)
514 AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE7)
515 AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE7)
516 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7)
517 AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7)
518 AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLUP, MUX_MODE7)
519 AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT, MUX_MODE7)
520 AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE7)
521 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7)
522 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT, MUX_MODE7)
523 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_OUTPUT_PULLUP, MUX_MODE7)
524 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_INPUT, MUX_MODE7)
525 AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE7)
526 AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT, MUX_MODE7)
527 AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE7)
528 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE7)
529 AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE7)
530 AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE7)
531 AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE7)
532 AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE7)
533 AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE7)
534 AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE7)
535 AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE7)
536 AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE7)
537 AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE7)
538 AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE7)
539 AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE7)
540 AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE7)
541 AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE7)
542 AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE7)
543 AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE7)
544 AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE7)
545 AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE7)
546 AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE7)
547 AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE7)
548 AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE7)
549 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
550 AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_OUTPUT, MUX_MODE7)
551 AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE7)
552 AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLUP, MUX_MODE7)
553 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE7)
554 AM33XX_PADCONF(AM335X_PIN_MCASP0_FSR, PIN_OUTPUT_PULLDOWN, MUX_MODE7)
555 AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE7)
556 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE7)
557 >;
558 };
559};