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1/*
2 * STMicroelectronics STM32 SPI Controller driver (master mode only)
3 *
4 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
5 * Author(s): Amelie Delaunay <amelie.delaunay@st.com> for STMicroelectronics.
6 *
7 * License terms: GPL V2.0.
8 *
9 * spi_stm32 driver is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * spi_stm32 driver is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
16 * details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * spi_stm32 driver. If not, see <http://www.gnu.org/licenses/>.
20 */
21#include <linux/debugfs.h>
22#include <linux/clk.h>
23#include <linux/delay.h>
24#include <linux/dmaengine.h>
25#include <linux/gpio.h>
26#include <linux/interrupt.h>
27#include <linux/iopoll.h>
28#include <linux/module.h>
29#include <linux/of_platform.h>
30#include <linux/pm_runtime.h>
31#include <linux/reset.h>
32#include <linux/spi/spi.h>
33
34#define DRIVER_NAME "spi_stm32"
35
36/* STM32 SPI registers */
37#define STM32_SPI_CR1 0x00
38#define STM32_SPI_CR2 0x04
39#define STM32_SPI_CFG1 0x08
40#define STM32_SPI_CFG2 0x0C
41#define STM32_SPI_IER 0x10
42#define STM32_SPI_SR 0x14
43#define STM32_SPI_IFCR 0x18
44#define STM32_SPI_TXDR 0x20
45#define STM32_SPI_RXDR 0x30
46#define STM32_SPI_I2SCFGR 0x50
47
48/* STM32_SPI_CR1 bit fields */
49#define SPI_CR1_SPE BIT(0)
50#define SPI_CR1_MASRX BIT(8)
51#define SPI_CR1_CSTART BIT(9)
52#define SPI_CR1_CSUSP BIT(10)
53#define SPI_CR1_HDDIR BIT(11)
54#define SPI_CR1_SSI BIT(12)
55
56/* STM32_SPI_CR2 bit fields */
57#define SPI_CR2_TSIZE_SHIFT 0
58#define SPI_CR2_TSIZE GENMASK(15, 0)
59
60/* STM32_SPI_CFG1 bit fields */
61#define SPI_CFG1_DSIZE_SHIFT 0
62#define SPI_CFG1_DSIZE GENMASK(4, 0)
63#define SPI_CFG1_FTHLV_SHIFT 5
64#define SPI_CFG1_FTHLV GENMASK(8, 5)
65#define SPI_CFG1_RXDMAEN BIT(14)
66#define SPI_CFG1_TXDMAEN BIT(15)
67#define SPI_CFG1_MBR_SHIFT 28
68#define SPI_CFG1_MBR GENMASK(30, 28)
69#define SPI_CFG1_MBR_MIN 0
70#define SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28)
71
72/* STM32_SPI_CFG2 bit fields */
73#define SPI_CFG2_MIDI_SHIFT 4
74#define SPI_CFG2_MIDI GENMASK(7, 4)
75#define SPI_CFG2_COMM_SHIFT 17
76#define SPI_CFG2_COMM GENMASK(18, 17)
77#define SPI_CFG2_SP_SHIFT 19
78#define SPI_CFG2_SP GENMASK(21, 19)
79#define SPI_CFG2_MASTER BIT(22)
80#define SPI_CFG2_LSBFRST BIT(23)
81#define SPI_CFG2_CPHA BIT(24)
82#define SPI_CFG2_CPOL BIT(25)
83#define SPI_CFG2_SSM BIT(26)
84#define SPI_CFG2_AFCNTR BIT(31)
85
86/* STM32_SPI_IER bit fields */
87#define SPI_IER_RXPIE BIT(0)
88#define SPI_IER_TXPIE BIT(1)
89#define SPI_IER_DXPIE BIT(2)
90#define SPI_IER_EOTIE BIT(3)
91#define SPI_IER_TXTFIE BIT(4)
92#define SPI_IER_OVRIE BIT(6)
93#define SPI_IER_MODFIE BIT(9)
94#define SPI_IER_ALL GENMASK(10, 0)
95
96/* STM32_SPI_SR bit fields */
97#define SPI_SR_RXP BIT(0)
98#define SPI_SR_TXP BIT(1)
99#define SPI_SR_EOT BIT(3)
100#define SPI_SR_OVR BIT(6)
101#define SPI_SR_MODF BIT(9)
102#define SPI_SR_SUSP BIT(11)
103#define SPI_SR_RXPLVL_SHIFT 13
104#define SPI_SR_RXPLVL GENMASK(14, 13)
105#define SPI_SR_RXWNE BIT(15)
106
107/* STM32_SPI_IFCR bit fields */
108#define SPI_IFCR_ALL GENMASK(11, 3)
109
110/* STM32_SPI_I2SCFGR bit fields */
111#define SPI_I2SCFGR_I2SMOD BIT(0)
112
113/* SPI Master Baud Rate min/max divisor */
114#define SPI_MBR_DIV_MIN (2 << SPI_CFG1_MBR_MIN)
115#define SPI_MBR_DIV_MAX (2 << SPI_CFG1_MBR_MAX)
116
117/* SPI Communication mode */
118#define SPI_FULL_DUPLEX 0
119#define SPI_SIMPLEX_TX 1
120#define SPI_SIMPLEX_RX 2
121#define SPI_HALF_DUPLEX 3
122
123#define SPI_1HZ_NS 1000000000
124
125/**
126 * struct stm32_spi - private data of the SPI controller
127 * @dev: driver model representation of the controller
128 * @master: controller master interface
129 * @base: virtual memory area
130 * @clk: hw kernel clock feeding the SPI clock generator
131 * @clk_rate: rate of the hw kernel clock feeding the SPI clock generator
132 * @rst: SPI controller reset line
133 * @lock: prevent I/O concurrent access
134 * @irq: SPI controller interrupt line
135 * @fifo_size: size of the embedded fifo in bytes
136 * @cur_midi: master inter-data idleness in ns
137 * @cur_speed: speed configured in Hz
138 * @cur_bpw: number of bits in a single SPI data frame
139 * @cur_fthlv: fifo threshold level (data frames in a single data packet)
140 * @cur_comm: SPI communication mode
141 * @cur_xferlen: current transfer length in bytes
142 * @cur_usedma: boolean to know if dma is used in current transfer
143 * @tx_buf: data to be written, or NULL
144 * @rx_buf: data to be read, or NULL
145 * @tx_len: number of data to be written in bytes
146 * @rx_len: number of data to be read in bytes
147 * @dma_tx: dma channel for TX transfer
148 * @dma_rx: dma channel for RX transfer
149 * @phys_addr: SPI registers physical base address
150 */
151struct stm32_spi {
152 struct device *dev;
153 struct spi_master *master;
154 void __iomem *base;
155 struct clk *clk;
156 u32 clk_rate;
157 struct reset_control *rst;
158 spinlock_t lock; /* prevent I/O concurrent access */
159 int irq;
160 unsigned int fifo_size;
161
162 unsigned int cur_midi;
163 unsigned int cur_speed;
164 unsigned int cur_bpw;
165 unsigned int cur_fthlv;
166 unsigned int cur_comm;
167 unsigned int cur_xferlen;
168 bool cur_usedma;
169
170 const void *tx_buf;
171 void *rx_buf;
172 int tx_len;
173 int rx_len;
174 struct dma_chan *dma_tx;
175 struct dma_chan *dma_rx;
176 dma_addr_t phys_addr;
177};
178
179static inline void stm32_spi_set_bits(struct stm32_spi *spi,
180 u32 offset, u32 bits)
181{
182 writel_relaxed(readl_relaxed(spi->base + offset) | bits,
183 spi->base + offset);
184}
185
186static inline void stm32_spi_clr_bits(struct stm32_spi *spi,
187 u32 offset, u32 bits)
188{
189 writel_relaxed(readl_relaxed(spi->base + offset) & ~bits,
190 spi->base + offset);
191}
192
193/**
194 * stm32_spi_get_fifo_size - Return fifo size
195 * @spi: pointer to the spi controller data structure
196 */
197static int stm32_spi_get_fifo_size(struct stm32_spi *spi)
198{
199 unsigned long flags;
200 u32 count = 0;
201
202 spin_lock_irqsave(&spi->lock, flags);
203
204 stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE);
205
206 while (readl_relaxed(spi->base + STM32_SPI_SR) & SPI_SR_TXP)
207 writeb_relaxed(++count, spi->base + STM32_SPI_TXDR);
208
209 stm32_spi_clr_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE);
210
211 spin_unlock_irqrestore(&spi->lock, flags);
212
213 dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count);
214
215 return count;
216}
217
218/**
219 * stm32_spi_get_bpw_mask - Return bits per word mask
220 * @spi: pointer to the spi controller data structure
221 */
222static int stm32_spi_get_bpw_mask(struct stm32_spi *spi)
223{
224 unsigned long flags;
225 u32 cfg1, max_bpw;
226
227 spin_lock_irqsave(&spi->lock, flags);
228
229 /*
230 * The most significant bit at DSIZE bit field is reserved when the
231 * maximum data size of periperal instances is limited to 16-bit
232 */
233 stm32_spi_set_bits(spi, STM32_SPI_CFG1, SPI_CFG1_DSIZE);
234
235 cfg1 = readl_relaxed(spi->base + STM32_SPI_CFG1);
236 max_bpw = (cfg1 & SPI_CFG1_DSIZE) >> SPI_CFG1_DSIZE_SHIFT;
237 max_bpw += 1;
238
239 spin_unlock_irqrestore(&spi->lock, flags);
240
241 dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw);
242
243 return SPI_BPW_RANGE_MASK(4, max_bpw);
244}
245
246/**
247 * stm32_spi_prepare_mbr - Determine SPI_CFG1.MBR value
248 * @spi: pointer to the spi controller data structure
249 * @speed_hz: requested speed
250 *
251 * Return SPI_CFG1.MBR value in case of success or -EINVAL
252 */
253static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz)
254{
255 u32 div, mbrdiv;
256
257 div = DIV_ROUND_UP(spi->clk_rate, speed_hz);
258
259 /*
260 * SPI framework set xfer->speed_hz to master->max_speed_hz if
261 * xfer->speed_hz is greater than master->max_speed_hz, and it returns
262 * an error when xfer->speed_hz is lower than master->min_speed_hz, so
263 * no need to check it there.
264 * However, we need to ensure the following calculations.
265 */
266 if (div < SPI_MBR_DIV_MIN ||
267 div > SPI_MBR_DIV_MAX)
268 return -EINVAL;
269
270 /* Determine the first power of 2 greater than or equal to div */
271 if (div & (div - 1))
272 mbrdiv = fls(div);
273 else
274 mbrdiv = fls(div) - 1;
275
276 spi->cur_speed = spi->clk_rate / (1 << mbrdiv);
277
278 return mbrdiv - 1;
279}
280
281/**
282 * stm32_spi_prepare_fthlv - Determine FIFO threshold level
283 * @spi: pointer to the spi controller data structure
284 */
285static u32 stm32_spi_prepare_fthlv(struct stm32_spi *spi)
286{
287 u32 fthlv, half_fifo;
288
289 /* data packet should not exceed 1/2 of fifo space */
290 half_fifo = (spi->fifo_size / 2);
291
292 if (spi->cur_bpw <= 8)
293 fthlv = half_fifo;
294 else if (spi->cur_bpw <= 16)
295 fthlv = half_fifo / 2;
296 else
297 fthlv = half_fifo / 4;
298
299 /* align packet size with data registers access */
300 if (spi->cur_bpw > 8)
301 fthlv -= (fthlv % 2); /* multiple of 2 */
302 else
303 fthlv -= (fthlv % 4); /* multiple of 4 */
304
305 return fthlv;
306}
307
308/**
309 * stm32_spi_write_txfifo - Write bytes in Transmit Data Register
310 * @spi: pointer to the spi controller data structure
311 *
312 * Read from tx_buf depends on remaining bytes to avoid to read beyond
313 * tx_buf end.
314 */
315static void stm32_spi_write_txfifo(struct stm32_spi *spi)
316{
317 while ((spi->tx_len > 0) &&
318 (readl_relaxed(spi->base + STM32_SPI_SR) & SPI_SR_TXP)) {
319 u32 offs = spi->cur_xferlen - spi->tx_len;
320
321 if (spi->tx_len >= sizeof(u32)) {
322 const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs);
323
324 writel_relaxed(*tx_buf32, spi->base + STM32_SPI_TXDR);
325 spi->tx_len -= sizeof(u32);
326 } else if (spi->tx_len >= sizeof(u16)) {
327 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
328
329 writew_relaxed(*tx_buf16, spi->base + STM32_SPI_TXDR);
330 spi->tx_len -= sizeof(u16);
331 } else {
332 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
333
334 writeb_relaxed(*tx_buf8, spi->base + STM32_SPI_TXDR);
335 spi->tx_len -= sizeof(u8);
336 }
337 }
338
339 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
340}
341
342/**
343 * stm32_spi_read_rxfifo - Read bytes in Receive Data Register
344 * @spi: pointer to the spi controller data structure
345 *
346 * Write in rx_buf depends on remaining bytes to avoid to write beyond
347 * rx_buf end.
348 */
349static void stm32_spi_read_rxfifo(struct stm32_spi *spi, bool flush)
350{
351 u32 sr = readl_relaxed(spi->base + STM32_SPI_SR);
352 u32 rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
353
354 while ((spi->rx_len > 0) &&
355 ((sr & SPI_SR_RXP) ||
356 (flush && ((sr & SPI_SR_RXWNE) || (rxplvl > 0))))) {
357 u32 offs = spi->cur_xferlen - spi->rx_len;
358
359 if ((spi->rx_len >= sizeof(u32)) ||
360 (flush && (sr & SPI_SR_RXWNE))) {
361 u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs);
362
363 *rx_buf32 = readl_relaxed(spi->base + STM32_SPI_RXDR);
364 spi->rx_len -= sizeof(u32);
365 } else if ((spi->rx_len >= sizeof(u16)) ||
366 (flush && (rxplvl >= 2 || spi->cur_bpw > 8))) {
367 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
368
369 *rx_buf16 = readw_relaxed(spi->base + STM32_SPI_RXDR);
370 spi->rx_len -= sizeof(u16);
371 } else {
372 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
373
374 *rx_buf8 = readb_relaxed(spi->base + STM32_SPI_RXDR);
375 spi->rx_len -= sizeof(u8);
376 }
377
378 sr = readl_relaxed(spi->base + STM32_SPI_SR);
379 rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
380 }
381
382 dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__,
383 flush ? "(flush)" : "", spi->rx_len);
384}
385
386/**
387 * stm32_spi_enable - Enable SPI controller
388 * @spi: pointer to the spi controller data structure
389 *
390 * SPI data transfer is enabled but spi_ker_ck is idle.
391 * SPI_CFG1 and SPI_CFG2 are now write protected.
392 */
393static void stm32_spi_enable(struct stm32_spi *spi)
394{
395 dev_dbg(spi->dev, "enable controller\n");
396
397 stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE);
398}
399
400/**
401 * stm32_spi_disable - Disable SPI controller
402 * @spi: pointer to the spi controller data structure
403 *
404 * RX-Fifo is flushed when SPI controller is disabled. To prevent any data
405 * loss, use stm32_spi_read_rxfifo(flush) to read the remaining bytes in
406 * RX-Fifo.
407 */
408static void stm32_spi_disable(struct stm32_spi *spi)
409{
410 unsigned long flags;
411 u32 cr1, sr;
412
413 dev_dbg(spi->dev, "disable controller\n");
414
415 spin_lock_irqsave(&spi->lock, flags);
416
417 cr1 = readl_relaxed(spi->base + STM32_SPI_CR1);
418
419 if (!(cr1 & SPI_CR1_SPE)) {
420 spin_unlock_irqrestore(&spi->lock, flags);
421 return;
422 }
423
424 /* Wait on EOT or suspend the flow */
425 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32_SPI_SR,
426 sr, !(sr & SPI_SR_EOT),
427 10, 100000) < 0) {
428 if (cr1 & SPI_CR1_CSTART) {
429 writel_relaxed(cr1 | SPI_CR1_CSUSP,
430 spi->base + STM32_SPI_CR1);
431 if (readl_relaxed_poll_timeout_atomic(
432 spi->base + STM32_SPI_SR,
433 sr, !(sr & SPI_SR_SUSP),
434 10, 100000) < 0)
435 dev_warn(spi->dev,
436 "Suspend request timeout\n");
437 }
438 }
439
440 if (!spi->cur_usedma && spi->rx_buf && (spi->rx_len > 0))
441 stm32_spi_read_rxfifo(spi, true);
442
443 if (spi->cur_usedma && spi->tx_buf)
444 dmaengine_terminate_all(spi->dma_tx);
445 if (spi->cur_usedma && spi->rx_buf)
446 dmaengine_terminate_all(spi->dma_rx);
447
448 stm32_spi_clr_bits(spi, STM32_SPI_CR1, SPI_CR1_SPE);
449
450 stm32_spi_clr_bits(spi, STM32_SPI_CFG1, SPI_CFG1_TXDMAEN |
451 SPI_CFG1_RXDMAEN);
452
453 /* Disable interrupts and clear status flags */
454 writel_relaxed(0, spi->base + STM32_SPI_IER);
455 writel_relaxed(SPI_IFCR_ALL, spi->base + STM32_SPI_IFCR);
456
457 spin_unlock_irqrestore(&spi->lock, flags);
458}
459
460/**
461 * stm32_spi_can_dma - Determine if the transfer is eligible for DMA use
462 *
463 * If the current transfer size is greater than fifo size, use DMA.
464 */
465static bool stm32_spi_can_dma(struct spi_master *master,
466 struct spi_device *spi_dev,
467 struct spi_transfer *transfer)
468{
469 struct stm32_spi *spi = spi_master_get_devdata(master);
470
471 dev_dbg(spi->dev, "%s: %s\n", __func__,
472 (transfer->len > spi->fifo_size) ? "true" : "false");
473
474 return (transfer->len > spi->fifo_size);
475}
476
477/**
478 * stm32_spi_irq - Interrupt handler for SPI controller events
479 * @irq: interrupt line
480 * @dev_id: SPI controller master interface
481 */
482static irqreturn_t stm32_spi_irq(int irq, void *dev_id)
483{
484 struct spi_master *master = dev_id;
485 struct stm32_spi *spi = spi_master_get_devdata(master);
486 u32 sr, ier, mask;
487 unsigned long flags;
488 bool end = false;
489
490 spin_lock_irqsave(&spi->lock, flags);
491
492 sr = readl_relaxed(spi->base + STM32_SPI_SR);
493 ier = readl_relaxed(spi->base + STM32_SPI_IER);
494
495 mask = ier;
496 /* EOTIE is triggered on EOT, SUSP and TXC events. */
497 mask |= SPI_SR_SUSP;
498 /*
499 * When TXTF is set, DXPIE and TXPIE are cleared. So in case of
500 * Full-Duplex, need to poll RXP event to know if there are remaining
501 * data, before disabling SPI.
502 */
503 if (spi->rx_buf && !spi->cur_usedma)
504 mask |= SPI_SR_RXP;
505
506 if (!(sr & mask)) {
507 dev_dbg(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
508 sr, ier);
509 spin_unlock_irqrestore(&spi->lock, flags);
510 return IRQ_NONE;
511 }
512
513 if (sr & SPI_SR_SUSP) {
514 dev_warn(spi->dev, "Communication suspended\n");
515 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
516 stm32_spi_read_rxfifo(spi, false);
517 /*
518 * If communication is suspended while using DMA, it means
519 * that something went wrong, so stop the current transfer
520 */
521 if (spi->cur_usedma)
522 end = true;
523 }
524
525 if (sr & SPI_SR_MODF) {
526 dev_warn(spi->dev, "Mode fault: transfer aborted\n");
527 end = true;
528 }
529
530 if (sr & SPI_SR_OVR) {
531 dev_warn(spi->dev, "Overrun: received value discarded\n");
532 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
533 stm32_spi_read_rxfifo(spi, false);
534 /*
535 * If overrun is detected while using DMA, it means that
536 * something went wrong, so stop the current transfer
537 */
538 if (spi->cur_usedma)
539 end = true;
540 }
541
542 if (sr & SPI_SR_EOT) {
543 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
544 stm32_spi_read_rxfifo(spi, true);
545 end = true;
546 }
547
548 if (sr & SPI_SR_TXP)
549 if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0)))
550 stm32_spi_write_txfifo(spi);
551
552 if (sr & SPI_SR_RXP)
553 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
554 stm32_spi_read_rxfifo(spi, false);
555
556 writel_relaxed(mask, spi->base + STM32_SPI_IFCR);
557
558 spin_unlock_irqrestore(&spi->lock, flags);
559
560 if (end) {
561 spi_finalize_current_transfer(master);
562 stm32_spi_disable(spi);
563 }
564
565 return IRQ_HANDLED;
566}
567
568/**
569 * stm32_spi_setup - setup device chip select
570 */
571static int stm32_spi_setup(struct spi_device *spi_dev)
572{
573 int ret = 0;
574
575 if (!gpio_is_valid(spi_dev->cs_gpio)) {
576 dev_err(&spi_dev->dev, "%d is not a valid gpio\n",
577 spi_dev->cs_gpio);
578 return -EINVAL;
579 }
580
581 dev_dbg(&spi_dev->dev, "%s: set gpio%d output %s\n", __func__,
582 spi_dev->cs_gpio,
583 (spi_dev->mode & SPI_CS_HIGH) ? "low" : "high");
584
585 ret = gpio_direction_output(spi_dev->cs_gpio,
586 !(spi_dev->mode & SPI_CS_HIGH));
587
588 return ret;
589}
590
591/**
592 * stm32_spi_prepare_msg - set up the controller to transfer a single message
593 */
594static int stm32_spi_prepare_msg(struct spi_master *master,
595 struct spi_message *msg)
596{
597 struct stm32_spi *spi = spi_master_get_devdata(master);
598 struct spi_device *spi_dev = msg->spi;
599 struct device_node *np = spi_dev->dev.of_node;
600 unsigned long flags;
601 u32 cfg2_clrb = 0, cfg2_setb = 0;
602
603 /* SPI slave device may need time between data frames */
604 spi->cur_midi = 0;
605 if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi))
606 dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi);
607
608 if (spi_dev->mode & SPI_CPOL)
609 cfg2_setb |= SPI_CFG2_CPOL;
610 else
611 cfg2_clrb |= SPI_CFG2_CPOL;
612
613 if (spi_dev->mode & SPI_CPHA)
614 cfg2_setb |= SPI_CFG2_CPHA;
615 else
616 cfg2_clrb |= SPI_CFG2_CPHA;
617
618 if (spi_dev->mode & SPI_LSB_FIRST)
619 cfg2_setb |= SPI_CFG2_LSBFRST;
620 else
621 cfg2_clrb |= SPI_CFG2_LSBFRST;
622
623 dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n",
624 spi_dev->mode & SPI_CPOL,
625 spi_dev->mode & SPI_CPHA,
626 spi_dev->mode & SPI_LSB_FIRST,
627 spi_dev->mode & SPI_CS_HIGH);
628
629 spin_lock_irqsave(&spi->lock, flags);
630
631 if (cfg2_clrb || cfg2_setb)
632 writel_relaxed(
633 (readl_relaxed(spi->base + STM32_SPI_CFG2) &
634 ~cfg2_clrb) | cfg2_setb,
635 spi->base + STM32_SPI_CFG2);
636
637 spin_unlock_irqrestore(&spi->lock, flags);
638
639 return 0;
640}
641
642/**
643 * stm32_spi_dma_cb - dma callback
644 *
645 * DMA callback is called when the transfer is complete or when an error
646 * occurs. If the transfer is complete, EOT flag is raised.
647 */
648static void stm32_spi_dma_cb(void *data)
649{
650 struct stm32_spi *spi = data;
651 unsigned long flags;
652 u32 sr;
653
654 spin_lock_irqsave(&spi->lock, flags);
655
656 sr = readl_relaxed(spi->base + STM32_SPI_SR);
657
658 spin_unlock_irqrestore(&spi->lock, flags);
659
660 if (!(sr & SPI_SR_EOT))
661 dev_warn(spi->dev, "DMA error (sr=0x%08x)\n", sr);
662
663 /* Now wait for EOT, or SUSP or OVR in case of error */
664}
665
666/**
667 * stm32_spi_dma_config - configure dma slave channel depending on current
668 * transfer bits_per_word.
669 */
670static void stm32_spi_dma_config(struct stm32_spi *spi,
671 struct dma_slave_config *dma_conf,
672 enum dma_transfer_direction dir)
673{
674 enum dma_slave_buswidth buswidth;
675 u32 maxburst;
676
677 if (spi->cur_bpw <= 8)
678 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
679 else if (spi->cur_bpw <= 16)
680 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
681 else
682 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
683
684 /* Valid for DMA Half or Full Fifo threshold */
685 if (spi->cur_fthlv == 2)
686 maxburst = 1;
687 else
688 maxburst = spi->cur_fthlv;
689
690 memset(dma_conf, 0, sizeof(struct dma_slave_config));
691 dma_conf->direction = dir;
692 if (dma_conf->direction == DMA_DEV_TO_MEM) { /* RX */
693 dma_conf->src_addr = spi->phys_addr + STM32_SPI_RXDR;
694 dma_conf->src_addr_width = buswidth;
695 dma_conf->src_maxburst = maxburst;
696
697 dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n",
698 buswidth, maxburst);
699 } else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */
700 dma_conf->dst_addr = spi->phys_addr + STM32_SPI_TXDR;
701 dma_conf->dst_addr_width = buswidth;
702 dma_conf->dst_maxburst = maxburst;
703
704 dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n",
705 buswidth, maxburst);
706 }
707}
708
709/**
710 * stm32_spi_transfer_one_irq - transfer a single spi_transfer using
711 * interrupts
712 *
713 * It must returns 0 if the transfer is finished or 1 if the transfer is still
714 * in progress.
715 */
716static int stm32_spi_transfer_one_irq(struct stm32_spi *spi)
717{
718 unsigned long flags;
719 u32 ier = 0;
720
721 /* Enable the interrupts relative to the current communication mode */
722 if (spi->tx_buf && spi->rx_buf) /* Full Duplex */
723 ier |= SPI_IER_DXPIE;
724 else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */
725 ier |= SPI_IER_TXPIE;
726 else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */
727 ier |= SPI_IER_RXPIE;
728
729 /* Enable the interrupts relative to the end of transfer */
730 ier |= SPI_IER_EOTIE | SPI_IER_TXTFIE | SPI_IER_OVRIE | SPI_IER_MODFIE;
731
732 spin_lock_irqsave(&spi->lock, flags);
733
734 stm32_spi_enable(spi);
735
736 /* Be sure to have data in fifo before starting data transfer */
737 if (spi->tx_buf)
738 stm32_spi_write_txfifo(spi);
739
740 stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_CSTART);
741
742 writel_relaxed(ier, spi->base + STM32_SPI_IER);
743
744 spin_unlock_irqrestore(&spi->lock, flags);
745
746 return 1;
747}
748
749/**
750 * stm32_spi_transfer_one_dma - transfer a single spi_transfer using DMA
751 *
752 * It must returns 0 if the transfer is finished or 1 if the transfer is still
753 * in progress.
754 */
755static int stm32_spi_transfer_one_dma(struct stm32_spi *spi,
756 struct spi_transfer *xfer)
757{
758 struct dma_slave_config tx_dma_conf, rx_dma_conf;
759 struct dma_async_tx_descriptor *tx_dma_desc, *rx_dma_desc;
760 unsigned long flags;
761 u32 ier = 0;
762
763 spin_lock_irqsave(&spi->lock, flags);
764
765 rx_dma_desc = NULL;
766 if (spi->rx_buf) {
767 stm32_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM);
768 dmaengine_slave_config(spi->dma_rx, &rx_dma_conf);
769
770 /* Enable Rx DMA request */
771 stm32_spi_set_bits(spi, STM32_SPI_CFG1, SPI_CFG1_RXDMAEN);
772
773 rx_dma_desc = dmaengine_prep_slave_sg(
774 spi->dma_rx, xfer->rx_sg.sgl,
775 xfer->rx_sg.nents,
776 rx_dma_conf.direction,
777 DMA_PREP_INTERRUPT);
778 }
779
780 tx_dma_desc = NULL;
781 if (spi->tx_buf) {
782 stm32_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV);
783 dmaengine_slave_config(spi->dma_tx, &tx_dma_conf);
784
785 tx_dma_desc = dmaengine_prep_slave_sg(
786 spi->dma_tx, xfer->tx_sg.sgl,
787 xfer->tx_sg.nents,
788 tx_dma_conf.direction,
789 DMA_PREP_INTERRUPT);
790 }
791
792 if ((spi->tx_buf && !tx_dma_desc) ||
793 (spi->rx_buf && !rx_dma_desc))
794 goto dma_desc_error;
795
796 if (rx_dma_desc) {
797 rx_dma_desc->callback = stm32_spi_dma_cb;
798 rx_dma_desc->callback_param = spi;
799
800 if (dma_submit_error(dmaengine_submit(rx_dma_desc))) {
801 dev_err(spi->dev, "Rx DMA submit failed\n");
802 goto dma_desc_error;
803 }
804 /* Enable Rx DMA channel */
805 dma_async_issue_pending(spi->dma_rx);
806 }
807
808 if (tx_dma_desc) {
809 if (spi->cur_comm == SPI_SIMPLEX_TX) {
810 tx_dma_desc->callback = stm32_spi_dma_cb;
811 tx_dma_desc->callback_param = spi;
812 }
813
814 if (dma_submit_error(dmaengine_submit(tx_dma_desc))) {
815 dev_err(spi->dev, "Tx DMA submit failed\n");
816 goto dma_submit_error;
817 }
818 /* Enable Tx DMA channel */
819 dma_async_issue_pending(spi->dma_tx);
820
821 /* Enable Tx DMA request */
822 stm32_spi_set_bits(spi, STM32_SPI_CFG1, SPI_CFG1_TXDMAEN);
823 }
824
825 /* Enable the interrupts relative to the end of transfer */
826 ier |= SPI_IER_EOTIE | SPI_IER_TXTFIE | SPI_IER_OVRIE | SPI_IER_MODFIE;
827 writel_relaxed(ier, spi->base + STM32_SPI_IER);
828
829 stm32_spi_enable(spi);
830
831 stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_CSTART);
832
833 spin_unlock_irqrestore(&spi->lock, flags);
834
835 return 1;
836
837dma_submit_error:
838 if (spi->rx_buf)
839 dmaengine_terminate_all(spi->dma_rx);
840
841dma_desc_error:
842 stm32_spi_clr_bits(spi, STM32_SPI_CFG1, SPI_CFG1_RXDMAEN);
843
844 spin_unlock_irqrestore(&spi->lock, flags);
845
846 dev_info(spi->dev, "DMA issue: fall back to irq transfer\n");
847
848 return stm32_spi_transfer_one_irq(spi);
849}
850
851/**
852 * stm32_spi_transfer_one_setup - common setup to transfer a single
853 * spi_transfer either using DMA or
854 * interrupts.
855 */
856static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
857 struct spi_device *spi_dev,
858 struct spi_transfer *transfer)
859{
860 unsigned long flags;
861 u32 cfg1_clrb = 0, cfg1_setb = 0, cfg2_clrb = 0, cfg2_setb = 0;
862 u32 mode, nb_words;
863 int ret = 0;
864
865 spin_lock_irqsave(&spi->lock, flags);
866
867 if (spi->cur_bpw != transfer->bits_per_word) {
868 u32 bpw, fthlv;
869
870 spi->cur_bpw = transfer->bits_per_word;
871 bpw = spi->cur_bpw - 1;
872
873 cfg1_clrb |= SPI_CFG1_DSIZE;
874 cfg1_setb |= (bpw << SPI_CFG1_DSIZE_SHIFT) & SPI_CFG1_DSIZE;
875
876 spi->cur_fthlv = stm32_spi_prepare_fthlv(spi);
877 fthlv = spi->cur_fthlv - 1;
878
879 cfg1_clrb |= SPI_CFG1_FTHLV;
880 cfg1_setb |= (fthlv << SPI_CFG1_FTHLV_SHIFT) & SPI_CFG1_FTHLV;
881 }
882
883 if (spi->cur_speed != transfer->speed_hz) {
884 int mbr;
885
886 /* Update spi->cur_speed with real clock speed */
887 mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz);
888 if (mbr < 0) {
889 ret = mbr;
890 goto out;
891 }
892
893 transfer->speed_hz = spi->cur_speed;
894
895 cfg1_clrb |= SPI_CFG1_MBR;
896 cfg1_setb |= ((u32)mbr << SPI_CFG1_MBR_SHIFT) & SPI_CFG1_MBR;
897 }
898
899 if (cfg1_clrb || cfg1_setb)
900 writel_relaxed((readl_relaxed(spi->base + STM32_SPI_CFG1) &
901 ~cfg1_clrb) | cfg1_setb,
902 spi->base + STM32_SPI_CFG1);
903
904 mode = SPI_FULL_DUPLEX;
905 if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */
906 /*
907 * SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL
908 * is forbidden und unvalidated by SPI subsystem so depending
909 * on the valid buffer, we can determine the direction of the
910 * transfer.
911 */
912 mode = SPI_HALF_DUPLEX;
913 if (!transfer->tx_buf)
914 stm32_spi_clr_bits(spi, STM32_SPI_CR1, SPI_CR1_HDDIR);
915 else if (!transfer->rx_buf)
916 stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_HDDIR);
917 } else {
918 if (!transfer->tx_buf)
919 mode = SPI_SIMPLEX_RX;
920 else if (!transfer->rx_buf)
921 mode = SPI_SIMPLEX_TX;
922 }
923 if (spi->cur_comm != mode) {
924 spi->cur_comm = mode;
925
926 cfg2_clrb |= SPI_CFG2_COMM;
927 cfg2_setb |= (mode << SPI_CFG2_COMM_SHIFT) & SPI_CFG2_COMM;
928 }
929
930 cfg2_clrb |= SPI_CFG2_MIDI;
931 if ((transfer->len > 1) && (spi->cur_midi > 0)) {
932 u32 sck_period_ns = DIV_ROUND_UP(SPI_1HZ_NS, spi->cur_speed);
933 u32 midi = min((u32)DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
934 (u32)SPI_CFG2_MIDI >> SPI_CFG2_MIDI_SHIFT);
935
936 dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n",
937 sck_period_ns, midi, midi * sck_period_ns);
938
939 cfg2_setb |= (midi << SPI_CFG2_MIDI_SHIFT) & SPI_CFG2_MIDI;
940 }
941
942 if (cfg2_clrb || cfg2_setb)
943 writel_relaxed((readl_relaxed(spi->base + STM32_SPI_CFG2) &
944 ~cfg2_clrb) | cfg2_setb,
945 spi->base + STM32_SPI_CFG2);
946
947 if (spi->cur_bpw <= 8)
948 nb_words = transfer->len;
949 else if (spi->cur_bpw <= 16)
950 nb_words = DIV_ROUND_UP(transfer->len * 8, 16);
951 else
952 nb_words = DIV_ROUND_UP(transfer->len * 8, 32);
953 nb_words <<= SPI_CR2_TSIZE_SHIFT;
954
955 if (nb_words <= SPI_CR2_TSIZE) {
956 writel_relaxed(nb_words, spi->base + STM32_SPI_CR2);
957 } else {
958 ret = -EMSGSIZE;
959 goto out;
960 }
961
962 spi->cur_xferlen = transfer->len;
963
964 dev_dbg(spi->dev, "transfer communication mode set to %d\n",
965 spi->cur_comm);
966 dev_dbg(spi->dev,
967 "data frame of %d-bit, data packet of %d data frames\n",
968 spi->cur_bpw, spi->cur_fthlv);
969 dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed);
970 dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n",
971 spi->cur_xferlen, nb_words);
972 dev_dbg(spi->dev, "dma %s\n",
973 (spi->cur_usedma) ? "enabled" : "disabled");
974
975out:
976 spin_unlock_irqrestore(&spi->lock, flags);
977
978 return ret;
979}
980
981/**
982 * stm32_spi_transfer_one - transfer a single spi_transfer
983 *
984 * It must return 0 if the transfer is finished or 1 if the transfer is still
985 * in progress.
986 */
987static int stm32_spi_transfer_one(struct spi_master *master,
988 struct spi_device *spi_dev,
989 struct spi_transfer *transfer)
990{
991 struct stm32_spi *spi = spi_master_get_devdata(master);
992 int ret;
993
994 spi->tx_buf = transfer->tx_buf;
995 spi->rx_buf = transfer->rx_buf;
996 spi->tx_len = spi->tx_buf ? transfer->len : 0;
997 spi->rx_len = spi->rx_buf ? transfer->len : 0;
998
999 spi->cur_usedma = (master->can_dma &&
1000 stm32_spi_can_dma(master, spi_dev, transfer));
1001
1002 ret = stm32_spi_transfer_one_setup(spi, spi_dev, transfer);
1003 if (ret) {
1004 dev_err(spi->dev, "SPI transfer setup failed\n");
1005 return ret;
1006 }
1007
1008 if (spi->cur_usedma)
1009 return stm32_spi_transfer_one_dma(spi, transfer);
1010 else
1011 return stm32_spi_transfer_one_irq(spi);
1012}
1013
1014/**
1015 * stm32_spi_unprepare_msg - relax the hardware
1016 *
1017 * Normally, if TSIZE has been configured, we should relax the hardware at the
1018 * reception of the EOT interrupt. But in case of error, EOT will not be
1019 * raised. So the subsystem unprepare_message call allows us to properly
1020 * complete the transfer from an hardware point of view.
1021 */
1022static int stm32_spi_unprepare_msg(struct spi_master *master,
1023 struct spi_message *msg)
1024{
1025 struct stm32_spi *spi = spi_master_get_devdata(master);
1026
1027 stm32_spi_disable(spi);
1028
1029 return 0;
1030}
1031
1032/**
1033 * stm32_spi_config - Configure SPI controller as SPI master
1034 */
1035static int stm32_spi_config(struct stm32_spi *spi)
1036{
1037 unsigned long flags;
1038
1039 spin_lock_irqsave(&spi->lock, flags);
1040
1041 /* Ensure I2SMOD bit is kept cleared */
1042 stm32_spi_clr_bits(spi, STM32_SPI_I2SCFGR, SPI_I2SCFGR_I2SMOD);
1043
1044 /*
1045 * - SS input value high
1046 * - transmitter half duplex direction
1047 * - automatic communication suspend when RX-Fifo is full
1048 */
1049 stm32_spi_set_bits(spi, STM32_SPI_CR1, SPI_CR1_SSI |
1050 SPI_CR1_HDDIR |
1051 SPI_CR1_MASRX);
1052
1053 /*
1054 * - Set the master mode (default Motorola mode)
1055 * - Consider 1 master/n slaves configuration and
1056 * SS input value is determined by the SSI bit
1057 * - keep control of all associated GPIOs
1058 */
1059 stm32_spi_set_bits(spi, STM32_SPI_CFG2, SPI_CFG2_MASTER |
1060 SPI_CFG2_SSM |
1061 SPI_CFG2_AFCNTR);
1062
1063 spin_unlock_irqrestore(&spi->lock, flags);
1064
1065 return 0;
1066}
1067
1068static const struct of_device_id stm32_spi_of_match[] = {
1069 { .compatible = "st,stm32h7-spi", },
1070 {},
1071};
1072MODULE_DEVICE_TABLE(of, stm32_spi_of_match);
1073
1074static int stm32_spi_probe(struct platform_device *pdev)
1075{
1076 struct spi_master *master;
1077 struct stm32_spi *spi;
1078 struct resource *res;
1079 int i, ret;
1080
1081 master = spi_alloc_master(&pdev->dev, sizeof(struct stm32_spi));
1082 if (!master) {
1083 dev_err(&pdev->dev, "spi master allocation failed\n");
1084 return -ENOMEM;
1085 }
1086 platform_set_drvdata(pdev, master);
1087
1088 spi = spi_master_get_devdata(master);
1089 spi->dev = &pdev->dev;
1090 spi->master = master;
1091 spin_lock_init(&spi->lock);
1092
1093 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1094 spi->base = devm_ioremap_resource(&pdev->dev, res);
1095 if (IS_ERR(spi->base)) {
1096 ret = PTR_ERR(spi->base);
1097 goto err_master_put;
1098 }
1099 spi->phys_addr = (dma_addr_t)res->start;
1100
1101 spi->irq = platform_get_irq(pdev, 0);
1102 if (spi->irq <= 0) {
1103 dev_err(&pdev->dev, "no irq: %d\n", spi->irq);
1104 ret = -ENOENT;
1105 goto err_master_put;
1106 }
1107 ret = devm_request_threaded_irq(&pdev->dev, spi->irq, NULL,
1108 stm32_spi_irq, IRQF_ONESHOT,
1109 pdev->name, master);
1110 if (ret) {
1111 dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq,
1112 ret);
1113 goto err_master_put;
1114 }
1115
1116 spi->clk = devm_clk_get(&pdev->dev, 0);
1117 if (IS_ERR(spi->clk)) {
1118 ret = PTR_ERR(spi->clk);
1119 dev_err(&pdev->dev, "clk get failed: %d\n", ret);
1120 goto err_master_put;
1121 }
1122
1123 ret = clk_prepare_enable(spi->clk);
1124 if (ret) {
1125 dev_err(&pdev->dev, "clk enable failed: %d\n", ret);
1126 goto err_master_put;
1127 }
1128 spi->clk_rate = clk_get_rate(spi->clk);
1129 if (!spi->clk_rate) {
1130 dev_err(&pdev->dev, "clk rate = 0\n");
1131 ret = -EINVAL;
1132 goto err_master_put;
1133 }
1134
1135 spi->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
1136 if (!IS_ERR(spi->rst)) {
1137 reset_control_assert(spi->rst);
1138 udelay(2);
1139 reset_control_deassert(spi->rst);
1140 }
1141
1142 spi->fifo_size = stm32_spi_get_fifo_size(spi);
1143
1144 ret = stm32_spi_config(spi);
1145 if (ret) {
1146 dev_err(&pdev->dev, "controller configuration failed: %d\n",
1147 ret);
1148 goto err_clk_disable;
1149 }
1150
1151 master->dev.of_node = pdev->dev.of_node;
1152 master->auto_runtime_pm = true;
1153 master->bus_num = pdev->id;
1154 master->mode_bits = SPI_MODE_3 | SPI_CS_HIGH | SPI_LSB_FIRST |
1155 SPI_3WIRE | SPI_LOOP;
1156 master->bits_per_word_mask = stm32_spi_get_bpw_mask(spi);
1157 master->max_speed_hz = spi->clk_rate / SPI_MBR_DIV_MIN;
1158 master->min_speed_hz = spi->clk_rate / SPI_MBR_DIV_MAX;
1159 master->setup = stm32_spi_setup;
1160 master->prepare_message = stm32_spi_prepare_msg;
1161 master->transfer_one = stm32_spi_transfer_one;
1162 master->unprepare_message = stm32_spi_unprepare_msg;
1163
1164 spi->dma_tx = dma_request_slave_channel(spi->dev, "tx");
1165 if (!spi->dma_tx)
1166 dev_warn(&pdev->dev, "failed to request tx dma channel\n");
1167 else
1168 master->dma_tx = spi->dma_tx;
1169
1170 spi->dma_rx = dma_request_slave_channel(spi->dev, "rx");
1171 if (!spi->dma_rx)
1172 dev_warn(&pdev->dev, "failed to request rx dma channel\n");
1173 else
1174 master->dma_rx = spi->dma_rx;
1175
1176 if (spi->dma_tx || spi->dma_rx)
1177 master->can_dma = stm32_spi_can_dma;
1178
1179 pm_runtime_set_active(&pdev->dev);
1180 pm_runtime_enable(&pdev->dev);
1181
1182 ret = devm_spi_register_master(&pdev->dev, master);
1183 if (ret) {
1184 dev_err(&pdev->dev, "spi master registration failed: %d\n",
1185 ret);
1186 goto err_dma_release;
1187 }
1188
1189 if (!master->cs_gpios) {
1190 dev_err(&pdev->dev, "no CS gpios available\n");
1191 ret = -EINVAL;
1192 goto err_dma_release;
1193 }
1194
1195 for (i = 0; i < master->num_chipselect; i++) {
1196 if (!gpio_is_valid(master->cs_gpios[i])) {
1197 dev_err(&pdev->dev, "%i is not a valid gpio\n",
1198 master->cs_gpios[i]);
1199 ret = -EINVAL;
1200 goto err_dma_release;
1201 }
1202
1203 ret = devm_gpio_request(&pdev->dev, master->cs_gpios[i],
1204 DRIVER_NAME);
1205 if (ret) {
1206 dev_err(&pdev->dev, "can't get CS gpio %i\n",
1207 master->cs_gpios[i]);
1208 goto err_dma_release;
1209 }
1210 }
1211
1212 dev_info(&pdev->dev, "driver initialized\n");
1213
1214 return 0;
1215
1216err_dma_release:
1217 if (spi->dma_tx)
1218 dma_release_channel(spi->dma_tx);
1219 if (spi->dma_rx)
1220 dma_release_channel(spi->dma_rx);
1221
1222 pm_runtime_disable(&pdev->dev);
1223err_clk_disable:
1224 clk_disable_unprepare(spi->clk);
1225err_master_put:
1226 spi_master_put(master);
1227
1228 return ret;
1229}
1230
1231static int stm32_spi_remove(struct platform_device *pdev)
1232{
1233 struct spi_master *master = platform_get_drvdata(pdev);
1234 struct stm32_spi *spi = spi_master_get_devdata(master);
1235
1236 stm32_spi_disable(spi);
1237
1238 if (master->dma_tx)
1239 dma_release_channel(master->dma_tx);
1240 if (master->dma_rx)
1241 dma_release_channel(master->dma_rx);
1242
1243 clk_disable_unprepare(spi->clk);
1244
1245 pm_runtime_disable(&pdev->dev);
1246
1247 return 0;
1248}
1249
1250#ifdef CONFIG_PM
1251static int stm32_spi_runtime_suspend(struct device *dev)
1252{
1253 struct spi_master *master = dev_get_drvdata(dev);
1254 struct stm32_spi *spi = spi_master_get_devdata(master);
1255
1256 clk_disable_unprepare(spi->clk);
1257
1258 return 0;
1259}
1260
1261static int stm32_spi_runtime_resume(struct device *dev)
1262{
1263 struct spi_master *master = dev_get_drvdata(dev);
1264 struct stm32_spi *spi = spi_master_get_devdata(master);
1265
1266 return clk_prepare_enable(spi->clk);
1267}
1268#endif
1269
1270#ifdef CONFIG_PM_SLEEP
1271static int stm32_spi_suspend(struct device *dev)
1272{
1273 struct spi_master *master = dev_get_drvdata(dev);
1274 int ret;
1275
1276 ret = spi_master_suspend(master);
1277 if (ret)
1278 return ret;
1279
1280 return pm_runtime_force_suspend(dev);
1281}
1282
1283static int stm32_spi_resume(struct device *dev)
1284{
1285 struct spi_master *master = dev_get_drvdata(dev);
1286 struct stm32_spi *spi = spi_master_get_devdata(master);
1287 int ret;
1288
1289 ret = pm_runtime_force_resume(dev);
1290 if (ret)
1291 return ret;
1292
1293 ret = spi_master_resume(master);
1294 if (ret)
1295 clk_disable_unprepare(spi->clk);
1296
1297 return ret;
1298}
1299#endif
1300
1301static const struct dev_pm_ops stm32_spi_pm_ops = {
1302 SET_SYSTEM_SLEEP_PM_OPS(stm32_spi_suspend, stm32_spi_resume)
1303 SET_RUNTIME_PM_OPS(stm32_spi_runtime_suspend,
1304 stm32_spi_runtime_resume, NULL)
1305};
1306
1307static struct platform_driver stm32_spi_driver = {
1308 .probe = stm32_spi_probe,
1309 .remove = stm32_spi_remove,
1310 .driver = {
1311 .name = DRIVER_NAME,
1312 .pm = &stm32_spi_pm_ops,
1313 .of_match_table = stm32_spi_of_match,
1314 },
1315};
1316
1317module_platform_driver(stm32_spi_driver);
1318
1319MODULE_ALIAS("platform:" DRIVER_NAME);
1320MODULE_DESCRIPTION("STMicroelectronics STM32 SPI Controller driver");
1321MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
1322MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2//
3// STMicroelectronics STM32 SPI Controller driver
4//
5// Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6// Author(s): Amelie Delaunay <amelie.delaunay@st.com> for STMicroelectronics.
7
8#include <linux/bitfield.h>
9#include <linux/debugfs.h>
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/dmaengine.h>
13#include <linux/interrupt.h>
14#include <linux/iopoll.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/platform_device.h>
18#include <linux/pinctrl/consumer.h>
19#include <linux/pm_runtime.h>
20#include <linux/reset.h>
21#include <linux/spi/spi.h>
22
23#define DRIVER_NAME "spi_stm32"
24
25/* STM32F4/7 SPI registers */
26#define STM32FX_SPI_CR1 0x00
27#define STM32FX_SPI_CR2 0x04
28#define STM32FX_SPI_SR 0x08
29#define STM32FX_SPI_DR 0x0C
30#define STM32FX_SPI_I2SCFGR 0x1C
31
32/* STM32FX_SPI_CR1 bit fields */
33#define STM32FX_SPI_CR1_CPHA BIT(0)
34#define STM32FX_SPI_CR1_CPOL BIT(1)
35#define STM32FX_SPI_CR1_MSTR BIT(2)
36#define STM32FX_SPI_CR1_BR_SHIFT 3
37#define STM32FX_SPI_CR1_BR GENMASK(5, 3)
38#define STM32FX_SPI_CR1_SPE BIT(6)
39#define STM32FX_SPI_CR1_LSBFRST BIT(7)
40#define STM32FX_SPI_CR1_SSI BIT(8)
41#define STM32FX_SPI_CR1_SSM BIT(9)
42#define STM32FX_SPI_CR1_RXONLY BIT(10)
43#define STM32F4_SPI_CR1_DFF BIT(11)
44#define STM32F7_SPI_CR1_CRCL BIT(11)
45#define STM32FX_SPI_CR1_CRCNEXT BIT(12)
46#define STM32FX_SPI_CR1_CRCEN BIT(13)
47#define STM32FX_SPI_CR1_BIDIOE BIT(14)
48#define STM32FX_SPI_CR1_BIDIMODE BIT(15)
49#define STM32FX_SPI_CR1_BR_MIN 0
50#define STM32FX_SPI_CR1_BR_MAX (GENMASK(5, 3) >> 3)
51
52/* STM32FX_SPI_CR2 bit fields */
53#define STM32FX_SPI_CR2_RXDMAEN BIT(0)
54#define STM32FX_SPI_CR2_TXDMAEN BIT(1)
55#define STM32FX_SPI_CR2_SSOE BIT(2)
56#define STM32FX_SPI_CR2_FRF BIT(4)
57#define STM32FX_SPI_CR2_ERRIE BIT(5)
58#define STM32FX_SPI_CR2_RXNEIE BIT(6)
59#define STM32FX_SPI_CR2_TXEIE BIT(7)
60#define STM32F7_SPI_CR2_DS GENMASK(11, 8)
61#define STM32F7_SPI_CR2_FRXTH BIT(12)
62#define STM32F7_SPI_CR2_LDMA_RX BIT(13)
63#define STM32F7_SPI_CR2_LDMA_TX BIT(14)
64
65/* STM32FX_SPI_SR bit fields */
66#define STM32FX_SPI_SR_RXNE BIT(0)
67#define STM32FX_SPI_SR_TXE BIT(1)
68#define STM32FX_SPI_SR_CHSIDE BIT(2)
69#define STM32FX_SPI_SR_UDR BIT(3)
70#define STM32FX_SPI_SR_CRCERR BIT(4)
71#define STM32FX_SPI_SR_MODF BIT(5)
72#define STM32FX_SPI_SR_OVR BIT(6)
73#define STM32FX_SPI_SR_BSY BIT(7)
74#define STM32FX_SPI_SR_FRE BIT(8)
75#define STM32F7_SPI_SR_FRLVL GENMASK(10, 9)
76#define STM32F7_SPI_SR_FTLVL GENMASK(12, 11)
77
78/* STM32FX_SPI_I2SCFGR bit fields */
79#define STM32FX_SPI_I2SCFGR_I2SMOD BIT(11)
80
81/* STM32F4 SPI Baud Rate min/max divisor */
82#define STM32FX_SPI_BR_DIV_MIN (2 << STM32FX_SPI_CR1_BR_MIN)
83#define STM32FX_SPI_BR_DIV_MAX (2 << STM32FX_SPI_CR1_BR_MAX)
84
85/* STM32H7 SPI registers */
86#define STM32H7_SPI_CR1 0x00
87#define STM32H7_SPI_CR2 0x04
88#define STM32H7_SPI_CFG1 0x08
89#define STM32H7_SPI_CFG2 0x0C
90#define STM32H7_SPI_IER 0x10
91#define STM32H7_SPI_SR 0x14
92#define STM32H7_SPI_IFCR 0x18
93#define STM32H7_SPI_TXDR 0x20
94#define STM32H7_SPI_RXDR 0x30
95#define STM32H7_SPI_I2SCFGR 0x50
96
97/* STM32H7_SPI_CR1 bit fields */
98#define STM32H7_SPI_CR1_SPE BIT(0)
99#define STM32H7_SPI_CR1_MASRX BIT(8)
100#define STM32H7_SPI_CR1_CSTART BIT(9)
101#define STM32H7_SPI_CR1_CSUSP BIT(10)
102#define STM32H7_SPI_CR1_HDDIR BIT(11)
103#define STM32H7_SPI_CR1_SSI BIT(12)
104
105/* STM32H7_SPI_CR2 bit fields */
106#define STM32H7_SPI_CR2_TSIZE GENMASK(15, 0)
107#define STM32H7_SPI_TSIZE_MAX GENMASK(15, 0)
108
109/* STM32H7_SPI_CFG1 bit fields */
110#define STM32H7_SPI_CFG1_DSIZE GENMASK(4, 0)
111#define STM32H7_SPI_CFG1_FTHLV GENMASK(8, 5)
112#define STM32H7_SPI_CFG1_RXDMAEN BIT(14)
113#define STM32H7_SPI_CFG1_TXDMAEN BIT(15)
114#define STM32H7_SPI_CFG1_MBR GENMASK(30, 28)
115#define STM32H7_SPI_CFG1_MBR_SHIFT 28
116#define STM32H7_SPI_CFG1_MBR_MIN 0
117#define STM32H7_SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28)
118
119/* STM32H7_SPI_CFG2 bit fields */
120#define STM32H7_SPI_CFG2_MIDI GENMASK(7, 4)
121#define STM32H7_SPI_CFG2_COMM GENMASK(18, 17)
122#define STM32H7_SPI_CFG2_SP GENMASK(21, 19)
123#define STM32H7_SPI_CFG2_MASTER BIT(22)
124#define STM32H7_SPI_CFG2_LSBFRST BIT(23)
125#define STM32H7_SPI_CFG2_CPHA BIT(24)
126#define STM32H7_SPI_CFG2_CPOL BIT(25)
127#define STM32H7_SPI_CFG2_SSM BIT(26)
128#define STM32H7_SPI_CFG2_SSIOP BIT(28)
129#define STM32H7_SPI_CFG2_AFCNTR BIT(31)
130
131/* STM32H7_SPI_IER bit fields */
132#define STM32H7_SPI_IER_RXPIE BIT(0)
133#define STM32H7_SPI_IER_TXPIE BIT(1)
134#define STM32H7_SPI_IER_DXPIE BIT(2)
135#define STM32H7_SPI_IER_EOTIE BIT(3)
136#define STM32H7_SPI_IER_TXTFIE BIT(4)
137#define STM32H7_SPI_IER_OVRIE BIT(6)
138#define STM32H7_SPI_IER_MODFIE BIT(9)
139#define STM32H7_SPI_IER_ALL GENMASK(10, 0)
140
141/* STM32H7_SPI_SR bit fields */
142#define STM32H7_SPI_SR_RXP BIT(0)
143#define STM32H7_SPI_SR_TXP BIT(1)
144#define STM32H7_SPI_SR_EOT BIT(3)
145#define STM32H7_SPI_SR_OVR BIT(6)
146#define STM32H7_SPI_SR_MODF BIT(9)
147#define STM32H7_SPI_SR_SUSP BIT(11)
148#define STM32H7_SPI_SR_RXPLVL GENMASK(14, 13)
149#define STM32H7_SPI_SR_RXWNE BIT(15)
150
151/* STM32H7_SPI_IFCR bit fields */
152#define STM32H7_SPI_IFCR_ALL GENMASK(11, 3)
153
154/* STM32H7_SPI_I2SCFGR bit fields */
155#define STM32H7_SPI_I2SCFGR_I2SMOD BIT(0)
156
157/* STM32MP25 SPI registers bit fields */
158#define STM32MP25_SPI_HWCFGR1 0x3F0
159
160/* STM32MP25_SPI_CR2 bit fields */
161#define STM32MP25_SPI_TSIZE_MAX_LIMITED GENMASK(9, 0)
162
163/* STM32MP25_SPI_HWCFGR1 */
164#define STM32MP25_SPI_HWCFGR1_FULLCFG GENMASK(27, 24)
165#define STM32MP25_SPI_HWCFGR1_FULLCFG_LIMITED 0x0
166#define STM32MP25_SPI_HWCFGR1_FULLCFG_FULL 0x1
167#define STM32MP25_SPI_HWCFGR1_DSCFG GENMASK(19, 16)
168#define STM32MP25_SPI_HWCFGR1_DSCFG_16_B 0x0
169#define STM32MP25_SPI_HWCFGR1_DSCFG_32_B 0x1
170
171/* STM32H7 SPI Master Baud Rate min/max divisor */
172#define STM32H7_SPI_MBR_DIV_MIN (2 << STM32H7_SPI_CFG1_MBR_MIN)
173#define STM32H7_SPI_MBR_DIV_MAX (2 << STM32H7_SPI_CFG1_MBR_MAX)
174
175/* STM32H7 SPI Communication mode */
176#define STM32H7_SPI_FULL_DUPLEX 0
177#define STM32H7_SPI_SIMPLEX_TX 1
178#define STM32H7_SPI_SIMPLEX_RX 2
179#define STM32H7_SPI_HALF_DUPLEX 3
180
181/* SPI Communication type */
182#define SPI_FULL_DUPLEX 0
183#define SPI_SIMPLEX_TX 1
184#define SPI_SIMPLEX_RX 2
185#define SPI_3WIRE_TX 3
186#define SPI_3WIRE_RX 4
187
188#define STM32_SPI_AUTOSUSPEND_DELAY 1 /* 1 ms */
189
190/*
191 * use PIO for small transfers, avoiding DMA setup/teardown overhead for drivers
192 * without fifo buffers.
193 */
194#define SPI_DMA_MIN_BYTES 16
195
196/* STM32 SPI driver helpers */
197#define STM32_SPI_HOST_MODE(stm32_spi) (!(stm32_spi)->device_mode)
198#define STM32_SPI_DEVICE_MODE(stm32_spi) ((stm32_spi)->device_mode)
199
200/**
201 * struct stm32_spi_reg - stm32 SPI register & bitfield desc
202 * @reg: register offset
203 * @mask: bitfield mask
204 * @shift: left shift
205 */
206struct stm32_spi_reg {
207 int reg;
208 int mask;
209 int shift;
210};
211
212/**
213 * struct stm32_spi_regspec - stm32 registers definition, compatible dependent data
214 * @en: enable register and SPI enable bit
215 * @dma_rx_en: SPI DMA RX enable register end SPI DMA RX enable bit
216 * @dma_tx_en: SPI DMA TX enable register end SPI DMA TX enable bit
217 * @cpol: clock polarity register and polarity bit
218 * @cpha: clock phase register and phase bit
219 * @lsb_first: LSB transmitted first register and bit
220 * @cs_high: chips select active value
221 * @br: baud rate register and bitfields
222 * @rx: SPI RX data register
223 * @tx: SPI TX data register
224 * @fullcfg: SPI full or limited feature set register
225 */
226struct stm32_spi_regspec {
227 const struct stm32_spi_reg en;
228 const struct stm32_spi_reg dma_rx_en;
229 const struct stm32_spi_reg dma_tx_en;
230 const struct stm32_spi_reg cpol;
231 const struct stm32_spi_reg cpha;
232 const struct stm32_spi_reg lsb_first;
233 const struct stm32_spi_reg cs_high;
234 const struct stm32_spi_reg br;
235 const struct stm32_spi_reg rx;
236 const struct stm32_spi_reg tx;
237 const struct stm32_spi_reg fullcfg;
238};
239
240struct stm32_spi;
241
242/**
243 * struct stm32_spi_cfg - stm32 compatible configuration data
244 * @regs: registers descriptions
245 * @get_fifo_size: routine to get fifo size
246 * @get_bpw_mask: routine to get bits per word mask
247 * @disable: routine to disable controller
248 * @config: routine to configure controller as SPI Host
249 * @set_bpw: routine to configure registers to for bits per word
250 * @set_mode: routine to configure registers to desired mode
251 * @set_data_idleness: optional routine to configure registers to desired idle
252 * time between frames (if driver has this functionality)
253 * @set_number_of_data: optional routine to configure registers to desired
254 * number of data (if driver has this functionality)
255 * @write_tx: routine to write to transmit register/FIFO
256 * @read_rx: routine to read from receive register/FIFO
257 * @transfer_one_dma_start: routine to start transfer a single spi_transfer
258 * using DMA
259 * @dma_rx_cb: routine to call after DMA RX channel operation is complete
260 * @dma_tx_cb: routine to call after DMA TX channel operation is complete
261 * @transfer_one_irq: routine to configure interrupts for driver
262 * @irq_handler_event: Interrupt handler for SPI controller events
263 * @irq_handler_thread: thread of interrupt handler for SPI controller
264 * @baud_rate_div_min: minimum baud rate divisor
265 * @baud_rate_div_max: maximum baud rate divisor
266 * @has_fifo: boolean to know if fifo is used for driver
267 * @has_device_mode: is this compatible capable to switch on device mode
268 * @flags: compatible specific SPI controller flags used at registration time
269 * @prevent_dma_burst: boolean to indicate to prevent DMA burst
270 */
271struct stm32_spi_cfg {
272 const struct stm32_spi_regspec *regs;
273 int (*get_fifo_size)(struct stm32_spi *spi);
274 int (*get_bpw_mask)(struct stm32_spi *spi);
275 void (*disable)(struct stm32_spi *spi);
276 int (*config)(struct stm32_spi *spi);
277 void (*set_bpw)(struct stm32_spi *spi);
278 int (*set_mode)(struct stm32_spi *spi, unsigned int comm_type);
279 void (*set_data_idleness)(struct stm32_spi *spi, u32 length);
280 int (*set_number_of_data)(struct stm32_spi *spi, u32 length);
281 void (*write_tx)(struct stm32_spi *spi);
282 void (*read_rx)(struct stm32_spi *spi);
283 void (*transfer_one_dma_start)(struct stm32_spi *spi);
284 void (*dma_rx_cb)(void *data);
285 void (*dma_tx_cb)(void *data);
286 int (*transfer_one_irq)(struct stm32_spi *spi);
287 irqreturn_t (*irq_handler_event)(int irq, void *dev_id);
288 irqreturn_t (*irq_handler_thread)(int irq, void *dev_id);
289 unsigned int baud_rate_div_min;
290 unsigned int baud_rate_div_max;
291 bool has_fifo;
292 bool has_device_mode;
293 u16 flags;
294 bool prevent_dma_burst;
295};
296
297/**
298 * struct stm32_spi - private data of the SPI controller
299 * @dev: driver model representation of the controller
300 * @ctrl: controller interface
301 * @cfg: compatible configuration data
302 * @base: virtual memory area
303 * @clk: hw kernel clock feeding the SPI clock generator
304 * @clk_rate: rate of the hw kernel clock feeding the SPI clock generator
305 * @lock: prevent I/O concurrent access
306 * @irq: SPI controller interrupt line
307 * @fifo_size: size of the embedded fifo in bytes
308 * @t_size_max: maximum number of data of one transfer
309 * @feature_set: SPI full or limited feature set
310 * @cur_midi: host inter-data idleness in ns
311 * @cur_speed: speed configured in Hz
312 * @cur_half_period: time of a half bit in us
313 * @cur_bpw: number of bits in a single SPI data frame
314 * @cur_fthlv: fifo threshold level (data frames in a single data packet)
315 * @cur_comm: SPI communication mode
316 * @cur_xferlen: current transfer length in bytes
317 * @cur_usedma: boolean to know if dma is used in current transfer
318 * @tx_buf: data to be written, or NULL
319 * @rx_buf: data to be read, or NULL
320 * @tx_len: number of data to be written in bytes
321 * @rx_len: number of data to be read in bytes
322 * @dma_tx: dma channel for TX transfer
323 * @dma_rx: dma channel for RX transfer
324 * @phys_addr: SPI registers physical base address
325 * @device_mode: the controller is configured as SPI device
326 */
327struct stm32_spi {
328 struct device *dev;
329 struct spi_controller *ctrl;
330 const struct stm32_spi_cfg *cfg;
331 void __iomem *base;
332 struct clk *clk;
333 u32 clk_rate;
334 spinlock_t lock; /* prevent I/O concurrent access */
335 int irq;
336 unsigned int fifo_size;
337 unsigned int t_size_max;
338 unsigned int feature_set;
339#define STM32_SPI_FEATURE_LIMITED STM32MP25_SPI_HWCFGR1_FULLCFG_LIMITED /* 0x0 */
340#define STM32_SPI_FEATURE_FULL STM32MP25_SPI_HWCFGR1_FULLCFG_FULL /* 0x1 */
341
342 unsigned int cur_midi;
343 unsigned int cur_speed;
344 unsigned int cur_half_period;
345 unsigned int cur_bpw;
346 unsigned int cur_fthlv;
347 unsigned int cur_comm;
348 unsigned int cur_xferlen;
349 bool cur_usedma;
350
351 const void *tx_buf;
352 void *rx_buf;
353 int tx_len;
354 int rx_len;
355 struct dma_chan *dma_tx;
356 struct dma_chan *dma_rx;
357 dma_addr_t phys_addr;
358
359 bool device_mode;
360};
361
362static const struct stm32_spi_regspec stm32fx_spi_regspec = {
363 .en = { STM32FX_SPI_CR1, STM32FX_SPI_CR1_SPE },
364
365 .dma_rx_en = { STM32FX_SPI_CR2, STM32FX_SPI_CR2_RXDMAEN },
366 .dma_tx_en = { STM32FX_SPI_CR2, STM32FX_SPI_CR2_TXDMAEN },
367
368 .cpol = { STM32FX_SPI_CR1, STM32FX_SPI_CR1_CPOL },
369 .cpha = { STM32FX_SPI_CR1, STM32FX_SPI_CR1_CPHA },
370 .lsb_first = { STM32FX_SPI_CR1, STM32FX_SPI_CR1_LSBFRST },
371 .cs_high = {},
372 .br = { STM32FX_SPI_CR1, STM32FX_SPI_CR1_BR, STM32FX_SPI_CR1_BR_SHIFT },
373
374 .rx = { STM32FX_SPI_DR },
375 .tx = { STM32FX_SPI_DR },
376};
377
378static const struct stm32_spi_regspec stm32h7_spi_regspec = {
379 /* SPI data transfer is enabled but spi_ker_ck is idle.
380 * CFG1 and CFG2 registers are write protected when SPE is enabled.
381 */
382 .en = { STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE },
383
384 .dma_rx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_RXDMAEN },
385 .dma_tx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN },
386
387 .cpol = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPOL },
388 .cpha = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPHA },
389 .lsb_first = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_LSBFRST },
390 .cs_high = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_SSIOP },
391 .br = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_MBR,
392 STM32H7_SPI_CFG1_MBR_SHIFT },
393
394 .rx = { STM32H7_SPI_RXDR },
395 .tx = { STM32H7_SPI_TXDR },
396};
397
398static const struct stm32_spi_regspec stm32mp25_spi_regspec = {
399 /* SPI data transfer is enabled but spi_ker_ck is idle.
400 * CFG1 and CFG2 registers are write protected when SPE is enabled.
401 */
402 .en = { STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE },
403
404 .dma_rx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_RXDMAEN },
405 .dma_tx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN },
406
407 .cpol = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPOL },
408 .cpha = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPHA },
409 .lsb_first = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_LSBFRST },
410 .cs_high = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_SSIOP },
411 .br = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_MBR,
412 STM32H7_SPI_CFG1_MBR_SHIFT },
413
414 .rx = { STM32H7_SPI_RXDR },
415 .tx = { STM32H7_SPI_TXDR },
416
417 .fullcfg = { STM32MP25_SPI_HWCFGR1, STM32MP25_SPI_HWCFGR1_FULLCFG },
418};
419
420static inline void stm32_spi_set_bits(struct stm32_spi *spi,
421 u32 offset, u32 bits)
422{
423 writel_relaxed(readl_relaxed(spi->base + offset) | bits,
424 spi->base + offset);
425}
426
427static inline void stm32_spi_clr_bits(struct stm32_spi *spi,
428 u32 offset, u32 bits)
429{
430 writel_relaxed(readl_relaxed(spi->base + offset) & ~bits,
431 spi->base + offset);
432}
433
434/**
435 * stm32h7_spi_get_fifo_size - Return fifo size
436 * @spi: pointer to the spi controller data structure
437 */
438static int stm32h7_spi_get_fifo_size(struct stm32_spi *spi)
439{
440 unsigned long flags;
441 u32 count = 0;
442
443 spin_lock_irqsave(&spi->lock, flags);
444
445 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
446
447 while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP)
448 writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR);
449
450 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
451
452 spin_unlock_irqrestore(&spi->lock, flags);
453
454 dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count);
455
456 return count;
457}
458
459/**
460 * stm32f4_spi_get_bpw_mask - Return bits per word mask
461 * @spi: pointer to the spi controller data structure
462 */
463static int stm32f4_spi_get_bpw_mask(struct stm32_spi *spi)
464{
465 dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n");
466 return SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
467}
468
469/**
470 * stm32f7_spi_get_bpw_mask - Return bits per word mask
471 * @spi: pointer to the spi controller data structure
472 */
473static int stm32f7_spi_get_bpw_mask(struct stm32_spi *spi)
474{
475 dev_dbg(spi->dev, "16-bit maximum data frame\n");
476 return SPI_BPW_RANGE_MASK(4, 16);
477}
478
479/**
480 * stm32h7_spi_get_bpw_mask - Return bits per word mask
481 * @spi: pointer to the spi controller data structure
482 */
483static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi)
484{
485 unsigned long flags;
486 u32 cfg1, max_bpw;
487
488 spin_lock_irqsave(&spi->lock, flags);
489
490 /*
491 * The most significant bit at DSIZE bit field is reserved when the
492 * maximum data size of periperal instances is limited to 16-bit
493 */
494 stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE);
495
496 cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1);
497 max_bpw = FIELD_GET(STM32H7_SPI_CFG1_DSIZE, cfg1) + 1;
498
499 spin_unlock_irqrestore(&spi->lock, flags);
500
501 dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw);
502
503 return SPI_BPW_RANGE_MASK(4, max_bpw);
504}
505
506/**
507 * stm32mp25_spi_get_bpw_mask - Return bits per word mask
508 * @spi: pointer to the spi controller data structure
509 */
510static int stm32mp25_spi_get_bpw_mask(struct stm32_spi *spi)
511{
512 u32 dscfg, max_bpw;
513
514 if (spi->feature_set == STM32_SPI_FEATURE_LIMITED) {
515 dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n");
516 return SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
517 }
518
519 dscfg = FIELD_GET(STM32MP25_SPI_HWCFGR1_DSCFG,
520 readl_relaxed(spi->base + STM32MP25_SPI_HWCFGR1));
521 max_bpw = 16;
522 if (dscfg == STM32MP25_SPI_HWCFGR1_DSCFG_32_B)
523 max_bpw = 32;
524 dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw);
525 return SPI_BPW_RANGE_MASK(4, max_bpw);
526}
527
528/**
529 * stm32_spi_prepare_mbr - Determine baud rate divisor value
530 * @spi: pointer to the spi controller data structure
531 * @speed_hz: requested speed
532 * @min_div: minimum baud rate divisor
533 * @max_div: maximum baud rate divisor
534 *
535 * Return baud rate divisor value in case of success or -EINVAL
536 */
537static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz,
538 u32 min_div, u32 max_div)
539{
540 u32 div, mbrdiv;
541
542 /* Ensure spi->clk_rate is even */
543 div = DIV_ROUND_CLOSEST(spi->clk_rate & ~0x1, speed_hz);
544
545 /*
546 * SPI framework set xfer->speed_hz to ctrl->max_speed_hz if
547 * xfer->speed_hz is greater than ctrl->max_speed_hz, and it returns
548 * an error when xfer->speed_hz is lower than ctrl->min_speed_hz, so
549 * no need to check it there.
550 * However, we need to ensure the following calculations.
551 */
552 if ((div < min_div) || (div > max_div))
553 return -EINVAL;
554
555 /* Determine the first power of 2 greater than or equal to div */
556 if (div & (div - 1))
557 mbrdiv = fls(div);
558 else
559 mbrdiv = fls(div) - 1;
560
561 spi->cur_speed = spi->clk_rate / (1 << mbrdiv);
562
563 spi->cur_half_period = DIV_ROUND_CLOSEST(USEC_PER_SEC, 2 * spi->cur_speed);
564
565 return mbrdiv - 1;
566}
567
568/**
569 * stm32h7_spi_prepare_fthlv - Determine FIFO threshold level
570 * @spi: pointer to the spi controller data structure
571 * @xfer_len: length of the message to be transferred
572 */
573static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len)
574{
575 u32 packet, bpw;
576
577 /* data packet should not exceed 1/2 of fifo space */
578 packet = clamp(xfer_len, 1U, spi->fifo_size / 2);
579
580 /* align packet size with data registers access */
581 bpw = DIV_ROUND_UP(spi->cur_bpw, 8);
582 return DIV_ROUND_UP(packet, bpw);
583}
584
585/**
586 * stm32f4_spi_write_tx - Write bytes to Transmit Data Register
587 * @spi: pointer to the spi controller data structure
588 *
589 * Read from tx_buf depends on remaining bytes to avoid to read beyond
590 * tx_buf end.
591 */
592static void stm32f4_spi_write_tx(struct stm32_spi *spi)
593{
594 if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32FX_SPI_SR) &
595 STM32FX_SPI_SR_TXE)) {
596 u32 offs = spi->cur_xferlen - spi->tx_len;
597
598 if (spi->cur_bpw == 16) {
599 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
600
601 writew_relaxed(*tx_buf16, spi->base + STM32FX_SPI_DR);
602 spi->tx_len -= sizeof(u16);
603 } else {
604 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
605
606 writeb_relaxed(*tx_buf8, spi->base + STM32FX_SPI_DR);
607 spi->tx_len -= sizeof(u8);
608 }
609 }
610
611 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
612}
613
614/**
615 * stm32f7_spi_write_tx - Write bytes to Transmit Data Register
616 * @spi: pointer to the spi controller data structure
617 *
618 * Read from tx_buf depends on remaining bytes to avoid to read beyond
619 * tx_buf end.
620 */
621static void stm32f7_spi_write_tx(struct stm32_spi *spi)
622{
623 if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32FX_SPI_SR) &
624 STM32FX_SPI_SR_TXE)) {
625 u32 offs = spi->cur_xferlen - spi->tx_len;
626
627 if (spi->tx_len >= sizeof(u16)) {
628 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
629
630 writew_relaxed(*tx_buf16, spi->base + STM32FX_SPI_DR);
631 spi->tx_len -= sizeof(u16);
632 } else {
633 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
634
635 writeb_relaxed(*tx_buf8, spi->base + STM32FX_SPI_DR);
636 spi->tx_len -= sizeof(u8);
637 }
638 }
639
640 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
641}
642
643/**
644 * stm32h7_spi_write_txfifo - Write bytes in Transmit Data Register
645 * @spi: pointer to the spi controller data structure
646 *
647 * Read from tx_buf depends on remaining bytes to avoid to read beyond
648 * tx_buf end.
649 */
650static void stm32h7_spi_write_txfifo(struct stm32_spi *spi)
651{
652 while ((spi->tx_len > 0) &&
653 (readl_relaxed(spi->base + STM32H7_SPI_SR) &
654 STM32H7_SPI_SR_TXP)) {
655 u32 offs = spi->cur_xferlen - spi->tx_len;
656
657 if (spi->tx_len >= sizeof(u32)) {
658 const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs);
659
660 writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR);
661 spi->tx_len -= sizeof(u32);
662 } else if (spi->tx_len >= sizeof(u16)) {
663 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
664
665 writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR);
666 spi->tx_len -= sizeof(u16);
667 } else {
668 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
669
670 writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR);
671 spi->tx_len -= sizeof(u8);
672 }
673 }
674
675 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
676}
677
678/**
679 * stm32f4_spi_read_rx - Read bytes from Receive Data Register
680 * @spi: pointer to the spi controller data structure
681 *
682 * Write in rx_buf depends on remaining bytes to avoid to write beyond
683 * rx_buf end.
684 */
685static void stm32f4_spi_read_rx(struct stm32_spi *spi)
686{
687 if ((spi->rx_len > 0) && (readl_relaxed(spi->base + STM32FX_SPI_SR) &
688 STM32FX_SPI_SR_RXNE)) {
689 u32 offs = spi->cur_xferlen - spi->rx_len;
690
691 if (spi->cur_bpw == 16) {
692 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
693
694 *rx_buf16 = readw_relaxed(spi->base + STM32FX_SPI_DR);
695 spi->rx_len -= sizeof(u16);
696 } else {
697 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
698
699 *rx_buf8 = readb_relaxed(spi->base + STM32FX_SPI_DR);
700 spi->rx_len -= sizeof(u8);
701 }
702 }
703
704 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len);
705}
706
707/**
708 * stm32f7_spi_read_rx - Read bytes from Receive Data Register
709 * @spi: pointer to the spi controller data structure
710 *
711 * Write in rx_buf depends on remaining bytes to avoid to write beyond
712 * rx_buf end.
713 */
714static void stm32f7_spi_read_rx(struct stm32_spi *spi)
715{
716 u32 sr = readl_relaxed(spi->base + STM32FX_SPI_SR);
717 u32 frlvl = FIELD_GET(STM32F7_SPI_SR_FRLVL, sr);
718
719 while ((spi->rx_len > 0) && (frlvl > 0)) {
720 u32 offs = spi->cur_xferlen - spi->rx_len;
721
722 if ((spi->rx_len >= sizeof(u16)) && (frlvl >= 2)) {
723 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
724
725 *rx_buf16 = readw_relaxed(spi->base + STM32FX_SPI_DR);
726 spi->rx_len -= sizeof(u16);
727 } else {
728 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
729
730 *rx_buf8 = readb_relaxed(spi->base + STM32FX_SPI_DR);
731 spi->rx_len -= sizeof(u8);
732 }
733
734 sr = readl_relaxed(spi->base + STM32FX_SPI_SR);
735 frlvl = FIELD_GET(STM32F7_SPI_SR_FRLVL, sr);
736 }
737
738 if (spi->rx_len >= sizeof(u16))
739 stm32_spi_clr_bits(spi, STM32FX_SPI_CR2, STM32F7_SPI_CR2_FRXTH);
740 else
741 stm32_spi_set_bits(spi, STM32FX_SPI_CR2, STM32F7_SPI_CR2_FRXTH);
742
743 dev_dbg(spi->dev, "%s: %d bytes left (sr=%08x)\n",
744 __func__, spi->rx_len, sr);
745}
746
747/**
748 * stm32h7_spi_read_rxfifo - Read bytes in Receive Data Register
749 * @spi: pointer to the spi controller data structure
750 *
751 * Write in rx_buf depends on remaining bytes to avoid to write beyond
752 * rx_buf end.
753 */
754static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi)
755{
756 u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
757 u32 rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr);
758
759 while ((spi->rx_len > 0) &&
760 ((sr & STM32H7_SPI_SR_RXP) ||
761 ((sr & STM32H7_SPI_SR_EOT) &&
762 ((sr & STM32H7_SPI_SR_RXWNE) || (rxplvl > 0))))) {
763 u32 offs = spi->cur_xferlen - spi->rx_len;
764
765 if ((spi->rx_len >= sizeof(u32)) ||
766 (sr & STM32H7_SPI_SR_RXWNE)) {
767 u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs);
768
769 *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR);
770 spi->rx_len -= sizeof(u32);
771 } else if ((spi->rx_len >= sizeof(u16)) ||
772 (!(sr & STM32H7_SPI_SR_RXWNE) &&
773 (rxplvl >= 2 || spi->cur_bpw > 8))) {
774 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
775
776 *rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR);
777 spi->rx_len -= sizeof(u16);
778 } else {
779 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
780
781 *rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR);
782 spi->rx_len -= sizeof(u8);
783 }
784
785 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
786 rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr);
787 }
788
789 dev_dbg(spi->dev, "%s: %d bytes left (sr=%08x)\n",
790 __func__, spi->rx_len, sr);
791}
792
793/**
794 * stm32_spi_enable - Enable SPI controller
795 * @spi: pointer to the spi controller data structure
796 */
797static void stm32_spi_enable(struct stm32_spi *spi)
798{
799 dev_dbg(spi->dev, "enable controller\n");
800
801 stm32_spi_set_bits(spi, spi->cfg->regs->en.reg,
802 spi->cfg->regs->en.mask);
803}
804
805/**
806 * stm32fx_spi_disable - Disable SPI controller
807 * @spi: pointer to the spi controller data structure
808 */
809static void stm32fx_spi_disable(struct stm32_spi *spi)
810{
811 unsigned long flags;
812 u32 sr;
813
814 dev_dbg(spi->dev, "disable controller\n");
815
816 spin_lock_irqsave(&spi->lock, flags);
817
818 if (!(readl_relaxed(spi->base + STM32FX_SPI_CR1) &
819 STM32FX_SPI_CR1_SPE)) {
820 spin_unlock_irqrestore(&spi->lock, flags);
821 return;
822 }
823
824 /* Disable interrupts */
825 stm32_spi_clr_bits(spi, STM32FX_SPI_CR2, STM32FX_SPI_CR2_TXEIE |
826 STM32FX_SPI_CR2_RXNEIE |
827 STM32FX_SPI_CR2_ERRIE);
828
829 /* Wait until BSY = 0 */
830 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32FX_SPI_SR,
831 sr, !(sr & STM32FX_SPI_SR_BSY),
832 10, 100000) < 0) {
833 dev_warn(spi->dev, "disabling condition timeout\n");
834 }
835
836 if (spi->cur_usedma && spi->dma_tx)
837 dmaengine_terminate_async(spi->dma_tx);
838 if (spi->cur_usedma && spi->dma_rx)
839 dmaengine_terminate_async(spi->dma_rx);
840
841 stm32_spi_clr_bits(spi, STM32FX_SPI_CR1, STM32FX_SPI_CR1_SPE);
842
843 stm32_spi_clr_bits(spi, STM32FX_SPI_CR2, STM32FX_SPI_CR2_TXDMAEN |
844 STM32FX_SPI_CR2_RXDMAEN);
845
846 /* Sequence to clear OVR flag */
847 readl_relaxed(spi->base + STM32FX_SPI_DR);
848 readl_relaxed(spi->base + STM32FX_SPI_SR);
849
850 spin_unlock_irqrestore(&spi->lock, flags);
851}
852
853/**
854 * stm32h7_spi_disable - Disable SPI controller
855 * @spi: pointer to the spi controller data structure
856 *
857 * RX-Fifo is flushed when SPI controller is disabled.
858 */
859static void stm32h7_spi_disable(struct stm32_spi *spi)
860{
861 unsigned long flags;
862 u32 cr1;
863
864 dev_dbg(spi->dev, "disable controller\n");
865
866 spin_lock_irqsave(&spi->lock, flags);
867
868 cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1);
869
870 if (!(cr1 & STM32H7_SPI_CR1_SPE)) {
871 spin_unlock_irqrestore(&spi->lock, flags);
872 return;
873 }
874
875 /* Add a delay to make sure that transmission is ended. */
876 if (spi->cur_half_period)
877 udelay(spi->cur_half_period);
878
879 if (spi->cur_usedma && spi->dma_tx)
880 dmaengine_terminate_async(spi->dma_tx);
881 if (spi->cur_usedma && spi->dma_rx)
882 dmaengine_terminate_async(spi->dma_rx);
883
884 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
885
886 stm32_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN |
887 STM32H7_SPI_CFG1_RXDMAEN);
888
889 /* Disable interrupts and clear status flags */
890 writel_relaxed(0, spi->base + STM32H7_SPI_IER);
891 writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR);
892
893 spin_unlock_irqrestore(&spi->lock, flags);
894}
895
896/**
897 * stm32_spi_can_dma - Determine if the transfer is eligible for DMA use
898 * @ctrl: controller interface
899 * @spi_dev: pointer to the spi device
900 * @transfer: pointer to spi transfer
901 *
902 * If driver has fifo and the current transfer size is greater than fifo size,
903 * use DMA. Otherwise use DMA for transfer longer than defined DMA min bytes.
904 */
905static bool stm32_spi_can_dma(struct spi_controller *ctrl,
906 struct spi_device *spi_dev,
907 struct spi_transfer *transfer)
908{
909 unsigned int dma_size;
910 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
911
912 if (spi->cfg->has_fifo)
913 dma_size = spi->fifo_size;
914 else
915 dma_size = SPI_DMA_MIN_BYTES;
916
917 dev_dbg(spi->dev, "%s: %s\n", __func__,
918 (transfer->len > dma_size) ? "true" : "false");
919
920 return (transfer->len > dma_size);
921}
922
923/**
924 * stm32fx_spi_irq_event - Interrupt handler for SPI controller events
925 * @irq: interrupt line
926 * @dev_id: SPI controller ctrl interface
927 */
928static irqreturn_t stm32fx_spi_irq_event(int irq, void *dev_id)
929{
930 struct spi_controller *ctrl = dev_id;
931 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
932 u32 sr, mask = 0;
933 bool end = false;
934
935 spin_lock(&spi->lock);
936
937 sr = readl_relaxed(spi->base + STM32FX_SPI_SR);
938 /*
939 * BSY flag is not handled in interrupt but it is normal behavior when
940 * this flag is set.
941 */
942 sr &= ~STM32FX_SPI_SR_BSY;
943
944 if (!spi->cur_usedma && (spi->cur_comm == SPI_SIMPLEX_TX ||
945 spi->cur_comm == SPI_3WIRE_TX)) {
946 /* OVR flag shouldn't be handled for TX only mode */
947 sr &= ~(STM32FX_SPI_SR_OVR | STM32FX_SPI_SR_RXNE);
948 mask |= STM32FX_SPI_SR_TXE;
949 }
950
951 if (!spi->cur_usedma && (spi->cur_comm == SPI_FULL_DUPLEX ||
952 spi->cur_comm == SPI_SIMPLEX_RX ||
953 spi->cur_comm == SPI_3WIRE_RX)) {
954 /* TXE flag is set and is handled when RXNE flag occurs */
955 sr &= ~STM32FX_SPI_SR_TXE;
956 mask |= STM32FX_SPI_SR_RXNE | STM32FX_SPI_SR_OVR;
957 }
958
959 if (!(sr & mask)) {
960 dev_dbg(spi->dev, "spurious IT (sr=0x%08x)\n", sr);
961 spin_unlock(&spi->lock);
962 return IRQ_NONE;
963 }
964
965 if (sr & STM32FX_SPI_SR_OVR) {
966 dev_warn(spi->dev, "Overrun: received value discarded\n");
967
968 /* Sequence to clear OVR flag */
969 readl_relaxed(spi->base + STM32FX_SPI_DR);
970 readl_relaxed(spi->base + STM32FX_SPI_SR);
971
972 /*
973 * If overrun is detected, it means that something went wrong,
974 * so stop the current transfer. Transfer can wait for next
975 * RXNE but DR is already read and end never happens.
976 */
977 end = true;
978 goto end_irq;
979 }
980
981 if (sr & STM32FX_SPI_SR_TXE) {
982 if (spi->tx_buf)
983 spi->cfg->write_tx(spi);
984 if (spi->tx_len == 0)
985 end = true;
986 }
987
988 if (sr & STM32FX_SPI_SR_RXNE) {
989 spi->cfg->read_rx(spi);
990 if (spi->rx_len == 0)
991 end = true;
992 else if (spi->tx_buf)/* Load data for discontinuous mode */
993 spi->cfg->write_tx(spi);
994 }
995
996end_irq:
997 if (end) {
998 /* Immediately disable interrupts to do not generate new one */
999 stm32_spi_clr_bits(spi, STM32FX_SPI_CR2,
1000 STM32FX_SPI_CR2_TXEIE |
1001 STM32FX_SPI_CR2_RXNEIE |
1002 STM32FX_SPI_CR2_ERRIE);
1003 spin_unlock(&spi->lock);
1004 return IRQ_WAKE_THREAD;
1005 }
1006
1007 spin_unlock(&spi->lock);
1008 return IRQ_HANDLED;
1009}
1010
1011/**
1012 * stm32fx_spi_irq_thread - Thread of interrupt handler for SPI controller
1013 * @irq: interrupt line
1014 * @dev_id: SPI controller interface
1015 */
1016static irqreturn_t stm32fx_spi_irq_thread(int irq, void *dev_id)
1017{
1018 struct spi_controller *ctrl = dev_id;
1019 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
1020
1021 spi_finalize_current_transfer(ctrl);
1022 stm32fx_spi_disable(spi);
1023
1024 return IRQ_HANDLED;
1025}
1026
1027/**
1028 * stm32h7_spi_irq_thread - Thread of interrupt handler for SPI controller
1029 * @irq: interrupt line
1030 * @dev_id: SPI controller interface
1031 */
1032static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id)
1033{
1034 struct spi_controller *ctrl = dev_id;
1035 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
1036 u32 sr, ier, mask;
1037 unsigned long flags;
1038 bool end = false;
1039
1040 spin_lock_irqsave(&spi->lock, flags);
1041
1042 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
1043 ier = readl_relaxed(spi->base + STM32H7_SPI_IER);
1044
1045 mask = ier;
1046 /*
1047 * EOTIE enables irq from EOT, SUSP and TXC events. We need to set
1048 * SUSP to acknowledge it later. TXC is automatically cleared
1049 */
1050
1051 mask |= STM32H7_SPI_SR_SUSP;
1052 /*
1053 * DXPIE is set in Full-Duplex, one IT will be raised if TXP and RXP
1054 * are set. So in case of Full-Duplex, need to poll TXP and RXP event.
1055 */
1056 if ((spi->cur_comm == SPI_FULL_DUPLEX) && !spi->cur_usedma)
1057 mask |= STM32H7_SPI_SR_TXP | STM32H7_SPI_SR_RXP;
1058
1059 if (!(sr & mask)) {
1060 dev_vdbg(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
1061 sr, ier);
1062 spin_unlock_irqrestore(&spi->lock, flags);
1063 return IRQ_NONE;
1064 }
1065
1066 if (sr & STM32H7_SPI_SR_SUSP) {
1067 static DEFINE_RATELIMIT_STATE(rs,
1068 DEFAULT_RATELIMIT_INTERVAL * 10,
1069 1);
1070 ratelimit_set_flags(&rs, RATELIMIT_MSG_ON_RELEASE);
1071 if (__ratelimit(&rs))
1072 dev_dbg_ratelimited(spi->dev, "Communication suspended\n");
1073 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
1074 stm32h7_spi_read_rxfifo(spi);
1075 /*
1076 * If communication is suspended while using DMA, it means
1077 * that something went wrong, so stop the current transfer
1078 */
1079 if (spi->cur_usedma)
1080 end = true;
1081 }
1082
1083 if (sr & STM32H7_SPI_SR_MODF) {
1084 dev_warn(spi->dev, "Mode fault: transfer aborted\n");
1085 end = true;
1086 }
1087
1088 if (sr & STM32H7_SPI_SR_OVR) {
1089 dev_err(spi->dev, "Overrun: RX data lost\n");
1090 end = true;
1091 }
1092
1093 if (sr & STM32H7_SPI_SR_EOT) {
1094 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
1095 stm32h7_spi_read_rxfifo(spi);
1096 if (!spi->cur_usedma ||
1097 (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX))
1098 end = true;
1099 }
1100
1101 if (sr & STM32H7_SPI_SR_TXP)
1102 if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0)))
1103 stm32h7_spi_write_txfifo(spi);
1104
1105 if (sr & STM32H7_SPI_SR_RXP)
1106 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
1107 stm32h7_spi_read_rxfifo(spi);
1108
1109 writel_relaxed(sr & mask, spi->base + STM32H7_SPI_IFCR);
1110
1111 spin_unlock_irqrestore(&spi->lock, flags);
1112
1113 if (end) {
1114 stm32h7_spi_disable(spi);
1115 spi_finalize_current_transfer(ctrl);
1116 }
1117
1118 return IRQ_HANDLED;
1119}
1120
1121static int stm32_spi_optimize_message(struct spi_message *msg)
1122{
1123 struct spi_controller *ctrl = msg->spi->controller;
1124 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
1125
1126 /* On STM32H7, messages should not exceed a maximum size set
1127 * later via the set_number_of_data function. In order to
1128 * ensure that, split large messages into several messages
1129 */
1130 if (spi->cfg->set_number_of_data)
1131 return spi_split_transfers_maxwords(ctrl, msg, spi->t_size_max);
1132
1133 return 0;
1134}
1135
1136/**
1137 * stm32_spi_prepare_msg - set up the controller to transfer a single message
1138 * @ctrl: controller interface
1139 * @msg: pointer to spi message
1140 */
1141static int stm32_spi_prepare_msg(struct spi_controller *ctrl,
1142 struct spi_message *msg)
1143{
1144 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
1145 struct spi_device *spi_dev = msg->spi;
1146 struct device_node *np = spi_dev->dev.of_node;
1147 unsigned long flags;
1148 u32 clrb = 0, setb = 0;
1149
1150 /* SPI target device may need time between data frames */
1151 spi->cur_midi = 0;
1152 if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi))
1153 dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi);
1154
1155 if (spi_dev->mode & SPI_CPOL)
1156 setb |= spi->cfg->regs->cpol.mask;
1157 else
1158 clrb |= spi->cfg->regs->cpol.mask;
1159
1160 if (spi_dev->mode & SPI_CPHA)
1161 setb |= spi->cfg->regs->cpha.mask;
1162 else
1163 clrb |= spi->cfg->regs->cpha.mask;
1164
1165 if (spi_dev->mode & SPI_LSB_FIRST)
1166 setb |= spi->cfg->regs->lsb_first.mask;
1167 else
1168 clrb |= spi->cfg->regs->lsb_first.mask;
1169
1170 if (STM32_SPI_DEVICE_MODE(spi) && spi_dev->mode & SPI_CS_HIGH)
1171 setb |= spi->cfg->regs->cs_high.mask;
1172 else
1173 clrb |= spi->cfg->regs->cs_high.mask;
1174
1175 dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n",
1176 !!(spi_dev->mode & SPI_CPOL),
1177 !!(spi_dev->mode & SPI_CPHA),
1178 !!(spi_dev->mode & SPI_LSB_FIRST),
1179 !!(spi_dev->mode & SPI_CS_HIGH));
1180
1181 spin_lock_irqsave(&spi->lock, flags);
1182
1183 /* CPOL, CPHA and LSB FIRST bits have common register */
1184 if (clrb || setb)
1185 writel_relaxed(
1186 (readl_relaxed(spi->base + spi->cfg->regs->cpol.reg) &
1187 ~clrb) | setb,
1188 spi->base + spi->cfg->regs->cpol.reg);
1189
1190 spin_unlock_irqrestore(&spi->lock, flags);
1191
1192 return 0;
1193}
1194
1195/**
1196 * stm32fx_spi_dma_tx_cb - dma callback
1197 * @data: pointer to the spi controller data structure
1198 *
1199 * DMA callback is called when the transfer is complete for DMA TX channel.
1200 */
1201static void stm32fx_spi_dma_tx_cb(void *data)
1202{
1203 struct stm32_spi *spi = data;
1204
1205 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
1206 spi_finalize_current_transfer(spi->ctrl);
1207 stm32fx_spi_disable(spi);
1208 }
1209}
1210
1211/**
1212 * stm32_spi_dma_rx_cb - dma callback
1213 * @data: pointer to the spi controller data structure
1214 *
1215 * DMA callback is called when the transfer is complete for DMA RX channel.
1216 */
1217static void stm32_spi_dma_rx_cb(void *data)
1218{
1219 struct stm32_spi *spi = data;
1220
1221 spi_finalize_current_transfer(spi->ctrl);
1222 spi->cfg->disable(spi);
1223}
1224
1225/**
1226 * stm32_spi_dma_config - configure dma slave channel depending on current
1227 * transfer bits_per_word.
1228 * @spi: pointer to the spi controller data structure
1229 * @dma_chan: pointer to the DMA channel
1230 * @dma_conf: pointer to the dma_slave_config structure
1231 * @dir: direction of the dma transfer
1232 */
1233static void stm32_spi_dma_config(struct stm32_spi *spi,
1234 struct dma_chan *dma_chan,
1235 struct dma_slave_config *dma_conf,
1236 enum dma_transfer_direction dir)
1237{
1238 enum dma_slave_buswidth buswidth;
1239 struct dma_slave_caps caps;
1240 u32 maxburst = 1;
1241 int ret;
1242
1243 if (spi->cur_bpw <= 8)
1244 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
1245 else if (spi->cur_bpw <= 16)
1246 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
1247 else
1248 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
1249
1250 /* Valid for DMA Half or Full Fifo threshold */
1251 if (!spi->cfg->prevent_dma_burst && spi->cfg->has_fifo && spi->cur_fthlv != 2)
1252 maxburst = spi->cur_fthlv;
1253
1254 /* Get the DMA channel caps, and adjust maxburst if possible */
1255 ret = dma_get_slave_caps(dma_chan, &caps);
1256 if (!ret)
1257 maxburst = min(maxburst, caps.max_burst);
1258
1259 memset(dma_conf, 0, sizeof(struct dma_slave_config));
1260 dma_conf->direction = dir;
1261 if (dma_conf->direction == DMA_DEV_TO_MEM) { /* RX */
1262 dma_conf->src_addr = spi->phys_addr + spi->cfg->regs->rx.reg;
1263 dma_conf->src_addr_width = buswidth;
1264 dma_conf->src_maxburst = maxburst;
1265
1266 dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n",
1267 buswidth, maxburst);
1268 } else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */
1269 dma_conf->dst_addr = spi->phys_addr + spi->cfg->regs->tx.reg;
1270 dma_conf->dst_addr_width = buswidth;
1271 dma_conf->dst_maxburst = maxburst;
1272
1273 dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n",
1274 buswidth, maxburst);
1275 }
1276}
1277
1278/**
1279 * stm32fx_spi_transfer_one_irq - transfer a single spi_transfer using
1280 * interrupts
1281 * @spi: pointer to the spi controller data structure
1282 *
1283 * It must returns 0 if the transfer is finished or 1 if the transfer is still
1284 * in progress.
1285 */
1286static int stm32fx_spi_transfer_one_irq(struct stm32_spi *spi)
1287{
1288 unsigned long flags;
1289 u32 cr2 = 0;
1290
1291 /* Enable the interrupts relative to the current communication mode */
1292 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
1293 cr2 |= STM32FX_SPI_CR2_TXEIE;
1294 } else if (spi->cur_comm == SPI_FULL_DUPLEX ||
1295 spi->cur_comm == SPI_SIMPLEX_RX ||
1296 spi->cur_comm == SPI_3WIRE_RX) {
1297 /* In transmit-only mode, the OVR flag is set in the SR register
1298 * since the received data are never read. Therefore set OVR
1299 * interrupt only when rx buffer is available.
1300 */
1301 cr2 |= STM32FX_SPI_CR2_RXNEIE | STM32FX_SPI_CR2_ERRIE;
1302 } else {
1303 return -EINVAL;
1304 }
1305
1306 spin_lock_irqsave(&spi->lock, flags);
1307
1308 stm32_spi_set_bits(spi, STM32FX_SPI_CR2, cr2);
1309
1310 stm32_spi_enable(spi);
1311
1312 /* starting data transfer when buffer is loaded */
1313 if (spi->tx_buf)
1314 spi->cfg->write_tx(spi);
1315
1316 spin_unlock_irqrestore(&spi->lock, flags);
1317
1318 return 1;
1319}
1320
1321/**
1322 * stm32h7_spi_transfer_one_irq - transfer a single spi_transfer using
1323 * interrupts
1324 * @spi: pointer to the spi controller data structure
1325 *
1326 * It must returns 0 if the transfer is finished or 1 if the transfer is still
1327 * in progress.
1328 */
1329static int stm32h7_spi_transfer_one_irq(struct stm32_spi *spi)
1330{
1331 unsigned long flags;
1332 u32 ier = 0;
1333
1334 /* Enable the interrupts relative to the current communication mode */
1335 if (spi->tx_buf && spi->rx_buf) /* Full Duplex */
1336 ier |= STM32H7_SPI_IER_DXPIE;
1337 else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */
1338 ier |= STM32H7_SPI_IER_TXPIE;
1339 else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */
1340 ier |= STM32H7_SPI_IER_RXPIE;
1341
1342 /* Enable the interrupts relative to the end of transfer */
1343 ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE |
1344 STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE;
1345
1346 spin_lock_irqsave(&spi->lock, flags);
1347
1348 stm32_spi_enable(spi);
1349
1350 /* Be sure to have data in fifo before starting data transfer */
1351 if (spi->tx_buf)
1352 stm32h7_spi_write_txfifo(spi);
1353
1354 if (STM32_SPI_HOST_MODE(spi))
1355 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
1356
1357 writel_relaxed(ier, spi->base + STM32H7_SPI_IER);
1358
1359 spin_unlock_irqrestore(&spi->lock, flags);
1360
1361 return 1;
1362}
1363
1364/**
1365 * stm32fx_spi_transfer_one_dma_start - Set SPI driver registers to start
1366 * transfer using DMA
1367 * @spi: pointer to the spi controller data structure
1368 */
1369static void stm32fx_spi_transfer_one_dma_start(struct stm32_spi *spi)
1370{
1371 /* In DMA mode end of transfer is handled by DMA TX or RX callback. */
1372 if (spi->cur_comm == SPI_SIMPLEX_RX || spi->cur_comm == SPI_3WIRE_RX ||
1373 spi->cur_comm == SPI_FULL_DUPLEX) {
1374 /*
1375 * In transmit-only mode, the OVR flag is set in the SR register
1376 * since the received data are never read. Therefore set OVR
1377 * interrupt only when rx buffer is available.
1378 */
1379 stm32_spi_set_bits(spi, STM32FX_SPI_CR2, STM32FX_SPI_CR2_ERRIE);
1380 }
1381
1382 stm32_spi_enable(spi);
1383}
1384
1385/**
1386 * stm32f7_spi_transfer_one_dma_start - Set SPI driver registers to start
1387 * transfer using DMA
1388 * @spi: pointer to the spi controller data structure
1389 */
1390static void stm32f7_spi_transfer_one_dma_start(struct stm32_spi *spi)
1391{
1392 /* Configure DMA request trigger threshold according to DMA width */
1393 if (spi->cur_bpw <= 8)
1394 stm32_spi_set_bits(spi, STM32FX_SPI_CR2, STM32F7_SPI_CR2_FRXTH);
1395 else
1396 stm32_spi_clr_bits(spi, STM32FX_SPI_CR2, STM32F7_SPI_CR2_FRXTH);
1397
1398 stm32fx_spi_transfer_one_dma_start(spi);
1399}
1400
1401/**
1402 * stm32h7_spi_transfer_one_dma_start - Set SPI driver registers to start
1403 * transfer using DMA
1404 * @spi: pointer to the spi controller data structure
1405 */
1406static void stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi)
1407{
1408 uint32_t ier = STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE;
1409
1410 /* Enable the interrupts */
1411 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX)
1412 ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE;
1413
1414 stm32_spi_set_bits(spi, STM32H7_SPI_IER, ier);
1415
1416 stm32_spi_enable(spi);
1417
1418 if (STM32_SPI_HOST_MODE(spi))
1419 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
1420}
1421
1422/**
1423 * stm32_spi_transfer_one_dma - transfer a single spi_transfer using DMA
1424 * @spi: pointer to the spi controller data structure
1425 * @xfer: pointer to the spi_transfer structure
1426 *
1427 * It must returns 0 if the transfer is finished or 1 if the transfer is still
1428 * in progress.
1429 */
1430static int stm32_spi_transfer_one_dma(struct stm32_spi *spi,
1431 struct spi_transfer *xfer)
1432{
1433 struct dma_slave_config tx_dma_conf, rx_dma_conf;
1434 struct dma_async_tx_descriptor *tx_dma_desc, *rx_dma_desc;
1435 unsigned long flags;
1436
1437 spin_lock_irqsave(&spi->lock, flags);
1438
1439 rx_dma_desc = NULL;
1440 if (spi->rx_buf && spi->dma_rx) {
1441 stm32_spi_dma_config(spi, spi->dma_rx, &rx_dma_conf, DMA_DEV_TO_MEM);
1442 dmaengine_slave_config(spi->dma_rx, &rx_dma_conf);
1443
1444 /* Enable Rx DMA request */
1445 stm32_spi_set_bits(spi, spi->cfg->regs->dma_rx_en.reg,
1446 spi->cfg->regs->dma_rx_en.mask);
1447
1448 rx_dma_desc = dmaengine_prep_slave_sg(
1449 spi->dma_rx, xfer->rx_sg.sgl,
1450 xfer->rx_sg.nents,
1451 rx_dma_conf.direction,
1452 DMA_PREP_INTERRUPT);
1453 }
1454
1455 tx_dma_desc = NULL;
1456 if (spi->tx_buf && spi->dma_tx) {
1457 stm32_spi_dma_config(spi, spi->dma_tx, &tx_dma_conf, DMA_MEM_TO_DEV);
1458 dmaengine_slave_config(spi->dma_tx, &tx_dma_conf);
1459
1460 tx_dma_desc = dmaengine_prep_slave_sg(
1461 spi->dma_tx, xfer->tx_sg.sgl,
1462 xfer->tx_sg.nents,
1463 tx_dma_conf.direction,
1464 DMA_PREP_INTERRUPT);
1465 }
1466
1467 if ((spi->tx_buf && spi->dma_tx && !tx_dma_desc) ||
1468 (spi->rx_buf && spi->dma_rx && !rx_dma_desc))
1469 goto dma_desc_error;
1470
1471 if (spi->cur_comm == SPI_FULL_DUPLEX && (!tx_dma_desc || !rx_dma_desc))
1472 goto dma_desc_error;
1473
1474 if (rx_dma_desc) {
1475 rx_dma_desc->callback = spi->cfg->dma_rx_cb;
1476 rx_dma_desc->callback_param = spi;
1477
1478 if (dma_submit_error(dmaengine_submit(rx_dma_desc))) {
1479 dev_err(spi->dev, "Rx DMA submit failed\n");
1480 goto dma_desc_error;
1481 }
1482 /* Enable Rx DMA channel */
1483 dma_async_issue_pending(spi->dma_rx);
1484 }
1485
1486 if (tx_dma_desc) {
1487 if (spi->cur_comm == SPI_SIMPLEX_TX ||
1488 spi->cur_comm == SPI_3WIRE_TX) {
1489 tx_dma_desc->callback = spi->cfg->dma_tx_cb;
1490 tx_dma_desc->callback_param = spi;
1491 }
1492
1493 if (dma_submit_error(dmaengine_submit(tx_dma_desc))) {
1494 dev_err(spi->dev, "Tx DMA submit failed\n");
1495 goto dma_submit_error;
1496 }
1497 /* Enable Tx DMA channel */
1498 dma_async_issue_pending(spi->dma_tx);
1499
1500 /* Enable Tx DMA request */
1501 stm32_spi_set_bits(spi, spi->cfg->regs->dma_tx_en.reg,
1502 spi->cfg->regs->dma_tx_en.mask);
1503 }
1504
1505 spi->cfg->transfer_one_dma_start(spi);
1506
1507 spin_unlock_irqrestore(&spi->lock, flags);
1508
1509 return 1;
1510
1511dma_submit_error:
1512 if (spi->dma_rx)
1513 dmaengine_terminate_sync(spi->dma_rx);
1514
1515dma_desc_error:
1516 stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg,
1517 spi->cfg->regs->dma_rx_en.mask);
1518
1519 spin_unlock_irqrestore(&spi->lock, flags);
1520
1521 dev_info(spi->dev, "DMA issue: fall back to irq transfer\n");
1522
1523 spi->cur_usedma = false;
1524 return spi->cfg->transfer_one_irq(spi);
1525}
1526
1527/**
1528 * stm32f4_spi_set_bpw - Configure bits per word
1529 * @spi: pointer to the spi controller data structure
1530 */
1531static void stm32f4_spi_set_bpw(struct stm32_spi *spi)
1532{
1533 if (spi->cur_bpw == 16)
1534 stm32_spi_set_bits(spi, STM32FX_SPI_CR1, STM32F4_SPI_CR1_DFF);
1535 else
1536 stm32_spi_clr_bits(spi, STM32FX_SPI_CR1, STM32F4_SPI_CR1_DFF);
1537}
1538
1539/**
1540 * stm32f7_spi_set_bpw - Configure bits per word
1541 * @spi: pointer to the spi controller data structure
1542 */
1543static void stm32f7_spi_set_bpw(struct stm32_spi *spi)
1544{
1545 u32 bpw;
1546 u32 cr2_clrb = 0, cr2_setb = 0;
1547
1548 bpw = spi->cur_bpw - 1;
1549
1550 cr2_clrb |= STM32F7_SPI_CR2_DS;
1551 cr2_setb |= FIELD_PREP(STM32F7_SPI_CR2_DS, bpw);
1552
1553 if (spi->rx_len >= sizeof(u16))
1554 cr2_clrb |= STM32F7_SPI_CR2_FRXTH;
1555 else
1556 cr2_setb |= STM32F7_SPI_CR2_FRXTH;
1557
1558 writel_relaxed(
1559 (readl_relaxed(spi->base + STM32FX_SPI_CR2) &
1560 ~cr2_clrb) | cr2_setb,
1561 spi->base + STM32FX_SPI_CR2);
1562}
1563
1564/**
1565 * stm32h7_spi_set_bpw - configure bits per word
1566 * @spi: pointer to the spi controller data structure
1567 */
1568static void stm32h7_spi_set_bpw(struct stm32_spi *spi)
1569{
1570 u32 bpw, fthlv;
1571 u32 cfg1_clrb = 0, cfg1_setb = 0;
1572
1573 bpw = spi->cur_bpw - 1;
1574
1575 cfg1_clrb |= STM32H7_SPI_CFG1_DSIZE;
1576 cfg1_setb |= FIELD_PREP(STM32H7_SPI_CFG1_DSIZE, bpw);
1577
1578 spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen);
1579 fthlv = spi->cur_fthlv - 1;
1580
1581 cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV;
1582 cfg1_setb |= FIELD_PREP(STM32H7_SPI_CFG1_FTHLV, fthlv);
1583
1584 writel_relaxed(
1585 (readl_relaxed(spi->base + STM32H7_SPI_CFG1) &
1586 ~cfg1_clrb) | cfg1_setb,
1587 spi->base + STM32H7_SPI_CFG1);
1588}
1589
1590/**
1591 * stm32_spi_set_mbr - Configure baud rate divisor in host mode
1592 * @spi: pointer to the spi controller data structure
1593 * @mbrdiv: baud rate divisor value
1594 */
1595static void stm32_spi_set_mbr(struct stm32_spi *spi, u32 mbrdiv)
1596{
1597 u32 clrb = 0, setb = 0;
1598
1599 clrb |= spi->cfg->regs->br.mask;
1600 setb |= (mbrdiv << spi->cfg->regs->br.shift) & spi->cfg->regs->br.mask;
1601
1602 writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) &
1603 ~clrb) | setb,
1604 spi->base + spi->cfg->regs->br.reg);
1605}
1606
1607/**
1608 * stm32_spi_communication_type - return transfer communication type
1609 * @spi_dev: pointer to the spi device
1610 * @transfer: pointer to spi transfer
1611 */
1612static unsigned int stm32_spi_communication_type(struct spi_device *spi_dev,
1613 struct spi_transfer *transfer)
1614{
1615 unsigned int type = SPI_FULL_DUPLEX;
1616
1617 if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */
1618 /*
1619 * SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL
1620 * is forbidden and unvalidated by SPI subsystem so depending
1621 * on the valid buffer, we can determine the direction of the
1622 * transfer.
1623 */
1624 if (!transfer->tx_buf)
1625 type = SPI_3WIRE_RX;
1626 else
1627 type = SPI_3WIRE_TX;
1628 } else {
1629 if (!transfer->tx_buf)
1630 type = SPI_SIMPLEX_RX;
1631 else if (!transfer->rx_buf)
1632 type = SPI_SIMPLEX_TX;
1633 }
1634
1635 return type;
1636}
1637
1638/**
1639 * stm32fx_spi_set_mode - configure communication mode
1640 * @spi: pointer to the spi controller data structure
1641 * @comm_type: type of communication to configure
1642 */
1643static int stm32fx_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
1644{
1645 if (comm_type == SPI_3WIRE_TX || comm_type == SPI_SIMPLEX_TX) {
1646 stm32_spi_set_bits(spi, STM32FX_SPI_CR1,
1647 STM32FX_SPI_CR1_BIDIMODE |
1648 STM32FX_SPI_CR1_BIDIOE);
1649 } else if (comm_type == SPI_FULL_DUPLEX ||
1650 comm_type == SPI_SIMPLEX_RX) {
1651 stm32_spi_clr_bits(spi, STM32FX_SPI_CR1,
1652 STM32FX_SPI_CR1_BIDIMODE |
1653 STM32FX_SPI_CR1_BIDIOE);
1654 } else if (comm_type == SPI_3WIRE_RX) {
1655 stm32_spi_set_bits(spi, STM32FX_SPI_CR1,
1656 STM32FX_SPI_CR1_BIDIMODE);
1657 stm32_spi_clr_bits(spi, STM32FX_SPI_CR1,
1658 STM32FX_SPI_CR1_BIDIOE);
1659 } else {
1660 return -EINVAL;
1661 }
1662
1663 return 0;
1664}
1665
1666/**
1667 * stm32h7_spi_set_mode - configure communication mode
1668 * @spi: pointer to the spi controller data structure
1669 * @comm_type: type of communication to configure
1670 */
1671static int stm32h7_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
1672{
1673 u32 mode;
1674 u32 cfg2_clrb = 0, cfg2_setb = 0;
1675
1676 if (comm_type == SPI_3WIRE_RX) {
1677 mode = STM32H7_SPI_HALF_DUPLEX;
1678 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
1679 } else if (comm_type == SPI_3WIRE_TX) {
1680 mode = STM32H7_SPI_HALF_DUPLEX;
1681 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
1682 } else if (comm_type == SPI_SIMPLEX_RX) {
1683 mode = STM32H7_SPI_SIMPLEX_RX;
1684 } else if (comm_type == SPI_SIMPLEX_TX) {
1685 mode = STM32H7_SPI_SIMPLEX_TX;
1686 } else {
1687 mode = STM32H7_SPI_FULL_DUPLEX;
1688 }
1689
1690 cfg2_clrb |= STM32H7_SPI_CFG2_COMM;
1691 cfg2_setb |= FIELD_PREP(STM32H7_SPI_CFG2_COMM, mode);
1692
1693 writel_relaxed(
1694 (readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
1695 ~cfg2_clrb) | cfg2_setb,
1696 spi->base + STM32H7_SPI_CFG2);
1697
1698 return 0;
1699}
1700
1701/**
1702 * stm32h7_spi_data_idleness - configure minimum time delay inserted between two
1703 * consecutive data frames in host mode
1704 * @spi: pointer to the spi controller data structure
1705 * @len: transfer len
1706 */
1707static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len)
1708{
1709 u32 cfg2_clrb = 0, cfg2_setb = 0;
1710
1711 cfg2_clrb |= STM32H7_SPI_CFG2_MIDI;
1712 if ((len > 1) && (spi->cur_midi > 0)) {
1713 u32 sck_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, spi->cur_speed);
1714 u32 midi = min_t(u32,
1715 DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
1716 FIELD_GET(STM32H7_SPI_CFG2_MIDI,
1717 STM32H7_SPI_CFG2_MIDI));
1718
1719
1720 dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n",
1721 sck_period_ns, midi, midi * sck_period_ns);
1722 cfg2_setb |= FIELD_PREP(STM32H7_SPI_CFG2_MIDI, midi);
1723 }
1724
1725 writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
1726 ~cfg2_clrb) | cfg2_setb,
1727 spi->base + STM32H7_SPI_CFG2);
1728}
1729
1730/**
1731 * stm32h7_spi_number_of_data - configure number of data at current transfer
1732 * @spi: pointer to the spi controller data structure
1733 * @nb_words: transfer length (in words)
1734 */
1735static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words)
1736{
1737 if (nb_words <= spi->t_size_max) {
1738 writel_relaxed(FIELD_PREP(STM32H7_SPI_CR2_TSIZE, nb_words),
1739 spi->base + STM32H7_SPI_CR2);
1740 } else {
1741 return -EMSGSIZE;
1742 }
1743
1744 return 0;
1745}
1746
1747/**
1748 * stm32_spi_transfer_one_setup - common setup to transfer a single
1749 * spi_transfer either using DMA or
1750 * interrupts.
1751 * @spi: pointer to the spi controller data structure
1752 * @spi_dev: pointer to the spi device
1753 * @transfer: pointer to spi transfer
1754 */
1755static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
1756 struct spi_device *spi_dev,
1757 struct spi_transfer *transfer)
1758{
1759 unsigned long flags;
1760 unsigned int comm_type;
1761 int nb_words, ret = 0;
1762 int mbr;
1763
1764 spin_lock_irqsave(&spi->lock, flags);
1765
1766 spi->cur_xferlen = transfer->len;
1767
1768 spi->cur_bpw = transfer->bits_per_word;
1769 spi->cfg->set_bpw(spi);
1770
1771 /* Update spi->cur_speed with real clock speed */
1772 if (STM32_SPI_HOST_MODE(spi)) {
1773 mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz,
1774 spi->cfg->baud_rate_div_min,
1775 spi->cfg->baud_rate_div_max);
1776 if (mbr < 0) {
1777 ret = mbr;
1778 goto out;
1779 }
1780
1781 transfer->speed_hz = spi->cur_speed;
1782 stm32_spi_set_mbr(spi, mbr);
1783 }
1784
1785 comm_type = stm32_spi_communication_type(spi_dev, transfer);
1786 ret = spi->cfg->set_mode(spi, comm_type);
1787 if (ret < 0)
1788 goto out;
1789
1790 spi->cur_comm = comm_type;
1791
1792 if (STM32_SPI_HOST_MODE(spi) && spi->cfg->set_data_idleness)
1793 spi->cfg->set_data_idleness(spi, transfer->len);
1794
1795 if (spi->cur_bpw <= 8)
1796 nb_words = transfer->len;
1797 else if (spi->cur_bpw <= 16)
1798 nb_words = DIV_ROUND_UP(transfer->len * 8, 16);
1799 else
1800 nb_words = DIV_ROUND_UP(transfer->len * 8, 32);
1801
1802 if (spi->cfg->set_number_of_data) {
1803 ret = spi->cfg->set_number_of_data(spi, nb_words);
1804 if (ret < 0)
1805 goto out;
1806 }
1807
1808 dev_dbg(spi->dev, "transfer communication mode set to %d\n",
1809 spi->cur_comm);
1810 dev_dbg(spi->dev,
1811 "data frame of %d-bit, data packet of %d data frames\n",
1812 spi->cur_bpw, spi->cur_fthlv);
1813 if (STM32_SPI_HOST_MODE(spi))
1814 dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed);
1815 dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n",
1816 spi->cur_xferlen, nb_words);
1817 dev_dbg(spi->dev, "dma %s\n",
1818 (spi->cur_usedma) ? "enabled" : "disabled");
1819
1820out:
1821 spin_unlock_irqrestore(&spi->lock, flags);
1822
1823 return ret;
1824}
1825
1826/**
1827 * stm32_spi_transfer_one - transfer a single spi_transfer
1828 * @ctrl: controller interface
1829 * @spi_dev: pointer to the spi device
1830 * @transfer: pointer to spi transfer
1831 *
1832 * It must return 0 if the transfer is finished or 1 if the transfer is still
1833 * in progress.
1834 */
1835static int stm32_spi_transfer_one(struct spi_controller *ctrl,
1836 struct spi_device *spi_dev,
1837 struct spi_transfer *transfer)
1838{
1839 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
1840 int ret;
1841
1842 spi->tx_buf = transfer->tx_buf;
1843 spi->rx_buf = transfer->rx_buf;
1844 spi->tx_len = spi->tx_buf ? transfer->len : 0;
1845 spi->rx_len = spi->rx_buf ? transfer->len : 0;
1846
1847 spi->cur_usedma = (ctrl->can_dma &&
1848 ctrl->can_dma(ctrl, spi_dev, transfer));
1849
1850 ret = stm32_spi_transfer_one_setup(spi, spi_dev, transfer);
1851 if (ret) {
1852 dev_err(spi->dev, "SPI transfer setup failed\n");
1853 return ret;
1854 }
1855
1856 if (spi->cur_usedma)
1857 return stm32_spi_transfer_one_dma(spi, transfer);
1858 else
1859 return spi->cfg->transfer_one_irq(spi);
1860}
1861
1862/**
1863 * stm32_spi_unprepare_msg - relax the hardware
1864 * @ctrl: controller interface
1865 * @msg: pointer to the spi message
1866 */
1867static int stm32_spi_unprepare_msg(struct spi_controller *ctrl,
1868 struct spi_message *msg)
1869{
1870 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
1871
1872 spi->cfg->disable(spi);
1873
1874 return 0;
1875}
1876
1877/**
1878 * stm32fx_spi_config - Configure SPI controller as SPI host
1879 * @spi: pointer to the spi controller data structure
1880 */
1881static int stm32fx_spi_config(struct stm32_spi *spi)
1882{
1883 unsigned long flags;
1884
1885 spin_lock_irqsave(&spi->lock, flags);
1886
1887 /* Ensure I2SMOD bit is kept cleared */
1888 stm32_spi_clr_bits(spi, STM32FX_SPI_I2SCFGR,
1889 STM32FX_SPI_I2SCFGR_I2SMOD);
1890
1891 /*
1892 * - SS input value high
1893 * - transmitter half duplex direction
1894 * - Set the host mode (default Motorola mode)
1895 * - Consider 1 host/n targets configuration and
1896 * SS input value is determined by the SSI bit
1897 */
1898 stm32_spi_set_bits(spi, STM32FX_SPI_CR1, STM32FX_SPI_CR1_SSI |
1899 STM32FX_SPI_CR1_BIDIOE |
1900 STM32FX_SPI_CR1_MSTR |
1901 STM32FX_SPI_CR1_SSM);
1902
1903 spin_unlock_irqrestore(&spi->lock, flags);
1904
1905 return 0;
1906}
1907
1908/**
1909 * stm32h7_spi_config - Configure SPI controller
1910 * @spi: pointer to the spi controller data structure
1911 */
1912static int stm32h7_spi_config(struct stm32_spi *spi)
1913{
1914 unsigned long flags;
1915 u32 cr1 = 0, cfg2 = 0;
1916
1917 spin_lock_irqsave(&spi->lock, flags);
1918
1919 /* Ensure I2SMOD bit is kept cleared */
1920 stm32_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR,
1921 STM32H7_SPI_I2SCFGR_I2SMOD);
1922
1923 if (STM32_SPI_DEVICE_MODE(spi)) {
1924 /* Use native device select */
1925 cfg2 &= ~STM32H7_SPI_CFG2_SSM;
1926 } else {
1927 /*
1928 * - Transmitter half duplex direction
1929 * - Automatic communication suspend when RX-Fifo is full
1930 * - SS input value high
1931 */
1932 cr1 |= STM32H7_SPI_CR1_HDDIR | STM32H7_SPI_CR1_MASRX | STM32H7_SPI_CR1_SSI;
1933
1934 /*
1935 * - Set the host mode (default Motorola mode)
1936 * - Consider 1 host/n devices configuration and
1937 * SS input value is determined by the SSI bit
1938 * - keep control of all associated GPIOs
1939 */
1940 cfg2 |= STM32H7_SPI_CFG2_MASTER | STM32H7_SPI_CFG2_SSM | STM32H7_SPI_CFG2_AFCNTR;
1941 }
1942
1943 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, cr1);
1944 stm32_spi_set_bits(spi, STM32H7_SPI_CFG2, cfg2);
1945
1946 spin_unlock_irqrestore(&spi->lock, flags);
1947
1948 return 0;
1949}
1950
1951static const struct stm32_spi_cfg stm32f4_spi_cfg = {
1952 .regs = &stm32fx_spi_regspec,
1953 .get_bpw_mask = stm32f4_spi_get_bpw_mask,
1954 .disable = stm32fx_spi_disable,
1955 .config = stm32fx_spi_config,
1956 .set_bpw = stm32f4_spi_set_bpw,
1957 .set_mode = stm32fx_spi_set_mode,
1958 .write_tx = stm32f4_spi_write_tx,
1959 .read_rx = stm32f4_spi_read_rx,
1960 .transfer_one_dma_start = stm32fx_spi_transfer_one_dma_start,
1961 .dma_tx_cb = stm32fx_spi_dma_tx_cb,
1962 .dma_rx_cb = stm32_spi_dma_rx_cb,
1963 .transfer_one_irq = stm32fx_spi_transfer_one_irq,
1964 .irq_handler_event = stm32fx_spi_irq_event,
1965 .irq_handler_thread = stm32fx_spi_irq_thread,
1966 .baud_rate_div_min = STM32FX_SPI_BR_DIV_MIN,
1967 .baud_rate_div_max = STM32FX_SPI_BR_DIV_MAX,
1968 .has_fifo = false,
1969 .has_device_mode = false,
1970 .flags = SPI_CONTROLLER_MUST_TX,
1971};
1972
1973static const struct stm32_spi_cfg stm32f7_spi_cfg = {
1974 .regs = &stm32fx_spi_regspec,
1975 .get_bpw_mask = stm32f7_spi_get_bpw_mask,
1976 .disable = stm32fx_spi_disable,
1977 .config = stm32fx_spi_config,
1978 .set_bpw = stm32f7_spi_set_bpw,
1979 .set_mode = stm32fx_spi_set_mode,
1980 .write_tx = stm32f7_spi_write_tx,
1981 .read_rx = stm32f7_spi_read_rx,
1982 .transfer_one_dma_start = stm32f7_spi_transfer_one_dma_start,
1983 .dma_tx_cb = stm32fx_spi_dma_tx_cb,
1984 .dma_rx_cb = stm32_spi_dma_rx_cb,
1985 .transfer_one_irq = stm32fx_spi_transfer_one_irq,
1986 .irq_handler_event = stm32fx_spi_irq_event,
1987 .irq_handler_thread = stm32fx_spi_irq_thread,
1988 .baud_rate_div_min = STM32FX_SPI_BR_DIV_MIN,
1989 .baud_rate_div_max = STM32FX_SPI_BR_DIV_MAX,
1990 .has_fifo = false,
1991 .flags = SPI_CONTROLLER_MUST_TX,
1992};
1993
1994static const struct stm32_spi_cfg stm32h7_spi_cfg = {
1995 .regs = &stm32h7_spi_regspec,
1996 .get_fifo_size = stm32h7_spi_get_fifo_size,
1997 .get_bpw_mask = stm32h7_spi_get_bpw_mask,
1998 .disable = stm32h7_spi_disable,
1999 .config = stm32h7_spi_config,
2000 .set_bpw = stm32h7_spi_set_bpw,
2001 .set_mode = stm32h7_spi_set_mode,
2002 .set_data_idleness = stm32h7_spi_data_idleness,
2003 .set_number_of_data = stm32h7_spi_number_of_data,
2004 .write_tx = stm32h7_spi_write_txfifo,
2005 .read_rx = stm32h7_spi_read_rxfifo,
2006 .transfer_one_dma_start = stm32h7_spi_transfer_one_dma_start,
2007 .dma_rx_cb = stm32_spi_dma_rx_cb,
2008 /*
2009 * dma_tx_cb is not necessary since in case of TX, dma is followed by
2010 * SPI access hence handling is performed within the SPI interrupt
2011 */
2012 .transfer_one_irq = stm32h7_spi_transfer_one_irq,
2013 .irq_handler_thread = stm32h7_spi_irq_thread,
2014 .baud_rate_div_min = STM32H7_SPI_MBR_DIV_MIN,
2015 .baud_rate_div_max = STM32H7_SPI_MBR_DIV_MAX,
2016 .has_fifo = true,
2017 .has_device_mode = true,
2018};
2019
2020/*
2021 * STM32MP2 is compatible with the STM32H7 except:
2022 * - enforce the DMA maxburst value to 1
2023 * - spi8 have limited feature set (TSIZE_MAX = 1024, BPW of 8 OR 16)
2024 */
2025static const struct stm32_spi_cfg stm32mp25_spi_cfg = {
2026 .regs = &stm32mp25_spi_regspec,
2027 .get_fifo_size = stm32h7_spi_get_fifo_size,
2028 .get_bpw_mask = stm32mp25_spi_get_bpw_mask,
2029 .disable = stm32h7_spi_disable,
2030 .config = stm32h7_spi_config,
2031 .set_bpw = stm32h7_spi_set_bpw,
2032 .set_mode = stm32h7_spi_set_mode,
2033 .set_data_idleness = stm32h7_spi_data_idleness,
2034 .set_number_of_data = stm32h7_spi_number_of_data,
2035 .transfer_one_dma_start = stm32h7_spi_transfer_one_dma_start,
2036 .dma_rx_cb = stm32_spi_dma_rx_cb,
2037 /*
2038 * dma_tx_cb is not necessary since in case of TX, dma is followed by
2039 * SPI access hence handling is performed within the SPI interrupt
2040 */
2041 .transfer_one_irq = stm32h7_spi_transfer_one_irq,
2042 .irq_handler_thread = stm32h7_spi_irq_thread,
2043 .baud_rate_div_min = STM32H7_SPI_MBR_DIV_MIN,
2044 .baud_rate_div_max = STM32H7_SPI_MBR_DIV_MAX,
2045 .has_fifo = true,
2046 .prevent_dma_burst = true,
2047 .has_device_mode = true,
2048};
2049
2050static const struct of_device_id stm32_spi_of_match[] = {
2051 { .compatible = "st,stm32mp25-spi", .data = (void *)&stm32mp25_spi_cfg },
2052 { .compatible = "st,stm32h7-spi", .data = (void *)&stm32h7_spi_cfg },
2053 { .compatible = "st,stm32f4-spi", .data = (void *)&stm32f4_spi_cfg },
2054 { .compatible = "st,stm32f7-spi", .data = (void *)&stm32f7_spi_cfg },
2055 {},
2056};
2057MODULE_DEVICE_TABLE(of, stm32_spi_of_match);
2058
2059static int stm32h7_spi_device_abort(struct spi_controller *ctrl)
2060{
2061 spi_finalize_current_transfer(ctrl);
2062 return 0;
2063}
2064
2065static int stm32_spi_probe(struct platform_device *pdev)
2066{
2067 struct spi_controller *ctrl;
2068 struct stm32_spi *spi;
2069 struct resource *res;
2070 struct reset_control *rst;
2071 struct device_node *np = pdev->dev.of_node;
2072 bool device_mode;
2073 int ret;
2074 const struct stm32_spi_cfg *cfg = of_device_get_match_data(&pdev->dev);
2075
2076 device_mode = of_property_read_bool(np, "spi-slave");
2077 if (!cfg->has_device_mode && device_mode) {
2078 dev_err(&pdev->dev, "spi-slave not supported\n");
2079 return -EPERM;
2080 }
2081
2082 if (device_mode)
2083 ctrl = devm_spi_alloc_target(&pdev->dev, sizeof(struct stm32_spi));
2084 else
2085 ctrl = devm_spi_alloc_host(&pdev->dev, sizeof(struct stm32_spi));
2086 if (!ctrl) {
2087 dev_err(&pdev->dev, "spi controller allocation failed\n");
2088 return -ENOMEM;
2089 }
2090 platform_set_drvdata(pdev, ctrl);
2091
2092 spi = spi_controller_get_devdata(ctrl);
2093 spi->dev = &pdev->dev;
2094 spi->ctrl = ctrl;
2095 spi->device_mode = device_mode;
2096 spin_lock_init(&spi->lock);
2097
2098 spi->cfg = cfg;
2099
2100 spi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2101 if (IS_ERR(spi->base))
2102 return PTR_ERR(spi->base);
2103
2104 spi->phys_addr = (dma_addr_t)res->start;
2105
2106 spi->irq = platform_get_irq(pdev, 0);
2107 if (spi->irq <= 0)
2108 return spi->irq;
2109
2110 ret = devm_request_threaded_irq(&pdev->dev, spi->irq,
2111 spi->cfg->irq_handler_event,
2112 spi->cfg->irq_handler_thread,
2113 IRQF_ONESHOT, pdev->name, ctrl);
2114 if (ret) {
2115 dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq,
2116 ret);
2117 return ret;
2118 }
2119
2120 spi->clk = devm_clk_get(&pdev->dev, NULL);
2121 if (IS_ERR(spi->clk)) {
2122 ret = PTR_ERR(spi->clk);
2123 dev_err(&pdev->dev, "clk get failed: %d\n", ret);
2124 return ret;
2125 }
2126
2127 ret = clk_prepare_enable(spi->clk);
2128 if (ret) {
2129 dev_err(&pdev->dev, "clk enable failed: %d\n", ret);
2130 return ret;
2131 }
2132 spi->clk_rate = clk_get_rate(spi->clk);
2133 if (!spi->clk_rate) {
2134 dev_err(&pdev->dev, "clk rate = 0\n");
2135 ret = -EINVAL;
2136 goto err_clk_disable;
2137 }
2138
2139 rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
2140 if (rst) {
2141 if (IS_ERR(rst)) {
2142 ret = dev_err_probe(&pdev->dev, PTR_ERR(rst),
2143 "failed to get reset\n");
2144 goto err_clk_disable;
2145 }
2146
2147 reset_control_assert(rst);
2148 udelay(2);
2149 reset_control_deassert(rst);
2150 }
2151
2152 if (spi->cfg->has_fifo)
2153 spi->fifo_size = spi->cfg->get_fifo_size(spi);
2154
2155 spi->feature_set = STM32_SPI_FEATURE_FULL;
2156 if (spi->cfg->regs->fullcfg.reg) {
2157 spi->feature_set =
2158 FIELD_GET(STM32MP25_SPI_HWCFGR1_FULLCFG,
2159 readl_relaxed(spi->base + spi->cfg->regs->fullcfg.reg));
2160
2161 dev_dbg(spi->dev, "%s feature set\n",
2162 spi->feature_set == STM32_SPI_FEATURE_FULL ? "full" : "limited");
2163 }
2164
2165 /* Only for STM32H7 and after */
2166 spi->t_size_max = spi->feature_set == STM32_SPI_FEATURE_FULL ?
2167 STM32H7_SPI_TSIZE_MAX :
2168 STM32MP25_SPI_TSIZE_MAX_LIMITED;
2169 dev_dbg(spi->dev, "one message max size %d\n", spi->t_size_max);
2170
2171 ret = spi->cfg->config(spi);
2172 if (ret) {
2173 dev_err(&pdev->dev, "controller configuration failed: %d\n",
2174 ret);
2175 goto err_clk_disable;
2176 }
2177
2178 ctrl->dev.of_node = pdev->dev.of_node;
2179 ctrl->auto_runtime_pm = true;
2180 ctrl->bus_num = pdev->id;
2181 ctrl->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST |
2182 SPI_3WIRE;
2183 ctrl->bits_per_word_mask = spi->cfg->get_bpw_mask(spi);
2184 ctrl->max_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_min;
2185 ctrl->min_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_max;
2186 ctrl->use_gpio_descriptors = true;
2187 ctrl->optimize_message = stm32_spi_optimize_message;
2188 ctrl->prepare_message = stm32_spi_prepare_msg;
2189 ctrl->transfer_one = stm32_spi_transfer_one;
2190 ctrl->unprepare_message = stm32_spi_unprepare_msg;
2191 ctrl->flags = spi->cfg->flags;
2192 if (STM32_SPI_DEVICE_MODE(spi))
2193 ctrl->target_abort = stm32h7_spi_device_abort;
2194
2195 spi->dma_tx = dma_request_chan(spi->dev, "tx");
2196 if (IS_ERR(spi->dma_tx)) {
2197 ret = PTR_ERR(spi->dma_tx);
2198 spi->dma_tx = NULL;
2199 if (ret == -EPROBE_DEFER)
2200 goto err_clk_disable;
2201
2202 dev_warn(&pdev->dev, "failed to request tx dma channel\n");
2203 } else {
2204 ctrl->dma_tx = spi->dma_tx;
2205 }
2206
2207 spi->dma_rx = dma_request_chan(spi->dev, "rx");
2208 if (IS_ERR(spi->dma_rx)) {
2209 ret = PTR_ERR(spi->dma_rx);
2210 spi->dma_rx = NULL;
2211 if (ret == -EPROBE_DEFER)
2212 goto err_dma_release;
2213
2214 dev_warn(&pdev->dev, "failed to request rx dma channel\n");
2215 } else {
2216 ctrl->dma_rx = spi->dma_rx;
2217 }
2218
2219 if (spi->dma_tx || spi->dma_rx)
2220 ctrl->can_dma = stm32_spi_can_dma;
2221
2222 pm_runtime_set_autosuspend_delay(&pdev->dev,
2223 STM32_SPI_AUTOSUSPEND_DELAY);
2224 pm_runtime_use_autosuspend(&pdev->dev);
2225 pm_runtime_set_active(&pdev->dev);
2226 pm_runtime_get_noresume(&pdev->dev);
2227 pm_runtime_enable(&pdev->dev);
2228
2229 ret = spi_register_controller(ctrl);
2230 if (ret) {
2231 dev_err(&pdev->dev, "spi controller registration failed: %d\n",
2232 ret);
2233 goto err_pm_disable;
2234 }
2235
2236 pm_runtime_mark_last_busy(&pdev->dev);
2237 pm_runtime_put_autosuspend(&pdev->dev);
2238
2239 dev_info(&pdev->dev, "driver initialized (%s mode)\n",
2240 STM32_SPI_HOST_MODE(spi) ? "host" : "device");
2241
2242 return 0;
2243
2244err_pm_disable:
2245 pm_runtime_disable(&pdev->dev);
2246 pm_runtime_put_noidle(&pdev->dev);
2247 pm_runtime_set_suspended(&pdev->dev);
2248 pm_runtime_dont_use_autosuspend(&pdev->dev);
2249err_dma_release:
2250 if (spi->dma_tx)
2251 dma_release_channel(spi->dma_tx);
2252 if (spi->dma_rx)
2253 dma_release_channel(spi->dma_rx);
2254err_clk_disable:
2255 clk_disable_unprepare(spi->clk);
2256
2257 return ret;
2258}
2259
2260static void stm32_spi_remove(struct platform_device *pdev)
2261{
2262 struct spi_controller *ctrl = platform_get_drvdata(pdev);
2263 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
2264
2265 pm_runtime_get_sync(&pdev->dev);
2266
2267 spi_unregister_controller(ctrl);
2268 spi->cfg->disable(spi);
2269
2270 pm_runtime_disable(&pdev->dev);
2271 pm_runtime_put_noidle(&pdev->dev);
2272 pm_runtime_set_suspended(&pdev->dev);
2273 pm_runtime_dont_use_autosuspend(&pdev->dev);
2274
2275 if (ctrl->dma_tx)
2276 dma_release_channel(ctrl->dma_tx);
2277 if (ctrl->dma_rx)
2278 dma_release_channel(ctrl->dma_rx);
2279
2280 clk_disable_unprepare(spi->clk);
2281
2282
2283 pinctrl_pm_select_sleep_state(&pdev->dev);
2284}
2285
2286static int __maybe_unused stm32_spi_runtime_suspend(struct device *dev)
2287{
2288 struct spi_controller *ctrl = dev_get_drvdata(dev);
2289 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
2290
2291 clk_disable_unprepare(spi->clk);
2292
2293 return pinctrl_pm_select_sleep_state(dev);
2294}
2295
2296static int __maybe_unused stm32_spi_runtime_resume(struct device *dev)
2297{
2298 struct spi_controller *ctrl = dev_get_drvdata(dev);
2299 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
2300 int ret;
2301
2302 ret = pinctrl_pm_select_default_state(dev);
2303 if (ret)
2304 return ret;
2305
2306 return clk_prepare_enable(spi->clk);
2307}
2308
2309static int __maybe_unused stm32_spi_suspend(struct device *dev)
2310{
2311 struct spi_controller *ctrl = dev_get_drvdata(dev);
2312 int ret;
2313
2314 ret = spi_controller_suspend(ctrl);
2315 if (ret)
2316 return ret;
2317
2318 return pm_runtime_force_suspend(dev);
2319}
2320
2321static int __maybe_unused stm32_spi_resume(struct device *dev)
2322{
2323 struct spi_controller *ctrl = dev_get_drvdata(dev);
2324 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
2325 int ret;
2326
2327 ret = pm_runtime_force_resume(dev);
2328 if (ret)
2329 return ret;
2330
2331 ret = spi_controller_resume(ctrl);
2332 if (ret) {
2333 clk_disable_unprepare(spi->clk);
2334 return ret;
2335 }
2336
2337 ret = pm_runtime_resume_and_get(dev);
2338 if (ret < 0) {
2339 dev_err(dev, "Unable to power device:%d\n", ret);
2340 return ret;
2341 }
2342
2343 spi->cfg->config(spi);
2344
2345 pm_runtime_mark_last_busy(dev);
2346 pm_runtime_put_autosuspend(dev);
2347
2348 return 0;
2349}
2350
2351static const struct dev_pm_ops stm32_spi_pm_ops = {
2352 SET_SYSTEM_SLEEP_PM_OPS(stm32_spi_suspend, stm32_spi_resume)
2353 SET_RUNTIME_PM_OPS(stm32_spi_runtime_suspend,
2354 stm32_spi_runtime_resume, NULL)
2355};
2356
2357static struct platform_driver stm32_spi_driver = {
2358 .probe = stm32_spi_probe,
2359 .remove = stm32_spi_remove,
2360 .driver = {
2361 .name = DRIVER_NAME,
2362 .pm = &stm32_spi_pm_ops,
2363 .of_match_table = stm32_spi_of_match,
2364 },
2365};
2366
2367module_platform_driver(stm32_spi_driver);
2368
2369MODULE_ALIAS("platform:" DRIVER_NAME);
2370MODULE_DESCRIPTION("STMicroelectronics STM32 SPI Controller driver");
2371MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
2372MODULE_LICENSE("GPL v2");