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1/*
2 * Freescale i.MX7ULP LPSPI driver
3 *
4 * Copyright 2016 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#include <linux/clk.h>
19#include <linux/completion.h>
20#include <linux/delay.h>
21#include <linux/err.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
24#include <linux/irq.h>
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/of.h>
28#include <linux/of_device.h>
29#include <linux/platform_device.h>
30#include <linux/slab.h>
31#include <linux/spi/spi.h>
32#include <linux/spi/spi_bitbang.h>
33#include <linux/types.h>
34
35#define DRIVER_NAME "fsl_lpspi"
36
37/* i.MX7ULP LPSPI registers */
38#define IMX7ULP_VERID 0x0
39#define IMX7ULP_PARAM 0x4
40#define IMX7ULP_CR 0x10
41#define IMX7ULP_SR 0x14
42#define IMX7ULP_IER 0x18
43#define IMX7ULP_DER 0x1c
44#define IMX7ULP_CFGR0 0x20
45#define IMX7ULP_CFGR1 0x24
46#define IMX7ULP_DMR0 0x30
47#define IMX7ULP_DMR1 0x34
48#define IMX7ULP_CCR 0x40
49#define IMX7ULP_FCR 0x58
50#define IMX7ULP_FSR 0x5c
51#define IMX7ULP_TCR 0x60
52#define IMX7ULP_TDR 0x64
53#define IMX7ULP_RSR 0x70
54#define IMX7ULP_RDR 0x74
55
56/* General control register field define */
57#define CR_RRF BIT(9)
58#define CR_RTF BIT(8)
59#define CR_RST BIT(1)
60#define CR_MEN BIT(0)
61#define SR_TCF BIT(10)
62#define SR_RDF BIT(1)
63#define SR_TDF BIT(0)
64#define IER_TCIE BIT(10)
65#define IER_RDIE BIT(1)
66#define IER_TDIE BIT(0)
67#define CFGR1_PCSCFG BIT(27)
68#define CFGR1_PCSPOL BIT(8)
69#define CFGR1_NOSTALL BIT(3)
70#define CFGR1_MASTER BIT(0)
71#define RSR_RXEMPTY BIT(1)
72#define TCR_CPOL BIT(31)
73#define TCR_CPHA BIT(30)
74#define TCR_CONT BIT(21)
75#define TCR_CONTC BIT(20)
76#define TCR_RXMSK BIT(19)
77#define TCR_TXMSK BIT(18)
78
79static int clkdivs[] = {1, 2, 4, 8, 16, 32, 64, 128};
80
81struct lpspi_config {
82 u8 bpw;
83 u8 chip_select;
84 u8 prescale;
85 u16 mode;
86 u32 speed_hz;
87};
88
89struct fsl_lpspi_data {
90 struct device *dev;
91 void __iomem *base;
92 struct clk *clk;
93
94 void *rx_buf;
95 const void *tx_buf;
96 void (*tx)(struct fsl_lpspi_data *);
97 void (*rx)(struct fsl_lpspi_data *);
98
99 u32 remain;
100 u8 txfifosize;
101 u8 rxfifosize;
102
103 struct lpspi_config config;
104 struct completion xfer_done;
105};
106
107static const struct of_device_id fsl_lpspi_dt_ids[] = {
108 { .compatible = "fsl,imx7ulp-spi", },
109 { /* sentinel */ }
110};
111MODULE_DEVICE_TABLE(of, fsl_lpspi_dt_ids);
112
113#define LPSPI_BUF_RX(type) \
114static void fsl_lpspi_buf_rx_##type(struct fsl_lpspi_data *fsl_lpspi) \
115{ \
116 unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR); \
117 \
118 if (fsl_lpspi->rx_buf) { \
119 *(type *)fsl_lpspi->rx_buf = val; \
120 fsl_lpspi->rx_buf += sizeof(type); \
121 } \
122}
123
124#define LPSPI_BUF_TX(type) \
125static void fsl_lpspi_buf_tx_##type(struct fsl_lpspi_data *fsl_lpspi) \
126{ \
127 type val = 0; \
128 \
129 if (fsl_lpspi->tx_buf) { \
130 val = *(type *)fsl_lpspi->tx_buf; \
131 fsl_lpspi->tx_buf += sizeof(type); \
132 } \
133 \
134 fsl_lpspi->remain -= sizeof(type); \
135 writel(val, fsl_lpspi->base + IMX7ULP_TDR); \
136}
137
138LPSPI_BUF_RX(u8)
139LPSPI_BUF_TX(u8)
140LPSPI_BUF_RX(u16)
141LPSPI_BUF_TX(u16)
142LPSPI_BUF_RX(u32)
143LPSPI_BUF_TX(u32)
144
145static void fsl_lpspi_intctrl(struct fsl_lpspi_data *fsl_lpspi,
146 unsigned int enable)
147{
148 writel(enable, fsl_lpspi->base + IMX7ULP_IER);
149}
150
151static int lpspi_prepare_xfer_hardware(struct spi_master *master)
152{
153 struct fsl_lpspi_data *fsl_lpspi = spi_master_get_devdata(master);
154
155 return clk_prepare_enable(fsl_lpspi->clk);
156}
157
158static int lpspi_unprepare_xfer_hardware(struct spi_master *master)
159{
160 struct fsl_lpspi_data *fsl_lpspi = spi_master_get_devdata(master);
161
162 clk_disable_unprepare(fsl_lpspi->clk);
163
164 return 0;
165}
166
167static int fsl_lpspi_txfifo_empty(struct fsl_lpspi_data *fsl_lpspi)
168{
169 u32 txcnt;
170 unsigned long orig_jiffies = jiffies;
171
172 do {
173 txcnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff;
174
175 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
176 dev_dbg(fsl_lpspi->dev, "txfifo empty timeout\n");
177 return -ETIMEDOUT;
178 }
179 cond_resched();
180
181 } while (txcnt);
182
183 return 0;
184}
185
186static void fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data *fsl_lpspi)
187{
188 u8 txfifo_cnt;
189
190 txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff;
191
192 while (txfifo_cnt < fsl_lpspi->txfifosize) {
193 if (!fsl_lpspi->remain)
194 break;
195 fsl_lpspi->tx(fsl_lpspi);
196 txfifo_cnt++;
197 }
198
199 if (!fsl_lpspi->remain && (txfifo_cnt < fsl_lpspi->txfifosize))
200 writel(0, fsl_lpspi->base + IMX7ULP_TDR);
201 else
202 fsl_lpspi_intctrl(fsl_lpspi, IER_TDIE);
203}
204
205static void fsl_lpspi_read_rx_fifo(struct fsl_lpspi_data *fsl_lpspi)
206{
207 while (!(readl(fsl_lpspi->base + IMX7ULP_RSR) & RSR_RXEMPTY))
208 fsl_lpspi->rx(fsl_lpspi);
209}
210
211static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi,
212 bool is_first_xfer)
213{
214 u32 temp = 0;
215
216 temp |= fsl_lpspi->config.bpw - 1;
217 temp |= fsl_lpspi->config.prescale << 27;
218 temp |= (fsl_lpspi->config.mode & 0x3) << 30;
219 temp |= (fsl_lpspi->config.chip_select & 0x3) << 24;
220
221 /*
222 * Set TCR_CONT will keep SS asserted after current transfer.
223 * For the first transfer, clear TCR_CONTC to assert SS.
224 * For subsequent transfer, set TCR_CONTC to keep SS asserted.
225 */
226 temp |= TCR_CONT;
227 if (is_first_xfer)
228 temp &= ~TCR_CONTC;
229 else
230 temp |= TCR_CONTC;
231
232 writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
233
234 dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp);
235}
236
237static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi)
238{
239 u32 temp;
240
241 temp = fsl_lpspi->txfifosize >> 1 | (fsl_lpspi->rxfifosize >> 1) << 16;
242
243 writel(temp, fsl_lpspi->base + IMX7ULP_FCR);
244
245 dev_dbg(fsl_lpspi->dev, "FCR=0x%x\n", temp);
246}
247
248static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi)
249{
250 struct lpspi_config config = fsl_lpspi->config;
251 unsigned int perclk_rate, scldiv;
252 u8 prescale;
253
254 perclk_rate = clk_get_rate(fsl_lpspi->clk);
255 for (prescale = 0; prescale < 8; prescale++) {
256 scldiv = perclk_rate /
257 (clkdivs[prescale] * config.speed_hz) - 2;
258 if (scldiv < 256) {
259 fsl_lpspi->config.prescale = prescale;
260 break;
261 }
262 }
263
264 if (prescale == 8 && scldiv >= 256)
265 return -EINVAL;
266
267 writel(scldiv, fsl_lpspi->base + IMX7ULP_CCR);
268
269 dev_dbg(fsl_lpspi->dev, "perclk=%d, speed=%d, prescale =%d, scldiv=%d\n",
270 perclk_rate, config.speed_hz, prescale, scldiv);
271
272 return 0;
273}
274
275static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi)
276{
277 u32 temp;
278 int ret;
279
280 temp = CR_RST;
281 writel(temp, fsl_lpspi->base + IMX7ULP_CR);
282 writel(0, fsl_lpspi->base + IMX7ULP_CR);
283
284 ret = fsl_lpspi_set_bitrate(fsl_lpspi);
285 if (ret)
286 return ret;
287
288 fsl_lpspi_set_watermark(fsl_lpspi);
289
290 temp = CFGR1_PCSCFG | CFGR1_MASTER | CFGR1_NOSTALL;
291 if (fsl_lpspi->config.mode & SPI_CS_HIGH)
292 temp |= CFGR1_PCSPOL;
293 writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);
294
295 temp = readl(fsl_lpspi->base + IMX7ULP_CR);
296 temp |= CR_RRF | CR_RTF | CR_MEN;
297 writel(temp, fsl_lpspi->base + IMX7ULP_CR);
298
299 return 0;
300}
301
302static void fsl_lpspi_setup_transfer(struct spi_device *spi,
303 struct spi_transfer *t)
304{
305 struct fsl_lpspi_data *fsl_lpspi = spi_master_get_devdata(spi->master);
306
307 fsl_lpspi->config.mode = spi->mode;
308 fsl_lpspi->config.bpw = t ? t->bits_per_word : spi->bits_per_word;
309 fsl_lpspi->config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
310 fsl_lpspi->config.chip_select = spi->chip_select;
311
312 if (!fsl_lpspi->config.speed_hz)
313 fsl_lpspi->config.speed_hz = spi->max_speed_hz;
314 if (!fsl_lpspi->config.bpw)
315 fsl_lpspi->config.bpw = spi->bits_per_word;
316
317 /* Initialize the functions for transfer */
318 if (fsl_lpspi->config.bpw <= 8) {
319 fsl_lpspi->rx = fsl_lpspi_buf_rx_u8;
320 fsl_lpspi->tx = fsl_lpspi_buf_tx_u8;
321 } else if (fsl_lpspi->config.bpw <= 16) {
322 fsl_lpspi->rx = fsl_lpspi_buf_rx_u16;
323 fsl_lpspi->tx = fsl_lpspi_buf_tx_u16;
324 } else {
325 fsl_lpspi->rx = fsl_lpspi_buf_rx_u32;
326 fsl_lpspi->tx = fsl_lpspi_buf_tx_u32;
327 }
328
329 fsl_lpspi_config(fsl_lpspi);
330}
331
332static int fsl_lpspi_transfer_one(struct spi_master *master,
333 struct spi_device *spi,
334 struct spi_transfer *t)
335{
336 struct fsl_lpspi_data *fsl_lpspi = spi_master_get_devdata(master);
337 int ret;
338
339 fsl_lpspi->tx_buf = t->tx_buf;
340 fsl_lpspi->rx_buf = t->rx_buf;
341 fsl_lpspi->remain = t->len;
342
343 reinit_completion(&fsl_lpspi->xfer_done);
344 fsl_lpspi_write_tx_fifo(fsl_lpspi);
345
346 ret = wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ);
347 if (!ret) {
348 dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n");
349 return -ETIMEDOUT;
350 }
351
352 ret = fsl_lpspi_txfifo_empty(fsl_lpspi);
353 if (ret)
354 return ret;
355
356 fsl_lpspi_read_rx_fifo(fsl_lpspi);
357
358 return 0;
359}
360
361static int fsl_lpspi_transfer_one_msg(struct spi_master *master,
362 struct spi_message *msg)
363{
364 struct fsl_lpspi_data *fsl_lpspi = spi_master_get_devdata(master);
365 struct spi_device *spi = msg->spi;
366 struct spi_transfer *xfer;
367 bool is_first_xfer = true;
368 u32 temp;
369 int ret = 0;
370
371 msg->status = 0;
372 msg->actual_length = 0;
373
374 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
375 fsl_lpspi_setup_transfer(spi, xfer);
376 fsl_lpspi_set_cmd(fsl_lpspi, is_first_xfer);
377
378 is_first_xfer = false;
379
380 ret = fsl_lpspi_transfer_one(master, spi, xfer);
381 if (ret < 0)
382 goto complete;
383
384 msg->actual_length += xfer->len;
385 }
386
387complete:
388 /* de-assert SS, then finalize current message */
389 temp = readl(fsl_lpspi->base + IMX7ULP_TCR);
390 temp &= ~TCR_CONTC;
391 writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
392
393 msg->status = ret;
394 spi_finalize_current_message(master);
395
396 return ret;
397}
398
399static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id)
400{
401 struct fsl_lpspi_data *fsl_lpspi = dev_id;
402 u32 temp;
403
404 fsl_lpspi_intctrl(fsl_lpspi, 0);
405 temp = readl(fsl_lpspi->base + IMX7ULP_SR);
406
407 fsl_lpspi_read_rx_fifo(fsl_lpspi);
408
409 if (temp & SR_TDF) {
410 fsl_lpspi_write_tx_fifo(fsl_lpspi);
411
412 if (!fsl_lpspi->remain)
413 complete(&fsl_lpspi->xfer_done);
414
415 return IRQ_HANDLED;
416 }
417
418 return IRQ_NONE;
419}
420
421static int fsl_lpspi_probe(struct platform_device *pdev)
422{
423 struct fsl_lpspi_data *fsl_lpspi;
424 struct spi_master *master;
425 struct resource *res;
426 int ret, irq;
427 u32 temp;
428
429 master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_lpspi_data));
430 if (!master)
431 return -ENOMEM;
432
433 platform_set_drvdata(pdev, master);
434
435 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
436 master->bus_num = pdev->id;
437
438 fsl_lpspi = spi_master_get_devdata(master);
439 fsl_lpspi->dev = &pdev->dev;
440
441 master->transfer_one_message = fsl_lpspi_transfer_one_msg;
442 master->prepare_transfer_hardware = lpspi_prepare_xfer_hardware;
443 master->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware;
444 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
445 master->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
446 master->dev.of_node = pdev->dev.of_node;
447 master->bus_num = pdev->id;
448
449 init_completion(&fsl_lpspi->xfer_done);
450
451 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
452 fsl_lpspi->base = devm_ioremap_resource(&pdev->dev, res);
453 if (IS_ERR(fsl_lpspi->base)) {
454 ret = PTR_ERR(fsl_lpspi->base);
455 goto out_master_put;
456 }
457
458 irq = platform_get_irq(pdev, 0);
459 if (irq < 0) {
460 ret = irq;
461 goto out_master_put;
462 }
463
464 ret = devm_request_irq(&pdev->dev, irq, fsl_lpspi_isr, 0,
465 dev_name(&pdev->dev), fsl_lpspi);
466 if (ret) {
467 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
468 goto out_master_put;
469 }
470
471 fsl_lpspi->clk = devm_clk_get(&pdev->dev, "ipg");
472 if (IS_ERR(fsl_lpspi->clk)) {
473 ret = PTR_ERR(fsl_lpspi->clk);
474 goto out_master_put;
475 }
476
477 ret = clk_prepare_enable(fsl_lpspi->clk);
478 if (ret) {
479 dev_err(&pdev->dev, "can't enable lpspi clock, ret=%d\n", ret);
480 goto out_master_put;
481 }
482
483 temp = readl(fsl_lpspi->base + IMX7ULP_PARAM);
484 fsl_lpspi->txfifosize = 1 << (temp & 0x0f);
485 fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f);
486
487 clk_disable_unprepare(fsl_lpspi->clk);
488
489 ret = devm_spi_register_master(&pdev->dev, master);
490 if (ret < 0) {
491 dev_err(&pdev->dev, "spi_register_master error.\n");
492 goto out_master_put;
493 }
494
495 return 0;
496
497out_master_put:
498 spi_master_put(master);
499
500 return ret;
501}
502
503static int fsl_lpspi_remove(struct platform_device *pdev)
504{
505 struct spi_master *master = platform_get_drvdata(pdev);
506 struct fsl_lpspi_data *fsl_lpspi = spi_master_get_devdata(master);
507
508 clk_disable_unprepare(fsl_lpspi->clk);
509
510 return 0;
511}
512
513static struct platform_driver fsl_lpspi_driver = {
514 .driver = {
515 .name = DRIVER_NAME,
516 .of_match_table = fsl_lpspi_dt_ids,
517 },
518 .probe = fsl_lpspi_probe,
519 .remove = fsl_lpspi_remove,
520};
521module_platform_driver(fsl_lpspi_driver);
522
523MODULE_DESCRIPTION("LPSPI Master Controller driver");
524MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>");
525MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0+
2//
3// Freescale i.MX7ULP LPSPI driver
4//
5// Copyright 2016 Freescale Semiconductor, Inc.
6// Copyright 2018 NXP Semiconductors
7
8#include <linux/clk.h>
9#include <linux/completion.h>
10#include <linux/delay.h>
11#include <linux/dmaengine.h>
12#include <linux/dma-mapping.h>
13#include <linux/err.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/irq.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/pinctrl/consumer.h>
21#include <linux/platform_device.h>
22#include <linux/dma/imx-dma.h>
23#include <linux/pm_runtime.h>
24#include <linux/slab.h>
25#include <linux/spi/spi.h>
26#include <linux/spi/spi_bitbang.h>
27#include <linux/types.h>
28
29#define DRIVER_NAME "fsl_lpspi"
30
31#define FSL_LPSPI_RPM_TIMEOUT 50 /* 50ms */
32
33/* The maximum bytes that edma can transfer once.*/
34#define FSL_LPSPI_MAX_EDMA_BYTES ((1 << 15) - 1)
35
36/* i.MX7ULP LPSPI registers */
37#define IMX7ULP_VERID 0x0
38#define IMX7ULP_PARAM 0x4
39#define IMX7ULP_CR 0x10
40#define IMX7ULP_SR 0x14
41#define IMX7ULP_IER 0x18
42#define IMX7ULP_DER 0x1c
43#define IMX7ULP_CFGR0 0x20
44#define IMX7ULP_CFGR1 0x24
45#define IMX7ULP_DMR0 0x30
46#define IMX7ULP_DMR1 0x34
47#define IMX7ULP_CCR 0x40
48#define IMX7ULP_FCR 0x58
49#define IMX7ULP_FSR 0x5c
50#define IMX7ULP_TCR 0x60
51#define IMX7ULP_TDR 0x64
52#define IMX7ULP_RSR 0x70
53#define IMX7ULP_RDR 0x74
54
55/* General control register field define */
56#define CR_RRF BIT(9)
57#define CR_RTF BIT(8)
58#define CR_RST BIT(1)
59#define CR_MEN BIT(0)
60#define SR_MBF BIT(24)
61#define SR_TCF BIT(10)
62#define SR_FCF BIT(9)
63#define SR_RDF BIT(1)
64#define SR_TDF BIT(0)
65#define IER_TCIE BIT(10)
66#define IER_FCIE BIT(9)
67#define IER_RDIE BIT(1)
68#define IER_TDIE BIT(0)
69#define DER_RDDE BIT(1)
70#define DER_TDDE BIT(0)
71#define CFGR1_PCSCFG BIT(27)
72#define CFGR1_PINCFG (BIT(24)|BIT(25))
73#define CFGR1_PCSPOL BIT(8)
74#define CFGR1_NOSTALL BIT(3)
75#define CFGR1_HOST BIT(0)
76#define FSR_TXCOUNT (0xFF)
77#define RSR_RXEMPTY BIT(1)
78#define TCR_CPOL BIT(31)
79#define TCR_CPHA BIT(30)
80#define TCR_CONT BIT(21)
81#define TCR_CONTC BIT(20)
82#define TCR_RXMSK BIT(19)
83#define TCR_TXMSK BIT(18)
84
85struct fsl_lpspi_devtype_data {
86 u8 prescale_max;
87};
88
89struct lpspi_config {
90 u8 bpw;
91 u8 chip_select;
92 u8 prescale;
93 u16 mode;
94 u32 speed_hz;
95 u32 effective_speed_hz;
96};
97
98struct fsl_lpspi_data {
99 struct device *dev;
100 void __iomem *base;
101 unsigned long base_phys;
102 struct clk *clk_ipg;
103 struct clk *clk_per;
104 bool is_target;
105 bool is_only_cs1;
106 bool is_first_byte;
107
108 void *rx_buf;
109 const void *tx_buf;
110 void (*tx)(struct fsl_lpspi_data *);
111 void (*rx)(struct fsl_lpspi_data *);
112
113 u32 remain;
114 u8 watermark;
115 u8 txfifosize;
116 u8 rxfifosize;
117
118 struct lpspi_config config;
119 struct completion xfer_done;
120
121 bool target_aborted;
122
123 /* DMA */
124 bool usedma;
125 struct completion dma_rx_completion;
126 struct completion dma_tx_completion;
127
128 const struct fsl_lpspi_devtype_data *devtype_data;
129};
130
131/*
132 * ERR051608 fixed or not:
133 * https://www.nxp.com/docs/en/errata/i.MX93_1P87f.pdf
134 */
135static struct fsl_lpspi_devtype_data imx93_lpspi_devtype_data = {
136 .prescale_max = 1,
137};
138
139static struct fsl_lpspi_devtype_data imx7ulp_lpspi_devtype_data = {
140 .prescale_max = 7,
141};
142
143static const struct of_device_id fsl_lpspi_dt_ids[] = {
144 { .compatible = "fsl,imx7ulp-spi", .data = &imx7ulp_lpspi_devtype_data,},
145 { .compatible = "fsl,imx93-spi", .data = &imx93_lpspi_devtype_data,},
146 { /* sentinel */ }
147};
148MODULE_DEVICE_TABLE(of, fsl_lpspi_dt_ids);
149
150#define LPSPI_BUF_RX(type) \
151static void fsl_lpspi_buf_rx_##type(struct fsl_lpspi_data *fsl_lpspi) \
152{ \
153 unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR); \
154 \
155 if (fsl_lpspi->rx_buf) { \
156 *(type *)fsl_lpspi->rx_buf = val; \
157 fsl_lpspi->rx_buf += sizeof(type); \
158 } \
159}
160
161#define LPSPI_BUF_TX(type) \
162static void fsl_lpspi_buf_tx_##type(struct fsl_lpspi_data *fsl_lpspi) \
163{ \
164 type val = 0; \
165 \
166 if (fsl_lpspi->tx_buf) { \
167 val = *(type *)fsl_lpspi->tx_buf; \
168 fsl_lpspi->tx_buf += sizeof(type); \
169 } \
170 \
171 fsl_lpspi->remain -= sizeof(type); \
172 writel(val, fsl_lpspi->base + IMX7ULP_TDR); \
173}
174
175LPSPI_BUF_RX(u8)
176LPSPI_BUF_TX(u8)
177LPSPI_BUF_RX(u16)
178LPSPI_BUF_TX(u16)
179LPSPI_BUF_RX(u32)
180LPSPI_BUF_TX(u32)
181
182static void fsl_lpspi_intctrl(struct fsl_lpspi_data *fsl_lpspi,
183 unsigned int enable)
184{
185 writel(enable, fsl_lpspi->base + IMX7ULP_IER);
186}
187
188static int fsl_lpspi_bytes_per_word(const int bpw)
189{
190 return DIV_ROUND_UP(bpw, BITS_PER_BYTE);
191}
192
193static bool fsl_lpspi_can_dma(struct spi_controller *controller,
194 struct spi_device *spi,
195 struct spi_transfer *transfer)
196{
197 unsigned int bytes_per_word;
198
199 if (!controller->dma_rx)
200 return false;
201
202 bytes_per_word = fsl_lpspi_bytes_per_word(transfer->bits_per_word);
203
204 switch (bytes_per_word) {
205 case 1:
206 case 2:
207 case 4:
208 break;
209 default:
210 return false;
211 }
212
213 return true;
214}
215
216static int lpspi_prepare_xfer_hardware(struct spi_controller *controller)
217{
218 struct fsl_lpspi_data *fsl_lpspi =
219 spi_controller_get_devdata(controller);
220 int ret;
221
222 ret = pm_runtime_resume_and_get(fsl_lpspi->dev);
223 if (ret < 0) {
224 dev_err(fsl_lpspi->dev, "failed to enable clock\n");
225 return ret;
226 }
227
228 return 0;
229}
230
231static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller)
232{
233 struct fsl_lpspi_data *fsl_lpspi =
234 spi_controller_get_devdata(controller);
235
236 pm_runtime_mark_last_busy(fsl_lpspi->dev);
237 pm_runtime_put_autosuspend(fsl_lpspi->dev);
238
239 return 0;
240}
241
242static void fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data *fsl_lpspi)
243{
244 u8 txfifo_cnt;
245 u32 temp;
246
247 txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff;
248
249 while (txfifo_cnt < fsl_lpspi->txfifosize) {
250 if (!fsl_lpspi->remain)
251 break;
252 fsl_lpspi->tx(fsl_lpspi);
253 txfifo_cnt++;
254 }
255
256 if (txfifo_cnt < fsl_lpspi->txfifosize) {
257 if (!fsl_lpspi->is_target) {
258 temp = readl(fsl_lpspi->base + IMX7ULP_TCR);
259 temp &= ~TCR_CONTC;
260 writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
261 }
262
263 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
264 } else
265 fsl_lpspi_intctrl(fsl_lpspi, IER_TDIE);
266}
267
268static void fsl_lpspi_read_rx_fifo(struct fsl_lpspi_data *fsl_lpspi)
269{
270 while (!(readl(fsl_lpspi->base + IMX7ULP_RSR) & RSR_RXEMPTY))
271 fsl_lpspi->rx(fsl_lpspi);
272}
273
274static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi)
275{
276 u32 temp = 0;
277
278 temp |= fsl_lpspi->config.bpw - 1;
279 temp |= (fsl_lpspi->config.mode & 0x3) << 30;
280 temp |= (fsl_lpspi->config.chip_select & 0x3) << 24;
281 if (!fsl_lpspi->is_target) {
282 temp |= fsl_lpspi->config.prescale << 27;
283 /*
284 * Set TCR_CONT will keep SS asserted after current transfer.
285 * For the first transfer, clear TCR_CONTC to assert SS.
286 * For subsequent transfer, set TCR_CONTC to keep SS asserted.
287 */
288 if (!fsl_lpspi->usedma) {
289 temp |= TCR_CONT;
290 if (fsl_lpspi->is_first_byte)
291 temp &= ~TCR_CONTC;
292 else
293 temp |= TCR_CONTC;
294 }
295 }
296 writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
297
298 dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp);
299}
300
301static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi)
302{
303 u32 temp;
304
305 if (!fsl_lpspi->usedma)
306 temp = fsl_lpspi->watermark >> 1 |
307 (fsl_lpspi->watermark >> 1) << 16;
308 else
309 temp = fsl_lpspi->watermark >> 1;
310
311 writel(temp, fsl_lpspi->base + IMX7ULP_FCR);
312
313 dev_dbg(fsl_lpspi->dev, "FCR=0x%x\n", temp);
314}
315
316static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi)
317{
318 struct lpspi_config config = fsl_lpspi->config;
319 unsigned int perclk_rate, div;
320 u8 prescale_max;
321 u8 prescale;
322 int scldiv;
323
324 perclk_rate = clk_get_rate(fsl_lpspi->clk_per);
325 prescale_max = fsl_lpspi->devtype_data->prescale_max;
326
327 if (!config.speed_hz) {
328 dev_err(fsl_lpspi->dev,
329 "error: the transmission speed provided is 0!\n");
330 return -EINVAL;
331 }
332
333 if (config.speed_hz > perclk_rate / 2) {
334 dev_err(fsl_lpspi->dev,
335 "per-clk should be at least two times of transfer speed");
336 return -EINVAL;
337 }
338
339 div = DIV_ROUND_UP(perclk_rate, config.speed_hz);
340
341 for (prescale = 0; prescale <= prescale_max; prescale++) {
342 scldiv = div / (1 << prescale) - 2;
343 if (scldiv >= 0 && scldiv < 256) {
344 fsl_lpspi->config.prescale = prescale;
345 break;
346 }
347 }
348
349 if (scldiv < 0 || scldiv >= 256)
350 return -EINVAL;
351
352 writel(scldiv | (scldiv << 8) | ((scldiv >> 1) << 16),
353 fsl_lpspi->base + IMX7ULP_CCR);
354
355 fsl_lpspi->config.effective_speed_hz = perclk_rate / (scldiv + 2) *
356 (1 << prescale);
357
358 dev_dbg(fsl_lpspi->dev, "perclk=%u, speed=%u, prescale=%u, scldiv=%d\n",
359 perclk_rate, config.speed_hz, prescale, scldiv);
360
361 return 0;
362}
363
364static int fsl_lpspi_dma_configure(struct spi_controller *controller)
365{
366 int ret;
367 enum dma_slave_buswidth buswidth;
368 struct dma_slave_config rx = {}, tx = {};
369 struct fsl_lpspi_data *fsl_lpspi =
370 spi_controller_get_devdata(controller);
371
372 switch (fsl_lpspi_bytes_per_word(fsl_lpspi->config.bpw)) {
373 case 4:
374 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
375 break;
376 case 2:
377 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
378 break;
379 case 1:
380 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
381 break;
382 default:
383 return -EINVAL;
384 }
385
386 tx.direction = DMA_MEM_TO_DEV;
387 tx.dst_addr = fsl_lpspi->base_phys + IMX7ULP_TDR;
388 tx.dst_addr_width = buswidth;
389 tx.dst_maxburst = 1;
390 ret = dmaengine_slave_config(controller->dma_tx, &tx);
391 if (ret) {
392 dev_err(fsl_lpspi->dev, "TX dma configuration failed with %d\n",
393 ret);
394 return ret;
395 }
396
397 rx.direction = DMA_DEV_TO_MEM;
398 rx.src_addr = fsl_lpspi->base_phys + IMX7ULP_RDR;
399 rx.src_addr_width = buswidth;
400 rx.src_maxburst = 1;
401 ret = dmaengine_slave_config(controller->dma_rx, &rx);
402 if (ret) {
403 dev_err(fsl_lpspi->dev, "RX dma configuration failed with %d\n",
404 ret);
405 return ret;
406 }
407
408 return 0;
409}
410
411static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi)
412{
413 u32 temp;
414 int ret;
415
416 if (!fsl_lpspi->is_target) {
417 ret = fsl_lpspi_set_bitrate(fsl_lpspi);
418 if (ret)
419 return ret;
420 }
421
422 fsl_lpspi_set_watermark(fsl_lpspi);
423
424 if (!fsl_lpspi->is_target)
425 temp = CFGR1_HOST;
426 else
427 temp = CFGR1_PINCFG;
428 if (fsl_lpspi->config.mode & SPI_CS_HIGH)
429 temp |= CFGR1_PCSPOL;
430 writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);
431
432 temp = readl(fsl_lpspi->base + IMX7ULP_CR);
433 temp |= CR_RRF | CR_RTF | CR_MEN;
434 writel(temp, fsl_lpspi->base + IMX7ULP_CR);
435
436 temp = 0;
437 if (fsl_lpspi->usedma)
438 temp = DER_TDDE | DER_RDDE;
439 writel(temp, fsl_lpspi->base + IMX7ULP_DER);
440
441 return 0;
442}
443
444static int fsl_lpspi_setup_transfer(struct spi_controller *controller,
445 struct spi_device *spi,
446 struct spi_transfer *t)
447{
448 struct fsl_lpspi_data *fsl_lpspi =
449 spi_controller_get_devdata(spi->controller);
450
451 if (t == NULL)
452 return -EINVAL;
453
454 fsl_lpspi->config.mode = spi->mode;
455 fsl_lpspi->config.bpw = t->bits_per_word;
456 fsl_lpspi->config.speed_hz = t->speed_hz;
457 if (fsl_lpspi->is_only_cs1)
458 fsl_lpspi->config.chip_select = 1;
459 else
460 fsl_lpspi->config.chip_select = spi_get_chipselect(spi, 0);
461
462 if (!fsl_lpspi->config.speed_hz)
463 fsl_lpspi->config.speed_hz = spi->max_speed_hz;
464 if (!fsl_lpspi->config.bpw)
465 fsl_lpspi->config.bpw = spi->bits_per_word;
466
467 /* Initialize the functions for transfer */
468 if (fsl_lpspi->config.bpw <= 8) {
469 fsl_lpspi->rx = fsl_lpspi_buf_rx_u8;
470 fsl_lpspi->tx = fsl_lpspi_buf_tx_u8;
471 } else if (fsl_lpspi->config.bpw <= 16) {
472 fsl_lpspi->rx = fsl_lpspi_buf_rx_u16;
473 fsl_lpspi->tx = fsl_lpspi_buf_tx_u16;
474 } else {
475 fsl_lpspi->rx = fsl_lpspi_buf_rx_u32;
476 fsl_lpspi->tx = fsl_lpspi_buf_tx_u32;
477 }
478
479 if (t->len <= fsl_lpspi->txfifosize)
480 fsl_lpspi->watermark = t->len;
481 else
482 fsl_lpspi->watermark = fsl_lpspi->txfifosize;
483
484 if (fsl_lpspi_can_dma(controller, spi, t))
485 fsl_lpspi->usedma = true;
486 else
487 fsl_lpspi->usedma = false;
488
489 return fsl_lpspi_config(fsl_lpspi);
490}
491
492static int fsl_lpspi_target_abort(struct spi_controller *controller)
493{
494 struct fsl_lpspi_data *fsl_lpspi =
495 spi_controller_get_devdata(controller);
496
497 fsl_lpspi->target_aborted = true;
498 if (!fsl_lpspi->usedma)
499 complete(&fsl_lpspi->xfer_done);
500 else {
501 complete(&fsl_lpspi->dma_tx_completion);
502 complete(&fsl_lpspi->dma_rx_completion);
503 }
504
505 return 0;
506}
507
508static int fsl_lpspi_wait_for_completion(struct spi_controller *controller)
509{
510 struct fsl_lpspi_data *fsl_lpspi =
511 spi_controller_get_devdata(controller);
512
513 if (fsl_lpspi->is_target) {
514 if (wait_for_completion_interruptible(&fsl_lpspi->xfer_done) ||
515 fsl_lpspi->target_aborted) {
516 dev_dbg(fsl_lpspi->dev, "interrupted\n");
517 return -EINTR;
518 }
519 } else {
520 if (!wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ)) {
521 dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n");
522 return -ETIMEDOUT;
523 }
524 }
525
526 return 0;
527}
528
529static int fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi)
530{
531 u32 temp;
532
533 if (!fsl_lpspi->usedma) {
534 /* Disable all interrupt */
535 fsl_lpspi_intctrl(fsl_lpspi, 0);
536 }
537
538 /* W1C for all flags in SR */
539 temp = 0x3F << 8;
540 writel(temp, fsl_lpspi->base + IMX7ULP_SR);
541
542 /* Clear FIFO and disable module */
543 temp = CR_RRF | CR_RTF;
544 writel(temp, fsl_lpspi->base + IMX7ULP_CR);
545
546 return 0;
547}
548
549static void fsl_lpspi_dma_rx_callback(void *cookie)
550{
551 struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
552
553 complete(&fsl_lpspi->dma_rx_completion);
554}
555
556static void fsl_lpspi_dma_tx_callback(void *cookie)
557{
558 struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
559
560 complete(&fsl_lpspi->dma_tx_completion);
561}
562
563static int fsl_lpspi_calculate_timeout(struct fsl_lpspi_data *fsl_lpspi,
564 int size)
565{
566 unsigned long timeout = 0;
567
568 /* Time with actual data transfer and CS change delay related to HW */
569 timeout = (8 + 4) * size / fsl_lpspi->config.speed_hz;
570
571 /* Add extra second for scheduler related activities */
572 timeout += 1;
573
574 /* Double calculated timeout */
575 return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
576}
577
578static int fsl_lpspi_dma_transfer(struct spi_controller *controller,
579 struct fsl_lpspi_data *fsl_lpspi,
580 struct spi_transfer *transfer)
581{
582 struct dma_async_tx_descriptor *desc_tx, *desc_rx;
583 unsigned long transfer_timeout;
584 unsigned long time_left;
585 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
586 int ret;
587
588 ret = fsl_lpspi_dma_configure(controller);
589 if (ret)
590 return ret;
591
592 desc_rx = dmaengine_prep_slave_sg(controller->dma_rx,
593 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
594 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
595 if (!desc_rx)
596 return -EINVAL;
597
598 desc_rx->callback = fsl_lpspi_dma_rx_callback;
599 desc_rx->callback_param = (void *)fsl_lpspi;
600 dmaengine_submit(desc_rx);
601 reinit_completion(&fsl_lpspi->dma_rx_completion);
602 dma_async_issue_pending(controller->dma_rx);
603
604 desc_tx = dmaengine_prep_slave_sg(controller->dma_tx,
605 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
606 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
607 if (!desc_tx) {
608 dmaengine_terminate_all(controller->dma_tx);
609 return -EINVAL;
610 }
611
612 desc_tx->callback = fsl_lpspi_dma_tx_callback;
613 desc_tx->callback_param = (void *)fsl_lpspi;
614 dmaengine_submit(desc_tx);
615 reinit_completion(&fsl_lpspi->dma_tx_completion);
616 dma_async_issue_pending(controller->dma_tx);
617
618 fsl_lpspi->target_aborted = false;
619
620 if (!fsl_lpspi->is_target) {
621 transfer_timeout = fsl_lpspi_calculate_timeout(fsl_lpspi,
622 transfer->len);
623
624 /* Wait eDMA to finish the data transfer.*/
625 time_left = wait_for_completion_timeout(&fsl_lpspi->dma_tx_completion,
626 transfer_timeout);
627 if (!time_left) {
628 dev_err(fsl_lpspi->dev, "I/O Error in DMA TX\n");
629 dmaengine_terminate_all(controller->dma_tx);
630 dmaengine_terminate_all(controller->dma_rx);
631 fsl_lpspi_reset(fsl_lpspi);
632 return -ETIMEDOUT;
633 }
634
635 time_left = wait_for_completion_timeout(&fsl_lpspi->dma_rx_completion,
636 transfer_timeout);
637 if (!time_left) {
638 dev_err(fsl_lpspi->dev, "I/O Error in DMA RX\n");
639 dmaengine_terminate_all(controller->dma_tx);
640 dmaengine_terminate_all(controller->dma_rx);
641 fsl_lpspi_reset(fsl_lpspi);
642 return -ETIMEDOUT;
643 }
644 } else {
645 if (wait_for_completion_interruptible(&fsl_lpspi->dma_tx_completion) ||
646 fsl_lpspi->target_aborted) {
647 dev_dbg(fsl_lpspi->dev,
648 "I/O Error in DMA TX interrupted\n");
649 dmaengine_terminate_all(controller->dma_tx);
650 dmaengine_terminate_all(controller->dma_rx);
651 fsl_lpspi_reset(fsl_lpspi);
652 return -EINTR;
653 }
654
655 if (wait_for_completion_interruptible(&fsl_lpspi->dma_rx_completion) ||
656 fsl_lpspi->target_aborted) {
657 dev_dbg(fsl_lpspi->dev,
658 "I/O Error in DMA RX interrupted\n");
659 dmaengine_terminate_all(controller->dma_tx);
660 dmaengine_terminate_all(controller->dma_rx);
661 fsl_lpspi_reset(fsl_lpspi);
662 return -EINTR;
663 }
664 }
665
666 fsl_lpspi_reset(fsl_lpspi);
667
668 return 0;
669}
670
671static void fsl_lpspi_dma_exit(struct spi_controller *controller)
672{
673 if (controller->dma_rx) {
674 dma_release_channel(controller->dma_rx);
675 controller->dma_rx = NULL;
676 }
677
678 if (controller->dma_tx) {
679 dma_release_channel(controller->dma_tx);
680 controller->dma_tx = NULL;
681 }
682}
683
684static int fsl_lpspi_dma_init(struct device *dev,
685 struct fsl_lpspi_data *fsl_lpspi,
686 struct spi_controller *controller)
687{
688 int ret;
689
690 /* Prepare for TX DMA: */
691 controller->dma_tx = dma_request_chan(dev, "tx");
692 if (IS_ERR(controller->dma_tx)) {
693 ret = PTR_ERR(controller->dma_tx);
694 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
695 controller->dma_tx = NULL;
696 goto err;
697 }
698
699 /* Prepare for RX DMA: */
700 controller->dma_rx = dma_request_chan(dev, "rx");
701 if (IS_ERR(controller->dma_rx)) {
702 ret = PTR_ERR(controller->dma_rx);
703 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
704 controller->dma_rx = NULL;
705 goto err;
706 }
707
708 init_completion(&fsl_lpspi->dma_rx_completion);
709 init_completion(&fsl_lpspi->dma_tx_completion);
710 controller->can_dma = fsl_lpspi_can_dma;
711 controller->max_dma_len = FSL_LPSPI_MAX_EDMA_BYTES;
712
713 return 0;
714err:
715 fsl_lpspi_dma_exit(controller);
716 return ret;
717}
718
719static int fsl_lpspi_pio_transfer(struct spi_controller *controller,
720 struct spi_transfer *t)
721{
722 struct fsl_lpspi_data *fsl_lpspi =
723 spi_controller_get_devdata(controller);
724 int ret;
725
726 fsl_lpspi->tx_buf = t->tx_buf;
727 fsl_lpspi->rx_buf = t->rx_buf;
728 fsl_lpspi->remain = t->len;
729
730 reinit_completion(&fsl_lpspi->xfer_done);
731 fsl_lpspi->target_aborted = false;
732
733 fsl_lpspi_write_tx_fifo(fsl_lpspi);
734
735 ret = fsl_lpspi_wait_for_completion(controller);
736 if (ret)
737 return ret;
738
739 fsl_lpspi_reset(fsl_lpspi);
740
741 return 0;
742}
743
744static int fsl_lpspi_transfer_one(struct spi_controller *controller,
745 struct spi_device *spi,
746 struct spi_transfer *t)
747{
748 struct fsl_lpspi_data *fsl_lpspi =
749 spi_controller_get_devdata(controller);
750 int ret;
751
752 fsl_lpspi->is_first_byte = true;
753 ret = fsl_lpspi_setup_transfer(controller, spi, t);
754 if (ret < 0)
755 return ret;
756
757 t->effective_speed_hz = fsl_lpspi->config.effective_speed_hz;
758
759 fsl_lpspi_set_cmd(fsl_lpspi);
760 fsl_lpspi->is_first_byte = false;
761
762 if (fsl_lpspi->usedma)
763 ret = fsl_lpspi_dma_transfer(controller, fsl_lpspi, t);
764 else
765 ret = fsl_lpspi_pio_transfer(controller, t);
766 if (ret < 0)
767 return ret;
768
769 return 0;
770}
771
772static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id)
773{
774 u32 temp_SR, temp_IER;
775 struct fsl_lpspi_data *fsl_lpspi = dev_id;
776
777 temp_IER = readl(fsl_lpspi->base + IMX7ULP_IER);
778 fsl_lpspi_intctrl(fsl_lpspi, 0);
779 temp_SR = readl(fsl_lpspi->base + IMX7ULP_SR);
780
781 fsl_lpspi_read_rx_fifo(fsl_lpspi);
782
783 if ((temp_SR & SR_TDF) && (temp_IER & IER_TDIE)) {
784 fsl_lpspi_write_tx_fifo(fsl_lpspi);
785 return IRQ_HANDLED;
786 }
787
788 if (temp_SR & SR_MBF ||
789 readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_TXCOUNT) {
790 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
791 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
792 return IRQ_HANDLED;
793 }
794
795 if (temp_SR & SR_FCF && (temp_IER & IER_FCIE)) {
796 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
797 complete(&fsl_lpspi->xfer_done);
798 return IRQ_HANDLED;
799 }
800
801 return IRQ_NONE;
802}
803
804#ifdef CONFIG_PM
805static int fsl_lpspi_runtime_resume(struct device *dev)
806{
807 struct spi_controller *controller = dev_get_drvdata(dev);
808 struct fsl_lpspi_data *fsl_lpspi;
809 int ret;
810
811 fsl_lpspi = spi_controller_get_devdata(controller);
812
813 ret = clk_prepare_enable(fsl_lpspi->clk_per);
814 if (ret)
815 return ret;
816
817 ret = clk_prepare_enable(fsl_lpspi->clk_ipg);
818 if (ret) {
819 clk_disable_unprepare(fsl_lpspi->clk_per);
820 return ret;
821 }
822
823 return 0;
824}
825
826static int fsl_lpspi_runtime_suspend(struct device *dev)
827{
828 struct spi_controller *controller = dev_get_drvdata(dev);
829 struct fsl_lpspi_data *fsl_lpspi;
830
831 fsl_lpspi = spi_controller_get_devdata(controller);
832
833 clk_disable_unprepare(fsl_lpspi->clk_per);
834 clk_disable_unprepare(fsl_lpspi->clk_ipg);
835
836 return 0;
837}
838#endif
839
840static int fsl_lpspi_init_rpm(struct fsl_lpspi_data *fsl_lpspi)
841{
842 struct device *dev = fsl_lpspi->dev;
843
844 pm_runtime_enable(dev);
845 pm_runtime_set_autosuspend_delay(dev, FSL_LPSPI_RPM_TIMEOUT);
846 pm_runtime_use_autosuspend(dev);
847
848 return 0;
849}
850
851static int fsl_lpspi_probe(struct platform_device *pdev)
852{
853 const struct fsl_lpspi_devtype_data *devtype_data;
854 struct fsl_lpspi_data *fsl_lpspi;
855 struct spi_controller *controller;
856 struct resource *res;
857 int ret, irq;
858 u32 num_cs;
859 u32 temp;
860 bool is_target;
861
862 devtype_data = of_device_get_match_data(&pdev->dev);
863 if (!devtype_data)
864 return -ENODEV;
865
866 is_target = of_property_read_bool((&pdev->dev)->of_node, "spi-slave");
867 if (is_target)
868 controller = devm_spi_alloc_target(&pdev->dev,
869 sizeof(struct fsl_lpspi_data));
870 else
871 controller = devm_spi_alloc_host(&pdev->dev,
872 sizeof(struct fsl_lpspi_data));
873
874 if (!controller)
875 return -ENOMEM;
876
877 platform_set_drvdata(pdev, controller);
878
879 fsl_lpspi = spi_controller_get_devdata(controller);
880 fsl_lpspi->dev = &pdev->dev;
881 fsl_lpspi->is_target = is_target;
882 fsl_lpspi->is_only_cs1 = of_property_read_bool((&pdev->dev)->of_node,
883 "fsl,spi-only-use-cs1-sel");
884 fsl_lpspi->devtype_data = devtype_data;
885
886 init_completion(&fsl_lpspi->xfer_done);
887
888 fsl_lpspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
889 if (IS_ERR(fsl_lpspi->base)) {
890 ret = PTR_ERR(fsl_lpspi->base);
891 return ret;
892 }
893 fsl_lpspi->base_phys = res->start;
894
895 irq = platform_get_irq(pdev, 0);
896 if (irq < 0) {
897 ret = irq;
898 return ret;
899 }
900
901 ret = devm_request_irq(&pdev->dev, irq, fsl_lpspi_isr, IRQF_NO_AUTOEN,
902 dev_name(&pdev->dev), fsl_lpspi);
903 if (ret) {
904 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
905 return ret;
906 }
907
908 fsl_lpspi->clk_per = devm_clk_get(&pdev->dev, "per");
909 if (IS_ERR(fsl_lpspi->clk_per)) {
910 ret = PTR_ERR(fsl_lpspi->clk_per);
911 return ret;
912 }
913
914 fsl_lpspi->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
915 if (IS_ERR(fsl_lpspi->clk_ipg)) {
916 ret = PTR_ERR(fsl_lpspi->clk_ipg);
917 return ret;
918 }
919
920 /* enable the clock */
921 ret = fsl_lpspi_init_rpm(fsl_lpspi);
922 if (ret)
923 return ret;
924
925 ret = pm_runtime_get_sync(fsl_lpspi->dev);
926 if (ret < 0) {
927 dev_err(fsl_lpspi->dev, "failed to enable clock\n");
928 goto out_pm_get;
929 }
930
931 temp = readl(fsl_lpspi->base + IMX7ULP_PARAM);
932 fsl_lpspi->txfifosize = 1 << (temp & 0x0f);
933 fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f);
934 if (of_property_read_u32((&pdev->dev)->of_node, "num-cs",
935 &num_cs)) {
936 if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx93-spi"))
937 num_cs = ((temp >> 16) & 0xf);
938 else
939 num_cs = 1;
940 }
941
942 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
943 controller->transfer_one = fsl_lpspi_transfer_one;
944 controller->prepare_transfer_hardware = lpspi_prepare_xfer_hardware;
945 controller->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware;
946 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
947 controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
948 controller->dev.of_node = pdev->dev.of_node;
949 controller->bus_num = pdev->id;
950 controller->num_chipselect = num_cs;
951 controller->target_abort = fsl_lpspi_target_abort;
952 if (!fsl_lpspi->is_target)
953 controller->use_gpio_descriptors = true;
954
955 ret = fsl_lpspi_dma_init(&pdev->dev, fsl_lpspi, controller);
956 if (ret == -EPROBE_DEFER)
957 goto out_pm_get;
958 if (ret < 0) {
959 dev_warn(&pdev->dev, "dma setup error %d, use pio\n", ret);
960 enable_irq(irq);
961 }
962
963 ret = devm_spi_register_controller(&pdev->dev, controller);
964 if (ret < 0) {
965 dev_err_probe(&pdev->dev, ret, "spi_register_controller error\n");
966 goto free_dma;
967 }
968
969 pm_runtime_mark_last_busy(fsl_lpspi->dev);
970 pm_runtime_put_autosuspend(fsl_lpspi->dev);
971
972 return 0;
973
974free_dma:
975 fsl_lpspi_dma_exit(controller);
976out_pm_get:
977 pm_runtime_dont_use_autosuspend(fsl_lpspi->dev);
978 pm_runtime_put_sync(fsl_lpspi->dev);
979 pm_runtime_disable(fsl_lpspi->dev);
980
981 return ret;
982}
983
984static void fsl_lpspi_remove(struct platform_device *pdev)
985{
986 struct spi_controller *controller = platform_get_drvdata(pdev);
987 struct fsl_lpspi_data *fsl_lpspi =
988 spi_controller_get_devdata(controller);
989
990 fsl_lpspi_dma_exit(controller);
991
992 pm_runtime_dont_use_autosuspend(fsl_lpspi->dev);
993 pm_runtime_disable(fsl_lpspi->dev);
994}
995
996static int fsl_lpspi_suspend(struct device *dev)
997{
998 pinctrl_pm_select_sleep_state(dev);
999 return pm_runtime_force_suspend(dev);
1000}
1001
1002static int fsl_lpspi_resume(struct device *dev)
1003{
1004 int ret;
1005
1006 ret = pm_runtime_force_resume(dev);
1007 if (ret) {
1008 dev_err(dev, "Error in resume: %d\n", ret);
1009 return ret;
1010 }
1011
1012 pinctrl_pm_select_default_state(dev);
1013
1014 return 0;
1015}
1016
1017static const struct dev_pm_ops fsl_lpspi_pm_ops = {
1018 SET_RUNTIME_PM_OPS(fsl_lpspi_runtime_suspend,
1019 fsl_lpspi_runtime_resume, NULL)
1020 SYSTEM_SLEEP_PM_OPS(fsl_lpspi_suspend, fsl_lpspi_resume)
1021};
1022
1023static struct platform_driver fsl_lpspi_driver = {
1024 .driver = {
1025 .name = DRIVER_NAME,
1026 .of_match_table = fsl_lpspi_dt_ids,
1027 .pm = pm_ptr(&fsl_lpspi_pm_ops),
1028 },
1029 .probe = fsl_lpspi_probe,
1030 .remove = fsl_lpspi_remove,
1031};
1032module_platform_driver(fsl_lpspi_driver);
1033
1034MODULE_DESCRIPTION("LPSPI Controller driver");
1035MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>");
1036MODULE_LICENSE("GPL");