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1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/* Copyright(c) 2019-2022 Realtek Corporation
3 */
4
5#include "chan.h"
6#include "coex.h"
7#include "debug.h"
8#include "fw.h"
9#include "mac.h"
10#include "phy.h"
11#include "reg.h"
12#include "rtw8852c.h"
13#include "rtw8852c_rfk.h"
14#include "rtw8852c_table.h"
15#include "util.h"
16
17#define RTW8852C_FW_FORMAT_MAX 1
18#define RTW8852C_FW_BASENAME "rtw89/rtw8852c_fw"
19#define RTW8852C_MODULE_FIRMWARE \
20 RTW8852C_FW_BASENAME "-" __stringify(RTW8852C_FW_FORMAT_MAX) ".bin"
21
22static const struct rtw89_hfc_ch_cfg rtw8852c_hfc_chcfg_pcie[] = {
23 {13, 1614, grp_0}, /* ACH 0 */
24 {13, 1614, grp_0}, /* ACH 1 */
25 {13, 1614, grp_0}, /* ACH 2 */
26 {13, 1614, grp_0}, /* ACH 3 */
27 {13, 1614, grp_1}, /* ACH 4 */
28 {13, 1614, grp_1}, /* ACH 5 */
29 {13, 1614, grp_1}, /* ACH 6 */
30 {13, 1614, grp_1}, /* ACH 7 */
31 {13, 1614, grp_0}, /* B0MGQ */
32 {13, 1614, grp_0}, /* B0HIQ */
33 {13, 1614, grp_1}, /* B1MGQ */
34 {13, 1614, grp_1}, /* B1HIQ */
35 {40, 0, 0} /* FWCMDQ */
36};
37
38static const struct rtw89_hfc_pub_cfg rtw8852c_hfc_pubcfg_pcie = {
39 1614, /* Group 0 */
40 1614, /* Group 1 */
41 3228, /* Public Max */
42 0 /* WP threshold */
43};
44
45static const struct rtw89_hfc_param_ini rtw8852c_hfc_param_ini_pcie[] = {
46 [RTW89_QTA_SCC] = {rtw8852c_hfc_chcfg_pcie, &rtw8852c_hfc_pubcfg_pcie,
47 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH},
48 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie,
49 RTW89_HCIFC_POH},
50 [RTW89_QTA_INVALID] = {NULL},
51};
52
53static const struct rtw89_dle_mem rtw8852c_dle_mem_pcie[] = {
54 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size19,
55 &rtw89_mac_size.ple_size19, &rtw89_mac_size.wde_qt18,
56 &rtw89_mac_size.wde_qt18, &rtw89_mac_size.ple_qt46,
57 &rtw89_mac_size.ple_qt47},
58 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size18,
59 &rtw89_mac_size.ple_size18, &rtw89_mac_size.wde_qt17,
60 &rtw89_mac_size.wde_qt17, &rtw89_mac_size.ple_qt44,
61 &rtw89_mac_size.ple_qt45},
62 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
63 NULL},
64};
65
66static const u32 rtw8852c_h2c_regs[RTW89_H2CREG_MAX] = {
67 R_AX_H2CREG_DATA0_V1, R_AX_H2CREG_DATA1_V1, R_AX_H2CREG_DATA2_V1,
68 R_AX_H2CREG_DATA3_V1
69};
70
71static const u32 rtw8852c_c2h_regs[RTW89_H2CREG_MAX] = {
72 R_AX_C2HREG_DATA0_V1, R_AX_C2HREG_DATA1_V1, R_AX_C2HREG_DATA2_V1,
73 R_AX_C2HREG_DATA3_V1
74};
75
76static const u32 rtw8852c_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = {
77 R_AX_C2HREG_DATA3_V1 + 3, R_AX_DBG_WOW,
78};
79
80static const struct rtw89_page_regs rtw8852c_page_regs = {
81 .hci_fc_ctrl = R_AX_HCI_FC_CTRL_V1,
82 .ch_page_ctrl = R_AX_CH_PAGE_CTRL_V1,
83 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL_V1,
84 .ach_page_info = R_AX_ACH0_PAGE_INFO_V1,
85 .pub_page_info3 = R_AX_PUB_PAGE_INFO3_V1,
86 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1_V1,
87 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2_V1,
88 .pub_page_info1 = R_AX_PUB_PAGE_INFO1_V1,
89 .pub_page_info2 = R_AX_PUB_PAGE_INFO2_V1,
90 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1_V1,
91 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2_V1,
92 .wp_page_info1 = R_AX_WP_PAGE_INFO1_V1,
93};
94
95static const struct rtw89_reg_def rtw8852c_dcfo_comp = {
96 R_DCFO_COMP_S0_V1, B_DCFO_COMP_S0_V1_MSK
97};
98
99static const struct rtw89_imr_info rtw8852c_imr_info = {
100 .wdrls_imr_set = B_AX_WDRLS_IMR_SET_V1,
101 .wsec_imr_reg = R_AX_SEC_ERROR_FLAG_IMR,
102 .wsec_imr_set = B_AX_TX_HANG_IMR | B_AX_RX_HANG_IMR,
103 .mpdu_tx_imr_set = B_AX_MPDU_TX_IMR_SET_V1,
104 .mpdu_rx_imr_set = B_AX_MPDU_RX_IMR_SET_V1,
105 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET,
106 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_B0_ERRFLAG_IMR,
107 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR_V1,
108 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET_V1,
109 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_B1_ERRFLAG_IMR,
110 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR_V1,
111 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET_V1,
112 .wde_imr_clr = B_AX_WDE_IMR_CLR_V1,
113 .wde_imr_set = B_AX_WDE_IMR_SET_V1,
114 .ple_imr_clr = B_AX_PLE_IMR_CLR_V1,
115 .ple_imr_set = B_AX_PLE_IMR_SET_V1,
116 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR_V1,
117 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET_V1,
118 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR_V1,
119 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET_V1,
120 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR_V1,
121 .other_disp_imr_set = B_AX_OTHER_DISP_IMR_SET_V1,
122 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR,
123 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR,
124 .bbrpt_err_imr_set = R_AX_BBRPT_CHINFO_IMR_SET_V1,
125 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR,
126 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR_V1,
127 .ptcl_imr_set = B_AX_PTCL_IMR_SET_V1,
128 .cdma_imr_0_reg = R_AX_RX_ERR_FLAG_IMR,
129 .cdma_imr_0_clr = B_AX_RX_ERR_IMR_CLR_V1,
130 .cdma_imr_0_set = B_AX_RX_ERR_IMR_SET_V1,
131 .cdma_imr_1_reg = R_AX_TX_ERR_FLAG_IMR,
132 .cdma_imr_1_clr = B_AX_TX_ERR_IMR_CLR_V1,
133 .cdma_imr_1_set = B_AX_TX_ERR_IMR_SET_V1,
134 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR_V1,
135 .phy_intf_imr_clr = B_AX_PHYINFO_IMR_CLR_V1,
136 .phy_intf_imr_set = B_AX_PHYINFO_IMR_SET_V1,
137 .rmac_imr_reg = R_AX_RX_ERR_IMR,
138 .rmac_imr_clr = B_AX_RMAC_IMR_CLR_V1,
139 .rmac_imr_set = B_AX_RMAC_IMR_SET_V1,
140 .tmac_imr_reg = R_AX_TRXPTCL_ERROR_INDICA_MASK,
141 .tmac_imr_clr = B_AX_TMAC_IMR_CLR_V1,
142 .tmac_imr_set = B_AX_TMAC_IMR_SET_V1,
143};
144
145static const struct rtw89_rrsr_cfgs rtw8852c_rrsr_cfgs = {
146 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0},
147 .rsc = {R_AX_PTCL_RRSR1, B_AX_RSC_MASK, 2},
148};
149
150static const struct rtw89_rfkill_regs rtw8852c_rfkill_regs = {
151 .pinmux = {R_AX_GPIO8_15_FUNC_SEL,
152 B_AX_PINMUX_GPIO9_FUNC_SEL_MASK,
153 0xf},
154 .mode = {R_AX_GPIO_EXT_CTRL + 2,
155 (B_AX_GPIO_MOD_9 | B_AX_GPIO_IO_SEL_9) >> 16,
156 0x0},
157};
158
159static const struct rtw89_dig_regs rtw8852c_dig_regs = {
160 .seg0_pd_reg = R_SEG0R_PD,
161 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
162 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK,
163 .bmode_pd_reg = R_BMODE_PDTH_EN_V1,
164 .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1,
165 .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1,
166 .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1,
167 .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK},
168 .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK},
169 .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1},
170 .p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1},
171 .p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1},
172 .p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1},
173 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V1,
174 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
175 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V1,
176 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
177 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V1,
178 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
179 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V1,
180 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
181};
182
183static const struct rtw89_edcca_regs rtw8852c_edcca_regs = {
184 .edcca_level = R_SEG0R_EDCCA_LVL,
185 .edcca_mask = B_EDCCA_LVL_MSK0,
186 .edcca_p_mask = B_EDCCA_LVL_MSK1,
187 .ppdu_level = R_SEG0R_EDCCA_LVL,
188 .ppdu_mask = B_EDCCA_LVL_MSK3,
189 .rpt_a = R_EDCCA_RPT_A,
190 .rpt_b = R_EDCCA_RPT_B,
191 .rpt_sel = R_EDCCA_RPT_SEL,
192 .rpt_sel_mask = B_EDCCA_RPT_SEL_MSK,
193 .tx_collision_t2r_st = R_TX_COLLISION_T2R_ST,
194 .tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M,
195};
196
197static void rtw8852c_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en,
198 enum rtw89_phy_idx phy_idx);
199
200static void rtw8852c_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev, u8 tx_path,
201 enum rtw89_mac_idx mac_idx);
202
203static int rtw8852c_pwr_on_func(struct rtw89_dev *rtwdev)
204{
205 u32 val32;
206 int ret;
207
208 val32 = rtw89_read32_mask(rtwdev, R_AX_SYS_STATUS1, B_AX_PAD_HCI_SEL_V2_MASK);
209 if (val32 == MAC_AX_HCI_SEL_PCIE_USB)
210 rtw89_write32_set(rtwdev, R_AX_LDO_AON_CTRL0, B_AX_PD_REGU_L);
211
212 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN |
213 B_AX_AFSM_PCIE_SUS_EN);
214 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC);
215 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC);
216 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN);
217 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
218
219 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0,
220 B_AX_OCP_L1_MASK, 0x7);
221
222 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR,
223 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
224 if (ret)
225 return ret;
226
227 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
228 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC);
229
230 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC),
231 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
232 if (ret)
233 return ret;
234
235 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
236 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
237 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
238 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
239
240 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
241 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1);
242
243 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_CMAC1_FEN);
244 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_R_SYM_ISO_CMAC12PP);
245 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, B_AX_R_SYM_WLCMAC1_P4_PC_EN |
246 B_AX_R_SYM_WLCMAC1_P3_PC_EN |
247 B_AX_R_SYM_WLCMAC1_P2_PC_EN |
248 B_AX_R_SYM_WLCMAC1_P1_PC_EN |
249 B_AX_R_SYM_WLCMAC1_PC_EN);
250 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3);
251
252 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL,
253 XTAL_SI_GND_SHDN_WL, XTAL_SI_GND_SHDN_WL);
254 if (ret)
255 return ret;
256
257 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3);
258
259 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL,
260 XTAL_SI_SHDN_WL, XTAL_SI_SHDN_WL);
261 if (ret)
262 return ret;
263 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI,
264 XTAL_SI_OFF_WEI);
265 if (ret)
266 return ret;
267 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI,
268 XTAL_SI_OFF_EI);
269 if (ret)
270 return ret;
271 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF);
272 if (ret)
273 return ret;
274 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI,
275 XTAL_SI_PON_WEI);
276 if (ret)
277 return ret;
278 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI,
279 XTAL_SI_PON_EI);
280 if (ret)
281 return ret;
282 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC);
283 if (ret)
284 return ret;
285 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0x10, XTAL_SI_LDO_LPS);
286 if (ret)
287 return ret;
288 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP);
289 if (ret)
290 return ret;
291
292 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
293 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE);
294 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15);
295
296 fsleep(1000);
297
298 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14);
299 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
300 rtw89_write32_set(rtwdev, R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN,
301 B_AX_EECS_PULL_LOW_EN | B_AX_EESK_PULL_LOW_EN |
302 B_AX_LED1_PULL_LOW_EN);
303
304 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN,
305 B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN |
306 B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN |
307 B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN |
308 B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN |
309 B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN |
310 B_AX_MAC_UN_EN | B_AX_H_AXIDMA_EN);
311
312 rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN,
313 B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN |
314 B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN |
315 B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN |
316 B_AX_TMAC_EN | B_AX_RMAC_EN);
317
318 rtw89_write32_mask(rtwdev, R_AX_LED1_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_V1_MASK,
319 PINMUX_EESK_FUNC_SEL_BT_LOG);
320
321 return 0;
322}
323
324static int rtw8852c_pwr_off_func(struct rtw89_dev *rtwdev)
325{
326 u32 val32;
327 int ret;
328
329 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF,
330 XTAL_SI_RFC2RF);
331 if (ret)
332 return ret;
333 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI);
334 if (ret)
335 return ret;
336 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI);
337 if (ret)
338 return ret;
339 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00);
340 if (ret)
341 return ret;
342 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0, XTAL_SI_RF10);
343 if (ret)
344 return ret;
345 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC,
346 XTAL_SI_SRAM2RFC);
347 if (ret)
348 return ret;
349 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI);
350 if (ret)
351 return ret;
352 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI);
353 if (ret)
354 return ret;
355
356 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
357 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
358 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB);
359 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
360 B_AX_R_SYM_FEN_WLBBGLB_1 | B_AX_R_SYM_FEN_WLBBFUN_1);
361 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3);
362
363 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SHDN_WL);
364 if (ret)
365 return ret;
366
367 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3);
368
369 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_GND_SHDN_WL);
370 if (ret)
371 return ret;
372
373 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC);
374
375 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC),
376 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
377 if (ret)
378 return ret;
379
380 rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION);
381 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_XTAL_OFF_A_DIE);
382 rtw89_write32_set(rtwdev, R_AX_SYS_SWR_CTRL1, B_AX_SYM_CTRL_SPS_PWMFREQ);
383 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0,
384 B_AX_REG_ZCDC_H_MASK, 0x3);
385 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
386
387 return 0;
388}
389
390static void rtw8852c_e_efuse_parsing(struct rtw89_efuse *efuse,
391 struct rtw8852c_efuse *map)
392{
393 ether_addr_copy(efuse->addr, map->e.mac_addr);
394 efuse->rfe_type = map->rfe_type;
395 efuse->xtal_cap = map->xtal_k;
396}
397
398static void rtw8852c_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
399 struct rtw8852c_efuse *map)
400{
401 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
402 struct rtw8852c_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi};
403 u8 *bw40_1s_tssi_6g_ofst[] = {map->bw40_1s_tssi_6g_a, map->bw40_1s_tssi_6g_b};
404 u8 i, j;
405
406 tssi->thermal[RF_PATH_A] = map->path_a_therm;
407 tssi->thermal[RF_PATH_B] = map->path_b_therm;
408
409 for (i = 0; i < RF_PATH_NUM_8852C; i++) {
410 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi,
411 sizeof(ofst[i]->cck_tssi));
412
413 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++)
414 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
415 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n",
416 i, j, tssi->tssi_cck[i][j]);
417
418 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi,
419 sizeof(ofst[i]->bw40_tssi));
420 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM,
421 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g));
422 memcpy(tssi->tssi_6g_mcs[i], bw40_1s_tssi_6g_ofst[i],
423 sizeof(tssi->tssi_6g_mcs[i]));
424
425 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++)
426 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
427 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n",
428 i, j, tssi->tssi_mcs[i][j]);
429 }
430}
431
432static bool _decode_efuse_gain(u8 data, s8 *high, s8 *low)
433{
434 if (high)
435 *high = sign_extend32(FIELD_GET(GENMASK(7, 4), data), 3);
436 if (low)
437 *low = sign_extend32(FIELD_GET(GENMASK(3, 0), data), 3);
438
439 return data != 0xff;
440}
441
442static void rtw8852c_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev,
443 struct rtw8852c_efuse *map)
444{
445 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
446 bool valid = false;
447
448 valid |= _decode_efuse_gain(map->rx_gain_2g_cck,
449 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK],
450 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_CCK]);
451 valid |= _decode_efuse_gain(map->rx_gain_2g_ofdm,
452 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM],
453 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_OFDM]);
454 valid |= _decode_efuse_gain(map->rx_gain_5g_low,
455 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW],
456 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_LOW]);
457 valid |= _decode_efuse_gain(map->rx_gain_5g_mid,
458 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID],
459 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_MID]);
460 valid |= _decode_efuse_gain(map->rx_gain_5g_high,
461 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH],
462 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_HIGH]);
463 valid |= _decode_efuse_gain(map->rx_gain_6g_l0,
464 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_L0],
465 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_L0]);
466 valid |= _decode_efuse_gain(map->rx_gain_6g_l1,
467 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_L1],
468 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_L1]);
469 valid |= _decode_efuse_gain(map->rx_gain_6g_m0,
470 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_M0],
471 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_M0]);
472 valid |= _decode_efuse_gain(map->rx_gain_6g_m1,
473 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_M1],
474 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_M1]);
475 valid |= _decode_efuse_gain(map->rx_gain_6g_h0,
476 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_H0],
477 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_H0]);
478 valid |= _decode_efuse_gain(map->rx_gain_6g_h1,
479 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_H1],
480 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_H1]);
481 valid |= _decode_efuse_gain(map->rx_gain_6g_uh0,
482 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_UH0],
483 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_UH0]);
484 valid |= _decode_efuse_gain(map->rx_gain_6g_uh1,
485 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_UH1],
486 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_UH1]);
487
488 gain->offset_valid = valid;
489}
490
491static int rtw8852c_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map,
492 enum rtw89_efuse_block block)
493{
494 struct rtw89_efuse *efuse = &rtwdev->efuse;
495 struct rtw8852c_efuse *map;
496
497 map = (struct rtw8852c_efuse *)log_map;
498
499 efuse->country_code[0] = map->country_code[0];
500 efuse->country_code[1] = map->country_code[1];
501 rtw8852c_efuse_parsing_tssi(rtwdev, map);
502 rtw8852c_efuse_parsing_gain_offset(rtwdev, map);
503
504 switch (rtwdev->hci.type) {
505 case RTW89_HCI_TYPE_PCIE:
506 rtw8852c_e_efuse_parsing(efuse, map);
507 break;
508 default:
509 return -ENOTSUPP;
510 }
511
512 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
513
514 return 0;
515}
516
517static void rtw8852c_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map)
518{
519 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
520 static const u32 tssi_trim_addr[RF_PATH_NUM_8852C] = {0x5D6, 0x5AB};
521 static const u32 tssi_trim_addr_6g[RF_PATH_NUM_8852C] = {0x5CE, 0x5A3};
522 u32 addr = rtwdev->chip->phycap_addr;
523 bool pg = false;
524 u32 ofst;
525 u8 i, j;
526
527 for (i = 0; i < RF_PATH_NUM_8852C; i++) {
528 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) {
529 /* addrs are in decreasing order */
530 ofst = tssi_trim_addr[i] - addr - j;
531 tssi->tssi_trim[i][j] = phycap_map[ofst];
532
533 if (phycap_map[ofst] != 0xff)
534 pg = true;
535 }
536
537 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM_6G; j++) {
538 /* addrs are in decreasing order */
539 ofst = tssi_trim_addr_6g[i] - addr - j;
540 tssi->tssi_trim_6g[i][j] = phycap_map[ofst];
541
542 if (phycap_map[ofst] != 0xff)
543 pg = true;
544 }
545 }
546
547 if (!pg) {
548 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim));
549 memset(tssi->tssi_trim_6g, 0, sizeof(tssi->tssi_trim_6g));
550 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
551 "[TSSI][TRIM] no PG, set all trim info to 0\n");
552 }
553
554 for (i = 0; i < RF_PATH_NUM_8852C; i++)
555 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++)
556 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
557 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n",
558 i, j, tssi->tssi_trim[i][j],
559 tssi_trim_addr[i] - j);
560}
561
562static void rtw8852c_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
563 u8 *phycap_map)
564{
565 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
566 static const u32 thm_trim_addr[RF_PATH_NUM_8852C] = {0x5DF, 0x5DC};
567 u32 addr = rtwdev->chip->phycap_addr;
568 u8 i;
569
570 for (i = 0; i < RF_PATH_NUM_8852C; i++) {
571 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr];
572
573 rtw89_debug(rtwdev, RTW89_DBG_RFK,
574 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n",
575 i, info->thermal_trim[i]);
576
577 if (info->thermal_trim[i] != 0xff)
578 info->pg_thermal_trim = true;
579 }
580}
581
582static void rtw8852c_thermal_trim(struct rtw89_dev *rtwdev)
583{
584#define __thm_setting(raw) \
585({ \
586 u8 __v = (raw); \
587 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \
588})
589 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
590 u8 i, val;
591
592 if (!info->pg_thermal_trim) {
593 rtw89_debug(rtwdev, RTW89_DBG_RFK,
594 "[THERMAL][TRIM] no PG, do nothing\n");
595
596 return;
597 }
598
599 for (i = 0; i < RF_PATH_NUM_8852C; i++) {
600 val = __thm_setting(info->thermal_trim[i]);
601 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val);
602
603 rtw89_debug(rtwdev, RTW89_DBG_RFK,
604 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n",
605 i, val);
606 }
607#undef __thm_setting
608}
609
610static void rtw8852c_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
611 u8 *phycap_map)
612{
613 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
614 static const u32 pabias_trim_addr[RF_PATH_NUM_8852C] = {0x5DE, 0x5DB};
615 u32 addr = rtwdev->chip->phycap_addr;
616 u8 i;
617
618 for (i = 0; i < RF_PATH_NUM_8852C; i++) {
619 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr];
620
621 rtw89_debug(rtwdev, RTW89_DBG_RFK,
622 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n",
623 i, info->pa_bias_trim[i]);
624
625 if (info->pa_bias_trim[i] != 0xff)
626 info->pg_pa_bias_trim = true;
627 }
628}
629
630static void rtw8852c_pa_bias_trim(struct rtw89_dev *rtwdev)
631{
632 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
633 u8 pabias_2g, pabias_5g;
634 u8 i;
635
636 if (!info->pg_pa_bias_trim) {
637 rtw89_debug(rtwdev, RTW89_DBG_RFK,
638 "[PA_BIAS][TRIM] no PG, do nothing\n");
639
640 return;
641 }
642
643 for (i = 0; i < RF_PATH_NUM_8852C; i++) {
644 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]);
645 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]);
646
647 rtw89_debug(rtwdev, RTW89_DBG_RFK,
648 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
649 i, pabias_2g, pabias_5g);
650
651 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g);
652 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g);
653 }
654}
655
656static int rtw8852c_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
657{
658 rtw8852c_phycap_parsing_tssi(rtwdev, phycap_map);
659 rtw8852c_phycap_parsing_thermal_trim(rtwdev, phycap_map);
660 rtw8852c_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
661
662 return 0;
663}
664
665static void rtw8852c_power_trim(struct rtw89_dev *rtwdev)
666{
667 rtw8852c_thermal_trim(rtwdev);
668 rtw8852c_pa_bias_trim(rtwdev);
669}
670
671static void rtw8852c_set_channel_mac(struct rtw89_dev *rtwdev,
672 const struct rtw89_chan *chan,
673 u8 mac_idx)
674{
675 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx);
676 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx);
677 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx);
678 u8 txsc20 = 0, txsc40 = 0, txsc80 = 0;
679 u8 rf_mod_val = 0, chk_rate_mask = 0;
680 u32 txsc;
681
682 switch (chan->band_width) {
683 case RTW89_CHANNEL_WIDTH_160:
684 txsc80 = rtw89_phy_get_txsc(rtwdev, chan,
685 RTW89_CHANNEL_WIDTH_80);
686 fallthrough;
687 case RTW89_CHANNEL_WIDTH_80:
688 txsc40 = rtw89_phy_get_txsc(rtwdev, chan,
689 RTW89_CHANNEL_WIDTH_40);
690 fallthrough;
691 case RTW89_CHANNEL_WIDTH_40:
692 txsc20 = rtw89_phy_get_txsc(rtwdev, chan,
693 RTW89_CHANNEL_WIDTH_20);
694 break;
695 default:
696 break;
697 }
698
699 switch (chan->band_width) {
700 case RTW89_CHANNEL_WIDTH_160:
701 rf_mod_val = AX_WMAC_RFMOD_160M;
702 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20) |
703 FIELD_PREP(B_AX_TXSC_40M_MASK, txsc40) |
704 FIELD_PREP(B_AX_TXSC_80M_MASK, txsc80);
705 break;
706 case RTW89_CHANNEL_WIDTH_80:
707 rf_mod_val = AX_WMAC_RFMOD_80M;
708 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20) |
709 FIELD_PREP(B_AX_TXSC_40M_MASK, txsc40);
710 break;
711 case RTW89_CHANNEL_WIDTH_40:
712 rf_mod_val = AX_WMAC_RFMOD_40M;
713 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20);
714 break;
715 case RTW89_CHANNEL_WIDTH_20:
716 default:
717 rf_mod_val = AX_WMAC_RFMOD_20M;
718 txsc = 0;
719 break;
720 }
721 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, rf_mod_val);
722 rtw89_write32(rtwdev, sub_carr, txsc);
723
724 switch (chan->band_type) {
725 case RTW89_BAND_2G:
726 chk_rate_mask = B_AX_BAND_MODE;
727 break;
728 case RTW89_BAND_5G:
729 case RTW89_BAND_6G:
730 chk_rate_mask = B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6;
731 break;
732 default:
733 rtw89_warn(rtwdev, "Invalid band_type:%d\n", chan->band_type);
734 return;
735 }
736 rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE | B_AX_CHECK_CCK_EN |
737 B_AX_RTS_LIMIT_IN_OFDM6);
738 rtw89_write8_set(rtwdev, chk_rate, chk_rate_mask);
739}
740
741static const u32 rtw8852c_sco_barker_threshold[14] = {
742 0x1fe4f, 0x1ff5e, 0x2006c, 0x2017b, 0x2028a, 0x20399, 0x204a8, 0x205b6,
743 0x206c5, 0x207d4, 0x208e3, 0x209f2, 0x20b00, 0x20d8a
744};
745
746static const u32 rtw8852c_sco_cck_threshold[14] = {
747 0x2bdac, 0x2bf21, 0x2c095, 0x2c209, 0x2c37e, 0x2c4f2, 0x2c666, 0x2c7db,
748 0x2c94f, 0x2cac3, 0x2cc38, 0x2cdac, 0x2cf21, 0x2d29e
749};
750
751static int rtw8852c_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch,
752 u8 primary_ch, enum rtw89_bandwidth bw)
753{
754 u8 ch_element;
755
756 if (bw == RTW89_CHANNEL_WIDTH_20) {
757 ch_element = central_ch - 1;
758 } else if (bw == RTW89_CHANNEL_WIDTH_40) {
759 if (primary_ch == 1)
760 ch_element = central_ch - 1 + 2;
761 else
762 ch_element = central_ch - 1 - 2;
763 } else {
764 rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw);
765 return -EINVAL;
766 }
767 rtw89_phy_write32_mask(rtwdev, R_BK_FC0_INV_V1, B_BK_FC0_INV_MSK_V1,
768 rtw8852c_sco_barker_threshold[ch_element]);
769 rtw89_phy_write32_mask(rtwdev, R_CCK_FC0_INV_V1, B_CCK_FC0_INV_MSK_V1,
770 rtw8852c_sco_cck_threshold[ch_element]);
771
772 return 0;
773}
774
775struct rtw8852c_bb_gain {
776 u32 gain_g[BB_PATH_NUM_8852C];
777 u32 gain_a[BB_PATH_NUM_8852C];
778 u32 gain_mask;
779};
780
781static const struct rtw8852c_bb_gain bb_gain_lna[LNA_GAIN_NUM] = {
782 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740},
783 .gain_mask = 0x00ff0000 },
784 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740},
785 .gain_mask = 0xff000000 },
786 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
787 .gain_mask = 0x000000ff },
788 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
789 .gain_mask = 0x0000ff00 },
790 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
791 .gain_mask = 0x00ff0000 },
792 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
793 .gain_mask = 0xff000000 },
794 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748},
795 .gain_mask = 0x000000ff },
796};
797
798static const struct rtw8852c_bb_gain bb_gain_tia[TIA_GAIN_NUM] = {
799 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748},
800 .gain_mask = 0x00ff0000 },
801 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748},
802 .gain_mask = 0xff000000 },
803};
804
805struct rtw8852c_bb_gain_bypass {
806 u32 gain_g[BB_PATH_NUM_8852C];
807 u32 gain_a[BB_PATH_NUM_8852C];
808 u32 gain_mask_g;
809 u32 gain_mask_a;
810};
811
812static
813const struct rtw8852c_bb_gain_bypass bb_gain_bypass_lna[LNA_GAIN_NUM] = {
814 { .gain_g = {0x4BB8, 0x4C7C}, .gain_a = {0x4BB4, 0x4C78},
815 .gain_mask_g = 0xff000000, .gain_mask_a = 0xff},
816 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78},
817 .gain_mask_g = 0xff, .gain_mask_a = 0xff00},
818 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78},
819 .gain_mask_g = 0xff00, .gain_mask_a = 0xff0000},
820 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78},
821 .gain_mask_g = 0xff0000, .gain_mask_a = 0xff000000},
822 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB8, 0x4C7C},
823 .gain_mask_g = 0xff000000, .gain_mask_a = 0xff},
824 { .gain_g = {0x4BC0, 0x4C84}, .gain_a = {0x4BB8, 0x4C7C},
825 .gain_mask_g = 0xff, .gain_mask_a = 0xff00},
826 { .gain_g = {0x4BC0, 0x4C84}, .gain_a = {0x4BB8, 0x4C7C},
827 .gain_mask_g = 0xff00, .gain_mask_a = 0xff0000},
828};
829
830struct rtw8852c_bb_gain_op1db {
831 struct {
832 u32 lna[BB_PATH_NUM_8852C];
833 u32 tia_lna[BB_PATH_NUM_8852C];
834 u32 mask;
835 } reg[LNA_GAIN_NUM];
836 u32 reg_tia0_lna6[BB_PATH_NUM_8852C];
837 u32 mask_tia0_lna6;
838};
839
840static const struct rtw8852c_bb_gain_op1db bb_gain_op1db_a = {
841 .reg = {
842 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754},
843 .mask = 0xff},
844 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754},
845 .mask = 0xff00},
846 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754},
847 .mask = 0xff0000},
848 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754},
849 .mask = 0xff000000},
850 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758},
851 .mask = 0xff},
852 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758},
853 .mask = 0xff00},
854 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758},
855 .mask = 0xff0000},
856 },
857 .reg_tia0_lna6 = {0x4674, 0x4758},
858 .mask_tia0_lna6 = 0xff000000,
859};
860
861static void rtw8852c_set_gain_error(struct rtw89_dev *rtwdev,
862 enum rtw89_subband subband,
863 enum rtw89_rf_path path)
864{
865 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
866 u8 gain_band = rtw89_subband_to_bb_gain_band(subband);
867 s32 val;
868 u32 reg;
869 u32 mask;
870 int i;
871
872 for (i = 0; i < LNA_GAIN_NUM; i++) {
873 if (subband == RTW89_CH_2G)
874 reg = bb_gain_lna[i].gain_g[path];
875 else
876 reg = bb_gain_lna[i].gain_a[path];
877
878 mask = bb_gain_lna[i].gain_mask;
879 val = gain->lna_gain[gain_band][path][i];
880 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
881
882 if (subband == RTW89_CH_2G) {
883 reg = bb_gain_bypass_lna[i].gain_g[path];
884 mask = bb_gain_bypass_lna[i].gain_mask_g;
885 } else {
886 reg = bb_gain_bypass_lna[i].gain_a[path];
887 mask = bb_gain_bypass_lna[i].gain_mask_a;
888 }
889
890 val = gain->lna_gain_bypass[gain_band][path][i];
891 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
892
893 if (subband != RTW89_CH_2G) {
894 reg = bb_gain_op1db_a.reg[i].lna[path];
895 mask = bb_gain_op1db_a.reg[i].mask;
896 val = gain->lna_op1db[gain_band][path][i];
897 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
898
899 reg = bb_gain_op1db_a.reg[i].tia_lna[path];
900 mask = bb_gain_op1db_a.reg[i].mask;
901 val = gain->tia_lna_op1db[gain_band][path][i];
902 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
903 }
904 }
905
906 if (subband != RTW89_CH_2G) {
907 reg = bb_gain_op1db_a.reg_tia0_lna6[path];
908 mask = bb_gain_op1db_a.mask_tia0_lna6;
909 val = gain->tia_lna_op1db[gain_band][path][7];
910 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
911 }
912
913 for (i = 0; i < TIA_GAIN_NUM; i++) {
914 if (subband == RTW89_CH_2G)
915 reg = bb_gain_tia[i].gain_g[path];
916 else
917 reg = bb_gain_tia[i].gain_a[path];
918
919 mask = bb_gain_tia[i].gain_mask;
920 val = gain->tia_gain[gain_band][path][i];
921 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
922 }
923}
924
925static void rtw8852c_set_gain_offset(struct rtw89_dev *rtwdev,
926 const struct rtw89_chan *chan,
927 enum rtw89_phy_idx phy_idx,
928 enum rtw89_rf_path path)
929{
930 static const u32 rssi_ofst_addr[2] = {R_PATH0_G_TIA0_LNA6_OP1DB_V1,
931 R_PATH1_G_TIA0_LNA6_OP1DB_V1};
932 static const u32 rpl_mask[2] = {B_RPL_PATHA_MASK, B_RPL_PATHB_MASK};
933 static const u32 rpl_tb_mask[2] = {B_RSSI_M_PATHA_MASK, B_RSSI_M_PATHB_MASK};
934 struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain;
935 enum rtw89_gain_offset gain_band;
936 s32 offset_q0, offset_base_q4;
937 s32 tmp = 0;
938
939 if (!efuse_gain->offset_valid)
940 return;
941
942 if (rtwdev->dbcc_en && path == RF_PATH_B)
943 phy_idx = RTW89_PHY_1;
944
945 if (chan->band_type == RTW89_BAND_2G) {
946 offset_q0 = efuse_gain->offset[path][RTW89_GAIN_OFFSET_2G_CCK];
947 offset_base_q4 = efuse_gain->offset_base[phy_idx];
948
949 tmp = clamp_t(s32, (-offset_q0 << 3) + (offset_base_q4 >> 1),
950 S8_MIN >> 1, S8_MAX >> 1);
951 rtw89_phy_write32_mask(rtwdev, R_RPL_OFST, B_RPL_OFST_MASK, tmp & 0x7f);
952 }
953
954 gain_band = rtw89_subband_to_gain_offset_band_of_ofdm(chan->subband_type);
955
956 offset_q0 = -efuse_gain->offset[path][gain_band];
957 offset_base_q4 = efuse_gain->offset_base[phy_idx];
958
959 tmp = (offset_q0 << 2) + (offset_base_q4 >> 2);
960 tmp = clamp_t(s32, -tmp, S8_MIN, S8_MAX);
961 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[path], B_PATH0_R_G_OFST_MASK, tmp & 0xff);
962
963 tmp = clamp_t(s32, offset_q0 << 4, S8_MIN, S8_MAX);
964 rtw89_phy_write32_idx(rtwdev, R_RPL_PATHAB, rpl_mask[path], tmp & 0xff, phy_idx);
965 rtw89_phy_write32_idx(rtwdev, R_RSSI_M_PATHAB, rpl_tb_mask[path], tmp & 0xff, phy_idx);
966}
967
968static void rtw8852c_ctrl_ch(struct rtw89_dev *rtwdev,
969 const struct rtw89_chan *chan,
970 enum rtw89_phy_idx phy_idx)
971{
972 u8 sco;
973 u16 central_freq = chan->freq;
974 u8 central_ch = chan->channel;
975 u8 band = chan->band_type;
976 u8 subband = chan->subband_type;
977 bool is_2g = band == RTW89_BAND_2G;
978 u8 chan_idx;
979
980 if (!central_freq) {
981 rtw89_warn(rtwdev, "Invalid central_freq\n");
982 return;
983 }
984
985 if (phy_idx == RTW89_PHY_0) {
986 /* Path A */
987 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_A);
988 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_A);
989
990 if (is_2g)
991 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
992 B_PATH0_BAND_SEL_MSK_V1, 1,
993 phy_idx);
994 else
995 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
996 B_PATH0_BAND_SEL_MSK_V1, 0,
997 phy_idx);
998 /* Path B */
999 if (!rtwdev->dbcc_en) {
1000 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_B);
1001 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_B);
1002
1003 if (is_2g)
1004 rtw89_phy_write32_idx(rtwdev,
1005 R_PATH1_BAND_SEL_V1,
1006 B_PATH1_BAND_SEL_MSK_V1,
1007 1, phy_idx);
1008 else
1009 rtw89_phy_write32_idx(rtwdev,
1010 R_PATH1_BAND_SEL_V1,
1011 B_PATH1_BAND_SEL_MSK_V1,
1012 0, phy_idx);
1013 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL);
1014 } else {
1015 if (is_2g)
1016 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL);
1017 else
1018 rtw89_phy_write32_set(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL);
1019 }
1020 /* SCO compensate FC setting */
1021 rtw89_phy_write32_idx(rtwdev, R_FC0_V1, B_FC0_MSK_V1,
1022 central_freq, phy_idx);
1023 /* round_up((1/fc0)*pow(2,18)) */
1024 sco = DIV_ROUND_CLOSEST(1 << 18, central_freq);
1025 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, sco,
1026 phy_idx);
1027 } else {
1028 /* Path B */
1029 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_B);
1030 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_B);
1031
1032 if (is_2g)
1033 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1,
1034 B_PATH1_BAND_SEL_MSK_V1,
1035 1, phy_idx);
1036 else
1037 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1,
1038 B_PATH1_BAND_SEL_MSK_V1,
1039 0, phy_idx);
1040 /* SCO compensate FC setting */
1041 rtw89_phy_write32_idx(rtwdev, R_FC0_V1, B_FC0_MSK_V1,
1042 central_freq, phy_idx);
1043 /* round_up((1/fc0)*pow(2,18)) */
1044 sco = DIV_ROUND_CLOSEST(1 << 18, central_freq);
1045 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, sco,
1046 phy_idx);
1047 }
1048 /* CCK parameters */
1049 if (band == RTW89_BAND_2G) {
1050 if (central_ch == 14) {
1051 rtw89_phy_write32_mask(rtwdev, R_PCOEFF0_V1,
1052 B_PCOEFF01_MSK_V1, 0x3b13ff);
1053 rtw89_phy_write32_mask(rtwdev, R_PCOEFF2_V1,
1054 B_PCOEFF23_MSK_V1, 0x1c42de);
1055 rtw89_phy_write32_mask(rtwdev, R_PCOEFF4_V1,
1056 B_PCOEFF45_MSK_V1, 0xfdb0ad);
1057 rtw89_phy_write32_mask(rtwdev, R_PCOEFF6_V1,
1058 B_PCOEFF67_MSK_V1, 0xf60f6e);
1059 rtw89_phy_write32_mask(rtwdev, R_PCOEFF8_V1,
1060 B_PCOEFF89_MSK_V1, 0xfd8f92);
1061 rtw89_phy_write32_mask(rtwdev, R_PCOEFFA_V1,
1062 B_PCOEFFAB_MSK_V1, 0x2d011);
1063 rtw89_phy_write32_mask(rtwdev, R_PCOEFFC_V1,
1064 B_PCOEFFCD_MSK_V1, 0x1c02c);
1065 rtw89_phy_write32_mask(rtwdev, R_PCOEFFE_V1,
1066 B_PCOEFFEF_MSK_V1, 0xfff00a);
1067 } else {
1068 rtw89_phy_write32_mask(rtwdev, R_PCOEFF0_V1,
1069 B_PCOEFF01_MSK_V1, 0x3d23ff);
1070 rtw89_phy_write32_mask(rtwdev, R_PCOEFF2_V1,
1071 B_PCOEFF23_MSK_V1, 0x29b354);
1072 rtw89_phy_write32_mask(rtwdev, R_PCOEFF4_V1,
1073 B_PCOEFF45_MSK_V1, 0xfc1c8);
1074 rtw89_phy_write32_mask(rtwdev, R_PCOEFF6_V1,
1075 B_PCOEFF67_MSK_V1, 0xfdb053);
1076 rtw89_phy_write32_mask(rtwdev, R_PCOEFF8_V1,
1077 B_PCOEFF89_MSK_V1, 0xf86f9a);
1078 rtw89_phy_write32_mask(rtwdev, R_PCOEFFA_V1,
1079 B_PCOEFFAB_MSK_V1, 0xfaef92);
1080 rtw89_phy_write32_mask(rtwdev, R_PCOEFFC_V1,
1081 B_PCOEFFCD_MSK_V1, 0xfe5fcc);
1082 rtw89_phy_write32_mask(rtwdev, R_PCOEFFE_V1,
1083 B_PCOEFFEF_MSK_V1, 0xffdff5);
1084 }
1085 }
1086
1087 chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band);
1088 rtw89_phy_write32_idx(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx, phy_idx);
1089}
1090
1091static void rtw8852c_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path)
1092{
1093 static const u32 adc_sel[2] = {0xC0EC, 0xC1EC};
1094 static const u32 wbadc_sel[2] = {0xC0E4, 0xC1E4};
1095
1096 switch (bw) {
1097 case RTW89_CHANNEL_WIDTH_5:
1098 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1);
1099 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0);
1100 break;
1101 case RTW89_CHANNEL_WIDTH_10:
1102 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2);
1103 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1);
1104 break;
1105 case RTW89_CHANNEL_WIDTH_20:
1106 case RTW89_CHANNEL_WIDTH_40:
1107 case RTW89_CHANNEL_WIDTH_80:
1108 case RTW89_CHANNEL_WIDTH_160:
1109 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
1110 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
1111 break;
1112 default:
1113 rtw89_warn(rtwdev, "Fail to set ADC\n");
1114 }
1115}
1116
1117static void rtw8852c_edcca_per20_bitmap_sifs(struct rtw89_dev *rtwdev, u8 bw,
1118 enum rtw89_phy_idx phy_idx)
1119{
1120 if (bw == RTW89_CHANNEL_WIDTH_20) {
1121 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A1, B_SNDCCA_A1_EN, 0xff, phy_idx);
1122 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A2, B_SNDCCA_A2_VAL, 0, phy_idx);
1123 } else {
1124 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A1, B_SNDCCA_A1_EN, 0, phy_idx);
1125 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A2, B_SNDCCA_A2_VAL, 0, phy_idx);
1126 }
1127}
1128
1129static void
1130rtw8852c_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw,
1131 enum rtw89_phy_idx phy_idx)
1132{
1133 u8 mod_sbw = 0;
1134
1135 switch (bw) {
1136 case RTW89_CHANNEL_WIDTH_5:
1137 case RTW89_CHANNEL_WIDTH_10:
1138 case RTW89_CHANNEL_WIDTH_20:
1139 if (bw == RTW89_CHANNEL_WIDTH_5)
1140 mod_sbw = 0x1;
1141 else if (bw == RTW89_CHANNEL_WIDTH_10)
1142 mod_sbw = 0x2;
1143 else if (bw == RTW89_CHANNEL_WIDTH_20)
1144 mod_sbw = 0x0;
1145 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0,
1146 phy_idx);
1147 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW,
1148 mod_sbw, phy_idx);
1149 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 0x0,
1150 phy_idx);
1151 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1,
1152 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x3);
1153 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1,
1154 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x3);
1155 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1,
1156 B_PATH0_BW_SEL_MSK_V1, 0xf);
1157 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1,
1158 B_PATH1_BW_SEL_MSK_V1, 0xf);
1159 break;
1160 case RTW89_CHANNEL_WIDTH_40:
1161 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1,
1162 phy_idx);
1163 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
1164 phy_idx);
1165 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1166 pri_ch,
1167 phy_idx);
1168 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1,
1169 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x3);
1170 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1,
1171 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x3);
1172 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1,
1173 B_PATH0_BW_SEL_MSK_V1, 0xf);
1174 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1,
1175 B_PATH1_BW_SEL_MSK_V1, 0xf);
1176 break;
1177 case RTW89_CHANNEL_WIDTH_80:
1178 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2,
1179 phy_idx);
1180 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
1181 phy_idx);
1182 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1183 pri_ch,
1184 phy_idx);
1185 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1,
1186 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x2);
1187 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1,
1188 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x2);
1189 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1,
1190 B_PATH0_BW_SEL_MSK_V1, 0xd);
1191 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1,
1192 B_PATH1_BW_SEL_MSK_V1, 0xd);
1193 break;
1194 case RTW89_CHANNEL_WIDTH_160:
1195 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x3,
1196 phy_idx);
1197 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
1198 phy_idx);
1199 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1200 pri_ch,
1201 phy_idx);
1202 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1,
1203 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x1);
1204 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1,
1205 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x1);
1206 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1,
1207 B_PATH0_BW_SEL_MSK_V1, 0xb);
1208 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1,
1209 B_PATH1_BW_SEL_MSK_V1, 0xb);
1210 break;
1211 default:
1212 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw,
1213 pri_ch);
1214 }
1215
1216 if (bw == RTW89_CHANNEL_WIDTH_40) {
1217 rtw89_phy_write32_idx(rtwdev, R_RX_BW40_2XFFT_EN_V1,
1218 B_RX_BW40_2XFFT_EN_MSK_V1, 0x1, phy_idx);
1219 rtw89_phy_write32_idx(rtwdev, R_T2F_GI_COMB, B_T2F_GI_COMB_EN, 1, phy_idx);
1220 } else {
1221 rtw89_phy_write32_idx(rtwdev, R_RX_BW40_2XFFT_EN_V1,
1222 B_RX_BW40_2XFFT_EN_MSK_V1, 0x0, phy_idx);
1223 rtw89_phy_write32_idx(rtwdev, R_T2F_GI_COMB, B_T2F_GI_COMB_EN, 0, phy_idx);
1224 }
1225
1226 if (phy_idx == RTW89_PHY_0) {
1227 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_A);
1228 if (!rtwdev->dbcc_en)
1229 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_B);
1230 } else {
1231 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_B);
1232 }
1233
1234 rtw8852c_edcca_per20_bitmap_sifs(rtwdev, bw, phy_idx);
1235}
1236
1237static u32 rtw8852c_spur_freq(struct rtw89_dev *rtwdev,
1238 const struct rtw89_chan *chan)
1239{
1240 u8 center_chan = chan->channel;
1241 u8 bw = chan->band_width;
1242
1243 switch (chan->band_type) {
1244 case RTW89_BAND_2G:
1245 if (bw == RTW89_CHANNEL_WIDTH_20) {
1246 if (center_chan >= 5 && center_chan <= 8)
1247 return 2440;
1248 if (center_chan == 13)
1249 return 2480;
1250 } else if (bw == RTW89_CHANNEL_WIDTH_40) {
1251 if (center_chan >= 3 && center_chan <= 10)
1252 return 2440;
1253 }
1254 break;
1255 case RTW89_BAND_5G:
1256 if (center_chan == 151 || center_chan == 153 ||
1257 center_chan == 155 || center_chan == 163)
1258 return 5760;
1259 break;
1260 case RTW89_BAND_6G:
1261 if (center_chan == 195 || center_chan == 197 ||
1262 center_chan == 199 || center_chan == 207)
1263 return 6920;
1264 break;
1265 default:
1266 break;
1267 }
1268
1269 return 0;
1270}
1271
1272#define CARRIER_SPACING_312_5 312500 /* 312.5 kHz */
1273#define CARRIER_SPACING_78_125 78125 /* 78.125 kHz */
1274#define MAX_TONE_NUM 2048
1275
1276static void rtw8852c_set_csi_tone_idx(struct rtw89_dev *rtwdev,
1277 const struct rtw89_chan *chan,
1278 enum rtw89_phy_idx phy_idx)
1279{
1280 u32 spur_freq;
1281 s32 freq_diff, csi_idx, csi_tone_idx;
1282
1283 spur_freq = rtw8852c_spur_freq(rtwdev, chan);
1284 if (spur_freq == 0) {
1285 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 0, phy_idx);
1286 return;
1287 }
1288
1289 freq_diff = (spur_freq - chan->freq) * 1000000;
1290 csi_idx = s32_div_u32_round_closest(freq_diff, CARRIER_SPACING_78_125);
1291 s32_div_u32_round_down(csi_idx, MAX_TONE_NUM, &csi_tone_idx);
1292
1293 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, csi_tone_idx, phy_idx);
1294 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1, phy_idx);
1295}
1296
1297static const struct rtw89_nbi_reg_def rtw8852c_nbi_reg_def[] = {
1298 [RF_PATH_A] = {
1299 .notch1_idx = {0x4C14, 0xFF},
1300 .notch1_frac_idx = {0x4C14, 0xC00},
1301 .notch1_en = {0x4C14, 0x1000},
1302 .notch2_idx = {0x4C20, 0xFF},
1303 .notch2_frac_idx = {0x4C20, 0xC00},
1304 .notch2_en = {0x4C20, 0x1000},
1305 },
1306 [RF_PATH_B] = {
1307 .notch1_idx = {0x4CD8, 0xFF},
1308 .notch1_frac_idx = {0x4CD8, 0xC00},
1309 .notch1_en = {0x4CD8, 0x1000},
1310 .notch2_idx = {0x4CE4, 0xFF},
1311 .notch2_frac_idx = {0x4CE4, 0xC00},
1312 .notch2_en = {0x4CE4, 0x1000},
1313 },
1314};
1315
1316static void rtw8852c_set_nbi_tone_idx(struct rtw89_dev *rtwdev,
1317 const struct rtw89_chan *chan,
1318 enum rtw89_rf_path path)
1319{
1320 const struct rtw89_nbi_reg_def *nbi = &rtw8852c_nbi_reg_def[path];
1321 u32 spur_freq, fc;
1322 s32 freq_diff;
1323 s32 nbi_idx, nbi_tone_idx;
1324 s32 nbi_frac_idx, nbi_frac_tone_idx;
1325 bool notch2_chk = false;
1326
1327 spur_freq = rtw8852c_spur_freq(rtwdev, chan);
1328 if (spur_freq == 0) {
1329 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0);
1330 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0);
1331 return;
1332 }
1333
1334 fc = chan->freq;
1335 if (chan->band_width == RTW89_CHANNEL_WIDTH_160) {
1336 fc = (spur_freq > fc) ? fc + 40 : fc - 40;
1337 if ((fc > spur_freq &&
1338 chan->channel < chan->primary_channel) ||
1339 (fc < spur_freq &&
1340 chan->channel > chan->primary_channel))
1341 notch2_chk = true;
1342 }
1343
1344 freq_diff = (spur_freq - fc) * 1000000;
1345 nbi_idx = s32_div_u32_round_down(freq_diff, CARRIER_SPACING_312_5, &nbi_frac_idx);
1346
1347 if (chan->band_width == RTW89_CHANNEL_WIDTH_20) {
1348 s32_div_u32_round_down(nbi_idx + 32, 64, &nbi_tone_idx);
1349 } else {
1350 u16 tone_para = (chan->band_width == RTW89_CHANNEL_WIDTH_40) ?
1351 128 : 256;
1352
1353 s32_div_u32_round_down(nbi_idx, tone_para, &nbi_tone_idx);
1354 }
1355 nbi_frac_tone_idx = s32_div_u32_round_closest(nbi_frac_idx, CARRIER_SPACING_78_125);
1356
1357 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && notch2_chk) {
1358 rtw89_phy_write32_mask(rtwdev, nbi->notch2_idx.addr,
1359 nbi->notch2_idx.mask, nbi_tone_idx);
1360 rtw89_phy_write32_mask(rtwdev, nbi->notch2_frac_idx.addr,
1361 nbi->notch2_frac_idx.mask, nbi_frac_tone_idx);
1362 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 0);
1363 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 1);
1364 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0);
1365 } else {
1366 rtw89_phy_write32_mask(rtwdev, nbi->notch1_idx.addr,
1367 nbi->notch1_idx.mask, nbi_tone_idx);
1368 rtw89_phy_write32_mask(rtwdev, nbi->notch1_frac_idx.addr,
1369 nbi->notch1_frac_idx.mask, nbi_frac_tone_idx);
1370 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0);
1371 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 1);
1372 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 0);
1373 }
1374}
1375
1376static void rtw8852c_spur_notch(struct rtw89_dev *rtwdev, u32 val,
1377 enum rtw89_phy_idx phy_idx)
1378{
1379 u32 notch;
1380 u32 notch2;
1381
1382 if (phy_idx == RTW89_PHY_0) {
1383 notch = R_PATH0_NOTCH;
1384 notch2 = R_PATH0_NOTCH2;
1385 } else {
1386 notch = R_PATH1_NOTCH;
1387 notch2 = R_PATH1_NOTCH2;
1388 }
1389
1390 rtw89_phy_write32_mask(rtwdev, notch,
1391 B_PATH0_NOTCH_VAL | B_PATH0_NOTCH_EN, val);
1392 rtw89_phy_write32_set(rtwdev, notch, B_PATH0_NOTCH_EN);
1393 rtw89_phy_write32_mask(rtwdev, notch2,
1394 B_PATH0_NOTCH2_VAL | B_PATH0_NOTCH2_EN, val);
1395 rtw89_phy_write32_set(rtwdev, notch2, B_PATH0_NOTCH2_EN);
1396}
1397
1398static void rtw8852c_spur_elimination(struct rtw89_dev *rtwdev,
1399 const struct rtw89_chan *chan,
1400 u8 pri_ch_idx,
1401 enum rtw89_phy_idx phy_idx)
1402{
1403 rtw8852c_set_csi_tone_idx(rtwdev, chan, phy_idx);
1404
1405 if (phy_idx == RTW89_PHY_0) {
1406 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 &&
1407 (pri_ch_idx == RTW89_SC_20_LOWER ||
1408 pri_ch_idx == RTW89_SC_20_UP3X)) {
1409 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_0);
1410 if (!rtwdev->dbcc_en)
1411 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_1);
1412 } else if (chan->band_width == RTW89_CHANNEL_WIDTH_160 &&
1413 (pri_ch_idx == RTW89_SC_20_UPPER ||
1414 pri_ch_idx == RTW89_SC_20_LOW3X)) {
1415 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_0);
1416 if (!rtwdev->dbcc_en)
1417 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_1);
1418 } else {
1419 rtw8852c_set_nbi_tone_idx(rtwdev, chan, RF_PATH_A);
1420 if (!rtwdev->dbcc_en)
1421 rtw8852c_set_nbi_tone_idx(rtwdev, chan,
1422 RF_PATH_B);
1423 }
1424 } else {
1425 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 &&
1426 (pri_ch_idx == RTW89_SC_20_LOWER ||
1427 pri_ch_idx == RTW89_SC_20_UP3X)) {
1428 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_1);
1429 } else if (chan->band_width == RTW89_CHANNEL_WIDTH_160 &&
1430 (pri_ch_idx == RTW89_SC_20_UPPER ||
1431 pri_ch_idx == RTW89_SC_20_LOW3X)) {
1432 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_1);
1433 } else {
1434 rtw8852c_set_nbi_tone_idx(rtwdev, chan, RF_PATH_B);
1435 }
1436 }
1437
1438 if (pri_ch_idx == RTW89_SC_20_UP3X || pri_ch_idx == RTW89_SC_20_LOW3X)
1439 rtw89_phy_write32_idx(rtwdev, R_PD_BOOST_EN, B_PD_BOOST_EN, 0, phy_idx);
1440 else
1441 rtw89_phy_write32_idx(rtwdev, R_PD_BOOST_EN, B_PD_BOOST_EN, 1, phy_idx);
1442}
1443
1444static void rtw8852c_5m_mask(struct rtw89_dev *rtwdev,
1445 const struct rtw89_chan *chan,
1446 enum rtw89_phy_idx phy_idx)
1447{
1448 u8 pri_ch = chan->pri_ch_idx;
1449 bool mask_5m_low;
1450 bool mask_5m_en;
1451
1452 switch (chan->band_width) {
1453 case RTW89_CHANNEL_WIDTH_40:
1454 mask_5m_en = true;
1455 mask_5m_low = pri_ch == RTW89_SC_20_LOWER;
1456 break;
1457 case RTW89_CHANNEL_WIDTH_80:
1458 mask_5m_en = pri_ch == RTW89_SC_20_UPMOST ||
1459 pri_ch == RTW89_SC_20_LOWEST;
1460 mask_5m_low = pri_ch == RTW89_SC_20_LOWEST;
1461 break;
1462 default:
1463 mask_5m_en = false;
1464 mask_5m_low = false;
1465 break;
1466 }
1467
1468 if (!mask_5m_en) {
1469 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x0);
1470 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x0);
1471 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT,
1472 B_ASSIGN_SBD_OPT_EN, 0x0, phy_idx);
1473 } else {
1474 if (mask_5m_low) {
1475 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_TH, 0x4);
1476 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x1);
1477 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB2, 0x0);
1478 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB0, 0x1);
1479 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_TH, 0x4);
1480 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x1);
1481 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB2, 0x0);
1482 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB0, 0x1);
1483 } else {
1484 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_TH, 0x4);
1485 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x1);
1486 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB2, 0x1);
1487 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB0, 0x0);
1488 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_TH, 0x4);
1489 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x1);
1490 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB2, 0x1);
1491 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB0, 0x0);
1492 }
1493 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT, B_ASSIGN_SBD_OPT_EN, 0x1, phy_idx);
1494 }
1495}
1496
1497static void rtw8852c_bb_reset_all(struct rtw89_dev *rtwdev,
1498 enum rtw89_phy_idx phy_idx)
1499{
1500 /*HW SI reset*/
1501 rtw89_phy_write32_mask(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG,
1502 0x7);
1503 rtw89_phy_write32_mask(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG,
1504 0x7);
1505
1506 udelay(1);
1507
1508 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1,
1509 phy_idx);
1510 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0,
1511 phy_idx);
1512 /*HW SI reset*/
1513 rtw89_phy_write32_mask(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG,
1514 0x0);
1515 rtw89_phy_write32_mask(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG,
1516 0x0);
1517
1518 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1,
1519 phy_idx);
1520}
1521
1522static void rtw8852c_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band,
1523 enum rtw89_phy_idx phy_idx, bool en)
1524{
1525 if (en) {
1526 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
1527 B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
1528 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS,
1529 B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
1530 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1,
1531 phy_idx);
1532 if (band == RTW89_BAND_2G)
1533 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0x0);
1534 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0);
1535 } else {
1536 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0x1);
1537 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1);
1538 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
1539 B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
1540 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS,
1541 B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
1542 fsleep(1);
1543 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0,
1544 phy_idx);
1545 }
1546}
1547
1548static void rtw8852c_bb_reset(struct rtw89_dev *rtwdev,
1549 enum rtw89_phy_idx phy_idx)
1550{
1551 rtw8852c_bb_reset_all(rtwdev, phy_idx);
1552}
1553
1554static
1555void rtw8852c_bb_gpio_trsw(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
1556 u8 tx_path_en, u8 trsw_tx,
1557 u8 trsw_rx, u8 trsw, u8 trsw_b)
1558{
1559 static const u32 path_cr_bases[] = {0x5868, 0x7868};
1560 u32 mask_ofst = 16;
1561 u32 cr;
1562 u32 val;
1563
1564 if (path >= ARRAY_SIZE(path_cr_bases))
1565 return;
1566
1567 cr = path_cr_bases[path];
1568
1569 mask_ofst += (tx_path_en * 4 + trsw_tx * 2 + trsw_rx) * 2;
1570 val = FIELD_PREP(B_P0_TRSW_A, trsw) | FIELD_PREP(B_P0_TRSW_B, trsw_b);
1571
1572 rtw89_phy_write32_mask(rtwdev, cr, (B_P0_TRSW_A | B_P0_TRSW_B) << mask_ofst, val);
1573}
1574
1575enum rtw8852c_rfe_src {
1576 PAPE_RFM,
1577 TRSW_RFM,
1578 LNAON_RFM,
1579};
1580
1581static
1582void rtw8852c_bb_gpio_rfm(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
1583 enum rtw8852c_rfe_src src, u8 dis_tx_gnt_wl,
1584 u8 active_tx_opt, u8 act_bt_en, u8 rfm_output_val)
1585{
1586 static const u32 path_cr_bases[] = {0x5894, 0x7894};
1587 static const u32 masks[] = {0, 8, 16};
1588 u32 mask, mask_ofst;
1589 u32 cr;
1590 u32 val;
1591
1592 if (src >= ARRAY_SIZE(masks) || path >= ARRAY_SIZE(path_cr_bases))
1593 return;
1594
1595 mask_ofst = masks[src];
1596 cr = path_cr_bases[path];
1597
1598 val = FIELD_PREP(B_P0_RFM_DIS_WL, dis_tx_gnt_wl) |
1599 FIELD_PREP(B_P0_RFM_TX_OPT, active_tx_opt) |
1600 FIELD_PREP(B_P0_RFM_BT_EN, act_bt_en) |
1601 FIELD_PREP(B_P0_RFM_OUT, rfm_output_val);
1602 mask = 0xff << mask_ofst;
1603
1604 rtw89_phy_write32_mask(rtwdev, cr, mask, val);
1605}
1606
1607static void rtw8852c_bb_gpio_init(struct rtw89_dev *rtwdev)
1608{
1609 static const u32 cr_bases[] = {0x5800, 0x7800};
1610 u32 addr;
1611 u8 i;
1612
1613 for (i = 0; i < ARRAY_SIZE(cr_bases); i++) {
1614 addr = cr_bases[i];
1615 rtw89_phy_write32_set(rtwdev, (addr | 0x68), B_P0_TRSW_A);
1616 rtw89_phy_write32_clr(rtwdev, (addr | 0x68), B_P0_TRSW_X);
1617 rtw89_phy_write32_clr(rtwdev, (addr | 0x68), B_P0_TRSW_SO_A2);
1618 rtw89_phy_write32(rtwdev, (addr | 0x80), 0x77777777);
1619 rtw89_phy_write32(rtwdev, (addr | 0x84), 0x77777777);
1620 }
1621
1622 rtw89_phy_write32(rtwdev, R_RFE_E_A2, 0xffffffff);
1623 rtw89_phy_write32(rtwdev, R_RFE_O_SEL_A2, 0);
1624 rtw89_phy_write32(rtwdev, R_RFE_SEL0_A2, 0);
1625 rtw89_phy_write32(rtwdev, R_RFE_SEL32_A2, 0);
1626
1627 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 0, 0, 1);
1628 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 1, 1, 0);
1629 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 0, 1, 0);
1630 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 1, 1, 0);
1631 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 0, 0, 1);
1632 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 1, 1, 0);
1633 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 0, 1, 0);
1634 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 1, 1, 0);
1635
1636 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 0, 0, 0, 1);
1637 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 0, 1, 1, 0);
1638 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 1, 0, 1, 0);
1639 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 1, 1, 1, 0);
1640 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 0, 0, 0, 1);
1641 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 0, 1, 1, 0);
1642 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 1, 0, 1, 0);
1643 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 1, 1, 1, 0);
1644
1645 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, PAPE_RFM, 0, 0, 0, 0x0);
1646 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, TRSW_RFM, 0, 0, 0, 0x4);
1647 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, LNAON_RFM, 0, 0, 0, 0x8);
1648
1649 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, PAPE_RFM, 0, 0, 0, 0x0);
1650 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, TRSW_RFM, 0, 0, 0, 0x4);
1651 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, LNAON_RFM, 0, 0, 0, 0x8);
1652}
1653
1654static void rtw8852c_bb_macid_ctrl_init(struct rtw89_dev *rtwdev,
1655 enum rtw89_phy_idx phy_idx)
1656{
1657 u32 addr;
1658
1659 for (addr = R_AX_PWR_MACID_LMT_TABLE0;
1660 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4)
1661 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
1662}
1663
1664static void rtw8852c_bb_sethw(struct rtw89_dev *rtwdev)
1665{
1666 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
1667
1668 rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT,
1669 B_DBCC_80P80_SEL_EVM_RPT_EN);
1670 rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT2,
1671 B_DBCC_80P80_SEL_EVM_RPT2_EN);
1672
1673 rtw8852c_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0);
1674 rtw8852c_bb_gpio_init(rtwdev);
1675
1676 /* read these registers after loading BB parameters */
1677 gain->offset_base[RTW89_PHY_0] =
1678 rtw89_phy_read32_mask(rtwdev, R_RPL_BIAS_COMP, B_RPL_BIAS_COMP_MASK);
1679 gain->offset_base[RTW89_PHY_1] =
1680 rtw89_phy_read32_mask(rtwdev, R_RPL_BIAS_COMP1, B_RPL_BIAS_COMP1_MASK);
1681}
1682
1683static void rtw8852c_set_channel_bb(struct rtw89_dev *rtwdev,
1684 const struct rtw89_chan *chan,
1685 enum rtw89_phy_idx phy_idx)
1686{
1687 static const u32 ru_alloc_msk[2] = {B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY0,
1688 B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY1};
1689 struct rtw89_hal *hal = &rtwdev->hal;
1690 bool cck_en = chan->band_type == RTW89_BAND_2G;
1691 u8 pri_ch_idx = chan->pri_ch_idx;
1692 u32 mask, reg;
1693 u8 ntx_path;
1694
1695 if (chan->band_type == RTW89_BAND_2G)
1696 rtw8852c_ctrl_sco_cck(rtwdev, chan->channel,
1697 chan->primary_channel,
1698 chan->band_width);
1699
1700 rtw8852c_ctrl_ch(rtwdev, chan, phy_idx);
1701 rtw8852c_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx);
1702 if (cck_en) {
1703 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1);
1704 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0);
1705 rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF,
1706 B_PD_ARBITER_OFF, 0x0, phy_idx);
1707 } else {
1708 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0);
1709 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 1);
1710 rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF,
1711 B_PD_ARBITER_OFF, 0x1, phy_idx);
1712 }
1713
1714 rtw8852c_spur_elimination(rtwdev, chan, pri_ch_idx, phy_idx);
1715 rtw8852c_ctrl_btg_bt_rx(rtwdev, chan->band_type == RTW89_BAND_2G,
1716 RTW89_PHY_0);
1717 rtw8852c_5m_mask(rtwdev, chan, phy_idx);
1718
1719 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 &&
1720 rtwdev->hal.cv != CHIP_CAV) {
1721 rtw89_phy_write32_idx(rtwdev, R_P80_AT_HIGH_FREQ,
1722 B_P80_AT_HIGH_FREQ, 0x0, phy_idx);
1723 reg = rtw89_mac_reg_by_idx(rtwdev, R_P80_AT_HIGH_FREQ_BB_WRP, phy_idx);
1724 if (chan->primary_channel > chan->channel) {
1725 rtw89_phy_write32_mask(rtwdev,
1726 R_P80_AT_HIGH_FREQ_RU_ALLOC,
1727 ru_alloc_msk[phy_idx], 1);
1728 rtw89_write32_mask(rtwdev, reg,
1729 B_P80_AT_HIGH_FREQ_BB_WRP, 1);
1730 } else {
1731 rtw89_phy_write32_mask(rtwdev,
1732 R_P80_AT_HIGH_FREQ_RU_ALLOC,
1733 ru_alloc_msk[phy_idx], 0);
1734 rtw89_write32_mask(rtwdev, reg,
1735 B_P80_AT_HIGH_FREQ_BB_WRP, 0);
1736 }
1737 }
1738
1739 if (chan->band_type == RTW89_BAND_6G &&
1740 chan->band_width == RTW89_CHANNEL_WIDTH_160)
1741 rtw89_phy_write32_idx(rtwdev, R_CDD_EVM_CHK_EN,
1742 B_CDD_EVM_CHK_EN, 0, phy_idx);
1743 else
1744 rtw89_phy_write32_idx(rtwdev, R_CDD_EVM_CHK_EN,
1745 B_CDD_EVM_CHK_EN, 1, phy_idx);
1746
1747 if (!rtwdev->dbcc_en) {
1748 mask = B_P0_TXPW_RSTB_TSSI | B_P0_TXPW_RSTB_MANON;
1749 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x1);
1750 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x3);
1751 mask = B_P1_TXPW_RSTB_TSSI | B_P1_TXPW_RSTB_MANON;
1752 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x1);
1753 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x3);
1754 } else {
1755 if (phy_idx == RTW89_PHY_0) {
1756 mask = B_P0_TXPW_RSTB_TSSI | B_P0_TXPW_RSTB_MANON;
1757 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x1);
1758 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x3);
1759 } else {
1760 mask = B_P1_TXPW_RSTB_TSSI | B_P1_TXPW_RSTB_MANON;
1761 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x1);
1762 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x3);
1763 }
1764 }
1765
1766 if (chan->band_type == RTW89_BAND_6G)
1767 rtw89_phy_write32_set(rtwdev, R_MUIC, B_MUIC_EN);
1768 else
1769 rtw89_phy_write32_clr(rtwdev, R_MUIC, B_MUIC_EN);
1770
1771 if (hal->antenna_tx)
1772 ntx_path = hal->antenna_tx;
1773 else
1774 ntx_path = chan->band_type == RTW89_BAND_6G ? RF_B : RF_AB;
1775
1776 rtw8852c_ctrl_tx_path_tmac(rtwdev, ntx_path, (enum rtw89_mac_idx)phy_idx);
1777
1778 rtw8852c_bb_reset_all(rtwdev, phy_idx);
1779}
1780
1781static void rtw8852c_set_channel(struct rtw89_dev *rtwdev,
1782 const struct rtw89_chan *chan,
1783 enum rtw89_mac_idx mac_idx,
1784 enum rtw89_phy_idx phy_idx)
1785{
1786 rtw8852c_set_channel_mac(rtwdev, chan, mac_idx);
1787 rtw8852c_set_channel_bb(rtwdev, chan, phy_idx);
1788 rtw8852c_set_channel_rf(rtwdev, chan, phy_idx);
1789}
1790
1791static void rtw8852c_dfs_en(struct rtw89_dev *rtwdev, bool en)
1792{
1793 if (en)
1794 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1);
1795 else
1796 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0);
1797}
1798
1799static void rtw8852c_adc_en(struct rtw89_dev *rtwdev, bool en)
1800{
1801 if (en)
1802 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST,
1803 0x0);
1804 else
1805 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST,
1806 0xf);
1807}
1808
1809static void rtw8852c_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
1810 struct rtw89_channel_help_params *p,
1811 const struct rtw89_chan *chan,
1812 enum rtw89_mac_idx mac_idx,
1813 enum rtw89_phy_idx phy_idx)
1814{
1815 if (enter) {
1816 rtw89_chip_stop_sch_tx(rtwdev, mac_idx, &p->tx_en,
1817 RTW89_SCH_TX_SEL_ALL);
1818 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, false);
1819 rtw8852c_dfs_en(rtwdev, false);
1820 rtw8852c_tssi_cont_en_phyidx(rtwdev, false, phy_idx, chan);
1821 rtw8852c_adc_en(rtwdev, false);
1822 fsleep(40);
1823 rtw8852c_bb_reset_en(rtwdev, chan->band_type, phy_idx, false);
1824 } else {
1825 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, true);
1826 rtw8852c_adc_en(rtwdev, true);
1827 rtw8852c_dfs_en(rtwdev, true);
1828 rtw8852c_tssi_cont_en_phyidx(rtwdev, true, phy_idx, chan);
1829 rtw8852c_bb_reset_en(rtwdev, chan->band_type, phy_idx, true);
1830 rtw89_chip_resume_sch_tx(rtwdev, mac_idx, p->tx_en);
1831 }
1832}
1833
1834static void rtw8852c_rfk_init(struct rtw89_dev *rtwdev)
1835{
1836 struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc;
1837
1838 rtwdev->is_tssi_mode[RF_PATH_A] = false;
1839 rtwdev->is_tssi_mode[RF_PATH_B] = false;
1840 memset(rfk_mcc, 0, sizeof(*rfk_mcc));
1841 rtw8852c_lck_init(rtwdev);
1842 rtw8852c_dpk_init(rtwdev);
1843
1844 rtw8852c_rck(rtwdev);
1845 rtw8852c_dack(rtwdev, RTW89_CHANCTX_0);
1846 rtw8852c_rx_dck(rtwdev, RTW89_PHY_0, false);
1847}
1848
1849static void rtw8852c_rfk_channel(struct rtw89_dev *rtwdev,
1850 struct rtw89_vif_link *rtwvif_link)
1851{
1852 enum rtw89_chanctx_idx chanctx_idx = rtwvif_link->chanctx_idx;
1853 enum rtw89_phy_idx phy_idx = rtwvif_link->phy_idx;
1854
1855 rtw8852c_mcc_get_ch_info(rtwdev, phy_idx);
1856 rtw8852c_rx_dck(rtwdev, phy_idx, false);
1857 rtw8852c_iqk(rtwdev, phy_idx, chanctx_idx);
1858 rtw8852c_tssi(rtwdev, phy_idx, chanctx_idx);
1859 rtw8852c_dpk(rtwdev, phy_idx, chanctx_idx);
1860 rtw89_fw_h2c_rf_ntfy_mcc(rtwdev);
1861}
1862
1863static void rtw8852c_rfk_band_changed(struct rtw89_dev *rtwdev,
1864 enum rtw89_phy_idx phy_idx,
1865 const struct rtw89_chan *chan)
1866{
1867 rtw8852c_tssi_scan(rtwdev, phy_idx, chan);
1868}
1869
1870static void rtw8852c_rfk_scan(struct rtw89_dev *rtwdev,
1871 struct rtw89_vif_link *rtwvif_link,
1872 bool start)
1873{
1874 rtw8852c_wifi_scan_notify(rtwdev, start, rtwvif_link->phy_idx);
1875}
1876
1877static void rtw8852c_rfk_track(struct rtw89_dev *rtwdev)
1878{
1879 rtw8852c_dpk_track(rtwdev);
1880 rtw8852c_lck_track(rtwdev);
1881 rtw8852c_rx_dck_track(rtwdev);
1882}
1883
1884static u32 rtw8852c_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev,
1885 enum rtw89_phy_idx phy_idx, s16 ref)
1886{
1887 s8 ofst_int = 0;
1888 u8 base_cw_0db = 0x27;
1889 u16 tssi_16dbm_cw = 0x12c;
1890 s16 pwr_s10_3 = 0;
1891 s16 rf_pwr_cw = 0;
1892 u16 bb_pwr_cw = 0;
1893 u32 pwr_cw = 0;
1894 u32 tssi_ofst_cw = 0;
1895
1896 pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3);
1897 bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3);
1898 rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3);
1899 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63);
1900 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw;
1901
1902 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3));
1903 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1904 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n",
1905 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw);
1906
1907 return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0));
1908}
1909
1910static
1911void rtw8852c_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
1912 s8 pw_ofst, enum rtw89_mac_idx mac_idx)
1913{
1914 s8 pw_ofst_2tx;
1915 s8 val_1t;
1916 s8 val_2t;
1917 u32 reg;
1918 u8 i;
1919
1920 if (pw_ofst < -32 || pw_ofst > 31) {
1921 rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst);
1922 return;
1923 }
1924 val_1t = pw_ofst << 2;
1925 pw_ofst_2tx = max(pw_ofst - 3, -32);
1926 val_2t = pw_ofst_2tx << 2;
1927
1928 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] val_1tx=0x%x\n", val_1t);
1929 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] val_2tx=0x%x\n", val_2t);
1930
1931 for (i = 0; i < 4; i++) {
1932 /* 1TX */
1933 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx);
1934 rtw89_write32_mask(rtwdev, reg,
1935 B_AX_PWR_UL_TB_1T_V1_MASK << (8 * i),
1936 val_1t);
1937 /* 2TX */
1938 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx);
1939 rtw89_write32_mask(rtwdev, reg,
1940 B_AX_PWR_UL_TB_2T_V1_MASK << (8 * i),
1941 val_2t);
1942 }
1943}
1944
1945static void rtw8852c_set_txpwr_ref(struct rtw89_dev *rtwdev,
1946 enum rtw89_phy_idx phy_idx)
1947{
1948 static const u32 addr[RF_PATH_NUM_8852C] = {0x5800, 0x7800};
1949 const u32 mask = 0x7FFFFFF;
1950 const u8 ofst_ofdm = 0x4;
1951 const u8 ofst_cck = 0x8;
1952 s16 ref_ofdm = 0;
1953 s16 ref_cck = 0;
1954 u32 val;
1955 u8 i;
1956
1957 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n");
1958
1959 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL,
1960 GENMASK(27, 10), 0x0);
1961
1962 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n");
1963 val = rtw8852c_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm);
1964
1965 for (i = 0; i < RF_PATH_NUM_8852C; i++)
1966 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val,
1967 phy_idx);
1968
1969 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n");
1970 val = rtw8852c_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck);
1971
1972 for (i = 0; i < RF_PATH_NUM_8852C; i++)
1973 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val,
1974 phy_idx);
1975}
1976
1977static void rtw8852c_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev,
1978 const struct rtw89_chan *chan,
1979 u8 tx_shape_idx,
1980 enum rtw89_phy_idx phy_idx)
1981{
1982#define __DFIR_CFG_MASK 0xffffff
1983#define __DFIR_CFG_NR 8
1984#define __DECL_DFIR_VAR(_prefix, _name, _val...) \
1985 static const u32 _prefix ## _ ## _name[] = {_val}; \
1986 static_assert(ARRAY_SIZE(_prefix ## _ ## _name) == __DFIR_CFG_NR)
1987#define __DECL_DFIR_PARAM(_name, _val...) __DECL_DFIR_VAR(param, _name, _val)
1988#define __DECL_DFIR_ADDR(_name, _val...) __DECL_DFIR_VAR(addr, _name, _val)
1989
1990 __DECL_DFIR_PARAM(flat,
1991 0x003D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053,
1992 0x00F86F9A, 0x00FAEF92, 0x00FE5FCC, 0x00FFDFF5);
1993 __DECL_DFIR_PARAM(sharp,
1994 0x003D83FF, 0x002C636A, 0x0013F204, 0x00008090,
1995 0x00F87FB0, 0x00F99F83, 0x00FDBFBA, 0x00003FF5);
1996 __DECL_DFIR_PARAM(sharp_14,
1997 0x003B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E,
1998 0x00FD8F92, 0x0002D011, 0x0001C02C, 0x00FFF00A);
1999 __DECL_DFIR_ADDR(filter,
2000 0x45BC, 0x45CC, 0x45D0, 0x45D4, 0x45D8, 0x45C0,
2001 0x45C4, 0x45C8);
2002 u8 ch = chan->channel;
2003 const u32 *param;
2004 int i;
2005
2006 if (ch > 14) {
2007 rtw89_warn(rtwdev,
2008 "set tx shape dfir by unknown ch: %d on 2G\n", ch);
2009 return;
2010 }
2011
2012 if (ch == 14)
2013 param = param_sharp_14;
2014 else
2015 param = tx_shape_idx == 0 ? param_flat : param_sharp;
2016
2017 for (i = 0; i < __DFIR_CFG_NR; i++) {
2018 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2019 "set tx shape dfir: 0x%x: 0x%x\n", addr_filter[i],
2020 param[i]);
2021 rtw89_phy_write32_idx(rtwdev, addr_filter[i], __DFIR_CFG_MASK,
2022 param[i], phy_idx);
2023 }
2024
2025#undef __DECL_DFIR_ADDR
2026#undef __DECL_DFIR_PARAM
2027#undef __DECL_DFIR_VAR
2028#undef __DFIR_CFG_NR
2029#undef __DFIR_CFG_MASK
2030}
2031
2032static void rtw8852c_set_tx_shape(struct rtw89_dev *rtwdev,
2033 const struct rtw89_chan *chan,
2034 enum rtw89_phy_idx phy_idx)
2035{
2036 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms;
2037 u8 band = chan->band_type;
2038 u8 regd = rtw89_regd_get(rtwdev, band);
2039 u8 tx_shape_cck = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_CCK][regd];
2040 u8 tx_shape_ofdm = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_OFDM][regd];
2041
2042 if (band == RTW89_BAND_2G)
2043 rtw8852c_bb_set_tx_shape_dfir(rtwdev, chan, tx_shape_cck, phy_idx);
2044
2045 rtw89_phy_tssi_ctrl_set_bandedge_cfg(rtwdev,
2046 (enum rtw89_mac_idx)phy_idx,
2047 tx_shape_ofdm);
2048
2049 rtw89_phy_write32_set(rtwdev, R_P0_DAC_COMP_POST_DPD_EN,
2050 B_P0_DAC_COMP_POST_DPD_EN);
2051 rtw89_phy_write32_set(rtwdev, R_P1_DAC_COMP_POST_DPD_EN,
2052 B_P1_DAC_COMP_POST_DPD_EN);
2053}
2054
2055static void rtw8852c_set_txpwr(struct rtw89_dev *rtwdev,
2056 const struct rtw89_chan *chan,
2057 enum rtw89_phy_idx phy_idx)
2058{
2059 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
2060 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
2061 rtw8852c_set_tx_shape(rtwdev, chan, phy_idx);
2062 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
2063 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
2064}
2065
2066static void rtw8852c_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
2067 enum rtw89_phy_idx phy_idx)
2068{
2069 rtw8852c_set_txpwr_ref(rtwdev, phy_idx);
2070}
2071
2072static void
2073rtw8852c_init_tssi_ctrl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
2074{
2075 static const struct rtw89_reg2_def ctrl_ini[] = {
2076 {0xD938, 0x00010100},
2077 {0xD93C, 0x0500D500},
2078 {0xD940, 0x00000500},
2079 {0xD944, 0x00000005},
2080 {0xD94C, 0x00220000},
2081 {0xD950, 0x00030000},
2082 };
2083 u32 addr;
2084 int i;
2085
2086 for (addr = R_AX_TSSI_CTRL_HEAD; addr <= R_AX_TSSI_CTRL_TAIL; addr += 4)
2087 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
2088
2089 for (i = 0; i < ARRAY_SIZE(ctrl_ini); i++)
2090 rtw89_mac_txpwr_write32(rtwdev, phy_idx, ctrl_ini[i].addr,
2091 ctrl_ini[i].data);
2092
2093 rtw89_phy_tssi_ctrl_set_bandedge_cfg(rtwdev,
2094 (enum rtw89_mac_idx)phy_idx,
2095 RTW89_TSSI_BANDEDGE_FLAT);
2096}
2097
2098static int
2099rtw8852c_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
2100{
2101 int ret;
2102
2103 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333);
2104 if (ret)
2105 return ret;
2106
2107 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000);
2108 if (ret)
2109 return ret;
2110
2111 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff);
2112 if (ret)
2113 return ret;
2114
2115 rtw8852c_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ?
2116 RTW89_MAC_1 :
2117 RTW89_MAC_0);
2118 rtw8852c_init_tssi_ctrl(rtwdev, phy_idx);
2119
2120 return 0;
2121}
2122
2123static void rtw8852c_bb_cfg_rx_path(struct rtw89_dev *rtwdev, u8 rx_path)
2124{
2125 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
2126 u8 band = chan->band_type;
2127 u32 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI;
2128 u32 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI;
2129
2130 if (rtwdev->dbcc_en) {
2131 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_ANT_RX_SEG0, 1);
2132 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_ANT_RX_SEG0, 2,
2133 RTW89_PHY_1);
2134
2135 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG0,
2136 1);
2137 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG1,
2138 1);
2139 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG0, 2,
2140 RTW89_PHY_1);
2141 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG1, 2,
2142 RTW89_PHY_1);
2143
2144 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT,
2145 B_RXHT_MCS_LIMIT, 0);
2146 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT,
2147 B_RXVHT_MCS_LIMIT, 0);
2148 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 8);
2149 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
2150 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
2151
2152 rtw89_phy_write32_idx(rtwdev, R_RXHT_MCS_LIMIT,
2153 B_RXHT_MCS_LIMIT, 0, RTW89_PHY_1);
2154 rtw89_phy_write32_idx(rtwdev, R_RXVHT_MCS_LIMIT,
2155 B_RXVHT_MCS_LIMIT, 0, RTW89_PHY_1);
2156 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHE_USER_MAX, 1,
2157 RTW89_PHY_1);
2158 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0,
2159 RTW89_PHY_1);
2160 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0,
2161 RTW89_PHY_1);
2162 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1);
2163 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3);
2164 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1);
2165 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3);
2166 } else {
2167 if (rx_path == RF_PATH_A) {
2168 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD,
2169 B_ANT_RX_SEG0, 1);
2170 rtw89_phy_write32_mask(rtwdev, R_FC0_BW,
2171 B_ANT_RX_1RCCA_SEG0, 1);
2172 rtw89_phy_write32_mask(rtwdev, R_FC0_BW,
2173 B_ANT_RX_1RCCA_SEG1, 1);
2174 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT,
2175 B_RXHT_MCS_LIMIT, 0);
2176 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT,
2177 B_RXVHT_MCS_LIMIT, 0);
2178 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS,
2179 0);
2180 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS,
2181 0);
2182 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
2183 rst_mask0, 1);
2184 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
2185 rst_mask0, 3);
2186 } else if (rx_path == RF_PATH_B) {
2187 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD,
2188 B_ANT_RX_SEG0, 2);
2189 rtw89_phy_write32_mask(rtwdev, R_FC0_BW,
2190 B_ANT_RX_1RCCA_SEG0, 2);
2191 rtw89_phy_write32_mask(rtwdev, R_FC0_BW,
2192 B_ANT_RX_1RCCA_SEG1, 2);
2193 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT,
2194 B_RXHT_MCS_LIMIT, 0);
2195 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT,
2196 B_RXVHT_MCS_LIMIT, 0);
2197 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS,
2198 0);
2199 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS,
2200 0);
2201 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB,
2202 rst_mask1, 1);
2203 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB,
2204 rst_mask1, 3);
2205 } else {
2206 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD,
2207 B_ANT_RX_SEG0, 3);
2208 rtw89_phy_write32_mask(rtwdev, R_FC0_BW,
2209 B_ANT_RX_1RCCA_SEG0, 3);
2210 rtw89_phy_write32_mask(rtwdev, R_FC0_BW,
2211 B_ANT_RX_1RCCA_SEG1, 3);
2212 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT,
2213 B_RXHT_MCS_LIMIT, 1);
2214 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT,
2215 B_RXVHT_MCS_LIMIT, 1);
2216 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS,
2217 1);
2218 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS,
2219 1);
2220 rtw8852c_ctrl_btg_bt_rx(rtwdev, band == RTW89_BAND_2G,
2221 RTW89_PHY_0);
2222 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
2223 rst_mask0, 1);
2224 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
2225 rst_mask0, 3);
2226 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB,
2227 rst_mask1, 1);
2228 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB,
2229 rst_mask1, 3);
2230 }
2231 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 8);
2232 }
2233}
2234
2235static void rtw8852c_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev, u8 tx_path,
2236 enum rtw89_mac_idx mac_idx)
2237{
2238 struct rtw89_reg2_def path_com[] = {
2239 {R_AX_PATH_COM0, AX_PATH_COM0_DFVAL},
2240 {R_AX_PATH_COM1, AX_PATH_COM1_DFVAL},
2241 {R_AX_PATH_COM2, AX_PATH_COM2_DFVAL},
2242 {R_AX_PATH_COM3, AX_PATH_COM3_DFVAL},
2243 {R_AX_PATH_COM4, AX_PATH_COM4_DFVAL},
2244 {R_AX_PATH_COM5, AX_PATH_COM5_DFVAL},
2245 {R_AX_PATH_COM6, AX_PATH_COM6_DFVAL},
2246 {R_AX_PATH_COM7, AX_PATH_COM7_DFVAL},
2247 {R_AX_PATH_COM8, AX_PATH_COM8_DFVAL},
2248 {R_AX_PATH_COM9, AX_PATH_COM9_DFVAL},
2249 {R_AX_PATH_COM10, AX_PATH_COM10_DFVAL},
2250 {R_AX_PATH_COM11, AX_PATH_COM11_DFVAL},
2251 };
2252 u32 addr;
2253 u32 reg;
2254 u8 cr_size = ARRAY_SIZE(path_com);
2255 u8 i = 0;
2256
2257 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, RTW89_PHY_0);
2258 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, RTW89_PHY_1);
2259
2260 for (addr = R_AX_MACID_ANT_TABLE;
2261 addr <= R_AX_MACID_ANT_TABLE_LAST; addr += 4) {
2262 reg = rtw89_mac_reg_by_idx(rtwdev, addr, mac_idx);
2263 rtw89_write32(rtwdev, reg, 0);
2264 }
2265
2266 if (tx_path == RF_A) {
2267 path_com[0].data = AX_PATH_COM0_PATHA;
2268 path_com[1].data = AX_PATH_COM1_PATHA;
2269 path_com[2].data = AX_PATH_COM2_PATHA;
2270 path_com[7].data = AX_PATH_COM7_PATHA;
2271 path_com[8].data = AX_PATH_COM8_PATHA;
2272 } else if (tx_path == RF_B) {
2273 path_com[0].data = AX_PATH_COM0_PATHB;
2274 path_com[1].data = AX_PATH_COM1_PATHB;
2275 path_com[2].data = AX_PATH_COM2_PATHB;
2276 path_com[7].data = AX_PATH_COM7_PATHB;
2277 path_com[8].data = AX_PATH_COM8_PATHB;
2278 } else if (tx_path == RF_AB) {
2279 path_com[0].data = AX_PATH_COM0_PATHAB;
2280 path_com[1].data = AX_PATH_COM1_PATHAB;
2281 path_com[2].data = AX_PATH_COM2_PATHAB;
2282 path_com[7].data = AX_PATH_COM7_PATHAB;
2283 path_com[8].data = AX_PATH_COM8_PATHAB;
2284 } else {
2285 rtw89_warn(rtwdev, "[Invalid Tx Path]Tx Path: %d\n", tx_path);
2286 return;
2287 }
2288
2289 for (i = 0; i < cr_size; i++) {
2290 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "0x%x = 0x%x\n",
2291 path_com[i].addr, path_com[i].data);
2292 reg = rtw89_mac_reg_by_idx(rtwdev, path_com[i].addr, mac_idx);
2293 rtw89_write32(rtwdev, reg, path_com[i].data);
2294 }
2295}
2296
2297static void rtw8852c_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en,
2298 enum rtw89_phy_idx phy_idx)
2299{
2300 if (en) {
2301 rtw89_phy_write32_mask(rtwdev, R_PATH0_FRC_FIR_TYPE_V1,
2302 B_PATH0_FRC_FIR_TYPE_MSK_V1, 0x3);
2303 rtw89_phy_write32_mask(rtwdev, R_PATH1_FRC_FIR_TYPE_V1,
2304 B_PATH1_FRC_FIR_TYPE_MSK_V1, 0x3);
2305 rtw89_phy_write32_mask(rtwdev, R_PATH0_RXBB_V1,
2306 B_PATH0_RXBB_MSK_V1, 0xf);
2307 rtw89_phy_write32_mask(rtwdev, R_PATH1_RXBB_V1,
2308 B_PATH1_RXBB_MSK_V1, 0xf);
2309 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
2310 B_PATH0_G_LNA6_OP1DB_V1, 0x80);
2311 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1,
2312 B_PATH1_G_LNA6_OP1DB_V1, 0x80);
2313 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
2314 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x80);
2315 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA1_LNA6_OP1DB_V1,
2316 B_PATH0_G_TIA1_LNA6_OP1DB_V1, 0x80);
2317 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1,
2318 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x80);
2319 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA1_LNA6_OP1DB_V1,
2320 B_PATH1_G_TIA1_LNA6_OP1DB_V1, 0x80);
2321 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_BACKOFF_V1,
2322 B_PATH0_BT_BACKOFF_V1, 0x780D1E);
2323 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_BACKOFF_V1,
2324 B_PATH1_BT_BACKOFF_V1, 0x780D1E);
2325 rtw89_phy_write32_mask(rtwdev, R_P0_BACKOFF_IBADC_V1,
2326 B_P0_BACKOFF_IBADC_V1, 0x34);
2327 rtw89_phy_write32_mask(rtwdev, R_P1_BACKOFF_IBADC_V1,
2328 B_P1_BACKOFF_IBADC_V1, 0x34);
2329 } else {
2330 rtw89_phy_write32_mask(rtwdev, R_PATH0_FRC_FIR_TYPE_V1,
2331 B_PATH0_FRC_FIR_TYPE_MSK_V1, 0x0);
2332 rtw89_phy_write32_mask(rtwdev, R_PATH1_FRC_FIR_TYPE_V1,
2333 B_PATH1_FRC_FIR_TYPE_MSK_V1, 0x0);
2334 rtw89_phy_write32_mask(rtwdev, R_PATH0_RXBB_V1,
2335 B_PATH0_RXBB_MSK_V1, 0x60);
2336 rtw89_phy_write32_mask(rtwdev, R_PATH1_RXBB_V1,
2337 B_PATH1_RXBB_MSK_V1, 0x60);
2338 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
2339 B_PATH0_G_LNA6_OP1DB_V1, 0x1a);
2340 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1,
2341 B_PATH1_G_LNA6_OP1DB_V1, 0x1a);
2342 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
2343 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x2a);
2344 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA1_LNA6_OP1DB_V1,
2345 B_PATH0_G_TIA1_LNA6_OP1DB_V1, 0x2a);
2346 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1,
2347 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a);
2348 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA1_LNA6_OP1DB_V1,
2349 B_PATH1_G_TIA1_LNA6_OP1DB_V1, 0x2a);
2350 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_BACKOFF_V1,
2351 B_PATH0_BT_BACKOFF_V1, 0x79E99E);
2352 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_BACKOFF_V1,
2353 B_PATH1_BT_BACKOFF_V1, 0x79E99E);
2354 rtw89_phy_write32_mask(rtwdev, R_P0_BACKOFF_IBADC_V1,
2355 B_P0_BACKOFF_IBADC_V1, 0x26);
2356 rtw89_phy_write32_mask(rtwdev, R_P1_BACKOFF_IBADC_V1,
2357 B_P1_BACKOFF_IBADC_V1, 0x26);
2358 }
2359}
2360
2361static void rtw8852c_bb_cfg_txrx_path(struct rtw89_dev *rtwdev)
2362{
2363 struct rtw89_hal *hal = &rtwdev->hal;
2364
2365 rtw8852c_bb_cfg_rx_path(rtwdev, RF_PATH_AB);
2366
2367 if (hal->rx_nss == 1) {
2368 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
2369 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
2370 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
2371 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
2372 } else {
2373 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1);
2374 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1);
2375 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1);
2376 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1);
2377 }
2378}
2379
2380static u8 rtw8852c_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
2381{
2382 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
2383 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0);
2384 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
2385
2386 fsleep(200);
2387
2388 return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL);
2389}
2390
2391static void rtw8852c_btc_set_rfe(struct rtw89_dev *rtwdev)
2392{
2393 const struct rtw89_btc_ver *ver = rtwdev->btc.ver;
2394 union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo;
2395
2396 if (ver->fcxinit == 7) {
2397 md->md_v7.rfe_type = rtwdev->efuse.rfe_type;
2398 md->md_v7.kt_ver = rtwdev->hal.cv;
2399 md->md_v7.bt_solo = 0;
2400 md->md_v7.switch_type = BTC_SWITCH_INTERNAL;
2401
2402 if (md->md_v7.rfe_type > 0)
2403 md->md_v7.ant.num = (md->md_v7.rfe_type % 2 ? 2 : 3);
2404 else
2405 md->md_v7.ant.num = 2;
2406
2407 md->md_v7.ant.diversity = 0;
2408 md->md_v7.ant.isolation = 10;
2409
2410 if (md->md_v7.ant.num == 3) {
2411 md->md_v7.ant.type = BTC_ANT_DEDICATED;
2412 md->md_v7.bt_pos = BTC_BT_ALONE;
2413 } else {
2414 md->md_v7.ant.type = BTC_ANT_SHARED;
2415 md->md_v7.bt_pos = BTC_BT_BTG;
2416 }
2417 rtwdev->btc.btg_pos = md->md_v7.ant.btg_pos;
2418 rtwdev->btc.ant_type = md->md_v7.ant.type;
2419 } else {
2420 md->md.rfe_type = rtwdev->efuse.rfe_type;
2421 md->md.cv = rtwdev->hal.cv;
2422 md->md.bt_solo = 0;
2423 md->md.switch_type = BTC_SWITCH_INTERNAL;
2424
2425 if (md->md.rfe_type > 0)
2426 md->md.ant.num = (md->md.rfe_type % 2 ? 2 : 3);
2427 else
2428 md->md.ant.num = 2;
2429
2430 md->md.ant.diversity = 0;
2431 md->md.ant.isolation = 10;
2432
2433 if (md->md.ant.num == 3) {
2434 md->md.ant.type = BTC_ANT_DEDICATED;
2435 md->md.bt_pos = BTC_BT_ALONE;
2436 } else {
2437 md->md.ant.type = BTC_ANT_SHARED;
2438 md->md.bt_pos = BTC_BT_BTG;
2439 }
2440 rtwdev->btc.btg_pos = md->md.ant.btg_pos;
2441 rtwdev->btc.ant_type = md->md.ant.type;
2442 }
2443}
2444
2445static void rtw8852c_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en,
2446 enum rtw89_phy_idx phy_idx)
2447{
2448 if (en) {
2449 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
2450 B_PATH0_BT_SHARE_V1, 0x1);
2451 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
2452 B_PATH0_BTG_PATH_V1, 0x0);
2453 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1,
2454 B_PATH1_G_LNA6_OP1DB_V1, 0x20);
2455 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1,
2456 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x30);
2457 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1,
2458 B_PATH1_BT_SHARE_V1, 0x1);
2459 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1,
2460 B_PATH1_BTG_PATH_V1, 0x1);
2461 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0);
2462 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_BT_SHARE, 0x1);
2463 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_BT_SEG0, 0x2);
2464 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN,
2465 B_BT_DYN_DC_EST_EN_MSK, 0x1);
2466 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN,
2467 0x1);
2468 } else {
2469 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
2470 B_PATH0_BT_SHARE_V1, 0x0);
2471 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
2472 B_PATH0_BTG_PATH_V1, 0x0);
2473 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1,
2474 B_PATH1_G_LNA6_OP1DB_V1, 0x1a);
2475 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1,
2476 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a);
2477 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1,
2478 B_PATH1_BT_SHARE_V1, 0x0);
2479 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1,
2480 B_PATH1_BTG_PATH_V1, 0x0);
2481 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf);
2482 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4);
2483 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_BT_SHARE, 0x0);
2484 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_BT_SEG0, 0x0);
2485 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN,
2486 B_BT_DYN_DC_EST_EN_MSK, 0x0);
2487 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN,
2488 0x0);
2489 }
2490}
2491
2492static
2493void rtw8852c_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)
2494{
2495 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x20000);
2496 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group);
2497 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val);
2498 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0);
2499}
2500
2501static void rtw8852c_btc_init_cfg(struct rtw89_dev *rtwdev)
2502{
2503 struct rtw89_btc *btc = &rtwdev->btc;
2504 const struct rtw89_chip_info *chip = rtwdev->chip;
2505 const struct rtw89_mac_ax_coex coex_params = {
2506 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE,
2507 .direction = RTW89_MAC_AX_COEX_INNER,
2508 };
2509
2510 /* PTA init */
2511 rtw89_mac_coex_init_v1(rtwdev, &coex_params);
2512
2513 /* set WL Tx response = Hi-Pri */
2514 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true);
2515 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true);
2516
2517 /* set rf gnt debug off */
2518 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, RFREG_MASK, 0x0);
2519 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, RFREG_MASK, 0x0);
2520
2521 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */
2522 if (btc->ant_type == BTC_ANT_SHARED) {
2523 rtw8852c_set_trx_mask(rtwdev,
2524 RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff);
2525 rtw8852c_set_trx_mask(rtwdev,
2526 RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff);
2527 /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */
2528 rtw8852c_set_trx_mask(rtwdev,
2529 RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff);
2530 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */
2531 rtw8852c_set_trx_mask(rtwdev,
2532 RF_PATH_A, BTC_BT_SS_GROUP, 0x5df);
2533 rtw8852c_set_trx_mask(rtwdev,
2534 RF_PATH_B, BTC_BT_SS_GROUP, 0x5df);
2535 }
2536
2537 /* set PTA break table */
2538 rtw89_write32(rtwdev, R_AX_BT_BREAK_TABLE, BTC_BREAK_PARAM);
2539
2540 /* enable BT counter 0xda10[1:0] = 2b'11 */
2541 rtw89_write32_set(rtwdev,
2542 R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN |
2543 B_AX_BT_CNT_RST_V1);
2544 btc->cx.wl.status.map.init_ok = true;
2545}
2546
2547static
2548void rtw8852c_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state)
2549{
2550 u32 bitmap = 0;
2551 u32 reg = 0;
2552
2553 switch (map) {
2554 case BTC_PRI_MASK_TX_RESP:
2555 reg = R_BTC_COEX_WL_REQ;
2556 bitmap = B_BTC_RSP_ACK_HI;
2557 break;
2558 case BTC_PRI_MASK_BEACON:
2559 reg = R_BTC_COEX_WL_REQ;
2560 bitmap = B_BTC_TX_BCN_HI;
2561 break;
2562 default:
2563 return;
2564 }
2565
2566 if (state)
2567 rtw89_write32_set(rtwdev, reg, bitmap);
2568 else
2569 rtw89_write32_clr(rtwdev, reg, bitmap);
2570}
2571
2572union rtw8852c_btc_wl_txpwr_ctrl {
2573 u32 txpwr_val;
2574 struct {
2575 union {
2576 u16 ctrl_all_time;
2577 struct {
2578 s16 data:9;
2579 u16 rsvd:6;
2580 u16 flag:1;
2581 } all_time;
2582 };
2583 union {
2584 u16 ctrl_gnt_bt;
2585 struct {
2586 s16 data:9;
2587 u16 rsvd:7;
2588 } gnt_bt;
2589 };
2590 };
2591} __packed;
2592
2593static void
2594rtw8852c_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
2595{
2596 union rtw8852c_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val };
2597 s32 val;
2598
2599#define __write_ctrl(_reg, _msk, _val, _en, _cond) \
2600do { \
2601 u32 _wrt = FIELD_PREP(_msk, _val); \
2602 BUILD_BUG_ON((_msk & _en) != 0); \
2603 if (_cond) \
2604 _wrt |= _en; \
2605 else \
2606 _wrt &= ~_en; \
2607 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \
2608 _msk | _en, _wrt); \
2609} while (0)
2610
2611 switch (arg.ctrl_all_time) {
2612 case 0xffff:
2613 val = 0;
2614 break;
2615 default:
2616 val = arg.all_time.data;
2617 break;
2618 }
2619
2620 __write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK,
2621 val, B_AX_FORCE_PWR_BY_RATE_EN,
2622 arg.ctrl_all_time != 0xffff);
2623
2624 switch (arg.ctrl_gnt_bt) {
2625 case 0xffff:
2626 val = 0;
2627 break;
2628 default:
2629 val = arg.gnt_bt.data;
2630 break;
2631 }
2632
2633 __write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val,
2634 B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff);
2635
2636#undef __write_ctrl
2637}
2638
2639static
2640s8 rtw8852c_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
2641{
2642 /* +6 for compensate offset */
2643 return clamp_t(s8, val + 6, -100, 0) + 100;
2644}
2645
2646static const struct rtw89_btc_rf_trx_para rtw89_btc_8852c_rf_ul[] = {
2647 {255, 0, 0, 7}, /* 0 -> original */
2648 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
2649 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
2650 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
2651 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
2652 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
2653 {6, 1, 0, 7},
2654 {13, 1, 0, 7},
2655 {13, 1, 0, 7}
2656};
2657
2658static const struct rtw89_btc_rf_trx_para rtw89_btc_8852c_rf_dl[] = {
2659 {255, 0, 0, 7}, /* 0 -> original */
2660 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */
2661 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
2662 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
2663 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
2664 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
2665 {255, 1, 0, 7},
2666 {255, 1, 0, 7},
2667 {255, 1, 0, 7}
2668};
2669
2670static const u8 rtw89_btc_8852c_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30};
2671static const u8 rtw89_btc_8852c_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28};
2672
2673static const struct rtw89_btc_fbtc_mreg rtw89_btc_8852c_mon_reg[] = {
2674 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda00),
2675 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda04),
2676 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24),
2677 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30),
2678 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34),
2679 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda38),
2680 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda44),
2681 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda48),
2682 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c),
2683 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200),
2684 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220),
2685 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980),
2686 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4aa4),
2687 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4778),
2688 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x476c),
2689};
2690
2691static
2692void rtw8852c_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
2693{
2694 /* Feature move to firmware */
2695}
2696
2697static
2698void rtw8852c_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
2699{
2700 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000);
2701 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
2702 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x620);
2703
2704 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */
2705 if (state)
2706 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0,
2707 RFREG_MASK, 0x179c);
2708 else
2709 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0,
2710 RFREG_MASK, 0x208);
2711
2712 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
2713}
2714
2715static void rtw8852c_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level)
2716{
2717 /* level=0 Default: TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB
2718 * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB
2719 * To improve BT ACI in co-rx
2720 */
2721
2722 switch (level) {
2723 case 0: /* default */
2724 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000);
2725 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0);
2726 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
2727 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
2728 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17);
2729 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2);
2730 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
2731 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3);
2732 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17);
2733 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
2734 break;
2735 case 1: /* Fix LNA2=5 */
2736 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000);
2737 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0);
2738 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
2739 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
2740 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5);
2741 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2);
2742 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
2743 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3);
2744 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5);
2745 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
2746 break;
2747 }
2748}
2749
2750static void rtw8852c_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level)
2751{
2752 struct rtw89_btc *btc = &rtwdev->btc;
2753
2754 switch (level) {
2755 case 0: /* original */
2756 default:
2757 rtw8852c_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0);
2758 btc->dm.wl_lna2 = 0;
2759 break;
2760 case 1: /* for FDD free-run */
2761 rtw8852c_ctrl_nbtg_bt_tx(rtwdev, true, RTW89_PHY_0);
2762 btc->dm.wl_lna2 = 0;
2763 break;
2764 case 2: /* for BTG Co-Rx*/
2765 rtw8852c_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0);
2766 btc->dm.wl_lna2 = 1;
2767 break;
2768 }
2769
2770 rtw8852c_set_wl_lna2(rtwdev, btc->dm.wl_lna2);
2771}
2772
2773static void rtw8852c_fill_freq_with_ppdu(struct rtw89_dev *rtwdev,
2774 struct rtw89_rx_phy_ppdu *phy_ppdu,
2775 struct ieee80211_rx_status *status)
2776{
2777 u8 chan_idx = phy_ppdu->chan_idx;
2778 enum nl80211_band band;
2779 u8 ch;
2780
2781 if (chan_idx == 0)
2782 return;
2783
2784 rtw89_decode_chan_idx(rtwdev, chan_idx, &ch, &band);
2785 status->freq = ieee80211_channel_to_frequency(ch, band);
2786 status->band = band;
2787}
2788
2789static void rtw8852c_query_ppdu(struct rtw89_dev *rtwdev,
2790 struct rtw89_rx_phy_ppdu *phy_ppdu,
2791 struct ieee80211_rx_status *status)
2792{
2793 u8 path;
2794 u8 *rx_power = phy_ppdu->rssi;
2795
2796 status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A], rx_power[RF_PATH_B]));
2797 for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
2798 status->chains |= BIT(path);
2799 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]);
2800 }
2801 if (phy_ppdu->valid)
2802 rtw8852c_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);
2803}
2804
2805static int rtw8852c_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
2806{
2807 int ret;
2808
2809 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN,
2810 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
2811
2812 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2813 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2814 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2815
2816 rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S0_LDO_VSEL_F_MASK, 0x1);
2817 rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S1_LDO_VSEL_F_MASK, 0x1);
2818
2819 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL0, 0x7, FULL_BIT_MASK);
2820 if (ret)
2821 return ret;
2822
2823 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x6c, FULL_BIT_MASK);
2824 if (ret)
2825 return ret;
2826
2827 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xc7, FULL_BIT_MASK);
2828 if (ret)
2829 return ret;
2830
2831 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xc7, FULL_BIT_MASK);
2832 if (ret)
2833 return ret;
2834
2835 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL3, 0xd, FULL_BIT_MASK);
2836 if (ret)
2837 return ret;
2838
2839 return 0;
2840}
2841
2842static int rtw8852c_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
2843{
2844 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2845 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN,
2846 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
2847
2848 return 0;
2849}
2850
2851static const struct rtw89_chanctx_listener rtw8852c_chanctx_listener = {
2852 .callbacks[RTW89_CHANCTX_CALLBACK_RFK] = rtw8852c_rfk_chanctx_cb,
2853};
2854
2855#ifdef CONFIG_PM
2856static const struct wiphy_wowlan_support rtw_wowlan_stub_8852c = {
2857 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT |
2858 WIPHY_WOWLAN_NET_DETECT,
2859 .n_patterns = RTW89_MAX_PATTERN_NUM,
2860 .pattern_max_len = RTW89_MAX_PATTERN_SIZE,
2861 .pattern_min_len = 1,
2862 .max_nd_match_sets = RTW89_SCANOFLD_MAX_SSID,
2863};
2864#endif
2865
2866static const struct rtw89_chip_ops rtw8852c_chip_ops = {
2867 .enable_bb_rf = rtw8852c_mac_enable_bb_rf,
2868 .disable_bb_rf = rtw8852c_mac_disable_bb_rf,
2869 .bb_preinit = NULL,
2870 .bb_postinit = NULL,
2871 .bb_reset = rtw8852c_bb_reset,
2872 .bb_sethw = rtw8852c_bb_sethw,
2873 .read_rf = rtw89_phy_read_rf_v1,
2874 .write_rf = rtw89_phy_write_rf_v1,
2875 .set_channel = rtw8852c_set_channel,
2876 .set_channel_help = rtw8852c_set_channel_help,
2877 .read_efuse = rtw8852c_read_efuse,
2878 .read_phycap = rtw8852c_read_phycap,
2879 .fem_setup = NULL,
2880 .rfe_gpio = NULL,
2881 .rfk_hw_init = NULL,
2882 .rfk_init = rtw8852c_rfk_init,
2883 .rfk_init_late = NULL,
2884 .rfk_channel = rtw8852c_rfk_channel,
2885 .rfk_band_changed = rtw8852c_rfk_band_changed,
2886 .rfk_scan = rtw8852c_rfk_scan,
2887 .rfk_track = rtw8852c_rfk_track,
2888 .power_trim = rtw8852c_power_trim,
2889 .set_txpwr = rtw8852c_set_txpwr,
2890 .set_txpwr_ctrl = rtw8852c_set_txpwr_ctrl,
2891 .init_txpwr_unit = rtw8852c_init_txpwr_unit,
2892 .get_thermal = rtw8852c_get_thermal,
2893 .ctrl_btg_bt_rx = rtw8852c_ctrl_btg_bt_rx,
2894 .query_ppdu = rtw8852c_query_ppdu,
2895 .convert_rpl_to_rssi = NULL,
2896 .ctrl_nbtg_bt_tx = rtw8852c_ctrl_nbtg_bt_tx,
2897 .cfg_txrx_path = rtw8852c_bb_cfg_txrx_path,
2898 .set_txpwr_ul_tb_offset = rtw8852c_set_txpwr_ul_tb_offset,
2899 .digital_pwr_comp = NULL,
2900 .pwr_on_func = rtw8852c_pwr_on_func,
2901 .pwr_off_func = rtw8852c_pwr_off_func,
2902 .query_rxdesc = rtw89_core_query_rxdesc,
2903 .fill_txdesc = rtw89_core_fill_txdesc_v1,
2904 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc_fwcmd_v1,
2905 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path_v1,
2906 .mac_cfg_gnt = rtw89_mac_cfg_gnt_v1,
2907 .stop_sch_tx = rtw89_mac_stop_sch_tx_v1,
2908 .resume_sch_tx = rtw89_mac_resume_sch_tx_v1,
2909 .h2c_dctl_sec_cam = rtw89_fw_h2c_dctl_sec_cam_v1,
2910 .h2c_default_cmac_tbl = rtw89_fw_h2c_default_cmac_tbl,
2911 .h2c_assoc_cmac_tbl = rtw89_fw_h2c_assoc_cmac_tbl,
2912 .h2c_ampdu_cmac_tbl = NULL,
2913 .h2c_default_dmac_tbl = NULL,
2914 .h2c_update_beacon = rtw89_fw_h2c_update_beacon,
2915 .h2c_ba_cam = rtw89_fw_h2c_ba_cam,
2916
2917 .btc_set_rfe = rtw8852c_btc_set_rfe,
2918 .btc_init_cfg = rtw8852c_btc_init_cfg,
2919 .btc_set_wl_pri = rtw8852c_btc_set_wl_pri,
2920 .btc_set_wl_txpwr_ctrl = rtw8852c_btc_set_wl_txpwr_ctrl,
2921 .btc_get_bt_rssi = rtw8852c_btc_get_bt_rssi,
2922 .btc_update_bt_cnt = rtw8852c_btc_update_bt_cnt,
2923 .btc_wl_s1_standby = rtw8852c_btc_wl_s1_standby,
2924 .btc_set_wl_rx_gain = rtw8852c_btc_set_wl_rx_gain,
2925 .btc_set_policy = rtw89_btc_set_policy_v1,
2926};
2927
2928const struct rtw89_chip_info rtw8852c_chip_info = {
2929 .chip_id = RTL8852C,
2930 .chip_gen = RTW89_CHIP_AX,
2931 .ops = &rtw8852c_chip_ops,
2932 .mac_def = &rtw89_mac_gen_ax,
2933 .phy_def = &rtw89_phy_gen_ax,
2934 .fw_basename = RTW8852C_FW_BASENAME,
2935 .fw_format_max = RTW8852C_FW_FORMAT_MAX,
2936 .try_ce_fw = false,
2937 .bbmcu_nr = 0,
2938 .needed_fw_elms = 0,
2939 .fifo_size = 458752,
2940 .small_fifo_size = false,
2941 .dle_scc_rsvd_size = 0,
2942 .max_amsdu_limit = 8000,
2943 .dis_2g_40m_ul_ofdma = false,
2944 .rsvd_ple_ofst = 0x6f800,
2945 .hfc_param_ini = rtw8852c_hfc_param_ini_pcie,
2946 .dle_mem = rtw8852c_dle_mem_pcie,
2947 .wde_qempty_acq_grpnum = 16,
2948 .wde_qempty_mgq_grpsel = 16,
2949 .rf_base_addr = {0xe000, 0xf000},
2950 .thermal_th = {0x32, 0x35},
2951 .pwr_on_seq = NULL,
2952 .pwr_off_seq = NULL,
2953 .bb_table = &rtw89_8852c_phy_bb_table,
2954 .bb_gain_table = &rtw89_8852c_phy_bb_gain_table,
2955 .rf_table = {&rtw89_8852c_phy_radiob_table,
2956 &rtw89_8852c_phy_radioa_table,},
2957 .nctl_table = &rtw89_8852c_phy_nctl_table,
2958 .nctl_post_table = NULL,
2959 .dflt_parms = &rtw89_8852c_dflt_parms,
2960 .rfe_parms_conf = NULL,
2961 .chanctx_listener = &rtw8852c_chanctx_listener,
2962 .txpwr_factor_rf = 2,
2963 .txpwr_factor_mac = 1,
2964 .dig_table = NULL,
2965 .dig_regs = &rtw8852c_dig_regs,
2966 .tssi_dbw_table = &rtw89_8852c_tssi_dbw_table,
2967 .support_macid_num = RTW89_MAX_MAC_ID_NUM,
2968 .support_link_num = 0,
2969 .support_chanctx_num = 2,
2970 .support_rnr = false,
2971 .support_bands = BIT(NL80211_BAND_2GHZ) |
2972 BIT(NL80211_BAND_5GHZ) |
2973 BIT(NL80211_BAND_6GHZ),
2974 .support_bandwidths = BIT(NL80211_CHAN_WIDTH_20) |
2975 BIT(NL80211_CHAN_WIDTH_40) |
2976 BIT(NL80211_CHAN_WIDTH_80) |
2977 BIT(NL80211_CHAN_WIDTH_160),
2978 .support_unii4 = true,
2979 .ul_tb_waveform_ctrl = false,
2980 .ul_tb_pwr_diff = true,
2981 .hw_sec_hdr = true,
2982 .hw_mgmt_tx_encrypt = true,
2983 .rf_path_num = 2,
2984 .tx_nss = 2,
2985 .rx_nss = 2,
2986 .acam_num = 128,
2987 .bcam_num = 20,
2988 .scam_num = 128,
2989 .bacam_num = 8,
2990 .bacam_dynamic_num = 8,
2991 .bacam_ver = RTW89_BACAM_V0_EXT,
2992 .ppdu_max_usr = 8,
2993 .sec_ctrl_efuse_size = 4,
2994 .physical_efuse_size = 1216,
2995 .logical_efuse_size = 2048,
2996 .limit_efuse_size = 1280,
2997 .dav_phy_efuse_size = 96,
2998 .dav_log_efuse_size = 16,
2999 .efuse_blocks = NULL,
3000 .phycap_addr = 0x590,
3001 .phycap_size = 0x60,
3002 .para_ver = 0x1,
3003 .wlcx_desired = 0x06000000,
3004 .btcx_desired = 0x7,
3005 .scbd = 0x1,
3006 .mailbox = 0x1,
3007
3008 .afh_guard_ch = 6,
3009 .wl_rssi_thres = rtw89_btc_8852c_wl_rssi_thres,
3010 .bt_rssi_thres = rtw89_btc_8852c_bt_rssi_thres,
3011 .rssi_tol = 2,
3012 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852c_mon_reg),
3013 .mon_reg = rtw89_btc_8852c_mon_reg,
3014 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852c_rf_ul),
3015 .rf_para_ulink = rtw89_btc_8852c_rf_ul,
3016 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852c_rf_dl),
3017 .rf_para_dlink = rtw89_btc_8852c_rf_dl,
3018 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) |
3019 BIT(RTW89_PS_MODE_CLK_GATED) |
3020 BIT(RTW89_PS_MODE_PWR_GATED),
3021 .low_power_hci_modes = BIT(RTW89_PS_MODE_CLK_GATED) |
3022 BIT(RTW89_PS_MODE_PWR_GATED),
3023 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD_V1,
3024 .hci_func_en_addr = R_AX_HCI_FUNC_EN_V1,
3025 .h2c_desc_size = sizeof(struct rtw89_rxdesc_short),
3026 .txwd_body_size = sizeof(struct rtw89_txwd_body_v1),
3027 .txwd_info_size = sizeof(struct rtw89_txwd_info),
3028 .h2c_ctrl_reg = R_AX_H2CREG_CTRL_V1,
3029 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8},
3030 .h2c_regs = rtw8852c_h2c_regs,
3031 .c2h_ctrl_reg = R_AX_C2HREG_CTRL_V1,
3032 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
3033 .c2h_regs = rtw8852c_c2h_regs,
3034 .page_regs = &rtw8852c_page_regs,
3035 .wow_reason_reg = rtw8852c_wow_wakeup_regs,
3036 .cfo_src_fd = false,
3037 .cfo_hw_comp = false,
3038 .dcfo_comp = &rtw8852c_dcfo_comp,
3039 .dcfo_comp_sft = 12,
3040 .imr_info = &rtw8852c_imr_info,
3041 .imr_dmac_table = NULL,
3042 .imr_cmac_table = NULL,
3043 .rrsr_cfgs = &rtw8852c_rrsr_cfgs,
3044 .bss_clr_vld = {R_BSS_CLR_MAP, B_BSS_CLR_MAP_VLD0},
3045 .bss_clr_map_reg = R_BSS_CLR_MAP,
3046 .rfkill_init = &rtw8852c_rfkill_regs,
3047 .rfkill_get = {R_AX_GPIO_EXT_CTRL, B_AX_GPIO_IN_9},
3048 .dma_ch_mask = 0,
3049 .edcca_regs = &rtw8852c_edcca_regs,
3050#ifdef CONFIG_PM
3051 .wowlan_stub = &rtw_wowlan_stub_8852c,
3052#endif
3053 .xtal_info = NULL,
3054};
3055EXPORT_SYMBOL(rtw8852c_chip_info);
3056
3057MODULE_FIRMWARE(RTW8852C_MODULE_FIRMWARE);
3058MODULE_AUTHOR("Realtek Corporation");
3059MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852C driver");
3060MODULE_LICENSE("Dual BSD/GPL");