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1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5#ifndef __RTW89_FW_H__
6#define __RTW89_FW_H__
7
8#include "core.h"
9
10enum rtw89_fw_dl_status {
11 RTW89_FWDL_INITIAL_STATE = 0,
12 RTW89_FWDL_FWDL_ONGOING = 1,
13 RTW89_FWDL_CHECKSUM_FAIL = 2,
14 RTW89_FWDL_SECURITY_FAIL = 3,
15 RTW89_FWDL_CV_NOT_MATCH = 4,
16 RTW89_FWDL_RSVD0 = 5,
17 RTW89_FWDL_WCPU_FWDL_RDY = 6,
18 RTW89_FWDL_WCPU_FW_INIT_RDY = 7
19};
20
21struct rtw89_c2hreg_hdr {
22 u32 w0;
23};
24
25#define RTW89_C2HREG_HDR_FUNC_MASK GENMASK(6, 0)
26#define RTW89_C2HREG_HDR_ACK BIT(7)
27#define RTW89_C2HREG_HDR_LEN_MASK GENMASK(11, 8)
28#define RTW89_C2HREG_HDR_SEQ_MASK GENMASK(15, 12)
29
30struct rtw89_c2hreg_phycap {
31 u32 w0;
32 u32 w1;
33 u32 w2;
34 u32 w3;
35} __packed;
36
37#define RTW89_C2HREG_PHYCAP_W0_FUNC GENMASK(6, 0)
38#define RTW89_C2HREG_PHYCAP_W0_ACK BIT(7)
39#define RTW89_C2HREG_PHYCAP_W0_LEN GENMASK(11, 8)
40#define RTW89_C2HREG_PHYCAP_W0_SEQ GENMASK(15, 12)
41#define RTW89_C2HREG_PHYCAP_W0_RX_NSS GENMASK(23, 16)
42#define RTW89_C2HREG_PHYCAP_W0_BW GENMASK(31, 24)
43#define RTW89_C2HREG_PHYCAP_W1_TX_NSS GENMASK(7, 0)
44#define RTW89_C2HREG_PHYCAP_W1_PROT GENMASK(15, 8)
45#define RTW89_C2HREG_PHYCAP_W1_NIC GENMASK(23, 16)
46#define RTW89_C2HREG_PHYCAP_W1_WL_FUNC GENMASK(31, 24)
47#define RTW89_C2HREG_PHYCAP_W2_HW_TYPE GENMASK(7, 0)
48#define RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM GENMASK(15, 8)
49#define RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM GENMASK(23, 16)
50
51#define RTW89_C2HREG_AOAC_RPT_1_W0_KEY_IDX GENMASK(23, 16)
52#define RTW89_C2HREG_AOAC_RPT_1_W1_IV_0 GENMASK(7, 0)
53#define RTW89_C2HREG_AOAC_RPT_1_W1_IV_1 GENMASK(15, 8)
54#define RTW89_C2HREG_AOAC_RPT_1_W1_IV_2 GENMASK(23, 16)
55#define RTW89_C2HREG_AOAC_RPT_1_W1_IV_3 GENMASK(31, 24)
56#define RTW89_C2HREG_AOAC_RPT_1_W2_IV_4 GENMASK(7, 0)
57#define RTW89_C2HREG_AOAC_RPT_1_W2_IV_5 GENMASK(15, 8)
58#define RTW89_C2HREG_AOAC_RPT_1_W2_IV_6 GENMASK(23, 16)
59#define RTW89_C2HREG_AOAC_RPT_1_W2_IV_7 GENMASK(31, 24)
60#define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_0 GENMASK(7, 0)
61#define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_1 GENMASK(15, 8)
62#define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_2 GENMASK(23, 16)
63#define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_3 GENMASK(31, 24)
64#define RTW89_C2HREG_AOAC_RPT_2_W0_PTK_IV_4 GENMASK(23, 16)
65#define RTW89_C2HREG_AOAC_RPT_2_W0_PTK_IV_5 GENMASK(31, 24)
66#define RTW89_C2HREG_AOAC_RPT_2_W1_PTK_IV_6 GENMASK(7, 0)
67#define RTW89_C2HREG_AOAC_RPT_2_W1_PTK_IV_7 GENMASK(15, 8)
68#define RTW89_C2HREG_AOAC_RPT_2_W1_IGTK_IPN_IV_0 GENMASK(23, 16)
69#define RTW89_C2HREG_AOAC_RPT_2_W1_IGTK_IPN_IV_1 GENMASK(31, 24)
70#define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_2 GENMASK(7, 0)
71#define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_3 GENMASK(15, 8)
72#define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_4 GENMASK(23, 16)
73#define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_5 GENMASK(31, 24)
74#define RTW89_C2HREG_AOAC_RPT_2_W3_IGTK_IPN_IV_6 GENMASK(7, 0)
75#define RTW89_C2HREG_AOAC_RPT_2_W3_IGTK_IPN_IV_7 GENMASK(15, 8)
76
77struct rtw89_h2creg_hdr {
78 u32 w0;
79};
80
81#define RTW89_H2CREG_HDR_FUNC_MASK GENMASK(6, 0)
82#define RTW89_H2CREG_HDR_LEN_MASK GENMASK(11, 8)
83
84struct rtw89_h2creg_sch_tx_en {
85 u32 w0;
86 u32 w1;
87} __packed;
88
89#define RTW89_H2CREG_SCH_TX_EN_W0_EN GENMASK(31, 16)
90#define RTW89_H2CREG_SCH_TX_EN_W1_MASK GENMASK(15, 0)
91#define RTW89_H2CREG_SCH_TX_EN_W1_BAND BIT(16)
92
93#define RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN GENMASK(23, 16)
94
95#define RTW89_H2CREG_MAX 4
96#define RTW89_C2HREG_MAX 4
97#define RTW89_C2HREG_HDR_LEN 2
98#define RTW89_H2CREG_HDR_LEN 2
99#define RTW89_C2H_TIMEOUT 1000000
100struct rtw89_mac_c2h_info {
101 u8 id;
102 u8 content_len;
103 union {
104 u32 c2hreg[RTW89_C2HREG_MAX];
105 struct rtw89_c2hreg_hdr hdr;
106 struct rtw89_c2hreg_phycap phycap;
107 } u;
108};
109
110struct rtw89_mac_h2c_info {
111 u8 id;
112 u8 content_len;
113 union {
114 u32 h2creg[RTW89_H2CREG_MAX];
115 struct rtw89_h2creg_hdr hdr;
116 struct rtw89_h2creg_sch_tx_en sch_tx_en;
117 } u;
118};
119
120enum rtw89_mac_h2c_type {
121 RTW89_FWCMD_H2CREG_FUNC_H2CREG_LB = 0,
122 RTW89_FWCMD_H2CREG_FUNC_CNSL_CMD,
123 RTW89_FWCMD_H2CREG_FUNC_FWERR,
124 RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE,
125 RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM,
126 RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN,
127 RTW89_FWCMD_H2CREG_FUNC_WOW_TRX_STOP,
128 RTW89_FWCMD_H2CREG_FUNC_AOAC_RPT_1,
129 RTW89_FWCMD_H2CREG_FUNC_AOAC_RPT_2,
130 RTW89_FWCMD_H2CREG_FUNC_AOAC_RPT_3_REQ,
131 RTW89_FWCMD_H2CREG_FUNC_WOW_CPUIO_RX_CTRL,
132};
133
134enum rtw89_mac_c2h_type {
135 RTW89_FWCMD_C2HREG_FUNC_C2HREG_LB = 0,
136 RTW89_FWCMD_C2HREG_FUNC_ERR_RPT,
137 RTW89_FWCMD_C2HREG_FUNC_ERR_MSG,
138 RTW89_FWCMD_C2HREG_FUNC_PHY_CAP,
139 RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT,
140 RTW89_FWCMD_C2HREG_FUNC_WOW_CPUIO_RX_ACK = 0xA,
141 RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF,
142};
143
144enum rtw89_fw_c2h_category {
145 RTW89_C2H_CAT_TEST,
146 RTW89_C2H_CAT_MAC,
147 RTW89_C2H_CAT_OUTSRC,
148};
149
150enum rtw89_fw_log_level {
151 RTW89_FW_LOG_LEVEL_OFF,
152 RTW89_FW_LOG_LEVEL_CRT,
153 RTW89_FW_LOG_LEVEL_SER,
154 RTW89_FW_LOG_LEVEL_WARN,
155 RTW89_FW_LOG_LEVEL_LOUD,
156 RTW89_FW_LOG_LEVEL_TR,
157};
158
159enum rtw89_fw_log_path {
160 RTW89_FW_LOG_LEVEL_UART,
161 RTW89_FW_LOG_LEVEL_C2H,
162 RTW89_FW_LOG_LEVEL_SNI,
163};
164
165enum rtw89_fw_log_comp {
166 RTW89_FW_LOG_COMP_VER,
167 RTW89_FW_LOG_COMP_INIT,
168 RTW89_FW_LOG_COMP_TASK,
169 RTW89_FW_LOG_COMP_CNS,
170 RTW89_FW_LOG_COMP_H2C,
171 RTW89_FW_LOG_COMP_C2H,
172 RTW89_FW_LOG_COMP_TX,
173 RTW89_FW_LOG_COMP_RX,
174 RTW89_FW_LOG_COMP_IPSEC,
175 RTW89_FW_LOG_COMP_TIMER,
176 RTW89_FW_LOG_COMP_DBGPKT,
177 RTW89_FW_LOG_COMP_PS,
178 RTW89_FW_LOG_COMP_ERROR,
179 RTW89_FW_LOG_COMP_WOWLAN,
180 RTW89_FW_LOG_COMP_SECURE_BOOT,
181 RTW89_FW_LOG_COMP_BTC,
182 RTW89_FW_LOG_COMP_BB,
183 RTW89_FW_LOG_COMP_TWT,
184 RTW89_FW_LOG_COMP_RF,
185 RTW89_FW_LOG_COMP_MCC = 20,
186 RTW89_FW_LOG_COMP_SCAN = 28,
187};
188
189enum rtw89_pkt_offload_op {
190 RTW89_PKT_OFLD_OP_ADD,
191 RTW89_PKT_OFLD_OP_DEL,
192 RTW89_PKT_OFLD_OP_READ,
193
194 NUM_OF_RTW89_PKT_OFFLOAD_OP,
195};
196
197#define RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op) \
198 ((pkt_id) * NUM_OF_RTW89_PKT_OFFLOAD_OP + (pkt_op))
199
200enum rtw89_scanofld_notify_reason {
201 RTW89_SCAN_DWELL_NOTIFY,
202 RTW89_SCAN_PRE_TX_NOTIFY,
203 RTW89_SCAN_POST_TX_NOTIFY,
204 RTW89_SCAN_ENTER_CH_NOTIFY,
205 RTW89_SCAN_LEAVE_CH_NOTIFY,
206 RTW89_SCAN_END_SCAN_NOTIFY,
207 RTW89_SCAN_REPORT_NOTIFY,
208 RTW89_SCAN_CHKPT_NOTIFY,
209 RTW89_SCAN_ENTER_OP_NOTIFY,
210 RTW89_SCAN_LEAVE_OP_NOTIFY,
211};
212
213enum rtw89_scanofld_status {
214 RTW89_SCAN_STATUS_NOTIFY,
215 RTW89_SCAN_STATUS_SUCCESS,
216 RTW89_SCAN_STATUS_FAIL,
217};
218
219enum rtw89_chan_type {
220 RTW89_CHAN_OPERATE = 0,
221 RTW89_CHAN_ACTIVE,
222 RTW89_CHAN_DFS,
223};
224
225enum rtw89_p2pps_action {
226 RTW89_P2P_ACT_INIT = 0,
227 RTW89_P2P_ACT_UPDATE = 1,
228 RTW89_P2P_ACT_REMOVE = 2,
229 RTW89_P2P_ACT_TERMINATE = 3,
230};
231
232#define RTW89_DEFAULT_CQM_HYST 4
233#define RTW89_DEFAULT_CQM_THOLD -70
234
235enum rtw89_bcn_fltr_offload_mode {
236 RTW89_BCN_FLTR_OFFLOAD_MODE_0 = 0,
237 RTW89_BCN_FLTR_OFFLOAD_MODE_1,
238 RTW89_BCN_FLTR_OFFLOAD_MODE_2,
239 RTW89_BCN_FLTR_OFFLOAD_MODE_3,
240
241 RTW89_BCN_FLTR_OFFLOAD_MODE_DEFAULT = RTW89_BCN_FLTR_OFFLOAD_MODE_0,
242};
243
244enum rtw89_bcn_fltr_type {
245 RTW89_BCN_FLTR_BEACON_LOSS,
246 RTW89_BCN_FLTR_RSSI,
247 RTW89_BCN_FLTR_NOTIFY,
248};
249
250enum rtw89_bcn_fltr_rssi_event {
251 RTW89_BCN_FLTR_RSSI_NOT_CHANGED,
252 RTW89_BCN_FLTR_RSSI_HIGH,
253 RTW89_BCN_FLTR_RSSI_LOW,
254};
255
256#define FWDL_SECTION_MAX_NUM 10
257#define FWDL_SECTION_CHKSUM_LEN 8
258#define FWDL_SECTION_PER_PKT_LEN 2020
259
260struct rtw89_fw_hdr_section_info {
261 u8 redl;
262 const u8 *addr;
263 u32 len;
264 u32 len_override;
265 u32 dladdr;
266 u32 mssc;
267 u8 type;
268 bool ignore;
269 const u8 *key_addr;
270 u32 key_len;
271 u32 key_idx;
272};
273
274struct rtw89_fw_bin_info {
275 u8 section_num;
276 u32 hdr_len;
277 bool dynamic_hdr_en;
278 u32 dynamic_hdr_len;
279 u8 idmem_share_mode;
280 bool dsp_checksum;
281 bool secure_section_exist;
282 struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM];
283};
284
285struct rtw89_fw_macid_pause_grp {
286 __le32 pause_grp[4];
287 __le32 mask_grp[4];
288} __packed;
289
290struct rtw89_fw_macid_pause_sleep_grp {
291 struct {
292 __le32 pause_grp[4];
293 __le32 pause_mask_grp[4];
294 __le32 sleep_grp[4];
295 __le32 sleep_mask_grp[4];
296 } __packed n[4];
297} __packed;
298
299#define RTW89_H2C_MAX_SIZE 2048
300#define RTW89_CHANNEL_TIME 45
301#define RTW89_CHANNEL_TIME_6G 20
302#define RTW89_DFS_CHAN_TIME 105
303#define RTW89_OFF_CHAN_TIME 100
304#define RTW89_DWELL_TIME 20
305#define RTW89_DWELL_TIME_6G 10
306#define RTW89_SCAN_WIDTH 0
307#define RTW89_SCANOFLD_MAX_SSID 8
308#define RTW89_SCANOFLD_MAX_IE_LEN 512
309#define RTW89_SCANOFLD_PKT_NONE 0xFF
310#define RTW89_SCANOFLD_DEBUG_MASK 0x1F
311#define RTW89_CHAN_INVALID 0xFF
312#define RTW89_MAC_CHINFO_SIZE 28
313#define RTW89_SCAN_LIST_GUARD 4
314#define RTW89_SCAN_LIST_LIMIT \
315 ((RTW89_H2C_MAX_SIZE / RTW89_MAC_CHINFO_SIZE) - RTW89_SCAN_LIST_GUARD)
316
317#define RTW89_BCN_LOSS_CNT 10
318
319struct rtw89_mac_chinfo {
320 u8 period;
321 u8 dwell_time;
322 u8 central_ch;
323 u8 pri_ch;
324 u8 bw:3;
325 u8 notify_action:5;
326 u8 num_pkt:4;
327 u8 tx_pkt:1;
328 u8 pause_data:1;
329 u8 ch_band:2;
330 u8 probe_id;
331 u8 dfs_ch:1;
332 u8 tx_null:1;
333 u8 rand_seq_num:1;
334 u8 cfg_tx_pwr:1;
335 u8 rsvd0: 4;
336 u8 pkt_id[RTW89_SCANOFLD_MAX_SSID];
337 u16 tx_pwr_idx;
338 u8 rsvd1;
339 struct list_head list;
340 bool is_psc;
341};
342
343struct rtw89_mac_chinfo_be {
344 u8 period;
345 u8 dwell_time;
346 u8 central_ch;
347 u8 pri_ch;
348 u8 bw:3;
349 u8 ch_band:2;
350 u8 dfs_ch:1;
351 u8 pause_data:1;
352 u8 tx_null:1;
353 u8 rand_seq_num:1;
354 u8 notify_action:5;
355 u8 probe_id;
356 u8 leave_crit;
357 u8 chkpt_timer;
358 u8 leave_time;
359 u8 leave_th;
360 u16 tx_pkt_ctrl;
361 u8 pkt_id[RTW89_SCANOFLD_MAX_SSID];
362 u8 sw_def;
363 u16 fw_probe0_ssids;
364 u16 fw_probe0_shortssids;
365 u16 fw_probe0_bssids;
366
367 struct list_head list;
368 bool is_psc;
369};
370
371struct rtw89_pktofld_info {
372 struct list_head list;
373 u8 id;
374 bool wildcard_6ghz;
375
376 /* Below fields are for WiFi 6 chips 6 GHz RNR use only */
377 u8 ssid[IEEE80211_MAX_SSID_LEN];
378 u8 ssid_len;
379 u8 bssid[ETH_ALEN];
380 u16 channel_6ghz;
381 bool cancel;
382};
383
384struct rtw89_h2c_ra {
385 __le32 w0;
386 __le32 w1;
387 __le32 w2;
388 __le32 w3;
389} __packed;
390
391#define RTW89_H2C_RA_W0_IS_DIS BIT(0)
392#define RTW89_H2C_RA_W0_MODE GENMASK(5, 1)
393#define RTW89_H2C_RA_W0_BW_CAP GENMASK(7, 6)
394#define RTW89_H2C_RA_W0_MACID GENMASK(15, 8)
395#define RTW89_H2C_RA_W0_DCM BIT(16)
396#define RTW89_H2C_RA_W0_ER BIT(17)
397#define RTW89_H2C_RA_W0_INIT_RATE_LV GENMASK(19, 18)
398#define RTW89_H2C_RA_W0_UPD_ALL BIT(20)
399#define RTW89_H2C_RA_W0_SGI BIT(21)
400#define RTW89_H2C_RA_W0_LDPC BIT(22)
401#define RTW89_H2C_RA_W0_STBC BIT(23)
402#define RTW89_H2C_RA_W0_SS_NUM GENMASK(26, 24)
403#define RTW89_H2C_RA_W0_GILTF GENMASK(29, 27)
404#define RTW89_H2C_RA_W0_UPD_BW_NSS_MASK BIT(30)
405#define RTW89_H2C_RA_W0_UPD_MASK BIT(31)
406#define RTW89_H2C_RA_W1_RAMASK_LO32 GENMASK(31, 0)
407#define RTW89_H2C_RA_W2_RAMASK_HI32 GENMASK(30, 0)
408#define RTW89_H2C_RA_W2_BFEE_CSI_CTL BIT(31)
409#define RTW89_H2C_RA_W3_BAND_NUM GENMASK(7, 0)
410#define RTW89_H2C_RA_W3_RA_CSI_RATE_EN BIT(8)
411#define RTW89_H2C_RA_W3_FIXED_CSI_RATE_EN BIT(9)
412#define RTW89_H2C_RA_W3_CR_TBL_SEL BIT(10)
413#define RTW89_H2C_RA_W3_FIX_GILTF_EN BIT(11)
414#define RTW89_H2C_RA_W3_FIX_GILTF GENMASK(14, 12)
415#define RTW89_H2C_RA_W3_FIXED_CSI_MCS_SS_IDX GENMASK(23, 16)
416#define RTW89_H2C_RA_W3_FIXED_CSI_MODE GENMASK(25, 24)
417#define RTW89_H2C_RA_W3_FIXED_CSI_GI_LTF GENMASK(28, 26)
418#define RTW89_H2C_RA_W3_FIXED_CSI_BW GENMASK(31, 29)
419
420struct rtw89_h2c_ra_v1 {
421 struct rtw89_h2c_ra v0;
422 __le32 w4;
423 __le32 w5;
424} __packed;
425
426#define RTW89_H2C_RA_V1_W4_MODE_EHT GENMASK(6, 0)
427#define RTW89_H2C_RA_V1_W4_BW_EHT GENMASK(10, 8)
428#define RTW89_H2C_RA_V1_W4_RAMASK_UHL16 GENMASK(31, 16)
429#define RTW89_H2C_RA_V1_W5_RAMASK_UHH16 GENMASK(15, 0)
430
431static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val)
432{
433 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0));
434}
435
436static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val)
437{
438 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8));
439}
440
441static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val)
442{
443 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16));
444}
445
446static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val)
447{
448 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0));
449}
450
451static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val)
452{
453 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4));
454}
455
456static inline void RTW89_SET_FWCMD_SEC_SPP_MODE(void *cmd, u32 val)
457{
458 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5));
459}
460
461static inline void RTW89_SET_FWCMD_SEC_KEY0(void *cmd, u32 val)
462{
463 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(31, 0));
464}
465
466static inline void RTW89_SET_FWCMD_SEC_KEY1(void *cmd, u32 val)
467{
468 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 0));
469}
470
471static inline void RTW89_SET_FWCMD_SEC_KEY2(void *cmd, u32 val)
472{
473 le32p_replace_bits((__le32 *)(cmd) + 0x04, val, GENMASK(31, 0));
474}
475
476static inline void RTW89_SET_FWCMD_SEC_KEY3(void *cmd, u32 val)
477{
478 le32p_replace_bits((__le32 *)(cmd) + 0x05, val, GENMASK(31, 0));
479}
480
481static inline void RTW89_SET_EDCA_SEL(void *cmd, u32 val)
482{
483 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(1, 0));
484}
485
486static inline void RTW89_SET_EDCA_BAND(void *cmd, u32 val)
487{
488 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3));
489}
490
491static inline void RTW89_SET_EDCA_WMM(void *cmd, u32 val)
492{
493 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4));
494}
495
496static inline void RTW89_SET_EDCA_AC(void *cmd, u32 val)
497{
498 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(6, 5));
499}
500
501static inline void RTW89_SET_EDCA_PARAM(void *cmd, u32 val)
502{
503 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 0));
504}
505#define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16)
506#define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12)
507#define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8)
508#define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0)
509
510#define FWDL_SECURITY_SECTION_TYPE 9
511#define FWDL_SECURITY_SIGLEN 512
512#define FWDL_SECURITY_CHKSUM_LEN 8
513
514struct rtw89_fw_dynhdr_sec {
515 __le32 w0;
516 u8 content[];
517} __packed;
518
519struct rtw89_fw_dynhdr_hdr {
520 __le32 hdr_len;
521 __le32 setcion_count;
522 /* struct rtw89_fw_dynhdr_sec (nested flexible structures) */
523} __packed;
524
525struct rtw89_fw_hdr_section {
526 __le32 w0;
527 __le32 w1;
528 __le32 w2;
529 __le32 w3;
530} __packed;
531
532#define FWSECTION_HDR_W0_DL_ADDR GENMASK(31, 0)
533#define FWSECTION_HDR_W1_METADATA GENMASK(31, 24)
534#define FWSECTION_HDR_W1_SECTIONTYPE GENMASK(27, 24)
535#define FWSECTION_HDR_W1_SEC_SIZE GENMASK(23, 0)
536#define FWSECTION_HDR_W1_CHECKSUM BIT(28)
537#define FWSECTION_HDR_W1_REDL BIT(29)
538#define FWSECTION_HDR_W2_MSSC GENMASK(31, 0)
539
540struct rtw89_fw_hdr {
541 __le32 w0;
542 __le32 w1;
543 __le32 w2;
544 __le32 w3;
545 __le32 w4;
546 __le32 w5;
547 __le32 w6;
548 __le32 w7;
549 struct rtw89_fw_hdr_section sections[];
550 /* struct rtw89_fw_dynhdr_hdr (optional) */
551} __packed;
552
553#define FW_HDR_W1_MAJOR_VERSION GENMASK(7, 0)
554#define FW_HDR_W1_MINOR_VERSION GENMASK(15, 8)
555#define FW_HDR_W1_SUBVERSION GENMASK(23, 16)
556#define FW_HDR_W1_SUBINDEX GENMASK(31, 24)
557#define FW_HDR_W2_COMMITID GENMASK(31, 0)
558#define FW_HDR_W3_LEN GENMASK(23, 16)
559#define FW_HDR_W3_HDR_VER GENMASK(31, 24)
560#define FW_HDR_W4_MONTH GENMASK(7, 0)
561#define FW_HDR_W4_DATE GENMASK(15, 8)
562#define FW_HDR_W4_HOUR GENMASK(23, 16)
563#define FW_HDR_W4_MIN GENMASK(31, 24)
564#define FW_HDR_W5_YEAR GENMASK(31, 0)
565#define FW_HDR_W6_SEC_NUM GENMASK(15, 8)
566#define FW_HDR_W7_PART_SIZE GENMASK(15, 0)
567#define FW_HDR_W7_DYN_HDR BIT(16)
568#define FW_HDR_W7_IDMEM_SHARE_MODE GENMASK(21, 18)
569#define FW_HDR_W7_CMD_VERSERION GENMASK(31, 24)
570
571struct rtw89_fw_hdr_section_v1 {
572 __le32 w0;
573 __le32 w1;
574 __le32 w2;
575 __le32 w3;
576} __packed;
577
578#define FWSECTION_HDR_V1_W0_DL_ADDR GENMASK(31, 0)
579#define FWSECTION_HDR_V1_W1_METADATA GENMASK(31, 24)
580#define FWSECTION_HDR_V1_W1_SECTIONTYPE GENMASK(27, 24)
581#define FWSECTION_HDR_V1_W1_SEC_SIZE GENMASK(23, 0)
582#define FWSECTION_HDR_V1_W1_CHECKSUM BIT(28)
583#define FWSECTION_HDR_V1_W1_REDL BIT(29)
584#define FWSECTION_HDR_V1_W2_MSSC GENMASK(7, 0)
585#define FORMATTED_MSSC 0xFF
586#define FORMATTED_MSSC_MASK GENMASK(7, 0)
587#define FWSECTION_HDR_V1_W2_BBMCU_IDX GENMASK(27, 24)
588
589struct rtw89_fw_hdr_v1 {
590 __le32 w0;
591 __le32 w1;
592 __le32 w2;
593 __le32 w3;
594 __le32 w4;
595 __le32 w5;
596 __le32 w6;
597 __le32 w7;
598 __le32 w8;
599 __le32 w9;
600 __le32 w10;
601 __le32 w11;
602 struct rtw89_fw_hdr_section_v1 sections[];
603} __packed;
604
605#define FW_HDR_V1_W1_MAJOR_VERSION GENMASK(7, 0)
606#define FW_HDR_V1_W1_MINOR_VERSION GENMASK(15, 8)
607#define FW_HDR_V1_W1_SUBVERSION GENMASK(23, 16)
608#define FW_HDR_V1_W1_SUBINDEX GENMASK(31, 24)
609#define FW_HDR_V1_W2_COMMITID GENMASK(31, 0)
610#define FW_HDR_V1_W3_CMD_VERSERION GENMASK(23, 16)
611#define FW_HDR_V1_W3_HDR_VER GENMASK(31, 24)
612#define FW_HDR_V1_W4_MONTH GENMASK(7, 0)
613#define FW_HDR_V1_W4_DATE GENMASK(15, 8)
614#define FW_HDR_V1_W4_HOUR GENMASK(23, 16)
615#define FW_HDR_V1_W4_MIN GENMASK(31, 24)
616#define FW_HDR_V1_W5_YEAR GENMASK(15, 0)
617#define FW_HDR_V1_W5_HDR_SIZE GENMASK(31, 16)
618#define FW_HDR_V1_W6_SEC_NUM GENMASK(15, 8)
619#define FW_HDR_V1_W6_DSP_CHKSUM BIT(24)
620#define FW_HDR_V1_W7_PART_SIZE GENMASK(15, 0)
621#define FW_HDR_V1_W7_DYN_HDR BIT(16)
622#define FW_HDR_V1_W7_IDMEM_SHARE_MODE GENMASK(21, 18)
623
624enum rtw89_fw_mss_pool_rmp_tbl_type {
625 MSS_POOL_RMP_TBL_BITMASK = 0x0,
626 MSS_POOL_RMP_TBL_RECORD = 0x1,
627};
628
629#define FWDL_MSS_POOL_DEFKEYSETS_SIZE 8
630
631struct rtw89_fw_mss_pool_hdr {
632 u8 signature[8]; /* equal to mss_signature[] */
633 __le32 rmp_tbl_offset;
634 __le32 key_raw_offset;
635 u8 defen;
636 u8 rsvd[3];
637 u8 rmpfmt; /* enum rtw89_fw_mss_pool_rmp_tbl_type */
638 u8 mssdev_max;
639 __le16 keypair_num;
640 __le16 msscust_max;
641 __le16 msskey_num_max;
642 __le32 rsvd3;
643 u8 rmp_tbl[];
644} __packed;
645
646union rtw89_fw_section_mssc_content {
647 struct {
648 u8 pad[58];
649 __le32 v;
650 } __packed sb_sel_ver;
651 struct {
652 u8 pad[60];
653 __le16 v;
654 } __packed key_sign_len;
655} __packed;
656
657static inline void SET_CTRL_INFO_MACID(void *table, u32 val)
658{
659 le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0));
660}
661
662static inline void SET_CTRL_INFO_OPERATION(void *table, u32 val)
663{
664 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7));
665}
666#define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0)
667static inline void SET_CMC_TBL_DATARATE(void *table, u32 val)
668{
669 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(8, 0));
670 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATARATE,
671 GENMASK(8, 0));
672}
673#define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0)
674static inline void SET_CMC_TBL_FORCE_TXOP(void *table, u32 val)
675{
676 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9));
677 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_FORCE_TXOP,
678 BIT(9));
679}
680#define SET_CMC_TBL_MASK_DATA_BW GENMASK(1, 0)
681static inline void SET_CMC_TBL_DATA_BW(void *table, u32 val)
682{
683 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(11, 10));
684 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_BW,
685 GENMASK(11, 10));
686}
687#define SET_CMC_TBL_MASK_DATA_GI_LTF GENMASK(2, 0)
688static inline void SET_CMC_TBL_DATA_GI_LTF(void *table, u32 val)
689{
690 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 12));
691 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_GI_LTF,
692 GENMASK(14, 12));
693}
694#define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0)
695static inline void SET_CMC_TBL_DARF_TC_INDEX(void *table, u32 val)
696{
697 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15));
698 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DARF_TC_INDEX,
699 BIT(15));
700}
701#define SET_CMC_TBL_MASK_ARFR_CTRL GENMASK(3, 0)
702static inline void SET_CMC_TBL_ARFR_CTRL(void *table, u32 val)
703{
704 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(19, 16));
705 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ARFR_CTRL,
706 GENMASK(19, 16));
707}
708#define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0)
709static inline void SET_CMC_TBL_ACQ_RPT_EN(void *table, u32 val)
710{
711 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20));
712 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ACQ_RPT_EN,
713 BIT(20));
714}
715#define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0)
716static inline void SET_CMC_TBL_MGQ_RPT_EN(void *table, u32 val)
717{
718 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21));
719 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_MGQ_RPT_EN,
720 BIT(21));
721}
722#define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0)
723static inline void SET_CMC_TBL_ULQ_RPT_EN(void *table, u32 val)
724{
725 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22));
726 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ULQ_RPT_EN,
727 BIT(22));
728}
729#define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0)
730static inline void SET_CMC_TBL_TWTQ_RPT_EN(void *table, u32 val)
731{
732 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23));
733 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TWTQ_RPT_EN,
734 BIT(23));
735}
736#define SET_CMC_TBL_MASK_DISRTSFB BIT(0)
737static inline void SET_CMC_TBL_DISRTSFB(void *table, u32 val)
738{
739 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25));
740 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISRTSFB,
741 BIT(25));
742}
743#define SET_CMC_TBL_MASK_DISDATAFB BIT(0)
744static inline void SET_CMC_TBL_DISDATAFB(void *table, u32 val)
745{
746 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26));
747 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISDATAFB,
748 BIT(26));
749}
750#define SET_CMC_TBL_MASK_TRYRATE BIT(0)
751static inline void SET_CMC_TBL_TRYRATE(void *table, u32 val)
752{
753 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27));
754 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TRYRATE,
755 BIT(27));
756}
757#define SET_CMC_TBL_MASK_AMPDU_DENSITY GENMASK(3, 0)
758static inline void SET_CMC_TBL_AMPDU_DENSITY(void *table, u32 val)
759{
760 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 28));
761 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_AMPDU_DENSITY,
762 GENMASK(31, 28));
763}
764#define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0)
765static inline void SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void *table, u32 val)
766{
767 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(8, 0));
768 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE,
769 GENMASK(8, 0));
770}
771#define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0)
772static inline void SET_CMC_TBL_AMPDU_TIME_SEL(void *table, u32 val)
773{
774 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9));
775 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_TIME_SEL,
776 BIT(9));
777}
778#define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0)
779static inline void SET_CMC_TBL_AMPDU_LEN_SEL(void *table, u32 val)
780{
781 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10));
782 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_LEN_SEL,
783 BIT(10));
784}
785#define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0)
786static inline void SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void *table, u32 val)
787{
788 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11));
789 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL,
790 BIT(11));
791}
792#define SET_CMC_TBL_MASK_RTS_TXCNT_LMT GENMASK(3, 0)
793static inline void SET_CMC_TBL_RTS_TXCNT_LMT(void *table, u32 val)
794{
795 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(15, 12));
796 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT,
797 GENMASK(15, 12));
798}
799#define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0)
800static inline void SET_CMC_TBL_RTSRATE(void *table, u32 val)
801{
802 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16));
803 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTSRATE,
804 GENMASK(24, 16));
805}
806#define SET_CMC_TBL_MASK_VCS_STBC BIT(0)
807static inline void SET_CMC_TBL_VCS_STBC(void *table, u32 val)
808{
809 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27));
810 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_VCS_STBC,
811 BIT(27));
812}
813#define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE GENMASK(3, 0)
814static inline void SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void *table, u32 val)
815{
816 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 28));
817 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE,
818 GENMASK(31, 28));
819}
820#define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT GENMASK(5, 0)
821static inline void SET_CMC_TBL_DATA_TX_CNT_LMT(void *table, u32 val)
822{
823 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(5, 0));
824 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TX_CNT_LMT,
825 GENMASK(5, 0));
826}
827#define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0)
828static inline void SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void *table, u32 val)
829{
830 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6));
831 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL,
832 BIT(6));
833}
834#define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0)
835static inline void SET_CMC_TBL_MAX_AGG_NUM_SEL(void *table, u32 val)
836{
837 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7));
838 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL,
839 BIT(7));
840}
841#define SET_CMC_TBL_MASK_RTS_EN BIT(0)
842static inline void SET_CMC_TBL_RTS_EN(void *table, u32 val)
843{
844 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8));
845 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_EN,
846 BIT(8));
847}
848#define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0)
849static inline void SET_CMC_TBL_CTS2SELF_EN(void *table, u32 val)
850{
851 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9));
852 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CTS2SELF_EN,
853 BIT(9));
854}
855#define SET_CMC_TBL_MASK_CCA_RTS GENMASK(1, 0)
856static inline void SET_CMC_TBL_CCA_RTS(void *table, u32 val)
857{
858 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 10));
859 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CCA_RTS,
860 GENMASK(11, 10));
861}
862#define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0)
863static inline void SET_CMC_TBL_HW_RTS_EN(void *table, u32 val)
864{
865 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12));
866 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_HW_RTS_EN,
867 BIT(12));
868}
869#define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE GENMASK(1, 0)
870static inline void SET_CMC_TBL_RTS_DROP_DATA_MODE(void *table, u32 val)
871{
872 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(14, 13));
873 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE,
874 GENMASK(14, 13));
875}
876#define SET_CMC_TBL_MASK_AMPDU_MAX_LEN GENMASK(10, 0)
877static inline void SET_CMC_TBL_AMPDU_MAX_LEN(void *table, u32 val)
878{
879 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 16));
880 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_LEN,
881 GENMASK(26, 16));
882}
883#define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0)
884static inline void SET_CMC_TBL_UL_MU_DIS(void *table, u32 val)
885{
886 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27));
887 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_UL_MU_DIS,
888 BIT(27));
889}
890#define SET_CMC_TBL_MASK_AMPDU_MAX_TIME GENMASK(3, 0)
891static inline void SET_CMC_TBL_AMPDU_MAX_TIME(void *table, u32 val)
892{
893 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(31, 28));
894 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_TIME,
895 GENMASK(31, 28));
896}
897#define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0)
898static inline void SET_CMC_TBL_MAX_AGG_NUM(void *table, u32 val)
899{
900 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(7, 0));
901 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_MAX_AGG_NUM,
902 GENMASK(7, 0));
903}
904#define SET_CMC_TBL_MASK_BA_BMAP GENMASK(1, 0)
905static inline void SET_CMC_TBL_BA_BMAP(void *table, u32 val)
906{
907 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(9, 8));
908 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BA_BMAP,
909 GENMASK(9, 8));
910}
911#define SET_CMC_TBL_MASK_VO_LFTIME_SEL GENMASK(2, 0)
912static inline void SET_CMC_TBL_VO_LFTIME_SEL(void *table, u32 val)
913{
914 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(18, 16));
915 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VO_LFTIME_SEL,
916 GENMASK(18, 16));
917}
918#define SET_CMC_TBL_MASK_VI_LFTIME_SEL GENMASK(2, 0)
919static inline void SET_CMC_TBL_VI_LFTIME_SEL(void *table, u32 val)
920{
921 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(21, 19));
922 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VI_LFTIME_SEL,
923 GENMASK(21, 19));
924}
925#define SET_CMC_TBL_MASK_BE_LFTIME_SEL GENMASK(2, 0)
926static inline void SET_CMC_TBL_BE_LFTIME_SEL(void *table, u32 val)
927{
928 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(24, 22));
929 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BE_LFTIME_SEL,
930 GENMASK(24, 22));
931}
932#define SET_CMC_TBL_MASK_BK_LFTIME_SEL GENMASK(2, 0)
933static inline void SET_CMC_TBL_BK_LFTIME_SEL(void *table, u32 val)
934{
935 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 25));
936 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BK_LFTIME_SEL,
937 GENMASK(27, 25));
938}
939#define SET_CMC_TBL_MASK_SECTYPE GENMASK(3, 0)
940static inline void SET_CMC_TBL_SECTYPE(void *table, u32 val)
941{
942 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 28));
943 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_SECTYPE,
944 GENMASK(31, 28));
945}
946#define SET_CMC_TBL_MASK_MULTI_PORT_ID GENMASK(2, 0)
947static inline void SET_CMC_TBL_MULTI_PORT_ID(void *table, u32 val)
948{
949 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(2, 0));
950 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MULTI_PORT_ID,
951 GENMASK(2, 0));
952}
953#define SET_CMC_TBL_MASK_BMC BIT(0)
954static inline void SET_CMC_TBL_BMC(void *table, u32 val)
955{
956 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3));
957 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_BMC,
958 BIT(3));
959}
960#define SET_CMC_TBL_MASK_MBSSID GENMASK(3, 0)
961static inline void SET_CMC_TBL_MBSSID(void *table, u32 val)
962{
963 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 4));
964 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MBSSID,
965 GENMASK(7, 4));
966}
967#define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0)
968static inline void SET_CMC_TBL_NAVUSEHDR(void *table, u32 val)
969{
970 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8));
971 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_NAVUSEHDR,
972 BIT(8));
973}
974#define SET_CMC_TBL_MASK_TXPWR_MODE GENMASK(2, 0)
975static inline void SET_CMC_TBL_TXPWR_MODE(void *table, u32 val)
976{
977 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(11, 9));
978 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_TXPWR_MODE,
979 GENMASK(11, 9));
980}
981#define SET_CMC_TBL_MASK_DATA_DCM BIT(0)
982static inline void SET_CMC_TBL_DATA_DCM(void *table, u32 val)
983{
984 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12));
985 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_DCM,
986 BIT(12));
987}
988#define SET_CMC_TBL_MASK_DATA_ER BIT(0)
989static inline void SET_CMC_TBL_DATA_ER(void *table, u32 val)
990{
991 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13));
992 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_ER,
993 BIT(13));
994}
995#define SET_CMC_TBL_MASK_DATA_LDPC BIT(0)
996static inline void SET_CMC_TBL_DATA_LDPC(void *table, u32 val)
997{
998 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14));
999 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_LDPC,
1000 BIT(14));
1001}
1002#define SET_CMC_TBL_MASK_DATA_STBC BIT(0)
1003static inline void SET_CMC_TBL_DATA_STBC(void *table, u32 val)
1004{
1005 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15));
1006 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_STBC,
1007 BIT(15));
1008}
1009#define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0)
1010static inline void SET_CMC_TBL_A_CTRL_BQR(void *table, u32 val)
1011{
1012 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16));
1013 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BQR,
1014 BIT(16));
1015}
1016#define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0)
1017static inline void SET_CMC_TBL_A_CTRL_UPH(void *table, u32 val)
1018{
1019 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17));
1020 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_UPH,
1021 BIT(17));
1022}
1023#define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0)
1024static inline void SET_CMC_TBL_A_CTRL_BSR(void *table, u32 val)
1025{
1026 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18));
1027 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BSR,
1028 BIT(18));
1029}
1030#define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0)
1031static inline void SET_CMC_TBL_A_CTRL_CAS(void *table, u32 val)
1032{
1033 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19));
1034 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_CAS,
1035 BIT(19));
1036}
1037#define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0)
1038static inline void SET_CMC_TBL_DATA_BW_ER(void *table, u32 val)
1039{
1040 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20));
1041 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_BW_ER,
1042 BIT(20));
1043}
1044#define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0)
1045static inline void SET_CMC_TBL_LSIG_TXOP_EN(void *table, u32 val)
1046{
1047 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21));
1048 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_LSIG_TXOP_EN,
1049 BIT(21));
1050}
1051#define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0)
1052static inline void SET_CMC_TBL_CTRL_CNT_VLD(void *table, u32 val)
1053{
1054 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27));
1055 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT_VLD,
1056 BIT(27));
1057}
1058#define SET_CMC_TBL_MASK_CTRL_CNT GENMASK(3, 0)
1059static inline void SET_CMC_TBL_CTRL_CNT(void *table, u32 val)
1060{
1061 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 28));
1062 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT,
1063 GENMASK(31, 28));
1064}
1065#define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0)
1066static inline void SET_CMC_TBL_RESP_REF_RATE(void *table, u32 val)
1067{
1068 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(8, 0));
1069 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_RESP_REF_RATE,
1070 GENMASK(8, 0));
1071}
1072#define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0)
1073static inline void SET_CMC_TBL_ALL_ACK_SUPPORT(void *table, u32 val)
1074{
1075 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12));
1076 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ALL_ACK_SUPPORT,
1077 BIT(12));
1078}
1079#define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0)
1080static inline void SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void *table, u32 val)
1081{
1082 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13));
1083 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT,
1084 BIT(13));
1085}
1086#define SET_CMC_TBL_MASK_NTX_PATH_EN GENMASK(3, 0)
1087static inline void SET_CMC_TBL_NTX_PATH_EN(void *table, u32 val)
1088{
1089 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(19, 16));
1090 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_NTX_PATH_EN,
1091 GENMASK(19, 16));
1092}
1093#define SET_CMC_TBL_MASK_PATH_MAP_A GENMASK(1, 0)
1094static inline void SET_CMC_TBL_PATH_MAP_A(void *table, u32 val)
1095{
1096 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(21, 20));
1097 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_A,
1098 GENMASK(21, 20));
1099}
1100#define SET_CMC_TBL_MASK_PATH_MAP_B GENMASK(1, 0)
1101static inline void SET_CMC_TBL_PATH_MAP_B(void *table, u32 val)
1102{
1103 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 22));
1104 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_B,
1105 GENMASK(23, 22));
1106}
1107#define SET_CMC_TBL_MASK_PATH_MAP_C GENMASK(1, 0)
1108static inline void SET_CMC_TBL_PATH_MAP_C(void *table, u32 val)
1109{
1110 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(25, 24));
1111 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_C,
1112 GENMASK(25, 24));
1113}
1114#define SET_CMC_TBL_MASK_PATH_MAP_D GENMASK(1, 0)
1115static inline void SET_CMC_TBL_PATH_MAP_D(void *table, u32 val)
1116{
1117 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(27, 26));
1118 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_D,
1119 GENMASK(27, 26));
1120}
1121#define SET_CMC_TBL_MASK_ANTSEL_A BIT(0)
1122static inline void SET_CMC_TBL_ANTSEL_A(void *table, u32 val)
1123{
1124 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28));
1125 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_A,
1126 BIT(28));
1127}
1128#define SET_CMC_TBL_MASK_ANTSEL_B BIT(0)
1129static inline void SET_CMC_TBL_ANTSEL_B(void *table, u32 val)
1130{
1131 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29));
1132 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_B,
1133 BIT(29));
1134}
1135#define SET_CMC_TBL_MASK_ANTSEL_C BIT(0)
1136static inline void SET_CMC_TBL_ANTSEL_C(void *table, u32 val)
1137{
1138 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30));
1139 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_C,
1140 BIT(30));
1141}
1142#define SET_CMC_TBL_MASK_ANTSEL_D BIT(0)
1143static inline void SET_CMC_TBL_ANTSEL_D(void *table, u32 val)
1144{
1145 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31));
1146 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_D,
1147 BIT(31));
1148}
1149
1150#define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING GENMASK(1, 0)
1151static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void *table, u32 val)
1152{
1153 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(1, 0));
1154 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1155 GENMASK(1, 0));
1156}
1157
1158static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void *table, u32 val)
1159{
1160 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(3, 2));
1161 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1162 GENMASK(3, 2));
1163}
1164
1165static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void *table, u32 val)
1166{
1167 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(5, 4));
1168 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1169 GENMASK(5, 4));
1170}
1171
1172static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void *table, u32 val)
1173{
1174 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 6));
1175 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1176 GENMASK(7, 6));
1177}
1178
1179#define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0)
1180static inline void SET_CMC_TBL_ADDR_CAM_INDEX(void *table, u32 val)
1181{
1182 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0));
1183 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ADDR_CAM_INDEX,
1184 GENMASK(7, 0));
1185}
1186#define SET_CMC_TBL_MASK_PAID GENMASK(8, 0)
1187static inline void SET_CMC_TBL_PAID(void *table, u32 val)
1188{
1189 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8));
1190 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_PAID,
1191 GENMASK(16, 8));
1192}
1193#define SET_CMC_TBL_MASK_ULDL BIT(0)
1194static inline void SET_CMC_TBL_ULDL(void *table, u32 val)
1195{
1196 le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17));
1197 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ULDL,
1198 BIT(17));
1199}
1200#define SET_CMC_TBL_MASK_DOPPLER_CTRL GENMASK(1, 0)
1201static inline void SET_CMC_TBL_DOPPLER_CTRL(void *table, u32 val)
1202{
1203 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(19, 18));
1204 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_DOPPLER_CTRL,
1205 GENMASK(19, 18));
1206}
1207static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING(void *table, u32 val)
1208{
1209 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(21, 20));
1210 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1211 GENMASK(21, 20));
1212}
1213
1214static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40(void *table, u32 val)
1215{
1216 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 22));
1217 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1218 GENMASK(23, 22));
1219}
1220#define SET_CMC_TBL_MASK_TXPWR_TOLERENCE GENMASK(3, 0)
1221static inline void SET_CMC_TBL_TXPWR_TOLERENCE(void *table, u32 val)
1222{
1223 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24));
1224 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_TXPWR_TOLERENCE,
1225 GENMASK(27, 24));
1226}
1227
1228static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80(void *table, u32 val)
1229{
1230 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 30));
1231 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1232 GENMASK(31, 30));
1233}
1234#define SET_CMC_TBL_MASK_NC GENMASK(2, 0)
1235static inline void SET_CMC_TBL_NC(void *table, u32 val)
1236{
1237 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(2, 0));
1238 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NC,
1239 GENMASK(2, 0));
1240}
1241#define SET_CMC_TBL_MASK_NR GENMASK(2, 0)
1242static inline void SET_CMC_TBL_NR(void *table, u32 val)
1243{
1244 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(5, 3));
1245 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NR,
1246 GENMASK(5, 3));
1247}
1248#define SET_CMC_TBL_MASK_NG GENMASK(1, 0)
1249static inline void SET_CMC_TBL_NG(void *table, u32 val)
1250{
1251 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6));
1252 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NG,
1253 GENMASK(7, 6));
1254}
1255#define SET_CMC_TBL_MASK_CB GENMASK(1, 0)
1256static inline void SET_CMC_TBL_CB(void *table, u32 val)
1257{
1258 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(9, 8));
1259 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CB,
1260 GENMASK(9, 8));
1261}
1262#define SET_CMC_TBL_MASK_CS GENMASK(1, 0)
1263static inline void SET_CMC_TBL_CS(void *table, u32 val)
1264{
1265 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(11, 10));
1266 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CS,
1267 GENMASK(11, 10));
1268}
1269#define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0)
1270static inline void SET_CMC_TBL_CSI_TXBF_EN(void *table, u32 val)
1271{
1272 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12));
1273 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_TXBF_EN,
1274 BIT(12));
1275}
1276#define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0)
1277static inline void SET_CMC_TBL_CSI_STBC_EN(void *table, u32 val)
1278{
1279 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13));
1280 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_STBC_EN,
1281 BIT(13));
1282}
1283#define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0)
1284static inline void SET_CMC_TBL_CSI_LDPC_EN(void *table, u32 val)
1285{
1286 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14));
1287 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_LDPC_EN,
1288 BIT(14));
1289}
1290#define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0)
1291static inline void SET_CMC_TBL_CSI_PARA_EN(void *table, u32 val)
1292{
1293 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15));
1294 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_PARA_EN,
1295 BIT(15));
1296}
1297#define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0)
1298static inline void SET_CMC_TBL_CSI_FIX_RATE(void *table, u32 val)
1299{
1300 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16));
1301 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_FIX_RATE,
1302 GENMASK(24, 16));
1303}
1304#define SET_CMC_TBL_MASK_CSI_GI_LTF GENMASK(2, 0)
1305static inline void SET_CMC_TBL_CSI_GI_LTF(void *table, u32 val)
1306{
1307 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(27, 25));
1308 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GI_LTF,
1309 GENMASK(27, 25));
1310}
1311
1312static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160(void *table, u32 val)
1313{
1314 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(29, 28));
1315 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1316 GENMASK(29, 28));
1317}
1318
1319#define SET_CMC_TBL_MASK_CSI_BW GENMASK(1, 0)
1320static inline void SET_CMC_TBL_CSI_BW(void *table, u32 val)
1321{
1322 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30));
1323 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_BW,
1324 GENMASK(31, 30));
1325}
1326
1327struct rtw89_h2c_cctlinfo_ud_g7 {
1328 __le32 c0;
1329 __le32 w0;
1330 __le32 w1;
1331 __le32 w2;
1332 __le32 w3;
1333 __le32 w4;
1334 __le32 w5;
1335 __le32 w6;
1336 __le32 w7;
1337 __le32 w8;
1338 __le32 w9;
1339 __le32 w10;
1340 __le32 w11;
1341 __le32 w12;
1342 __le32 w13;
1343 __le32 w14;
1344 __le32 w15;
1345 __le32 m0;
1346 __le32 m1;
1347 __le32 m2;
1348 __le32 m3;
1349 __le32 m4;
1350 __le32 m5;
1351 __le32 m6;
1352 __le32 m7;
1353 __le32 m8;
1354 __le32 m9;
1355 __le32 m10;
1356 __le32 m11;
1357 __le32 m12;
1358 __le32 m13;
1359 __le32 m14;
1360 __le32 m15;
1361} __packed;
1362
1363#define CCTLINFO_G7_C0_MACID GENMASK(6, 0)
1364#define CCTLINFO_G7_C0_OP BIT(7)
1365
1366#define CCTLINFO_G7_W0_DATARATE GENMASK(11, 0)
1367#define CCTLINFO_G7_W0_DATA_GI_LTF GENMASK(14, 12)
1368#define CCTLINFO_G7_W0_TRYRATE BIT(15)
1369#define CCTLINFO_G7_W0_ARFR_CTRL GENMASK(17, 16)
1370#define CCTLINFO_G7_W0_DIS_HE1SS_STBC BIT(18)
1371#define CCTLINFO_G7_W0_ACQ_RPT_EN BIT(20)
1372#define CCTLINFO_G7_W0_MGQ_RPT_EN BIT(21)
1373#define CCTLINFO_G7_W0_ULQ_RPT_EN BIT(22)
1374#define CCTLINFO_G7_W0_TWTQ_RPT_EN BIT(23)
1375#define CCTLINFO_G7_W0_FORCE_TXOP BIT(24)
1376#define CCTLINFO_G7_W0_DISRTSFB BIT(25)
1377#define CCTLINFO_G7_W0_DISDATAFB BIT(26)
1378#define CCTLINFO_G7_W0_NSTR_EN BIT(27)
1379#define CCTLINFO_G7_W0_AMPDU_DENSITY GENMASK(31, 28)
1380#define CCTLINFO_G7_W0_ALL (GENMASK(31, 20) | GENMASK(18, 0))
1381#define CCTLINFO_G7_W1_DATA_RTY_LOWEST_RATE GENMASK(11, 0)
1382#define CCTLINFO_G7_W1_RTS_TXCNT_LMT GENMASK(15, 12)
1383#define CCTLINFO_G7_W1_RTSRATE GENMASK(27, 16)
1384#define CCTLINFO_G7_W1_RTS_RTY_LOWEST_RATE GENMASK(31, 28)
1385#define CCTLINFO_G7_W1_ALL GENMASK(31, 0)
1386#define CCTLINFO_G7_W2_DATA_TX_CNT_LMT GENMASK(5, 0)
1387#define CCTLINFO_G7_W2_DATA_TXCNT_LMT_SEL BIT(6)
1388#define CCTLINFO_G7_W2_MAX_AGG_NUM_SEL BIT(7)
1389#define CCTLINFO_G7_W2_RTS_EN BIT(8)
1390#define CCTLINFO_G7_W2_CTS2SELF_EN BIT(9)
1391#define CCTLINFO_G7_W2_CCA_RTS GENMASK(11, 10)
1392#define CCTLINFO_G7_W2_HW_RTS_EN BIT(12)
1393#define CCTLINFO_G7_W2_RTS_DROP_DATA_MODE GENMASK(14, 13)
1394#define CCTLINFO_G7_W2_PRELD_EN BIT(15)
1395#define CCTLINFO_G7_W2_AMPDU_MAX_LEN GENMASK(26, 16)
1396#define CCTLINFO_G7_W2_UL_MU_DIS BIT(27)
1397#define CCTLINFO_G7_W2_AMPDU_MAX_TIME GENMASK(31, 28)
1398#define CCTLINFO_G7_W2_ALL GENMASK(31, 0)
1399#define CCTLINFO_G7_W3_MAX_AGG_NUM GENMASK(7, 0)
1400#define CCTLINFO_G7_W3_DATA_BW GENMASK(10, 8)
1401#define CCTLINFO_G7_W3_DATA_BW_ER BIT(11)
1402#define CCTLINFO_G7_W3_BA_BMAP GENMASK(14, 12)
1403#define CCTLINFO_G7_W3_VCS_STBC BIT(15)
1404#define CCTLINFO_G7_W3_VO_LFTIME_SEL GENMASK(18, 16)
1405#define CCTLINFO_G7_W3_VI_LFTIME_SEL GENMASK(21, 19)
1406#define CCTLINFO_G7_W3_BE_LFTIME_SEL GENMASK(24, 22)
1407#define CCTLINFO_G7_W3_BK_LFTIME_SEL GENMASK(27, 25)
1408#define CCTLINFO_G7_W3_AMPDU_TIME_SEL BIT(28)
1409#define CCTLINFO_G7_W3_AMPDU_LEN_SEL BIT(29)
1410#define CCTLINFO_G7_W3_RTS_TXCNT_LMT_SEL BIT(30)
1411#define CCTLINFO_G7_W3_LSIG_TXOP_EN BIT(31)
1412#define CCTLINFO_G7_W3_ALL GENMASK(31, 0)
1413#define CCTLINFO_G7_W4_MULTI_PORT_ID GENMASK(2, 0)
1414#define CCTLINFO_G7_W4_BYPASS_PUNC BIT(3)
1415#define CCTLINFO_G7_W4_MBSSID GENMASK(7, 4)
1416#define CCTLINFO_G7_W4_DATA_DCM BIT(8)
1417#define CCTLINFO_G7_W4_DATA_ER BIT(9)
1418#define CCTLINFO_G7_W4_DATA_LDPC BIT(10)
1419#define CCTLINFO_G7_W4_DATA_STBC BIT(11)
1420#define CCTLINFO_G7_W4_A_CTRL_BQR BIT(12)
1421#define CCTLINFO_G7_W4_A_CTRL_BSR BIT(14)
1422#define CCTLINFO_G7_W4_A_CTRL_CAS BIT(15)
1423#define CCTLINFO_G7_W4_ACT_SUBCH_CBW GENMASK(31, 16)
1424#define CCTLINFO_G7_W4_ALL (GENMASK(31, 14) | GENMASK(12, 0))
1425#define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING0 GENMASK(1, 0)
1426#define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING1 GENMASK(3, 2)
1427#define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING2 GENMASK(5, 4)
1428#define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING3 GENMASK(7, 6)
1429#define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING4 GENMASK(9, 8)
1430#define CCTLINFO_G7_W5_SR_RATE GENMASK(14, 10)
1431#define CCTLINFO_G7_W5_TID_DISABLE GENMASK(23, 16)
1432#define CCTLINFO_G7_W5_ADDR_CAM_INDEX GENMASK(31, 24)
1433#define CCTLINFO_G7_W5_ALL (GENMASK(31, 16) | GENMASK(14, 0))
1434#define CCTLINFO_G7_W6_AID12_PAID GENMASK(11, 0)
1435#define CCTLINFO_G7_W6_RESP_REF_RATE GENMASK(23, 12)
1436#define CCTLINFO_G7_W6_ULDL BIT(31)
1437#define CCTLINFO_G7_W6_ALL (BIT(31) | GENMASK(23, 0))
1438#define CCTLINFO_G7_W7_NC GENMASK(2, 0)
1439#define CCTLINFO_G7_W7_NR GENMASK(5, 3)
1440#define CCTLINFO_G7_W7_NG GENMASK(7, 6)
1441#define CCTLINFO_G7_W7_CB GENMASK(9, 8)
1442#define CCTLINFO_G7_W7_CS GENMASK(11, 10)
1443#define CCTLINFO_G7_W7_CSI_STBC_EN BIT(13)
1444#define CCTLINFO_G7_W7_CSI_LDPC_EN BIT(14)
1445#define CCTLINFO_G7_W7_CSI_PARA_EN BIT(15)
1446#define CCTLINFO_G7_W7_CSI_FIX_RATE GENMASK(27, 16)
1447#define CCTLINFO_G7_W7_CSI_BW GENMASK(31, 29)
1448#define CCTLINFO_G7_W7_ALL (GENMASK(31, 29) | GENMASK(27, 13) | GENMASK(11, 0))
1449#define CCTLINFO_G7_W8_ALL_ACK_SUPPORT BIT(0)
1450#define CCTLINFO_G7_W8_BSR_QUEUE_SIZE_FORMAT BIT(1)
1451#define CCTLINFO_G7_W8_BSR_OM_UPD_EN BIT(2)
1452#define CCTLINFO_G7_W8_MACID_FWD_IDC BIT(3)
1453#define CCTLINFO_G7_W8_AZ_SEC_EN BIT(4)
1454#define CCTLINFO_G7_W8_CSI_SEC_EN BIT(5)
1455#define CCTLINFO_G7_W8_FIX_UL_ADDRCAM_IDX BIT(6)
1456#define CCTLINFO_G7_W8_CTRL_CNT_VLD BIT(7)
1457#define CCTLINFO_G7_W8_CTRL_CNT GENMASK(11, 8)
1458#define CCTLINFO_G7_W8_RESP_SEC_TYPE GENMASK(15, 12)
1459#define CCTLINFO_G7_W8_ALL GENMASK(15, 0)
1460/* W9~13 are reserved */
1461#define CCTLINFO_G7_W14_VO_CURR_RATE GENMASK(11, 0)
1462#define CCTLINFO_G7_W14_VI_CURR_RATE GENMASK(23, 12)
1463#define CCTLINFO_G7_W14_BE_CURR_RATE_L GENMASK(31, 24)
1464#define CCTLINFO_G7_W14_ALL GENMASK(31, 0)
1465#define CCTLINFO_G7_W15_BE_CURR_RATE_H GENMASK(3, 0)
1466#define CCTLINFO_G7_W15_BK_CURR_RATE GENMASK(15, 4)
1467#define CCTLINFO_G7_W15_MGNT_CURR_RATE GENMASK(27, 16)
1468#define CCTLINFO_G7_W15_ALL GENMASK(27, 0)
1469
1470struct rtw89_h2c_bcn_upd {
1471 __le32 w0;
1472 __le32 w1;
1473 __le32 w2;
1474} __packed;
1475
1476#define RTW89_H2C_BCN_UPD_W0_PORT GENMASK(7, 0)
1477#define RTW89_H2C_BCN_UPD_W0_MBSSID GENMASK(15, 8)
1478#define RTW89_H2C_BCN_UPD_W0_BAND GENMASK(23, 16)
1479#define RTW89_H2C_BCN_UPD_W0_GRP_IE_OFST GENMASK(31, 24)
1480#define RTW89_H2C_BCN_UPD_W1_MACID GENMASK(7, 0)
1481#define RTW89_H2C_BCN_UPD_W1_SSN_SEL GENMASK(9, 8)
1482#define RTW89_H2C_BCN_UPD_W1_SSN_MODE GENMASK(11, 10)
1483#define RTW89_H2C_BCN_UPD_W1_RATE GENMASK(20, 12)
1484#define RTW89_H2C_BCN_UPD_W1_TXPWR GENMASK(23, 21)
1485#define RTW89_H2C_BCN_UPD_W2_TXINFO_CTRL_EN BIT(0)
1486#define RTW89_H2C_BCN_UPD_W2_NTX_PATH_EN GENMASK(4, 1)
1487#define RTW89_H2C_BCN_UPD_W2_PATH_MAP_A GENMASK(6, 5)
1488#define RTW89_H2C_BCN_UPD_W2_PATH_MAP_B GENMASK(8, 7)
1489#define RTW89_H2C_BCN_UPD_W2_PATH_MAP_C GENMASK(10, 9)
1490#define RTW89_H2C_BCN_UPD_W2_PATH_MAP_D GENMASK(12, 11)
1491#define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_A BIT(13)
1492#define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_B BIT(14)
1493#define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_C BIT(15)
1494#define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_D BIT(16)
1495#define RTW89_H2C_BCN_UPD_W2_CSA_OFST GENMASK(31, 17)
1496
1497struct rtw89_h2c_bcn_upd_be {
1498 __le32 w0;
1499 __le32 w1;
1500 __le32 w2;
1501 __le32 w3;
1502 __le32 w4;
1503 __le32 w5;
1504 __le32 w6;
1505 __le32 w7;
1506 __le32 w8;
1507 __le32 w9;
1508 __le32 w10;
1509 __le32 w11;
1510 __le32 w12;
1511 __le32 w13;
1512 __le32 w14;
1513 __le32 w15;
1514 __le32 w16;
1515 __le32 w17;
1516 __le32 w18;
1517 __le32 w19;
1518 __le32 w20;
1519 __le32 w21;
1520 __le32 w22;
1521 __le32 w23;
1522 __le32 w24;
1523 __le32 w25;
1524 __le32 w26;
1525 __le32 w27;
1526 __le32 w28;
1527 __le32 w29;
1528} __packed;
1529
1530#define RTW89_H2C_BCN_UPD_BE_W0_PORT GENMASK(7, 0)
1531#define RTW89_H2C_BCN_UPD_BE_W0_MBSSID GENMASK(15, 8)
1532#define RTW89_H2C_BCN_UPD_BE_W0_BAND GENMASK(23, 16)
1533#define RTW89_H2C_BCN_UPD_BE_W0_GRP_IE_OFST GENMASK(31, 24)
1534#define RTW89_H2C_BCN_UPD_BE_W1_MACID GENMASK(7, 0)
1535#define RTW89_H2C_BCN_UPD_BE_W1_SSN_SEL GENMASK(9, 8)
1536#define RTW89_H2C_BCN_UPD_BE_W1_SSN_MODE GENMASK(11, 10)
1537#define RTW89_H2C_BCN_UPD_BE_W1_RATE GENMASK(20, 12)
1538#define RTW89_H2C_BCN_UPD_BE_W1_TXPWR GENMASK(23, 21)
1539#define RTW89_H2C_BCN_UPD_BE_W1_MACID_EXT GENMASK(31, 24)
1540#define RTW89_H2C_BCN_UPD_BE_W2_TXINFO_CTRL_EN BIT(0)
1541#define RTW89_H2C_BCN_UPD_BE_W2_NTX_PATH_EN GENMASK(4, 1)
1542#define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_A GENMASK(6, 5)
1543#define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_B GENMASK(8, 7)
1544#define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_C GENMASK(10, 9)
1545#define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_D GENMASK(12, 11)
1546#define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_A BIT(13)
1547#define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_B BIT(14)
1548#define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_C BIT(15)
1549#define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_D BIT(16)
1550#define RTW89_H2C_BCN_UPD_BE_W2_CSA_OFST GENMASK(31, 17)
1551#define RTW89_H2C_BCN_UPD_BE_W3_MLIE_CSA_OFST GENMASK(15, 0)
1552#define RTW89_H2C_BCN_UPD_BE_W3_CRITICAL_UPD_FLAG_OFST GENMASK(31, 16)
1553#define RTW89_H2C_BCN_UPD_BE_W4_VAP1_DTIM_CNT_OFST GENMASK(15, 0)
1554#define RTW89_H2C_BCN_UPD_BE_W4_VAP2_DTIM_CNT_OFST GENMASK(31, 16)
1555#define RTW89_H2C_BCN_UPD_BE_W5_VAP3_DTIM_CNT_OFST GENMASK(15, 0)
1556#define RTW89_H2C_BCN_UPD_BE_W5_VAP4_DTIM_CNT_OFST GENMASK(31, 16)
1557#define RTW89_H2C_BCN_UPD_BE_W6_VAP5_DTIM_CNT_OFST GENMASK(15, 0)
1558#define RTW89_H2C_BCN_UPD_BE_W6_VAP6_DTIM_CNT_OFST GENMASK(31, 16)
1559#define RTW89_H2C_BCN_UPD_BE_W7_VAP7_DTIM_CNT_OFST GENMASK(15, 0)
1560#define RTW89_H2C_BCN_UPD_BE_W7_ECSA_OFST GENMASK(30, 16)
1561#define RTW89_H2C_BCN_UPD_BE_W7_PROTECTION_KEY_ID BIT(31)
1562
1563static inline void SET_FWROLE_MAINTAIN_MACID(void *h2c, u32 val)
1564{
1565 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1566}
1567
1568static inline void SET_FWROLE_MAINTAIN_SELF_ROLE(void *h2c, u32 val)
1569{
1570 le32p_replace_bits((__le32 *)h2c, val, GENMASK(9, 8));
1571}
1572
1573static inline void SET_FWROLE_MAINTAIN_UPD_MODE(void *h2c, u32 val)
1574{
1575 le32p_replace_bits((__le32 *)h2c, val, GENMASK(12, 10));
1576}
1577
1578static inline void SET_FWROLE_MAINTAIN_WIFI_ROLE(void *h2c, u32 val)
1579{
1580 le32p_replace_bits((__le32 *)h2c, val, GENMASK(16, 13));
1581}
1582
1583enum rtw89_fw_sta_type { /* value of RTW89_H2C_JOININFO_W1_STA_TYPE */
1584 RTW89_FW_N_AC_STA = 0,
1585 RTW89_FW_AX_STA = 1,
1586 RTW89_FW_BE_STA = 2,
1587};
1588
1589struct rtw89_h2c_join {
1590 __le32 w0;
1591} __packed;
1592
1593struct rtw89_h2c_join_v1 {
1594 __le32 w0;
1595 __le32 w1;
1596 __le32 w2;
1597} __packed;
1598
1599#define RTW89_H2C_JOININFO_W0_MACID GENMASK(7, 0)
1600#define RTW89_H2C_JOININFO_W0_OP BIT(8)
1601#define RTW89_H2C_JOININFO_W0_BAND BIT(9)
1602#define RTW89_H2C_JOININFO_W0_WMM GENMASK(11, 10)
1603#define RTW89_H2C_JOININFO_W0_TGR BIT(12)
1604#define RTW89_H2C_JOININFO_W0_ISHESTA BIT(13)
1605#define RTW89_H2C_JOININFO_W0_DLBW GENMASK(15, 14)
1606#define RTW89_H2C_JOININFO_W0_TF_MAC_PAD GENMASK(17, 16)
1607#define RTW89_H2C_JOININFO_W0_DL_T_PE GENMASK(20, 18)
1608#define RTW89_H2C_JOININFO_W0_PORT_ID GENMASK(23, 21)
1609#define RTW89_H2C_JOININFO_W0_NET_TYPE GENMASK(25, 24)
1610#define RTW89_H2C_JOININFO_W0_WIFI_ROLE GENMASK(29, 26)
1611#define RTW89_H2C_JOININFO_W0_SELF_ROLE GENMASK(31, 30)
1612#define RTW89_H2C_JOININFO_W1_STA_TYPE GENMASK(2, 0)
1613#define RTW89_H2C_JOININFO_W1_IS_MLD BIT(3)
1614#define RTW89_H2C_JOININFO_W1_MAIN_MACID GENMASK(11, 4)
1615#define RTW89_H2C_JOININFO_W1_MLO_MODE BIT(12)
1616#define RTW89_H2C_JOININFO_W1_EMLSR_CAB BIT(13)
1617#define RTW89_H2C_JOININFO_W1_NSTR_EN BIT(14)
1618#define RTW89_H2C_JOININFO_W1_INIT_PWR_STATE BIT(15)
1619#define RTW89_H2C_JOININFO_W1_EMLSR_PADDING GENMASK(18, 16)
1620#define RTW89_H2C_JOININFO_W1_EMLSR_TRANS_DELAY GENMASK(21, 19)
1621#define RTW89_H2C_JOININFO_W2_MACID_EXT GENMASK(7, 0)
1622#define RTW89_H2C_JOININFO_W2_MAIN_MACID_EXT GENMASK(15, 8)
1623
1624struct rtw89_h2c_notify_dbcc {
1625 __le32 w0;
1626} __packed;
1627
1628#define RTW89_H2C_NOTIFY_DBCC_EN BIT(0)
1629
1630static inline void SET_GENERAL_PKT_MACID(void *h2c, u32 val)
1631{
1632 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1633}
1634
1635static inline void SET_GENERAL_PKT_PROBRSP_ID(void *h2c, u32 val)
1636{
1637 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1638}
1639
1640static inline void SET_GENERAL_PKT_PSPOLL_ID(void *h2c, u32 val)
1641{
1642 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1643}
1644
1645static inline void SET_GENERAL_PKT_NULL_ID(void *h2c, u32 val)
1646{
1647 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1648}
1649
1650static inline void SET_GENERAL_PKT_QOS_NULL_ID(void *h2c, u32 val)
1651{
1652 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1653}
1654
1655static inline void SET_GENERAL_PKT_CTS2SELF_ID(void *h2c, u32 val)
1656{
1657 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));
1658}
1659
1660static inline void SET_LOG_CFG_LEVEL(void *h2c, u32 val)
1661{
1662 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1663}
1664
1665static inline void SET_LOG_CFG_PATH(void *h2c, u32 val)
1666{
1667 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1668}
1669
1670static inline void SET_LOG_CFG_COMP(void *h2c, u32 val)
1671{
1672 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0));
1673}
1674
1675static inline void SET_LOG_CFG_COMP_EXT(void *h2c, u32 val)
1676{
1677 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 0));
1678}
1679
1680struct rtw89_h2c_ba_cam {
1681 __le32 w0;
1682 __le32 w1;
1683} __packed;
1684
1685#define RTW89_H2C_BA_CAM_W0_VALID BIT(0)
1686#define RTW89_H2C_BA_CAM_W0_INIT_REQ BIT(1)
1687#define RTW89_H2C_BA_CAM_W0_ENTRY_IDX GENMASK(3, 2)
1688#define RTW89_H2C_BA_CAM_W0_TID GENMASK(7, 4)
1689#define RTW89_H2C_BA_CAM_W0_MACID GENMASK(15, 8)
1690#define RTW89_H2C_BA_CAM_W0_BMAP_SIZE GENMASK(19, 16)
1691#define RTW89_H2C_BA_CAM_W0_SSN GENMASK(31, 20)
1692#define RTW89_H2C_BA_CAM_W1_UID GENMASK(7, 0)
1693#define RTW89_H2C_BA_CAM_W1_STD_EN BIT(8)
1694#define RTW89_H2C_BA_CAM_W1_BAND BIT(9)
1695#define RTW89_H2C_BA_CAM_W1_ENTRY_IDX_V1 GENMASK(31, 28)
1696
1697struct rtw89_h2c_ba_cam_v1 {
1698 __le32 w0;
1699 __le32 w1;
1700} __packed;
1701
1702#define RTW89_H2C_BA_CAM_V1_W0_VALID BIT(0)
1703#define RTW89_H2C_BA_CAM_V1_W0_INIT_REQ BIT(1)
1704#define RTW89_H2C_BA_CAM_V1_W0_TID_MASK GENMASK(7, 4)
1705#define RTW89_H2C_BA_CAM_V1_W0_MACID_MASK GENMASK(15, 8)
1706#define RTW89_H2C_BA_CAM_V1_W0_BMAP_SIZE_MASK GENMASK(19, 16)
1707#define RTW89_H2C_BA_CAM_V1_W0_SSN_MASK GENMASK(31, 20)
1708#define RTW89_H2C_BA_CAM_V1_W1_UID_VALUE_MASK GENMASK(7, 0)
1709#define RTW89_H2C_BA_CAM_V1_W1_STD_ENTRY_EN BIT(8)
1710#define RTW89_H2C_BA_CAM_V1_W1_BAND_SEL BIT(9)
1711#define RTW89_H2C_BA_CAM_V1_W1_MLD_EN BIT(10)
1712#define RTW89_H2C_BA_CAM_V1_W1_ENTRY_IDX_MASK GENMASK(31, 24)
1713
1714struct rtw89_h2c_ba_cam_init {
1715 __le32 w0;
1716} __packed;
1717
1718#define RTW89_H2C_BA_CAM_INIT_USERS_MASK GENMASK(7, 0)
1719#define RTW89_H2C_BA_CAM_INIT_OFFSET_MASK GENMASK(19, 12)
1720#define RTW89_H2C_BA_CAM_INIT_BAND_SEL BIT(24)
1721
1722static inline void SET_LPS_PARM_MACID(void *h2c, u32 val)
1723{
1724 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1725}
1726
1727static inline void SET_LPS_PARM_PSMODE(void *h2c, u32 val)
1728{
1729 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1730}
1731
1732static inline void SET_LPS_PARM_RLBM(void *h2c, u32 val)
1733{
1734 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16));
1735}
1736
1737static inline void SET_LPS_PARM_SMARTPS(void *h2c, u32 val)
1738{
1739 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 20));
1740}
1741
1742static inline void SET_LPS_PARM_AWAKEINTERVAL(void *h2c, u32 val)
1743{
1744 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1745}
1746
1747static inline void SET_LPS_PARM_VOUAPSD(void *h2c, u32 val)
1748{
1749 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0));
1750}
1751
1752static inline void SET_LPS_PARM_VIUAPSD(void *h2c, u32 val)
1753{
1754 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1));
1755}
1756
1757static inline void SET_LPS_PARM_BEUAPSD(void *h2c, u32 val)
1758{
1759 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2));
1760}
1761
1762static inline void SET_LPS_PARM_BKUAPSD(void *h2c, u32 val)
1763{
1764 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3));
1765}
1766
1767static inline void SET_LPS_PARM_LASTRPWM(void *h2c, u32 val)
1768{
1769 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));
1770}
1771
1772struct rtw89_h2c_lps_ch_info {
1773 struct {
1774 u8 pri_ch;
1775 u8 central_ch;
1776 u8 bw;
1777 u8 band;
1778 } __packed info[2];
1779
1780 __le32 mlo_dbcc_mode_lps;
1781} __packed;
1782
1783static inline void RTW89_SET_FWCMD_CPU_EXCEPTION_TYPE(void *cmd, u32 val)
1784{
1785 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 0));
1786}
1787
1788static inline void RTW89_SET_FWCMD_PKT_DROP_SEL(void *cmd, u32 val)
1789{
1790 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
1791}
1792
1793static inline void RTW89_SET_FWCMD_PKT_DROP_MACID(void *cmd, u32 val)
1794{
1795 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
1796}
1797
1798static inline void RTW89_SET_FWCMD_PKT_DROP_BAND(void *cmd, u32 val)
1799{
1800 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
1801}
1802
1803static inline void RTW89_SET_FWCMD_PKT_DROP_PORT(void *cmd, u32 val)
1804{
1805 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
1806}
1807
1808static inline void RTW89_SET_FWCMD_PKT_DROP_MBSSID(void *cmd, u32 val)
1809{
1810 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 0));
1811}
1812
1813static inline void RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void *cmd, u32 val)
1814{
1815 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(15, 8));
1816}
1817
1818static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void *cmd, u32 val)
1819{
1820 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
1821}
1822
1823static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void *cmd, u32 val)
1824{
1825 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));
1826}
1827
1828static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void *cmd, u32 val)
1829{
1830 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));
1831}
1832
1833static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void *cmd, u32 val)
1834{
1835 le32p_replace_bits((__le32 *)cmd + 5, val, GENMASK(31, 0));
1836}
1837
1838static inline void RTW89_SET_KEEP_ALIVE_ENABLE(void *h2c, u32 val)
1839{
1840 le32p_replace_bits((__le32 *)h2c, val, GENMASK(1, 0));
1841}
1842
1843static inline void RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void *h2c, u32 val)
1844{
1845 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1846}
1847
1848static inline void RTW89_SET_KEEP_ALIVE_PERIOD(void *h2c, u32 val)
1849{
1850 le32p_replace_bits((__le32 *)h2c, val, GENMASK(24, 16));
1851}
1852
1853static inline void RTW89_SET_KEEP_ALIVE_MACID(void *h2c, u32 val)
1854{
1855 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1856}
1857
1858static inline void RTW89_SET_DISCONNECT_DETECT_ENABLE(void *h2c, u32 val)
1859{
1860 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1861}
1862
1863static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void *h2c, u32 val)
1864{
1865 le32p_replace_bits((__le32 *)h2c, val, BIT(1));
1866}
1867
1868static inline void RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void *h2c, u32 val)
1869{
1870 le32p_replace_bits((__le32 *)h2c, val, BIT(2));
1871}
1872
1873static inline void RTW89_SET_DISCONNECT_DETECT_MAC_ID(void *h2c, u32 val)
1874{
1875 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1876}
1877
1878static inline void RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void *h2c, u32 val)
1879{
1880 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1881}
1882
1883static inline void RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void *h2c, u32 val)
1884{
1885 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1886}
1887
1888static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void *h2c, u32 val)
1889{
1890 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1891}
1892
1893struct rtw89_h2c_wow_global {
1894 __le32 w0;
1895 struct rtw89_wow_key_info key_info;
1896} __packed;
1897
1898#define RTW89_H2C_WOW_GLOBAL_W0_ENABLE BIT(0)
1899#define RTW89_H2C_WOW_GLOBAL_W0_DROP_ALL_PKT BIT(1)
1900#define RTW89_H2C_WOW_GLOBAL_W0_RX_PARSE_AFTER_WAKE BIT(2)
1901#define RTW89_H2C_WOW_GLOBAL_W0_WAKE_BAR_PULLED BIT(3)
1902#define RTW89_H2C_WOW_GLOBAL_W0_MAC_ID GENMASK(15, 8)
1903#define RTW89_H2C_WOW_GLOBAL_W0_PAIRWISE_SEC_ALGO GENMASK(23, 16)
1904#define RTW89_H2C_WOW_GLOBAL_W0_GROUP_SEC_ALGO GENMASK(31, 24)
1905
1906#define RTW89_MAX_SUPPORT_NL_NUM 16
1907struct rtw89_h2c_cfg_nlo {
1908 __le32 w0;
1909 u8 nlo_cnt;
1910 u8 rsvd[3];
1911 __le32 patterncheck;
1912 __le32 rsvd1;
1913 __le32 rsvd2;
1914 u8 ssid_len[RTW89_MAX_SUPPORT_NL_NUM];
1915 u8 chiper[RTW89_MAX_SUPPORT_NL_NUM];
1916 u8 rsvd3[24];
1917 u8 ssid[RTW89_MAX_SUPPORT_NL_NUM][IEEE80211_MAX_SSID_LEN];
1918} __packed;
1919
1920#define RTW89_H2C_NLO_W0_ENABLE BIT(0)
1921#define RTW89_H2C_NLO_W0_IGNORE_CIPHER BIT(2)
1922#define RTW89_H2C_NLO_W0_MACID GENMASK(31, 24)
1923
1924static inline void RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void *h2c, u32 val)
1925{
1926 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1927}
1928
1929static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void *h2c, u32 val)
1930{
1931 le32p_replace_bits((__le32 *)h2c, val, BIT(1));
1932}
1933
1934static inline void RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void *h2c, u32 val)
1935{
1936 le32p_replace_bits((__le32 *)h2c, val, BIT(2));
1937}
1938
1939static inline void RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void *h2c, u32 val)
1940{
1941 le32p_replace_bits((__le32 *)h2c, val, BIT(3));
1942}
1943
1944static inline void RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void *h2c, u32 val)
1945{
1946 le32p_replace_bits((__le32 *)h2c, val, BIT(4));
1947}
1948
1949static inline void RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void *h2c, u32 val)
1950{
1951 le32p_replace_bits((__le32 *)h2c, val, BIT(5));
1952}
1953
1954static inline void RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void *h2c, u32 val)
1955{
1956 le32p_replace_bits((__le32 *)h2c, val, BIT(6));
1957}
1958
1959static inline void RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void *h2c, u32 val)
1960{
1961 le32p_replace_bits((__le32 *)h2c, val, BIT(7));
1962}
1963
1964static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void *h2c, u32 val)
1965{
1966 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1967}
1968
1969static inline void RTW89_SET_WOW_CAM_UPD_R_W(void *h2c, u32 val)
1970{
1971 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1972}
1973
1974static inline void RTW89_SET_WOW_CAM_UPD_IDX(void *h2c, u32 val)
1975{
1976 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 1));
1977}
1978
1979static inline void RTW89_SET_WOW_CAM_UPD_WKFM1(void *h2c, u32 val)
1980{
1981 le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 0));
1982}
1983
1984static inline void RTW89_SET_WOW_CAM_UPD_WKFM2(void *h2c, u32 val)
1985{
1986 le32p_replace_bits((__le32 *)h2c + 2, val, GENMASK(31, 0));
1987}
1988
1989static inline void RTW89_SET_WOW_CAM_UPD_WKFM3(void *h2c, u32 val)
1990{
1991 le32p_replace_bits((__le32 *)h2c + 3, val, GENMASK(31, 0));
1992}
1993
1994static inline void RTW89_SET_WOW_CAM_UPD_WKFM4(void *h2c, u32 val)
1995{
1996 le32p_replace_bits((__le32 *)h2c + 4, val, GENMASK(31, 0));
1997}
1998
1999static inline void RTW89_SET_WOW_CAM_UPD_CRC(void *h2c, u32 val)
2000{
2001 le32p_replace_bits((__le32 *)h2c + 5, val, GENMASK(15, 0));
2002}
2003
2004static inline void RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(void *h2c, u32 val)
2005{
2006 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(22));
2007}
2008
2009static inline void RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(void *h2c, u32 val)
2010{
2011 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(23));
2012}
2013
2014static inline void RTW89_SET_WOW_CAM_UPD_UC(void *h2c, u32 val)
2015{
2016 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(24));
2017}
2018
2019static inline void RTW89_SET_WOW_CAM_UPD_MC(void *h2c, u32 val)
2020{
2021 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(25));
2022}
2023
2024static inline void RTW89_SET_WOW_CAM_UPD_BC(void *h2c, u32 val)
2025{
2026 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(26));
2027}
2028
2029static inline void RTW89_SET_WOW_CAM_UPD_VALID(void *h2c, u32 val)
2030{
2031 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(31));
2032}
2033
2034struct rtw89_h2c_wow_gtk_ofld {
2035 __le32 w0;
2036 __le32 w1;
2037 struct rtw89_wow_gtk_info gtk_info;
2038} __packed;
2039
2040#define RTW89_H2C_WOW_GTK_OFLD_W0_EN BIT(0)
2041#define RTW89_H2C_WOW_GTK_OFLD_W0_TKIP_EN BIT(1)
2042#define RTW89_H2C_WOW_GTK_OFLD_W0_IEEE80211W_EN BIT(2)
2043#define RTW89_H2C_WOW_GTK_OFLD_W0_PAIRWISE_WAKEUP BIT(3)
2044#define RTW89_H2C_WOW_GTK_OFLD_W0_NOREKEY_WAKEUP BIT(4)
2045#define RTW89_H2C_WOW_GTK_OFLD_W0_MAC_ID GENMASK(23, 16)
2046#define RTW89_H2C_WOW_GTK_OFLD_W0_GTK_RSP_ID GENMASK(31, 24)
2047#define RTW89_H2C_WOW_GTK_OFLD_W1_PMF_SA_QUERY_ID GENMASK(7, 0)
2048#define RTW89_H2C_WOW_GTK_OFLD_W1_PMF_BIP_SEC_ALGO GENMASK(9, 8)
2049#define RTW89_H2C_WOW_GTK_OFLD_W1_ALGO_AKM_SUIT GENMASK(17, 10)
2050
2051struct rtw89_h2c_arp_offload {
2052 __le32 w0;
2053 __le32 w1;
2054} __packed;
2055
2056#define RTW89_H2C_ARP_OFFLOAD_W0_ENABLE BIT(0)
2057#define RTW89_H2C_ARP_OFFLOAD_W0_ACTION BIT(1)
2058#define RTW89_H2C_ARP_OFFLOAD_W0_MACID GENMASK(23, 16)
2059#define RTW89_H2C_ARP_OFFLOAD_W0_PKT_ID GENMASK(31, 24)
2060#define RTW89_H2C_ARP_OFFLOAD_W1_CONTENT GENMASK(31, 0)
2061
2062enum rtw89_btc_btf_h2c_class {
2063 BTFC_SET = 0x10,
2064 BTFC_GET = 0x11,
2065 BTFC_FW_EVENT = 0x12,
2066};
2067
2068enum rtw89_btc_btf_set {
2069 SET_REPORT_EN = 0x0,
2070 SET_SLOT_TABLE,
2071 SET_MREG_TABLE,
2072 SET_CX_POLICY,
2073 SET_GPIO_DBG,
2074 SET_DRV_INFO,
2075 SET_DRV_EVENT,
2076 SET_BT_WREG_ADDR,
2077 SET_BT_WREG_VAL,
2078 SET_BT_RREG_ADDR,
2079 SET_BT_WL_CH_INFO,
2080 SET_BT_INFO_REPORT,
2081 SET_BT_IGNORE_WLAN_ACT,
2082 SET_BT_TX_PWR,
2083 SET_BT_LNA_CONSTRAIN,
2084 SET_BT_QUERY_DEV_LIST,
2085 SET_BT_QUERY_DEV_INFO,
2086 SET_BT_PSD_REPORT,
2087 SET_H2C_TEST,
2088 SET_IOFLD_RF,
2089 SET_IOFLD_BB,
2090 SET_IOFLD_MAC,
2091 SET_IOFLD_SCBD,
2092 SET_H2C_MACRO,
2093 SET_MAX1,
2094};
2095
2096enum rtw89_btc_cxdrvinfo {
2097 CXDRVINFO_INIT = 0,
2098 CXDRVINFO_ROLE,
2099 CXDRVINFO_DBCC,
2100 CXDRVINFO_SMAP,
2101 CXDRVINFO_RFK,
2102 CXDRVINFO_RUN,
2103 CXDRVINFO_CTRL,
2104 CXDRVINFO_SCAN,
2105 CXDRVINFO_TRX, /* WL traffic to WL fw */
2106 CXDRVINFO_TXPWR,
2107 CXDRVINFO_FDDT,
2108 CXDRVINFO_MLO,
2109 CXDRVINFO_OSI,
2110 CXDRVINFO_MAX,
2111};
2112
2113enum rtw89_scan_mode {
2114 RTW89_SCAN_IMMEDIATE,
2115 RTW89_SCAN_DELAY,
2116};
2117
2118enum rtw89_scan_type {
2119 RTW89_SCAN_ONCE,
2120 RTW89_SCAN_NORMAL,
2121 RTW89_SCAN_NORMAL_SLOW,
2122 RTW89_SCAN_SEAMLESS,
2123 RTW89_SCAN_MAX,
2124};
2125
2126static inline void RTW89_SET_FWCMD_CXHDR_TYPE(void *cmd, u8 val)
2127{
2128 u8p_replace_bits((u8 *)(cmd) + 0, val, GENMASK(7, 0));
2129}
2130
2131static inline void RTW89_SET_FWCMD_CXHDR_LEN(void *cmd, u8 val)
2132{
2133 u8p_replace_bits((u8 *)(cmd) + 1, val, GENMASK(7, 0));
2134}
2135
2136struct rtw89_h2c_cxhdr {
2137 u8 type;
2138 u8 len;
2139} __packed;
2140
2141struct rtw89_h2c_cxhdr_v7 {
2142 u8 type;
2143 u8 ver;
2144 u8 len;
2145} __packed;
2146
2147struct rtw89_h2c_cxctrl_v7 {
2148 struct rtw89_h2c_cxhdr_v7 hdr;
2149 struct rtw89_btc_ctrl_v7 ctrl;
2150} __packed;
2151
2152#define H2C_LEN_CXDRVHDR sizeof(struct rtw89_h2c_cxhdr)
2153#define H2C_LEN_CXDRVHDR_V7 sizeof(struct rtw89_h2c_cxhdr_v7)
2154
2155struct rtw89_btc_wl_role_info_v7_u8 {
2156 u8 connect_cnt;
2157 u8 link_mode;
2158 u8 link_mode_chg;
2159 u8 p2p_2g;
2160
2161 struct rtw89_btc_wl_active_role_v7 active_role[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER];
2162} __packed;
2163
2164struct rtw89_btc_wl_role_info_v7_u32 {
2165 __le32 role_map;
2166 __le32 mrole_type;
2167 __le32 mrole_noa_duration;
2168 __le32 dbcc_en;
2169 __le32 dbcc_chg;
2170 __le32 dbcc_2g_phy;
2171} __packed;
2172
2173struct rtw89_h2c_cxrole_v7 {
2174 struct rtw89_h2c_cxhdr_v7 hdr;
2175 struct rtw89_btc_wl_role_info_v7_u8 _u8;
2176 struct rtw89_btc_wl_role_info_v7_u32 _u32;
2177} __packed;
2178
2179struct rtw89_btc_wl_role_info_v8_u8 {
2180 u8 connect_cnt;
2181 u8 link_mode;
2182 u8 link_mode_chg;
2183 u8 p2p_2g;
2184
2185 u8 pta_req_band;
2186 u8 dbcc_en;
2187 u8 dbcc_chg;
2188 u8 dbcc_2g_phy;
2189
2190 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM];
2191} __packed;
2192
2193struct rtw89_btc_wl_role_info_v8_u32 {
2194 __le32 role_map;
2195 __le32 mrole_type;
2196 __le32 mrole_noa_duration;
2197} __packed;
2198
2199struct rtw89_h2c_cxrole_v8 {
2200 struct rtw89_h2c_cxhdr_v7 hdr;
2201 struct rtw89_btc_wl_role_info_v8_u8 _u8;
2202 struct rtw89_btc_wl_role_info_v8_u32 _u32;
2203} __packed;
2204
2205struct rtw89_h2c_cxinit {
2206 struct rtw89_h2c_cxhdr hdr;
2207 u8 ant_type;
2208 u8 ant_num;
2209 u8 ant_iso;
2210 u8 ant_info;
2211 u8 mod_rfe;
2212 u8 mod_cv;
2213 u8 mod_info;
2214 u8 mod_adie_kt;
2215 u8 wl_gch;
2216 u8 info;
2217 u8 rsvd;
2218 u8 rsvd1;
2219} __packed;
2220
2221#define RTW89_H2C_CXINIT_ANT_INFO_POS BIT(0)
2222#define RTW89_H2C_CXINIT_ANT_INFO_DIVERSITY BIT(1)
2223#define RTW89_H2C_CXINIT_ANT_INFO_BTG_POS GENMASK(3, 2)
2224#define RTW89_H2C_CXINIT_ANT_INFO_STREAM_CNT GENMASK(7, 4)
2225
2226#define RTW89_H2C_CXINIT_MOD_INFO_BT_SOLO BIT(0)
2227#define RTW89_H2C_CXINIT_MOD_INFO_BT_POS BIT(1)
2228#define RTW89_H2C_CXINIT_MOD_INFO_SW_TYPE BIT(2)
2229#define RTW89_H2C_CXINIT_MOD_INFO_WA_TYPE GENMASK(5, 3)
2230
2231#define RTW89_H2C_CXINIT_INFO_WL_ONLY BIT(0)
2232#define RTW89_H2C_CXINIT_INFO_WL_INITOK BIT(1)
2233#define RTW89_H2C_CXINIT_INFO_DBCC_EN BIT(2)
2234#define RTW89_H2C_CXINIT_INFO_CX_OTHER BIT(3)
2235#define RTW89_H2C_CXINIT_INFO_BT_ONLY BIT(4)
2236
2237struct rtw89_h2c_cxinit_v7 {
2238 struct rtw89_h2c_cxhdr_v7 hdr;
2239 struct rtw89_btc_init_info_v7 init;
2240} __packed;
2241
2242static inline void RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void *cmd, u8 val)
2243{
2244 u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0));
2245}
2246
2247static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE(void *cmd, u8 val)
2248{
2249 u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0));
2250}
2251
2252static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void *cmd, u16 val)
2253{
2254 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0));
2255}
2256
2257static inline void RTW89_SET_FWCMD_CXROLE_ROLE_STA(void *cmd, u16 val)
2258{
2259 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1));
2260}
2261
2262static inline void RTW89_SET_FWCMD_CXROLE_ROLE_AP(void *cmd, u16 val)
2263{
2264 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2));
2265}
2266
2267static inline void RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void *cmd, u16 val)
2268{
2269 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3));
2270}
2271
2272static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void *cmd, u16 val)
2273{
2274 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4));
2275}
2276
2277static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void *cmd, u16 val)
2278{
2279 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5));
2280}
2281
2282static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void *cmd, u16 val)
2283{
2284 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6));
2285}
2286
2287static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void *cmd, u16 val)
2288{
2289 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7));
2290}
2291
2292static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void *cmd, u16 val)
2293{
2294 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8));
2295}
2296
2297static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void *cmd, u16 val)
2298{
2299 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9));
2300}
2301
2302static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void *cmd, u16 val)
2303{
2304 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10));
2305}
2306
2307static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void *cmd, u16 val)
2308{
2309 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11));
2310}
2311
2312static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void *cmd, u8 val, int n, u8 offset)
2313{
2314 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2315}
2316
2317static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID(void *cmd, u8 val, int n, u8 offset)
2318{
2319 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));
2320}
2321
2322static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY(void *cmd, u8 val, int n, u8 offset)
2323{
2324 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2325}
2326
2327static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA(void *cmd, u8 val, int n, u8 offset)
2328{
2329 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2330}
2331
2332static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND(void *cmd, u8 val, int n, u8 offset)
2333{
2334 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));
2335}
2336
2337static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void *cmd, u8 val, int n, u8 offset)
2338{
2339 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2340}
2341
2342static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW(void *cmd, u8 val, int n, u8 offset)
2343{
2344 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));
2345}
2346
2347static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void *cmd, u8 val, int n, u8 offset)
2348{
2349 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));
2350}
2351
2352static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH(void *cmd, u8 val, int n, u8 offset)
2353{
2354 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));
2355}
2356
2357static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void *cmd, u16 val, int n, u8 offset)
2358{
2359 le16p_replace_bits((__le16 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(15, 0));
2360}
2361
2362static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void *cmd, u16 val, int n, u8 offset)
2363{
2364 le16p_replace_bits((__le16 *)((u8 *)cmd + (12 + (12 + offset) * n)), val, GENMASK(15, 0));
2365}
2366
2367static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void *cmd, u16 val, int n, u8 offset)
2368{
2369 le16p_replace_bits((__le16 *)((u8 *)cmd + (14 + (12 + offset) * n)), val, GENMASK(15, 0));
2370}
2371
2372static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void *cmd, u16 val, int n, u8 offset)
2373{
2374 le16p_replace_bits((__le16 *)((u8 *)cmd + (16 + (12 + offset) * n)), val, GENMASK(15, 0));
2375}
2376
2377static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void *cmd, u32 val, int n, u8 offset)
2378{
2379 le32p_replace_bits((__le32 *)((u8 *)cmd + (20 + (12 + offset) * n)), val, GENMASK(31, 0));
2380}
2381
2382static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2(void *cmd, u8 val, int n, u8 offset)
2383{
2384 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2385}
2386
2387static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID_V2(void *cmd, u8 val, int n, u8 offset)
2388{
2389 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));
2390}
2391
2392static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2(void *cmd, u8 val, int n, u8 offset)
2393{
2394 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2395}
2396
2397static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2(void *cmd, u8 val, int n, u8 offset)
2398{
2399 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2400}
2401
2402static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2(void *cmd, u8 val, int n, u8 offset)
2403{
2404 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));
2405}
2406
2407static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2(void *cmd, u8 val, int n, u8 offset)
2408{
2409 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2410}
2411
2412static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW_V2(void *cmd, u8 val, int n, u8 offset)
2413{
2414 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));
2415}
2416
2417static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2(void *cmd, u8 val, int n, u8 offset)
2418{
2419 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));
2420}
2421
2422static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH_V2(void *cmd, u8 val, int n, u8 offset)
2423{
2424 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));
2425}
2426
2427static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2(void *cmd, u32 val, int n, u8 offset)
2428{
2429 le32p_replace_bits((__le32 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(31, 0));
2430}
2431
2432static inline void RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void *cmd, u32 val, u8 offset)
2433{
2434 le32p_replace_bits((__le32 *)((u8 *)cmd + offset), val, GENMASK(31, 0));
2435}
2436
2437static inline void RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void *cmd, u32 val, u8 offset)
2438{
2439 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 4), val, GENMASK(31, 0));
2440}
2441
2442static inline void RTW89_SET_FWCMD_CXROLE_DBCC_EN(void *cmd, u32 val, u8 offset)
2443{
2444 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(0));
2445}
2446
2447static inline void RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void *cmd, u32 val, u8 offset)
2448{
2449 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(1));
2450}
2451
2452static inline void RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void *cmd, u32 val, u8 offset)
2453{
2454 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, GENMASK(3, 2));
2455}
2456
2457static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void *cmd, u32 val, u8 offset)
2458{
2459 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(4));
2460}
2461
2462static inline void RTW89_SET_FWCMD_CXCTRL_MANUAL(void *cmd, u32 val)
2463{
2464 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0));
2465}
2466
2467static inline void RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void *cmd, u32 val)
2468{
2469 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1));
2470}
2471
2472static inline void RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void *cmd, u32 val)
2473{
2474 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2));
2475}
2476
2477static inline void RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void *cmd, u32 val)
2478{
2479 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(18, 3));
2480}
2481
2482static inline void RTW89_SET_FWCMD_CXTRX_TXLV(void *cmd, u8 val)
2483{
2484 u8p_replace_bits((u8 *)cmd + 2, val, GENMASK(7, 0));
2485}
2486
2487static inline void RTW89_SET_FWCMD_CXTRX_RXLV(void *cmd, u8 val)
2488{
2489 u8p_replace_bits((u8 *)cmd + 3, val, GENMASK(7, 0));
2490}
2491
2492static inline void RTW89_SET_FWCMD_CXTRX_WLRSSI(void *cmd, u8 val)
2493{
2494 u8p_replace_bits((u8 *)cmd + 4, val, GENMASK(7, 0));
2495}
2496
2497static inline void RTW89_SET_FWCMD_CXTRX_BTRSSI(void *cmd, u8 val)
2498{
2499 u8p_replace_bits((u8 *)cmd + 5, val, GENMASK(7, 0));
2500}
2501
2502static inline void RTW89_SET_FWCMD_CXTRX_TXPWR(void *cmd, s8 val)
2503{
2504 u8p_replace_bits((u8 *)cmd + 6, val, GENMASK(7, 0));
2505}
2506
2507static inline void RTW89_SET_FWCMD_CXTRX_RXGAIN(void *cmd, s8 val)
2508{
2509 u8p_replace_bits((u8 *)cmd + 7, val, GENMASK(7, 0));
2510}
2511
2512static inline void RTW89_SET_FWCMD_CXTRX_BTTXPWR(void *cmd, s8 val)
2513{
2514 u8p_replace_bits((u8 *)cmd + 8, val, GENMASK(7, 0));
2515}
2516
2517static inline void RTW89_SET_FWCMD_CXTRX_BTRXGAIN(void *cmd, s8 val)
2518{
2519 u8p_replace_bits((u8 *)cmd + 9, val, GENMASK(7, 0));
2520}
2521
2522static inline void RTW89_SET_FWCMD_CXTRX_CN(void *cmd, u8 val)
2523{
2524 u8p_replace_bits((u8 *)cmd + 10, val, GENMASK(7, 0));
2525}
2526
2527static inline void RTW89_SET_FWCMD_CXTRX_NHM(void *cmd, s8 val)
2528{
2529 u8p_replace_bits((u8 *)cmd + 11, val, GENMASK(7, 0));
2530}
2531
2532static inline void RTW89_SET_FWCMD_CXTRX_BTPROFILE(void *cmd, u8 val)
2533{
2534 u8p_replace_bits((u8 *)cmd + 12, val, GENMASK(7, 0));
2535}
2536
2537static inline void RTW89_SET_FWCMD_CXTRX_RSVD2(void *cmd, u8 val)
2538{
2539 u8p_replace_bits((u8 *)cmd + 13, val, GENMASK(7, 0));
2540}
2541
2542static inline void RTW89_SET_FWCMD_CXTRX_TXRATE(void *cmd, u16 val)
2543{
2544 le16p_replace_bits((__le16 *)((u8 *)cmd + 14), val, GENMASK(15, 0));
2545}
2546
2547static inline void RTW89_SET_FWCMD_CXTRX_RXRATE(void *cmd, u16 val)
2548{
2549 le16p_replace_bits((__le16 *)((u8 *)cmd + 16), val, GENMASK(15, 0));
2550}
2551
2552static inline void RTW89_SET_FWCMD_CXTRX_TXTP(void *cmd, u32 val)
2553{
2554 le32p_replace_bits((__le32 *)((u8 *)cmd + 18), val, GENMASK(31, 0));
2555}
2556
2557static inline void RTW89_SET_FWCMD_CXTRX_RXTP(void *cmd, u32 val)
2558{
2559 le32p_replace_bits((__le32 *)((u8 *)cmd + 22), val, GENMASK(31, 0));
2560}
2561
2562static inline void RTW89_SET_FWCMD_CXTRX_RXERRRA(void *cmd, u32 val)
2563{
2564 le32p_replace_bits((__le32 *)((u8 *)cmd + 26), val, GENMASK(31, 0));
2565}
2566
2567static inline void RTW89_SET_FWCMD_CXRFK_STATE(void *cmd, u32 val)
2568{
2569 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(1, 0));
2570}
2571
2572static inline void RTW89_SET_FWCMD_CXRFK_PATH_MAP(void *cmd, u32 val)
2573{
2574 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(5, 2));
2575}
2576
2577static inline void RTW89_SET_FWCMD_CXRFK_PHY_MAP(void *cmd, u32 val)
2578{
2579 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(7, 6));
2580}
2581
2582static inline void RTW89_SET_FWCMD_CXRFK_BAND(void *cmd, u32 val)
2583{
2584 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(9, 8));
2585}
2586
2587static inline void RTW89_SET_FWCMD_CXRFK_TYPE(void *cmd, u32 val)
2588{
2589 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(17, 10));
2590}
2591
2592static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void *cmd, u32 val)
2593{
2594 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));
2595}
2596
2597static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void *cmd, u32 val)
2598{
2599 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(10, 8));
2600}
2601
2602static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void *cmd, u32 val)
2603{
2604 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 16));
2605}
2606
2607struct rtw89_h2c_chinfo_elem {
2608 __le32 w0;
2609 __le32 w1;
2610 __le32 w2;
2611 __le32 w3;
2612 __le32 w4;
2613 __le32 w5;
2614 __le32 w6;
2615} __packed;
2616
2617#define RTW89_H2C_CHINFO_W0_PERIOD GENMASK(7, 0)
2618#define RTW89_H2C_CHINFO_W0_DWELL GENMASK(15, 8)
2619#define RTW89_H2C_CHINFO_W0_CENTER_CH GENMASK(23, 16)
2620#define RTW89_H2C_CHINFO_W0_PRI_CH GENMASK(31, 24)
2621#define RTW89_H2C_CHINFO_W1_BW GENMASK(2, 0)
2622#define RTW89_H2C_CHINFO_W1_ACTION GENMASK(7, 3)
2623#define RTW89_H2C_CHINFO_W1_NUM_PKT GENMASK(11, 8)
2624#define RTW89_H2C_CHINFO_W1_TX BIT(12)
2625#define RTW89_H2C_CHINFO_W1_PAUSE_DATA BIT(13)
2626#define RTW89_H2C_CHINFO_W1_BAND GENMASK(15, 14)
2627#define RTW89_H2C_CHINFO_W1_PKT_ID GENMASK(23, 16)
2628#define RTW89_H2C_CHINFO_W1_DFS BIT(24)
2629#define RTW89_H2C_CHINFO_W1_TX_NULL BIT(25)
2630#define RTW89_H2C_CHINFO_W1_RANDOM BIT(26)
2631#define RTW89_H2C_CHINFO_W1_CFG_TX BIT(27)
2632#define RTW89_H2C_CHINFO_W2_PKT0 GENMASK(7, 0)
2633#define RTW89_H2C_CHINFO_W2_PKT1 GENMASK(15, 8)
2634#define RTW89_H2C_CHINFO_W2_PKT2 GENMASK(23, 16)
2635#define RTW89_H2C_CHINFO_W2_PKT3 GENMASK(31, 24)
2636#define RTW89_H2C_CHINFO_W3_PKT4 GENMASK(7, 0)
2637#define RTW89_H2C_CHINFO_W3_PKT5 GENMASK(15, 8)
2638#define RTW89_H2C_CHINFO_W3_PKT6 GENMASK(23, 16)
2639#define RTW89_H2C_CHINFO_W3_PKT7 GENMASK(31, 24)
2640#define RTW89_H2C_CHINFO_W4_POWER_IDX GENMASK(15, 0)
2641
2642struct rtw89_h2c_chinfo_elem_be {
2643 __le32 w0;
2644 __le32 w1;
2645 __le32 w2;
2646 __le32 w3;
2647 __le32 w4;
2648 __le32 w5;
2649 __le32 w6;
2650} __packed;
2651
2652#define RTW89_H2C_CHINFO_BE_W0_PERIOD GENMASK(7, 0)
2653#define RTW89_H2C_CHINFO_BE_W0_DWELL GENMASK(15, 8)
2654#define RTW89_H2C_CHINFO_BE_W0_CENTER_CH GENMASK(23, 16)
2655#define RTW89_H2C_CHINFO_BE_W0_PRI_CH GENMASK(31, 24)
2656#define RTW89_H2C_CHINFO_BE_W1_BW GENMASK(2, 0)
2657#define RTW89_H2C_CHINFO_BE_W1_CH_BAND GENMASK(4, 3)
2658#define RTW89_H2C_CHINFO_BE_W1_DFS BIT(5)
2659#define RTW89_H2C_CHINFO_BE_W1_PAUSE_DATA BIT(6)
2660#define RTW89_H2C_CHINFO_BE_W1_TX_NULL BIT(7)
2661#define RTW89_H2C_CHINFO_BE_W1_RANDOM BIT(8)
2662#define RTW89_H2C_CHINFO_BE_W1_NOTIFY GENMASK(13, 9)
2663#define RTW89_H2C_CHINFO_BE_W1_PROBE BIT(14)
2664#define RTW89_H2C_CHINFO_BE_W1_EARLY_LEAVE_CRIT GENMASK(17, 15)
2665#define RTW89_H2C_CHINFO_BE_W1_CHKPT_TIMER GENMASK(31, 24)
2666#define RTW89_H2C_CHINFO_BE_W2_EARLY_LEAVE_TIME GENMASK(7, 0)
2667#define RTW89_H2C_CHINFO_BE_W2_EARLY_LEAVE_TH GENMASK(15, 8)
2668#define RTW89_H2C_CHINFO_BE_W2_TX_PKT_CTRL GENMASK(31, 16)
2669#define RTW89_H2C_CHINFO_BE_W3_PKT0 GENMASK(7, 0)
2670#define RTW89_H2C_CHINFO_BE_W3_PKT1 GENMASK(15, 8)
2671#define RTW89_H2C_CHINFO_BE_W3_PKT2 GENMASK(23, 16)
2672#define RTW89_H2C_CHINFO_BE_W3_PKT3 GENMASK(31, 24)
2673#define RTW89_H2C_CHINFO_BE_W4_PKT4 GENMASK(7, 0)
2674#define RTW89_H2C_CHINFO_BE_W4_PKT5 GENMASK(15, 8)
2675#define RTW89_H2C_CHINFO_BE_W4_PKT6 GENMASK(23, 16)
2676#define RTW89_H2C_CHINFO_BE_W4_PKT7 GENMASK(31, 24)
2677#define RTW89_H2C_CHINFO_BE_W5_SW_DEF GENMASK(7, 0)
2678#define RTW89_H2C_CHINFO_BE_W5_FW_PROBE0_SSIDS GENMASK(31, 16)
2679#define RTW89_H2C_CHINFO_BE_W6_FW_PROBE0_SHORTSSIDS GENMASK(15, 0)
2680#define RTW89_H2C_CHINFO_BE_W6_FW_PROBE0_BSSIDS GENMASK(31, 16)
2681
2682struct rtw89_h2c_chinfo {
2683 u8 ch_num;
2684 u8 elem_size;
2685 u8 arg;
2686 u8 rsvd0;
2687 struct rtw89_h2c_chinfo_elem elem[] __counted_by(ch_num);
2688} __packed;
2689
2690#define RTW89_H2C_CHINFO_ARG_MAC_IDX_MASK BIT(0)
2691#define RTW89_H2C_CHINFO_ARG_APPEND_MASK BIT(1)
2692
2693struct rtw89_h2c_scanofld {
2694 __le32 w0;
2695 __le32 w1;
2696 __le32 w2;
2697 __le32 tsf_high;
2698 __le32 tsf_low;
2699 __le32 w5;
2700 __le32 w6;
2701} __packed;
2702
2703#define RTW89_H2C_SCANOFLD_W0_MACID GENMASK(7, 0)
2704#define RTW89_H2C_SCANOFLD_W0_NORM_CY GENMASK(15, 8)
2705#define RTW89_H2C_SCANOFLD_W0_PORT_ID GENMASK(18, 16)
2706#define RTW89_H2C_SCANOFLD_W0_BAND BIT(19)
2707#define RTW89_H2C_SCANOFLD_W0_OPERATION GENMASK(21, 20)
2708#define RTW89_H2C_SCANOFLD_W0_TARGET_CH_BAND GENMASK(23, 22)
2709#define RTW89_H2C_SCANOFLD_W1_NOTIFY_END BIT(0)
2710#define RTW89_H2C_SCANOFLD_W1_TARGET_CH_MODE BIT(1)
2711#define RTW89_H2C_SCANOFLD_W1_START_MODE BIT(2)
2712#define RTW89_H2C_SCANOFLD_W1_SCAN_TYPE GENMASK(4, 3)
2713#define RTW89_H2C_SCANOFLD_W1_TARGET_CH_BW GENMASK(7, 5)
2714#define RTW89_H2C_SCANOFLD_W1_TARGET_PRI_CH GENMASK(15, 8)
2715#define RTW89_H2C_SCANOFLD_W1_TARGET_CENTRAL_CH GENMASK(23, 16)
2716#define RTW89_H2C_SCANOFLD_W1_PROBE_REQ_PKT_ID GENMASK(31, 24)
2717#define RTW89_H2C_SCANOFLD_W2_NORM_PD GENMASK(15, 0)
2718#define RTW89_H2C_SCANOFLD_W2_SLOW_PD GENMASK(23, 16)
2719#define RTW89_H2C_SCANOFLD_W3_TSF_HIGH GENMASK(31, 0)
2720#define RTW89_H2C_SCANOFLD_W4_TSF_LOW GENMASK(31, 0)
2721
2722struct rtw89_h2c_scanofld_be_macc_role {
2723 __le32 w0;
2724} __packed;
2725
2726#define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_BAND GENMASK(1, 0)
2727#define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_PORT GENMASK(4, 2)
2728#define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_MACID GENMASK(23, 8)
2729#define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_OPCH_END GENMASK(31, 24)
2730
2731struct rtw89_h2c_scanofld_be_opch {
2732 __le32 w0;
2733 __le32 w1;
2734 __le32 w2;
2735 __le32 w3;
2736} __packed;
2737
2738#define RTW89_H2C_SCANOFLD_BE_OPCH_W0_MACID GENMASK(15, 0)
2739#define RTW89_H2C_SCANOFLD_BE_OPCH_W0_BAND GENMASK(17, 16)
2740#define RTW89_H2C_SCANOFLD_BE_OPCH_W0_PORT GENMASK(20, 18)
2741#define RTW89_H2C_SCANOFLD_BE_OPCH_W0_POLICY GENMASK(22, 21)
2742#define RTW89_H2C_SCANOFLD_BE_OPCH_W0_TXNULL BIT(23)
2743#define RTW89_H2C_SCANOFLD_BE_OPCH_W0_POLICY_VAL GENMASK(31, 24)
2744#define RTW89_H2C_SCANOFLD_BE_OPCH_W1_DURATION GENMASK(7, 0)
2745#define RTW89_H2C_SCANOFLD_BE_OPCH_W1_CH_BAND GENMASK(9, 8)
2746#define RTW89_H2C_SCANOFLD_BE_OPCH_W1_BW GENMASK(12, 10)
2747#define RTW89_H2C_SCANOFLD_BE_OPCH_W1_NOTIFY GENMASK(14, 13)
2748#define RTW89_H2C_SCANOFLD_BE_OPCH_W1_PRI_CH GENMASK(23, 16)
2749#define RTW89_H2C_SCANOFLD_BE_OPCH_W1_CENTRAL_CH GENMASK(31, 24)
2750#define RTW89_H2C_SCANOFLD_BE_OPCH_W2_PKTS_CTRL GENMASK(7, 0)
2751#define RTW89_H2C_SCANOFLD_BE_OPCH_W2_SW_DEF GENMASK(15, 8)
2752#define RTW89_H2C_SCANOFLD_BE_OPCH_W2_SS GENMASK(18, 16)
2753#define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT0 GENMASK(7, 0)
2754#define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT1 GENMASK(15, 8)
2755#define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT2 GENMASK(23, 16)
2756#define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT3 GENMASK(31, 24)
2757
2758struct rtw89_h2c_scanofld_be {
2759 __le32 w0;
2760 __le32 w1;
2761 __le32 w2;
2762 __le32 w3;
2763 __le32 w4;
2764 __le32 w5;
2765 __le32 w6;
2766 __le32 w7;
2767 __le32 w8;
2768 __le32 w9; /* Added after SCAN_OFFLOAD_BE_V1 */
2769 /* struct rtw89_h2c_scanofld_be_macc_role (flexible number) */
2770 /* struct rtw89_h2c_scanofld_be_opch (flexible number) */
2771} __packed;
2772
2773#define RTW89_H2C_SCANOFLD_BE_W0_OP GENMASK(1, 0)
2774#define RTW89_H2C_SCANOFLD_BE_W0_SCAN_MODE GENMASK(3, 2)
2775#define RTW89_H2C_SCANOFLD_BE_W0_REPEAT GENMASK(5, 4)
2776#define RTW89_H2C_SCANOFLD_BE_W0_NOTIFY_END BIT(6)
2777#define RTW89_H2C_SCANOFLD_BE_W0_LEARN_CH BIT(7)
2778#define RTW89_H2C_SCANOFLD_BE_W0_MACID GENMASK(23, 8)
2779#define RTW89_H2C_SCANOFLD_BE_W0_PORT GENMASK(26, 24)
2780#define RTW89_H2C_SCANOFLD_BE_W0_BAND GENMASK(28, 27)
2781#define RTW89_H2C_SCANOFLD_BE_W0_PROBE_WITH_RATE BIT(29)
2782#define RTW89_H2C_SCANOFLD_BE_W1_NUM_MACC_ROLE GENMASK(7, 0)
2783#define RTW89_H2C_SCANOFLD_BE_W1_NUM_OP GENMASK(15, 8)
2784#define RTW89_H2C_SCANOFLD_BE_W1_NORM_PD GENMASK(31, 16)
2785#define RTW89_H2C_SCANOFLD_BE_W2_SLOW_PD GENMASK(15, 0)
2786#define RTW89_H2C_SCANOFLD_BE_W2_NORM_CY GENMASK(23, 16)
2787#define RTW89_H2C_SCANOFLD_BE_W2_OPCH_END GENMASK(31, 24)
2788#define RTW89_H2C_SCANOFLD_BE_W3_NUM_SSID GENMASK(7, 0)
2789#define RTW89_H2C_SCANOFLD_BE_W3_NUM_SHORT_SSID GENMASK(15, 8)
2790#define RTW89_H2C_SCANOFLD_BE_W3_NUM_BSSID GENMASK(23, 16)
2791#define RTW89_H2C_SCANOFLD_BE_W3_PROBEID GENMASK(31, 24)
2792#define RTW89_H2C_SCANOFLD_BE_W4_PROBE_5G GENMASK(7, 0)
2793#define RTW89_H2C_SCANOFLD_BE_W4_PROBE_6G GENMASK(15, 8)
2794#define RTW89_H2C_SCANOFLD_BE_W4_DELAY_START GENMASK(31, 16)
2795#define RTW89_H2C_SCANOFLD_BE_W5_MLO_MODE GENMASK(31, 0)
2796#define RTW89_H2C_SCANOFLD_BE_W6_CHAN_PROHIB_LOW GENMASK(31, 0)
2797#define RTW89_H2C_SCANOFLD_BE_W7_CHAN_PROHIB_HIGH GENMASK(31, 0)
2798#define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_2GHZ GENMASK(7, 0)
2799#define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_5GHZ GENMASK(15, 8)
2800#define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_6GHZ GENMASK(23, 16)
2801#define RTW89_H2C_SCANOFLD_BE_W9_SIZE_CFG GENMASK(7, 0)
2802#define RTW89_H2C_SCANOFLD_BE_W9_SIZE_MACC GENMASK(15, 8)
2803#define RTW89_H2C_SCANOFLD_BE_W9_SIZE_OP GENMASK(23, 16)
2804
2805struct rtw89_h2c_fwips {
2806 __le32 w0;
2807} __packed;
2808
2809#define RTW89_H2C_FW_IPS_W0_MACID GENMASK(7, 0)
2810#define RTW89_H2C_FW_IPS_W0_ENABLE BIT(8)
2811
2812static inline void RTW89_SET_FWCMD_P2P_MACID(void *cmd, u32 val)
2813{
2814 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
2815}
2816
2817static inline void RTW89_SET_FWCMD_P2P_P2PID(void *cmd, u32 val)
2818{
2819 le32p_replace_bits((__le32 *)cmd, val, GENMASK(11, 8));
2820}
2821
2822static inline void RTW89_SET_FWCMD_P2P_NOAID(void *cmd, u32 val)
2823{
2824 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 12));
2825}
2826
2827static inline void RTW89_SET_FWCMD_P2P_ACT(void *cmd, u32 val)
2828{
2829 le32p_replace_bits((__le32 *)cmd, val, GENMASK(19, 16));
2830}
2831
2832static inline void RTW89_SET_FWCMD_P2P_TYPE(void *cmd, u32 val)
2833{
2834 le32p_replace_bits((__le32 *)cmd, val, BIT(20));
2835}
2836
2837static inline void RTW89_SET_FWCMD_P2P_ALL_SLEP(void *cmd, u32 val)
2838{
2839 le32p_replace_bits((__le32 *)cmd, val, BIT(21));
2840}
2841
2842static inline void RTW89_SET_FWCMD_NOA_START_TIME(void *cmd, __le32 val)
2843{
2844 *((__le32 *)cmd + 1) = val;
2845}
2846
2847static inline void RTW89_SET_FWCMD_NOA_INTERVAL(void *cmd, __le32 val)
2848{
2849 *((__le32 *)cmd + 2) = val;
2850}
2851
2852static inline void RTW89_SET_FWCMD_NOA_DURATION(void *cmd, __le32 val)
2853{
2854 *((__le32 *)cmd + 3) = val;
2855}
2856
2857static inline void RTW89_SET_FWCMD_NOA_COUNT(void *cmd, u32 val)
2858{
2859 le32p_replace_bits((__le32 *)(cmd) + 4, val, GENMASK(7, 0));
2860}
2861
2862static inline void RTW89_SET_FWCMD_NOA_CTWINDOW(void *cmd, u32 val)
2863{
2864 u8 ctwnd;
2865
2866 if (!(val & IEEE80211_P2P_OPPPS_ENABLE_BIT))
2867 return;
2868 ctwnd = FIELD_GET(IEEE80211_P2P_OPPPS_CTWINDOW_MASK, val);
2869 le32p_replace_bits((__le32 *)(cmd) + 4, ctwnd, GENMASK(23, 8));
2870}
2871
2872static inline void RTW89_SET_FWCMD_TSF32_TOGL_BAND(void *cmd, u32 val)
2873{
2874 le32p_replace_bits((__le32 *)cmd, val, BIT(0));
2875}
2876
2877static inline void RTW89_SET_FWCMD_TSF32_TOGL_EN(void *cmd, u32 val)
2878{
2879 le32p_replace_bits((__le32 *)cmd, val, BIT(1));
2880}
2881
2882static inline void RTW89_SET_FWCMD_TSF32_TOGL_PORT(void *cmd, u32 val)
2883{
2884 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 2));
2885}
2886
2887static inline void RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void *cmd, u32 val)
2888{
2889 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 16));
2890}
2891
2892enum rtw89_fw_mcc_c2h_rpt_cfg {
2893 RTW89_FW_MCC_C2H_RPT_OFF = 0,
2894 RTW89_FW_MCC_C2H_RPT_FAIL_ONLY = 1,
2895 RTW89_FW_MCC_C2H_RPT_ALL = 2,
2896};
2897
2898struct rtw89_fw_mcc_add_req {
2899 u8 macid;
2900 u8 central_ch_seg0;
2901 u8 central_ch_seg1;
2902 u8 primary_ch;
2903 enum rtw89_bandwidth bandwidth: 4;
2904 u32 group: 2;
2905 u32 c2h_rpt: 2;
2906 u32 dis_tx_null: 1;
2907 u32 dis_sw_retry: 1;
2908 u32 in_curr_ch: 1;
2909 u32 sw_retry_count: 3;
2910 u32 tx_null_early: 4;
2911 u32 btc_in_2g: 1;
2912 u32 pta_en: 1;
2913 u32 rfk_by_pass: 1;
2914 u32 ch_band_type: 2;
2915 u32 rsvd0: 9;
2916 u32 duration;
2917 u8 courtesy_en;
2918 u8 courtesy_num;
2919 u8 courtesy_target;
2920 u8 rsvd1;
2921};
2922
2923static inline void RTW89_SET_FWCMD_ADD_MCC_MACID(void *cmd, u32 val)
2924{
2925 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
2926}
2927
2928static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void *cmd, u32 val)
2929{
2930 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
2931}
2932
2933static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void *cmd, u32 val)
2934{
2935 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
2936}
2937
2938static inline void RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void *cmd, u32 val)
2939{
2940 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
2941}
2942
2943static inline void RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void *cmd, u32 val)
2944{
2945 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(3, 0));
2946}
2947
2948static inline void RTW89_SET_FWCMD_ADD_MCC_GROUP(void *cmd, u32 val)
2949{
2950 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(5, 4));
2951}
2952
2953static inline void RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void *cmd, u32 val)
2954{
2955 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 6));
2956}
2957
2958static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void *cmd, u32 val)
2959{
2960 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(8));
2961}
2962
2963static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void *cmd, u32 val)
2964{
2965 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(9));
2966}
2967
2968static inline void RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void *cmd, u32 val)
2969{
2970 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(10));
2971}
2972
2973static inline void RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void *cmd, u32 val)
2974{
2975 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(13, 11));
2976}
2977
2978static inline void RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void *cmd, u32 val)
2979{
2980 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(17, 14));
2981}
2982
2983static inline void RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void *cmd, u32 val)
2984{
2985 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(18));
2986}
2987
2988static inline void RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void *cmd, u32 val)
2989{
2990 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(19));
2991}
2992
2993static inline void RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void *cmd, u32 val)
2994{
2995 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(20));
2996}
2997
2998static inline void RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void *cmd, u32 val)
2999{
3000 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(22, 21));
3001}
3002
3003static inline void RTW89_SET_FWCMD_ADD_MCC_DURATION(void *cmd, u32 val)
3004{
3005 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3006}
3007
3008static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void *cmd, u32 val)
3009{
3010 le32p_replace_bits((__le32 *)cmd + 3, val, BIT(0));
3011}
3012
3013static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void *cmd, u32 val)
3014{
3015 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(15, 8));
3016}
3017
3018static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void *cmd, u32 val)
3019{
3020 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(23, 16));
3021}
3022
3023enum rtw89_fw_mcc_old_group_actions {
3024 RTW89_FW_MCC_OLD_GROUP_ACT_NONE = 0,
3025 RTW89_FW_MCC_OLD_GROUP_ACT_REPLACE = 1,
3026};
3027
3028struct rtw89_fw_mcc_start_req {
3029 u32 group: 2;
3030 u32 btc_in_group: 1;
3031 u32 old_group_action: 2;
3032 u32 old_group: 2;
3033 u32 rsvd0: 9;
3034 u32 notify_cnt: 3;
3035 u32 rsvd1: 2;
3036 u32 notify_rxdbg_en: 1;
3037 u32 rsvd2: 2;
3038 u32 macid: 8;
3039 u32 tsf_low;
3040 u32 tsf_high;
3041};
3042
3043static inline void RTW89_SET_FWCMD_START_MCC_GROUP(void *cmd, u32 val)
3044{
3045 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3046}
3047
3048static inline void RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void *cmd, u32 val)
3049{
3050 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3051}
3052
3053static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void *cmd, u32 val)
3054{
3055 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 3));
3056}
3057
3058static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void *cmd, u32 val)
3059{
3060 le32p_replace_bits((__le32 *)cmd, val, GENMASK(6, 5));
3061}
3062
3063static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void *cmd, u32 val)
3064{
3065 le32p_replace_bits((__le32 *)cmd, val, GENMASK(18, 16));
3066}
3067
3068static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void *cmd, u32 val)
3069{
3070 le32p_replace_bits((__le32 *)cmd, val, BIT(21));
3071}
3072
3073static inline void RTW89_SET_FWCMD_START_MCC_MACID(void *cmd, u32 val)
3074{
3075 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3076}
3077
3078static inline void RTW89_SET_FWCMD_START_MCC_TSF_LOW(void *cmd, u32 val)
3079{
3080 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));
3081}
3082
3083static inline void RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void *cmd, u32 val)
3084{
3085 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3086}
3087
3088static inline void RTW89_SET_FWCMD_STOP_MCC_MACID(void *cmd, u32 val)
3089{
3090 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
3091}
3092
3093static inline void RTW89_SET_FWCMD_STOP_MCC_GROUP(void *cmd, u32 val)
3094{
3095 le32p_replace_bits((__le32 *)cmd, val, GENMASK(9, 8));
3096}
3097
3098static inline void RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void *cmd, u32 val)
3099{
3100 le32p_replace_bits((__le32 *)cmd, val, BIT(10));
3101}
3102
3103static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void *cmd, u32 val)
3104{
3105 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3106}
3107
3108static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void *cmd, u32 val)
3109{
3110 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3111}
3112
3113static inline void RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void *cmd, u32 val)
3114{
3115 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3116}
3117
3118struct rtw89_fw_mcc_tsf_req {
3119 u8 group: 2;
3120 u8 rsvd0: 6;
3121 u8 macid_x;
3122 u8 macid_y;
3123 u8 rsvd1;
3124};
3125
3126static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void *cmd, u32 val)
3127{
3128 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3129}
3130
3131static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void *cmd, u32 val)
3132{
3133 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3134}
3135
3136static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void *cmd, u32 val)
3137{
3138 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3139}
3140
3141static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void *cmd, u32 val)
3142{
3143 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3144}
3145
3146static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void *cmd, u32 val)
3147{
3148 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3149}
3150
3151static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void *cmd, u32 val)
3152{
3153 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3154}
3155
3156static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(void *cmd,
3157 u8 *bitmap, u8 len)
3158{
3159 memcpy((__le32 *)cmd + 1, bitmap, len);
3160}
3161
3162static inline void RTW89_SET_FWCMD_MCC_SYNC_GROUP(void *cmd, u32 val)
3163{
3164 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3165}
3166
3167static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void *cmd, u32 val)
3168{
3169 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3170}
3171
3172static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void *cmd, u32 val)
3173{
3174 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3175}
3176
3177static inline void RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void *cmd, u32 val)
3178{
3179 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3180}
3181
3182struct rtw89_fw_mcc_duration {
3183 u32 group: 2;
3184 u32 btc_in_group: 1;
3185 u32 rsvd0: 5;
3186 u32 start_macid: 8;
3187 u32 macid_x: 8;
3188 u32 macid_y: 8;
3189 u32 start_tsf_low;
3190 u32 start_tsf_high;
3191 u32 duration_x;
3192 u32 duration_y;
3193};
3194
3195static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void *cmd, u32 val)
3196{
3197 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3198}
3199
3200static
3201inline void RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void *cmd, u32 val)
3202{
3203 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3204}
3205
3206static
3207inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void *cmd, u32 val)
3208{
3209 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3210}
3211
3212static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void *cmd, u32 val)
3213{
3214 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3215}
3216
3217static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void *cmd, u32 val)
3218{
3219 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3220}
3221
3222static
3223inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void *cmd, u32 val)
3224{
3225 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));
3226}
3227
3228static
3229inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void *cmd, u32 val)
3230{
3231 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3232}
3233
3234static
3235inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void *cmd, u32 val)
3236{
3237 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));
3238}
3239
3240static
3241inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void *cmd, u32 val)
3242{
3243 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));
3244}
3245
3246enum rtw89_h2c_mrc_sch_types {
3247 RTW89_H2C_MRC_SCH_BAND0_ONLY = 0,
3248 RTW89_H2C_MRC_SCH_BAND1_ONLY = 1,
3249 RTW89_H2C_MRC_SCH_DUAL_BAND = 2,
3250};
3251
3252enum rtw89_h2c_mrc_role_types {
3253 RTW89_H2C_MRC_ROLE_WIFI = 0,
3254 RTW89_H2C_MRC_ROLE_BT = 1,
3255 RTW89_H2C_MRC_ROLE_EMPTY = 2,
3256};
3257
3258#define RTW89_MAC_MRC_MAX_ADD_SLOT_NUM 3
3259#define RTW89_MAC_MRC_MAX_ADD_ROLE_NUM_PER_SLOT 1 /* before MLO */
3260
3261struct rtw89_fw_mrc_add_slot_arg {
3262 u16 duration; /* unit: TU */
3263 bool courtesy_en;
3264 u8 courtesy_period;
3265 u8 courtesy_target; /* slot idx */
3266
3267 unsigned int role_num;
3268 struct {
3269 enum rtw89_h2c_mrc_role_types role_type;
3270 bool is_master;
3271 bool en_tx_null;
3272 enum rtw89_band band;
3273 enum rtw89_bandwidth bw;
3274 u8 macid;
3275 u8 central_ch;
3276 u8 primary_ch;
3277 u8 null_early; /* unit: TU */
3278
3279 /* if MLD, for macid: [0, chip::support_mld_num)
3280 * otherwise, for macid: [0, 32)
3281 */
3282 u32 macid_main_bitmap;
3283 /* for MLD, bit X maps to macid: X + chip::support_mld_num */
3284 u32 macid_paired_bitmap;
3285 } roles[RTW89_MAC_MRC_MAX_ADD_ROLE_NUM_PER_SLOT];
3286};
3287
3288struct rtw89_fw_mrc_add_arg {
3289 u8 sch_idx;
3290 enum rtw89_h2c_mrc_sch_types sch_type;
3291 bool btc_in_sch;
3292
3293 unsigned int slot_num;
3294 struct rtw89_fw_mrc_add_slot_arg slots[RTW89_MAC_MRC_MAX_ADD_SLOT_NUM];
3295};
3296
3297struct rtw89_h2c_mrc_add_role {
3298 __le32 w0;
3299 __le32 w1;
3300 __le32 w2;
3301 __le32 macid_main_bitmap;
3302 __le32 macid_paired_bitmap;
3303} __packed;
3304
3305#define RTW89_H2C_MRC_ADD_ROLE_W0_MACID GENMASK(15, 0)
3306#define RTW89_H2C_MRC_ADD_ROLE_W0_ROLE_TYPE GENMASK(23, 16)
3307#define RTW89_H2C_MRC_ADD_ROLE_W0_IS_MASTER BIT(24)
3308#define RTW89_H2C_MRC_ADD_ROLE_W0_IS_ALT_ROLE BIT(25)
3309#define RTW89_H2C_MRC_ADD_ROLE_W0_TX_NULL_EN BIT(26)
3310#define RTW89_H2C_MRC_ADD_ROLE_W0_ROLE_ALT_EN BIT(27)
3311#define RTW89_H2C_MRC_ADD_ROLE_W1_CENTRAL_CH_SEG GENMASK(7, 0)
3312#define RTW89_H2C_MRC_ADD_ROLE_W1_PRI_CH GENMASK(15, 8)
3313#define RTW89_H2C_MRC_ADD_ROLE_W1_BW GENMASK(19, 16)
3314#define RTW89_H2C_MRC_ADD_ROLE_W1_CH_BAND_TYPE GENMASK(21, 20)
3315#define RTW89_H2C_MRC_ADD_ROLE_W1_RFK_BY_PASS BIT(22)
3316#define RTW89_H2C_MRC_ADD_ROLE_W1_CAN_BTC BIT(23)
3317#define RTW89_H2C_MRC_ADD_ROLE_W1_NULL_EARLY GENMASK(31, 24)
3318#define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_PERIOD GENMASK(7, 0)
3319#define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_ROLE_TYPE GENMASK(15, 8)
3320#define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_ROLE_MACID GENMASK(23, 16)
3321
3322struct rtw89_h2c_mrc_add_slot {
3323 __le32 w0;
3324 __le32 w1;
3325 struct rtw89_h2c_mrc_add_role roles[];
3326} __packed;
3327
3328#define RTW89_H2C_MRC_ADD_SLOT_W0_DURATION GENMASK(15, 0)
3329#define RTW89_H2C_MRC_ADD_SLOT_W0_COURTESY_EN BIT(17)
3330#define RTW89_H2C_MRC_ADD_SLOT_W0_ROLE_NUM GENMASK(31, 24)
3331#define RTW89_H2C_MRC_ADD_SLOT_W1_COURTESY_PERIOD GENMASK(7, 0)
3332#define RTW89_H2C_MRC_ADD_SLOT_W1_COURTESY_TARGET GENMASK(15, 8)
3333
3334struct rtw89_h2c_mrc_add {
3335 __le32 w0;
3336 /* Logically append flexible struct rtw89_h2c_mrc_add_slot, but there
3337 * are other flexible array inside it. We cannot access them correctly
3338 * through this struct. So, in case misusing, we don't really declare
3339 * it here.
3340 */
3341} __packed;
3342
3343#define RTW89_H2C_MRC_ADD_W0_SCH_IDX GENMASK(3, 0)
3344#define RTW89_H2C_MRC_ADD_W0_SCH_TYPE GENMASK(7, 4)
3345#define RTW89_H2C_MRC_ADD_W0_SLOT_NUM GENMASK(15, 8)
3346#define RTW89_H2C_MRC_ADD_W0_BTC_IN_SCH BIT(16)
3347
3348enum rtw89_h2c_mrc_start_actions {
3349 RTW89_H2C_MRC_START_ACTION_START_NEW = 0,
3350 RTW89_H2C_MRC_START_ACTION_REPLACE_OLD = 1,
3351};
3352
3353struct rtw89_fw_mrc_start_arg {
3354 u8 sch_idx;
3355 u8 old_sch_idx;
3356 u64 start_tsf;
3357 enum rtw89_h2c_mrc_start_actions action;
3358};
3359
3360struct rtw89_h2c_mrc_start {
3361 __le32 w0;
3362 __le32 start_tsf_low;
3363 __le32 start_tsf_high;
3364} __packed;
3365
3366#define RTW89_H2C_MRC_START_W0_SCH_IDX GENMASK(3, 0)
3367#define RTW89_H2C_MRC_START_W0_OLD_SCH_IDX GENMASK(7, 4)
3368#define RTW89_H2C_MRC_START_W0_ACTION GENMASK(15, 8)
3369
3370struct rtw89_h2c_mrc_del {
3371 __le32 w0;
3372} __packed;
3373
3374#define RTW89_H2C_MRC_DEL_W0_SCH_IDX GENMASK(3, 0)
3375#define RTW89_H2C_MRC_DEL_W0_DEL_ALL BIT(4)
3376#define RTW89_H2C_MRC_DEL_W0_STOP_ONLY BIT(5)
3377#define RTW89_H2C_MRC_DEL_W0_SPECIFIC_ROLE_EN BIT(6)
3378#define RTW89_H2C_MRC_DEL_W0_STOP_SLOT_IDX GENMASK(15, 8)
3379#define RTW89_H2C_MRC_DEL_W0_SPECIFIC_ROLE_MACID GENMASK(31, 16)
3380
3381#define RTW89_MAC_MRC_MAX_REQ_TSF_NUM 2
3382
3383struct rtw89_fw_mrc_req_tsf_arg {
3384 unsigned int num;
3385 struct {
3386 u8 band;
3387 u8 port;
3388 } infos[RTW89_MAC_MRC_MAX_REQ_TSF_NUM];
3389};
3390
3391struct rtw89_h2c_mrc_req_tsf {
3392 u8 req_tsf_num;
3393 u8 infos[] __counted_by(req_tsf_num);
3394} __packed;
3395
3396#define RTW89_H2C_MRC_REQ_TSF_INFO_BAND GENMASK(3, 0)
3397#define RTW89_H2C_MRC_REQ_TSF_INFO_PORT GENMASK(7, 4)
3398
3399enum rtw89_h2c_mrc_upd_bitmap_actions {
3400 RTW89_H2C_MRC_UPD_BITMAP_ACTION_DEL = 0,
3401 RTW89_H2C_MRC_UPD_BITMAP_ACTION_ADD = 1,
3402};
3403
3404struct rtw89_fw_mrc_upd_bitmap_arg {
3405 u8 sch_idx;
3406 u8 macid;
3407 u8 client_macid;
3408 enum rtw89_h2c_mrc_upd_bitmap_actions action;
3409};
3410
3411struct rtw89_h2c_mrc_upd_bitmap {
3412 __le32 w0;
3413 __le32 w1;
3414} __packed;
3415
3416#define RTW89_H2C_MRC_UPD_BITMAP_W0_SCH_IDX GENMASK(3, 0)
3417#define RTW89_H2C_MRC_UPD_BITMAP_W0_ACTION BIT(4)
3418#define RTW89_H2C_MRC_UPD_BITMAP_W0_MACID GENMASK(31, 16)
3419#define RTW89_H2C_MRC_UPD_BITMAP_W1_CLIENT_MACID GENMASK(15, 0)
3420
3421struct rtw89_fw_mrc_sync_arg {
3422 u8 offset; /* unit: TU */
3423 struct {
3424 u8 band;
3425 u8 port;
3426 } src, dest;
3427};
3428
3429struct rtw89_h2c_mrc_sync {
3430 __le32 w0;
3431 __le32 w1;
3432} __packed;
3433
3434#define RTW89_H2C_MRC_SYNC_W0_SYNC_EN BIT(0)
3435#define RTW89_H2C_MRC_SYNC_W0_SRC_PORT GENMASK(11, 8)
3436#define RTW89_H2C_MRC_SYNC_W0_SRC_BAND GENMASK(15, 12)
3437#define RTW89_H2C_MRC_SYNC_W0_DEST_PORT GENMASK(19, 16)
3438#define RTW89_H2C_MRC_SYNC_W0_DEST_BAND GENMASK(23, 20)
3439#define RTW89_H2C_MRC_SYNC_W1_OFFSET GENMASK(15, 0)
3440
3441struct rtw89_fw_mrc_upd_duration_arg {
3442 u8 sch_idx;
3443 u64 start_tsf;
3444
3445 unsigned int slot_num;
3446 struct {
3447 u8 slot_idx;
3448 u16 duration; /* unit: TU */
3449 } slots[RTW89_MAC_MRC_MAX_ADD_SLOT_NUM];
3450};
3451
3452struct rtw89_h2c_mrc_upd_duration {
3453 __le32 w0;
3454 __le32 start_tsf_low;
3455 __le32 start_tsf_high;
3456 __le32 slots[];
3457} __packed;
3458
3459#define RTW89_H2C_MRC_UPD_DURATION_W0_SCH_IDX GENMASK(3, 0)
3460#define RTW89_H2C_MRC_UPD_DURATION_W0_SLOT_NUM GENMASK(15, 8)
3461#define RTW89_H2C_MRC_UPD_DURATION_W0_BTC_IN_SCH BIT(16)
3462#define RTW89_H2C_MRC_UPD_DURATION_SLOT_SLOT_IDX GENMASK(7, 0)
3463#define RTW89_H2C_MRC_UPD_DURATION_SLOT_DURATION GENMASK(31, 16)
3464
3465struct rtw89_h2c_wow_aoac {
3466 __le32 w0;
3467} __packed;
3468
3469#define RTW89_C2H_HEADER_LEN 8
3470
3471struct rtw89_c2h_hdr {
3472 __le32 w0;
3473 __le32 w1;
3474} __packed;
3475
3476#define RTW89_C2H_HDR_W0_CATEGORY GENMASK(1, 0)
3477#define RTW89_C2H_HDR_W0_CLASS GENMASK(7, 2)
3478#define RTW89_C2H_HDR_W0_FUNC GENMASK(15, 8)
3479#define RTW89_C2H_HDR_W1_LEN GENMASK(13, 0)
3480
3481struct rtw89_fw_c2h_attr {
3482 u8 category;
3483 u8 class;
3484 u8 func;
3485 u16 len;
3486};
3487
3488static inline struct rtw89_fw_c2h_attr *RTW89_SKB_C2H_CB(struct sk_buff *skb)
3489{
3490 static_assert(sizeof(skb->cb) >= sizeof(struct rtw89_fw_c2h_attr));
3491
3492 return (struct rtw89_fw_c2h_attr *)skb->cb;
3493}
3494
3495struct rtw89_c2h_done_ack {
3496 __le32 w0;
3497 __le32 w1;
3498 __le32 w2;
3499} __packed;
3500
3501#define RTW89_C2H_DONE_ACK_W2_CAT GENMASK(1, 0)
3502#define RTW89_C2H_DONE_ACK_W2_CLASS GENMASK(7, 2)
3503#define RTW89_C2H_DONE_ACK_W2_FUNC GENMASK(15, 8)
3504#define RTW89_C2H_DONE_ACK_W2_H2C_RETURN GENMASK(23, 16)
3505#define RTW89_C2H_DONE_ACK_W2_H2C_SEQ GENMASK(31, 24)
3506
3507#define RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h) \
3508 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3509#define RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h) \
3510 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
3511#define RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h) \
3512 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3513#define RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h) \
3514 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16))
3515
3516struct rtw89_fw_c2h_log_fmt {
3517 __le16 signature;
3518 u8 feature;
3519 u8 syntax;
3520 __le32 fmt_id;
3521 u8 file_num;
3522 __le16 line_num;
3523 u8 argc;
3524 union {
3525 DECLARE_FLEX_ARRAY(u8, raw);
3526 DECLARE_FLEX_ARRAY(__le32, argv);
3527 } __packed u;
3528} __packed;
3529
3530#define RTW89_C2H_FW_FORMATTED_LOG_MIN_LEN 11
3531#define RTW89_C2H_FW_LOG_FEATURE_PARA_INT BIT(2)
3532#define RTW89_C2H_FW_LOG_MAX_PARA_NUM 16
3533#define RTW89_C2H_FW_LOG_SIGNATURE 0xA5A5
3534#define RTW89_C2H_FW_LOG_STR_BUF_SIZE 512
3535
3536struct rtw89_c2h_mac_bcnfltr_rpt {
3537 __le32 w0;
3538 __le32 w1;
3539 __le32 w2;
3540} __packed;
3541
3542#define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID GENMASK(7, 0)
3543#define RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE GENMASK(9, 8)
3544#define RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT GENMASK(11, 10)
3545#define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA GENMASK(23, 16)
3546
3547struct rtw89_c2h_ra_rpt {
3548 struct rtw89_c2h_hdr hdr;
3549 __le32 w2;
3550 __le32 w3;
3551} __packed;
3552
3553#define RTW89_C2H_RA_RPT_W2_MACID GENMASK(15, 0)
3554#define RTW89_C2H_RA_RPT_W2_RETRY_RATIO GENMASK(23, 16)
3555#define RTW89_C2H_RA_RPT_W2_MCSNSS_B7 BIT(31)
3556#define RTW89_C2H_RA_RPT_W3_MCSNSS GENMASK(6, 0)
3557#define RTW89_C2H_RA_RPT_W3_MD_SEL GENMASK(9, 8)
3558#define RTW89_C2H_RA_RPT_W3_GILTF GENMASK(12, 10)
3559#define RTW89_C2H_RA_RPT_W3_BW GENMASK(14, 13)
3560#define RTW89_C2H_RA_RPT_W3_MD_SEL_B2 BIT(15)
3561#define RTW89_C2H_RA_RPT_W3_BW_B2 BIT(16)
3562
3563/* For WiFi 6 chips:
3564 * VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS
3565 * HT-new: [6:5]: NA, [4:0]: MCS
3566 * For WiFi 7 chips (V1):
3567 * HT, VHT, HE, EHT: [7:5]: NSS, [4:0]: MCS
3568 */
3569#define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4)
3570#define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0)
3571#define RTW89_RA_RATE_MASK_NSS_V1 GENMASK(7, 5)
3572#define RTW89_RA_RATE_MASK_MCS_V1 GENMASK(4, 0)
3573#define RTW89_RA_RATE_MASK_HT_MCS GENMASK(4, 0)
3574#define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \
3575 FIELD_PREP(GENMASK(2, 0), mcs))
3576
3577#define RTW89_GET_MAC_C2H_PKTOFLD_ID(c2h) \
3578 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3579#define RTW89_GET_MAC_C2H_PKTOFLD_OP(c2h) \
3580 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(10, 8))
3581#define RTW89_GET_MAC_C2H_PKTOFLD_LEN(c2h) \
3582 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 16))
3583
3584struct rtw89_c2h_scanofld {
3585 __le32 w0;
3586 __le32 w1;
3587 __le32 w2;
3588 __le32 w3;
3589 __le32 w4;
3590 __le32 w5;
3591 __le32 w6;
3592 __le32 w7;
3593} __packed;
3594
3595#define RTW89_C2H_SCANOFLD_W2_PRI_CH GENMASK(7, 0)
3596#define RTW89_C2H_SCANOFLD_W2_RSN GENMASK(19, 16)
3597#define RTW89_C2H_SCANOFLD_W2_STATUS GENMASK(23, 20)
3598#define RTW89_C2H_SCANOFLD_W2_PERIOD GENMASK(31, 24)
3599#define RTW89_C2H_SCANOFLD_W5_TX_FAIL GENMASK(3, 0)
3600#define RTW89_C2H_SCANOFLD_W5_AIR_DENSITY GENMASK(7, 4)
3601#define RTW89_C2H_SCANOFLD_W5_BAND GENMASK(25, 24)
3602#define RTW89_C2H_SCANOFLD_W5_MAC_IDX BIT(26)
3603#define RTW89_C2H_SCANOFLD_W6_SW_DEF GENMASK(7, 0)
3604#define RTW89_C2H_SCANOFLD_W6_EXPECT_PERIOD GENMASK(15, 8)
3605#define RTW89_C2H_SCANOFLD_W6_FW_DEF GENMASK(23, 16)
3606#define RTW89_C2H_SCANOFLD_W7_REPORT_TSF GENMASK(31, 0)
3607
3608#define RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h) \
3609 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3610#define RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h) \
3611 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3612
3613#define RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h) \
3614 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3615#define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h) \
3616 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
3617#define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h) \
3618 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3619
3620struct rtw89_mac_mcc_tsf_rpt {
3621 u32 macid_x;
3622 u32 macid_y;
3623 u32 tsf_x_low;
3624 u32 tsf_x_high;
3625 u32 tsf_y_low;
3626 u32 tsf_y_high;
3627};
3628
3629static_assert(sizeof(struct rtw89_mac_mcc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE);
3630
3631#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h) \
3632 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3633#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h) \
3634 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3635#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h) \
3636 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(17, 16))
3637#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h) \
3638 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
3639#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h) \
3640 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
3641#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h) \
3642 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(31, 0))
3643#define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h) \
3644 le32_get_bits(*((const __le32 *)(c2h) + 6), GENMASK(31, 0))
3645
3646#define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h) \
3647 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(5, 0))
3648#define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h) \
3649 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 6))
3650#define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h) \
3651 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3652#define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h) \
3653 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
3654#define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h) \
3655 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
3656
3657struct rtw89_mac_mrc_tsf_rpt {
3658 unsigned int num;
3659 u64 tsfs[RTW89_MAC_MRC_MAX_REQ_TSF_NUM];
3660};
3661
3662static_assert(sizeof(struct rtw89_mac_mrc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE);
3663
3664struct rtw89_c2h_mrc_tsf_rpt_info {
3665 __le32 tsf_low;
3666 __le32 tsf_high;
3667} __packed;
3668
3669struct rtw89_c2h_mrc_tsf_rpt {
3670 struct rtw89_c2h_hdr hdr;
3671 __le32 w2;
3672 struct rtw89_c2h_mrc_tsf_rpt_info infos[];
3673} __packed;
3674
3675#define RTW89_C2H_MRC_TSF_RPT_W2_REQ_TSF_NUM GENMASK(7, 0)
3676
3677struct rtw89_c2h_mrc_status_rpt {
3678 struct rtw89_c2h_hdr hdr;
3679 __le32 w2;
3680 __le32 tsf_low;
3681 __le32 tsf_high;
3682} __packed;
3683
3684#define RTW89_C2H_MRC_STATUS_RPT_W2_STATUS GENMASK(5, 0)
3685#define RTW89_C2H_MRC_STATUS_RPT_W2_SCH_IDX GENMASK(7, 6)
3686
3687struct rtw89_c2h_pkt_ofld_rsp {
3688 __le32 w0;
3689 __le32 w1;
3690 __le32 w2;
3691} __packed;
3692
3693#define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID GENMASK(7, 0)
3694#define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP GENMASK(10, 8)
3695#define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN GENMASK(31, 16)
3696
3697struct rtw89_c2h_tx_duty_rpt {
3698 struct rtw89_c2h_hdr c2h_hdr;
3699 __le32 w2;
3700} __packed;
3701
3702#define RTW89_C2H_TX_DUTY_RPT_W2_TIMER_ERR GENMASK(2, 0)
3703
3704struct rtw89_c2h_wow_aoac_report {
3705 struct rtw89_c2h_hdr c2h_hdr;
3706 u8 rpt_ver;
3707 u8 sec_type;
3708 u8 key_idx;
3709 u8 pattern_idx;
3710 u8 rekey_ok;
3711 u8 rsvd1[3];
3712 u8 ptk_tx_iv[8];
3713 u8 eapol_key_replay_count[8];
3714 u8 gtk[32];
3715 u8 ptk_rx_iv[8];
3716 u8 gtk_rx_iv[4][8];
3717 __le64 igtk_key_id;
3718 __le64 igtk_ipn;
3719 u8 igtk[32];
3720 u8 csa_pri_ch;
3721 u8 csa_bw_ch_offset;
3722 u8 csa_ch_band_chsw_failed;
3723 u8 csa_rsvd1;
3724} __packed;
3725
3726#define RTW89_C2H_WOW_AOAC_RPT_REKEY_IDX BIT(0)
3727
3728struct rtw89_h2c_tx_duty {
3729 __le32 w0;
3730 __le32 w1;
3731} __packed;
3732
3733#define RTW89_H2C_TX_DUTY_W0_PAUSE_INTVL_MASK GENMASK(15, 0)
3734#define RTW89_H2C_TX_DUTY_W0_TX_INTVL_MASK GENMASK(31, 16)
3735#define RTW89_H2C_TX_DUTY_W1_STOP BIT(0)
3736
3737struct rtw89_h2c_bcnfltr {
3738 __le32 w0;
3739} __packed;
3740
3741#define RTW89_H2C_BCNFLTR_W0_MON_RSSI BIT(0)
3742#define RTW89_H2C_BCNFLTR_W0_MON_BCN BIT(1)
3743#define RTW89_H2C_BCNFLTR_W0_MON_EN BIT(2)
3744#define RTW89_H2C_BCNFLTR_W0_MODE GENMASK(4, 3)
3745#define RTW89_H2C_BCNFLTR_W0_BCN_LOSS_CNT GENMASK(11, 8)
3746#define RTW89_H2C_BCNFLTR_W0_RSSI_HYST GENMASK(15, 12)
3747#define RTW89_H2C_BCNFLTR_W0_RSSI_THRESHOLD GENMASK(23, 16)
3748#define RTW89_H2C_BCNFLTR_W0_MAC_ID GENMASK(31, 24)
3749
3750struct rtw89_h2c_ofld_rssi {
3751 __le32 w0;
3752 __le32 w1;
3753} __packed;
3754
3755#define RTW89_H2C_OFLD_RSSI_W0_MACID GENMASK(7, 0)
3756#define RTW89_H2C_OFLD_RSSI_W0_NUM GENMASK(15, 8)
3757#define RTW89_H2C_OFLD_RSSI_W1_VAL GENMASK(7, 0)
3758
3759struct rtw89_h2c_ofld {
3760 __le32 w0;
3761} __packed;
3762
3763#define RTW89_H2C_OFLD_W0_MAC_ID GENMASK(7, 0)
3764#define RTW89_H2C_OFLD_W0_TX_TP GENMASK(17, 8)
3765#define RTW89_H2C_OFLD_W0_RX_TP GENMASK(27, 18)
3766
3767#define RTW89_MFW_SIG 0xFF
3768
3769struct rtw89_mfw_info {
3770 u8 cv;
3771 u8 type; /* enum rtw89_fw_type */
3772 u8 mp;
3773 u8 rsvd;
3774 __le32 shift;
3775 __le32 size;
3776 u8 rsvd2[4];
3777} __packed;
3778
3779struct rtw89_mfw_hdr {
3780 u8 sig; /* RTW89_MFW_SIG */
3781 u8 fw_nr;
3782 u8 rsvd0[2];
3783 struct {
3784 u8 major;
3785 u8 minor;
3786 u8 sub;
3787 u8 idx;
3788 } ver;
3789 u8 rsvd1[8];
3790 struct rtw89_mfw_info info[];
3791} __packed;
3792
3793struct rtw89_fw_logsuit_hdr {
3794 __le32 rsvd;
3795 __le32 count;
3796 __le32 ids[];
3797} __packed;
3798
3799#define RTW89_FW_ELEMENT_ALIGN 16
3800
3801enum rtw89_fw_element_id {
3802 RTW89_FW_ELEMENT_ID_BBMCU0 = 0,
3803 RTW89_FW_ELEMENT_ID_BBMCU1 = 1,
3804 RTW89_FW_ELEMENT_ID_BB_REG = 2,
3805 RTW89_FW_ELEMENT_ID_BB_GAIN = 3,
3806 RTW89_FW_ELEMENT_ID_RADIO_A = 4,
3807 RTW89_FW_ELEMENT_ID_RADIO_B = 5,
3808 RTW89_FW_ELEMENT_ID_RADIO_C = 6,
3809 RTW89_FW_ELEMENT_ID_RADIO_D = 7,
3810 RTW89_FW_ELEMENT_ID_RF_NCTL = 8,
3811 RTW89_FW_ELEMENT_ID_TXPWR_BYRATE = 9,
3812 RTW89_FW_ELEMENT_ID_TXPWR_LMT_2GHZ = 10,
3813 RTW89_FW_ELEMENT_ID_TXPWR_LMT_5GHZ = 11,
3814 RTW89_FW_ELEMENT_ID_TXPWR_LMT_6GHZ = 12,
3815 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_2GHZ = 13,
3816 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_5GHZ = 14,
3817 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_6GHZ = 15,
3818 RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT = 16,
3819 RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT_RU = 17,
3820 RTW89_FW_ELEMENT_ID_TXPWR_TRK = 18,
3821 RTW89_FW_ELEMENT_ID_RFKLOG_FMT = 19,
3822
3823 RTW89_FW_ELEMENT_ID_NUM,
3824};
3825
3826#define BITS_OF_RTW89_TXPWR_FW_ELEMENTS_NO_6GHZ \
3827 (BIT(RTW89_FW_ELEMENT_ID_TXPWR_BYRATE) | \
3828 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_2GHZ) | \
3829 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_5GHZ) | \
3830 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_2GHZ) | \
3831 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_5GHZ) | \
3832 BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT) | \
3833 BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT_RU))
3834
3835#define BITS_OF_RTW89_TXPWR_FW_ELEMENTS \
3836 (BITS_OF_RTW89_TXPWR_FW_ELEMENTS_NO_6GHZ | \
3837 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_6GHZ) | \
3838 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_6GHZ))
3839
3840#define RTW89_AX_GEN_DEF_NEEDED_FW_ELEMENTS_NO_6GHZ \
3841 (BIT(RTW89_FW_ELEMENT_ID_BB_REG) | \
3842 BIT(RTW89_FW_ELEMENT_ID_RADIO_A) | \
3843 BIT(RTW89_FW_ELEMENT_ID_RADIO_B) | \
3844 BIT(RTW89_FW_ELEMENT_ID_RF_NCTL) | \
3845 BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \
3846 BITS_OF_RTW89_TXPWR_FW_ELEMENTS_NO_6GHZ)
3847
3848#define RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS (BIT(RTW89_FW_ELEMENT_ID_BBMCU0) | \
3849 BIT(RTW89_FW_ELEMENT_ID_BB_REG) | \
3850 BIT(RTW89_FW_ELEMENT_ID_RADIO_A) | \
3851 BIT(RTW89_FW_ELEMENT_ID_RADIO_B) | \
3852 BIT(RTW89_FW_ELEMENT_ID_RF_NCTL) | \
3853 BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \
3854 BITS_OF_RTW89_TXPWR_FW_ELEMENTS)
3855
3856struct __rtw89_fw_txpwr_element {
3857 u8 rsvd0;
3858 u8 rsvd1;
3859 u8 rfe_type;
3860 u8 ent_sz;
3861 __le32 num_ents;
3862 u8 content[];
3863} __packed;
3864
3865enum rtw89_fw_txpwr_trk_type {
3866 __RTW89_FW_TXPWR_TRK_TYPE_6GHZ_START = 0,
3867 RTW89_FW_TXPWR_TRK_TYPE_6GB_N = 0,
3868 RTW89_FW_TXPWR_TRK_TYPE_6GB_P = 1,
3869 RTW89_FW_TXPWR_TRK_TYPE_6GA_N = 2,
3870 RTW89_FW_TXPWR_TRK_TYPE_6GA_P = 3,
3871 __RTW89_FW_TXPWR_TRK_TYPE_6GHZ_MAX = 3,
3872
3873 __RTW89_FW_TXPWR_TRK_TYPE_5GHZ_START = 4,
3874 RTW89_FW_TXPWR_TRK_TYPE_5GB_N = 4,
3875 RTW89_FW_TXPWR_TRK_TYPE_5GB_P = 5,
3876 RTW89_FW_TXPWR_TRK_TYPE_5GA_N = 6,
3877 RTW89_FW_TXPWR_TRK_TYPE_5GA_P = 7,
3878 __RTW89_FW_TXPWR_TRK_TYPE_5GHZ_MAX = 7,
3879
3880 __RTW89_FW_TXPWR_TRK_TYPE_2GHZ_START = 8,
3881 RTW89_FW_TXPWR_TRK_TYPE_2GB_N = 8,
3882 RTW89_FW_TXPWR_TRK_TYPE_2GB_P = 9,
3883 RTW89_FW_TXPWR_TRK_TYPE_2GA_N = 10,
3884 RTW89_FW_TXPWR_TRK_TYPE_2GA_P = 11,
3885 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N = 12,
3886 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_P = 13,
3887 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N = 14,
3888 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P = 15,
3889 __RTW89_FW_TXPWR_TRK_TYPE_2GHZ_MAX = 15,
3890
3891 RTW89_FW_TXPWR_TRK_TYPE_NR,
3892};
3893
3894struct rtw89_fw_txpwr_track_cfg {
3895 const s8 (*delta[RTW89_FW_TXPWR_TRK_TYPE_NR])[DELTA_SWINGIDX_SIZE];
3896};
3897
3898#define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_6GHZ \
3899 (BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_N) | \
3900 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_P) | \
3901 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_N) | \
3902 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_P))
3903#define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_5GHZ \
3904 (BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_N) | \
3905 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_P) | \
3906 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_N) | \
3907 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_P))
3908#define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_2GHZ \
3909 (BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_N) | \
3910 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_P) | \
3911 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_N) | \
3912 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_P) | \
3913 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N) | \
3914 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_P) | \
3915 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N) | \
3916 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P))
3917
3918struct rtw89_fw_element_hdr {
3919 __le32 id; /* enum rtw89_fw_element_id */
3920 __le32 size; /* exclude header size */
3921 u8 ver[4];
3922 __le32 rsvd0;
3923 __le32 rsvd1;
3924 __le32 rsvd2;
3925 union {
3926 struct {
3927 u8 priv[8];
3928 u8 contents[];
3929 } __packed common;
3930 struct {
3931 u8 idx;
3932 u8 rsvd[7];
3933 struct {
3934 __le32 addr;
3935 __le32 data;
3936 } __packed regs[];
3937 } __packed reg2;
3938 struct {
3939 u8 cv;
3940 u8 priv[7];
3941 u8 contents[];
3942 } __packed bbmcu;
3943 struct {
3944 __le32 bitmap; /* bitmap of enum rtw89_fw_txpwr_trk_type */
3945 __le32 rsvd;
3946 s8 contents[][DELTA_SWINGIDX_SIZE];
3947 } __packed txpwr_trk;
3948 struct {
3949 u8 nr;
3950 u8 rsvd[3];
3951 u8 rfk_id; /* enum rtw89_phy_c2h_rfk_log_func */
3952 u8 rsvd1[3];
3953 __le16 offset[];
3954 } __packed rfk_log_fmt;
3955 struct __rtw89_fw_txpwr_element txpwr;
3956 } __packed u;
3957} __packed;
3958
3959struct fwcmd_hdr {
3960 __le32 hdr0;
3961 __le32 hdr1;
3962};
3963
3964union rtw89_compat_fw_hdr {
3965 struct rtw89_mfw_hdr mfw_hdr;
3966 struct rtw89_fw_hdr fw_hdr;
3967};
3968
3969static inline u32 rtw89_compat_fw_hdr_ver_code(const void *fw_buf)
3970{
3971 const union rtw89_compat_fw_hdr *compat = (typeof(compat))fw_buf;
3972
3973 if (compat->mfw_hdr.sig == RTW89_MFW_SIG)
3974 return RTW89_MFW_HDR_VER_CODE(&compat->mfw_hdr);
3975 else
3976 return RTW89_FW_HDR_VER_CODE(&compat->fw_hdr);
3977}
3978
3979static inline void rtw89_fw_get_filename(char *buf, size_t size,
3980 const char *fw_basename, int fw_format)
3981{
3982 if (fw_format <= 0)
3983 snprintf(buf, size, "%s.bin", fw_basename);
3984 else
3985 snprintf(buf, size, "%s-%d.bin", fw_basename, fw_format);
3986}
3987
3988#define RTW89_H2C_RF_PAGE_SIZE 500
3989#define RTW89_H2C_RF_PAGE_NUM 3
3990struct rtw89_fw_h2c_rf_reg_info {
3991 enum rtw89_rf_path rf_path;
3992 __le32 rtw89_phy_config_rf_h2c[RTW89_H2C_RF_PAGE_NUM][RTW89_H2C_RF_PAGE_SIZE];
3993 u16 curr_idx;
3994};
3995
3996#define H2C_SEC_CAM_LEN 24
3997
3998#define H2C_HEADER_LEN 8
3999#define H2C_HDR_CAT GENMASK(1, 0)
4000#define H2C_HDR_CLASS GENMASK(7, 2)
4001#define H2C_HDR_FUNC GENMASK(15, 8)
4002#define H2C_HDR_DEL_TYPE GENMASK(19, 16)
4003#define H2C_HDR_H2C_SEQ GENMASK(31, 24)
4004#define H2C_HDR_TOTAL_LEN GENMASK(13, 0)
4005#define H2C_HDR_REC_ACK BIT(14)
4006#define H2C_HDR_DONE_ACK BIT(15)
4007
4008#define FWCMD_TYPE_H2C 0
4009
4010#define H2C_CAT_TEST 0x0
4011
4012/* CLASS 5 - FW STATUS TEST */
4013#define H2C_CL_FW_STATUS_TEST 0x5
4014#define H2C_FUNC_CPU_EXCEPTION 0x1
4015
4016#define H2C_CAT_MAC 0x1
4017
4018/* CLASS 0 - FW INFO */
4019#define H2C_CL_FW_INFO 0x0
4020#define H2C_FUNC_LOG_CFG 0x0
4021#define H2C_FUNC_MAC_GENERAL_PKT 0x1
4022
4023/* CLASS 1 - WOW */
4024#define H2C_CL_MAC_WOW 0x1
4025enum rtw89_wow_h2c_func {
4026 H2C_FUNC_KEEP_ALIVE = 0x0,
4027 H2C_FUNC_DISCONNECT_DETECT = 0x1,
4028 H2C_FUNC_WOW_GLOBAL = 0x2,
4029 H2C_FUNC_GTK_OFLD = 0x3,
4030 H2C_FUNC_ARP_OFLD = 0x4,
4031 H2C_FUNC_NLO = 0x7,
4032 H2C_FUNC_WAKEUP_CTRL = 0x8,
4033 H2C_FUNC_WOW_CAM_UPD = 0xC,
4034 H2C_FUNC_AOAC_REPORT_REQ = 0xD,
4035
4036 NUM_OF_RTW89_WOW_H2C_FUNC,
4037};
4038
4039#define RTW89_WOW_WAIT_COND(tag, func) \
4040 ((tag) * NUM_OF_RTW89_WOW_H2C_FUNC + (func))
4041
4042#define RTW89_WOW_WAIT_COND_AOAC \
4043 RTW89_WOW_WAIT_COND(0 /* don't care */, H2C_FUNC_AOAC_REPORT_REQ)
4044
4045/* CLASS 2 - PS */
4046#define H2C_CL_MAC_PS 0x2
4047enum rtw89_ps_h2c_func {
4048 H2C_FUNC_MAC_LPS_PARM = 0x0,
4049 H2C_FUNC_P2P_ACT = 0x1,
4050 H2C_FUNC_IPS_CFG = 0x3,
4051
4052 NUM_OF_RTW89_PS_H2C_FUNC,
4053};
4054
4055#define RTW89_PS_WAIT_COND(tag, func) \
4056 ((tag) * NUM_OF_RTW89_PS_H2C_FUNC + (func))
4057
4058#define RTW89_PS_WAIT_COND_IPS_CFG \
4059 RTW89_PS_WAIT_COND(0 /* don't care */, H2C_FUNC_IPS_CFG)
4060
4061/* CLASS 3 - FW download */
4062#define H2C_CL_MAC_FWDL 0x3
4063#define H2C_FUNC_MAC_FWHDR_DL 0x0
4064
4065/* CLASS 5 - Frame Exchange */
4066#define H2C_CL_MAC_FR_EXCHG 0x5
4067#define H2C_FUNC_MAC_CCTLINFO_UD 0x2
4068#define H2C_FUNC_MAC_BCN_UPD 0x5
4069#define H2C_FUNC_MAC_DCTLINFO_UD_V1 0x9
4070#define H2C_FUNC_MAC_CCTLINFO_UD_V1 0xa
4071#define H2C_FUNC_MAC_DCTLINFO_UD_V2 0xc
4072#define H2C_FUNC_MAC_BCN_UPD_BE 0xd
4073#define H2C_FUNC_MAC_CCTLINFO_UD_G7 0x11
4074
4075/* CLASS 6 - Address CAM */
4076#define H2C_CL_MAC_ADDR_CAM_UPDATE 0x6
4077#define H2C_FUNC_MAC_ADDR_CAM_UPD 0x0
4078
4079/* CLASS 8 - Media Status Report */
4080#define H2C_CL_MAC_MEDIA_RPT 0x8
4081#define H2C_FUNC_MAC_JOININFO 0x0
4082#define H2C_FUNC_MAC_FWROLE_MAINTAIN 0x4
4083#define H2C_FUNC_NOTIFY_DBCC 0x5
4084
4085/* CLASS 9 - FW offload */
4086#define H2C_CL_MAC_FW_OFLD 0x9
4087enum rtw89_fw_ofld_h2c_func {
4088 H2C_FUNC_PACKET_OFLD = 0x1,
4089 H2C_FUNC_MAC_MACID_PAUSE = 0x8,
4090 H2C_FUNC_USR_EDCA = 0xF,
4091 H2C_FUNC_TSF32_TOGL = 0x10,
4092 H2C_FUNC_OFLD_CFG = 0x14,
4093 H2C_FUNC_ADD_SCANOFLD_CH = 0x16,
4094 H2C_FUNC_SCANOFLD = 0x17,
4095 H2C_FUNC_TX_DUTY = 0x18,
4096 H2C_FUNC_PKT_DROP = 0x1b,
4097 H2C_FUNC_CFG_BCNFLTR = 0x1e,
4098 H2C_FUNC_OFLD_RSSI = 0x1f,
4099 H2C_FUNC_OFLD_TP = 0x20,
4100 H2C_FUNC_MAC_MACID_PAUSE_SLEEP = 0x28,
4101 H2C_FUNC_SCANOFLD_BE = 0x2c,
4102
4103 NUM_OF_RTW89_FW_OFLD_H2C_FUNC,
4104};
4105
4106#define RTW89_FW_OFLD_WAIT_COND(tag, func) \
4107 ((tag) * NUM_OF_RTW89_FW_OFLD_H2C_FUNC + (func))
4108
4109#define RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op) \
4110 RTW89_FW_OFLD_WAIT_COND(RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op), \
4111 H2C_FUNC_PACKET_OFLD)
4112
4113#define RTW89_SCANOFLD_WAIT_COND_ADD_CH RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_ADD_SCANOFLD_CH)
4114
4115#define RTW89_SCANOFLD_WAIT_COND_START RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_SCANOFLD)
4116#define RTW89_SCANOFLD_WAIT_COND_STOP RTW89_FW_OFLD_WAIT_COND(1, H2C_FUNC_SCANOFLD)
4117#define RTW89_SCANOFLD_BE_WAIT_COND_START RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_SCANOFLD_BE)
4118#define RTW89_SCANOFLD_BE_WAIT_COND_STOP RTW89_FW_OFLD_WAIT_COND(1, H2C_FUNC_SCANOFLD_BE)
4119
4120
4121/* CLASS 10 - Security CAM */
4122#define H2C_CL_MAC_SEC_CAM 0xa
4123#define H2C_FUNC_MAC_SEC_UPD 0x1
4124
4125/* CLASS 12 - BA CAM */
4126#define H2C_CL_BA_CAM 0xc
4127#define H2C_FUNC_MAC_BA_CAM 0x0
4128#define H2C_FUNC_MAC_BA_CAM_V1 0x1
4129#define H2C_FUNC_MAC_BA_CAM_INIT 0x2
4130
4131/* CLASS 14 - MCC */
4132#define H2C_CL_MCC 0xe
4133enum rtw89_mcc_h2c_func {
4134 H2C_FUNC_ADD_MCC = 0x0,
4135 H2C_FUNC_START_MCC = 0x1,
4136 H2C_FUNC_STOP_MCC = 0x2,
4137 H2C_FUNC_DEL_MCC_GROUP = 0x3,
4138 H2C_FUNC_RESET_MCC_GROUP = 0x4,
4139 H2C_FUNC_MCC_REQ_TSF = 0x5,
4140 H2C_FUNC_MCC_MACID_BITMAP = 0x6,
4141 H2C_FUNC_MCC_SYNC = 0x7,
4142 H2C_FUNC_MCC_SET_DURATION = 0x8,
4143
4144 NUM_OF_RTW89_MCC_H2C_FUNC,
4145};
4146
4147#define RTW89_MCC_WAIT_COND(group, func) \
4148 ((group) * NUM_OF_RTW89_MCC_H2C_FUNC + (func))
4149
4150/* CLASS 24 - MRC */
4151#define H2C_CL_MRC 0x18
4152enum rtw89_mrc_h2c_func {
4153 H2C_FUNC_MRC_REQ_TSF = 0x0,
4154 H2C_FUNC_ADD_MRC = 0x1,
4155 H2C_FUNC_START_MRC = 0x2,
4156 H2C_FUNC_DEL_MRC = 0x3,
4157 H2C_FUNC_MRC_SYNC = 0x4,
4158 H2C_FUNC_MRC_UPD_DURATION = 0x5,
4159 H2C_FUNC_MRC_UPD_BITMAP = 0x6,
4160
4161 NUM_OF_RTW89_MRC_H2C_FUNC,
4162};
4163
4164/* can consider MRC's sch_idx as MCC's group */
4165#define RTW89_MRC_WAIT_COND(sch_idx, func) \
4166 ((sch_idx) * NUM_OF_RTW89_MRC_H2C_FUNC + (func))
4167
4168#define RTW89_MRC_WAIT_COND_REQ_TSF \
4169 RTW89_MRC_WAIT_COND(0 /* don't care */, H2C_FUNC_MRC_REQ_TSF)
4170
4171#define H2C_CAT_OUTSRC 0x2
4172
4173#define H2C_CL_OUTSRC_RA 0x1
4174#define H2C_FUNC_OUTSRC_RA_MACIDCFG 0x0
4175
4176#define H2C_CL_OUTSRC_DM 0x2
4177#define H2C_FUNC_FW_LPS_CH_INFO 0xb
4178
4179#define H2C_CL_OUTSRC_RF_REG_A 0x8
4180#define H2C_CL_OUTSRC_RF_REG_B 0x9
4181#define H2C_CL_OUTSRC_RF_FW_NOTIFY 0xa
4182#define H2C_FUNC_OUTSRC_RF_GET_MCCCH 0x2
4183#define H2C_CL_OUTSRC_RF_FW_RFK 0xb
4184
4185enum rtw89_rfk_offload_h2c_func {
4186 H2C_FUNC_RFK_TSSI_OFFLOAD = 0x0,
4187 H2C_FUNC_RFK_IQK_OFFLOAD = 0x1,
4188 H2C_FUNC_RFK_DPK_OFFLOAD = 0x3,
4189 H2C_FUNC_RFK_TXGAPK_OFFLOAD = 0x4,
4190 H2C_FUNC_RFK_DACK_OFFLOAD = 0x5,
4191 H2C_FUNC_RFK_RXDCK_OFFLOAD = 0x6,
4192 H2C_FUNC_RFK_PRE_NOTIFY = 0x8,
4193};
4194
4195struct rtw89_fw_h2c_rf_get_mccch {
4196 __le32 ch_0;
4197 __le32 ch_1;
4198 __le32 band_0;
4199 __le32 band_1;
4200 __le32 current_channel;
4201 __le32 current_band_type;
4202} __packed;
4203
4204#define NUM_OF_RTW89_FW_RFK_PATH 2
4205#define NUM_OF_RTW89_FW_RFK_TBL 3
4206
4207struct rtw89_fw_h2c_rfk_pre_info_common {
4208 struct {
4209 __le32 ch[NUM_OF_RTW89_FW_RFK_PATH][NUM_OF_RTW89_FW_RFK_TBL];
4210 __le32 band[NUM_OF_RTW89_FW_RFK_PATH][NUM_OF_RTW89_FW_RFK_TBL];
4211 } __packed dbcc;
4212
4213 __le32 mlo_mode;
4214 struct {
4215 __le32 cur_ch[NUM_OF_RTW89_FW_RFK_PATH];
4216 __le32 cur_band[NUM_OF_RTW89_FW_RFK_PATH];
4217 } __packed tbl;
4218
4219 __le32 phy_idx;
4220} __packed;
4221
4222struct rtw89_fw_h2c_rfk_pre_info_v0 {
4223 struct rtw89_fw_h2c_rfk_pre_info_common common;
4224
4225 __le32 cur_band;
4226 __le32 cur_bw;
4227 __le32 cur_center_ch;
4228
4229 __le32 ktbl_sel0;
4230 __le32 ktbl_sel1;
4231 __le32 rfmod0;
4232 __le32 rfmod1;
4233
4234 __le32 mlo_1_1;
4235 __le32 rfe_type;
4236 __le32 drv_mode;
4237
4238 struct {
4239 __le32 ch[NUM_OF_RTW89_FW_RFK_PATH];
4240 __le32 band[NUM_OF_RTW89_FW_RFK_PATH];
4241 } __packed mlo;
4242} __packed;
4243
4244struct rtw89_fw_h2c_rfk_pre_info {
4245 struct rtw89_fw_h2c_rfk_pre_info_common common;
4246 __le32 mlo_1_1;
4247} __packed;
4248
4249struct rtw89_h2c_rf_tssi {
4250 __le16 len;
4251 u8 phy;
4252 u8 ch;
4253 u8 bw;
4254 u8 band;
4255 u8 hwtx_en;
4256 u8 cv;
4257 s8 curr_tssi_cck_de[2];
4258 s8 curr_tssi_cck_de_20m[2];
4259 s8 curr_tssi_cck_de_40m[2];
4260 s8 curr_tssi_efuse_cck_de[2];
4261 s8 curr_tssi_ofdm_de[2];
4262 s8 curr_tssi_ofdm_de_20m[2];
4263 s8 curr_tssi_ofdm_de_40m[2];
4264 s8 curr_tssi_ofdm_de_80m[2];
4265 s8 curr_tssi_ofdm_de_160m[2];
4266 s8 curr_tssi_ofdm_de_320m[2];
4267 s8 curr_tssi_efuse_ofdm_de[2];
4268 s8 curr_tssi_ofdm_de_diff_20m[2];
4269 s8 curr_tssi_ofdm_de_diff_80m[2];
4270 s8 curr_tssi_ofdm_de_diff_160m[2];
4271 s8 curr_tssi_ofdm_de_diff_320m[2];
4272 s8 curr_tssi_trim_de[2];
4273 u8 pg_thermal[2];
4274 u8 ftable[2][128];
4275 u8 tssi_mode;
4276} __packed;
4277
4278struct rtw89_h2c_rf_iqk {
4279 __le32 phy_idx;
4280 __le32 dbcc;
4281} __packed;
4282
4283struct rtw89_h2c_rf_dpk {
4284 u8 len;
4285 u8 phy;
4286 u8 dpk_enable;
4287 u8 kpath;
4288 u8 cur_band;
4289 u8 cur_bw;
4290 u8 cur_ch;
4291 u8 dpk_dbg_en;
4292} __packed;
4293
4294struct rtw89_h2c_rf_txgapk {
4295 u8 len;
4296 u8 ktype;
4297 u8 phy;
4298 u8 kpath;
4299 u8 band;
4300 u8 bw;
4301 u8 ch;
4302 u8 cv;
4303} __packed;
4304
4305struct rtw89_h2c_rf_dack {
4306 __le32 len;
4307 __le32 phy;
4308 __le32 type;
4309} __packed;
4310
4311struct rtw89_h2c_rf_rxdck_v0 {
4312 u8 len;
4313 u8 phy;
4314 u8 is_afe;
4315 u8 kpath;
4316 u8 cur_band;
4317 u8 cur_bw;
4318 u8 cur_ch;
4319 u8 rxdck_dbg_en;
4320} __packed;
4321
4322struct rtw89_h2c_rf_rxdck {
4323 struct rtw89_h2c_rf_rxdck_v0 v0;
4324 u8 is_chl_k;
4325} __packed;
4326
4327enum rtw89_rf_log_type {
4328 RTW89_RF_RUN_LOG = 0,
4329 RTW89_RF_RPT_LOG = 1,
4330};
4331
4332struct rtw89_c2h_rf_log_hdr {
4333 u8 type; /* enum rtw89_rf_log_type */
4334 __le16 len;
4335 u8 content[];
4336} __packed;
4337
4338struct rtw89_c2h_rf_run_log {
4339 __le32 fmt_idx;
4340 __le32 arg[4];
4341} __packed;
4342
4343struct rtw89_c2h_rf_iqk_rpt_log {
4344 bool iqk_tx_fail[2];
4345 bool iqk_rx_fail[2];
4346 bool is_iqk_init;
4347 bool is_reload;
4348 bool is_wb_txiqk[2];
4349 bool is_wb_rxiqk[2];
4350 bool is_nbiqk;
4351 bool txiqk_en;
4352 bool rxiqk_en;
4353 bool lok_en;
4354 bool iqk_xym_en;
4355 bool iqk_sram_en;
4356 bool iqk_fft_en;
4357 bool is_fw_iqk;
4358 bool is_iqk_enable;
4359 bool iqk_cfir_en;
4360 bool thermal_rek_en;
4361 u8 iqk_band[2];
4362 u8 iqk_ch[2];
4363 u8 iqk_bw[2];
4364 u8 iqk_times;
4365 u8 version;
4366 u8 phy;
4367 u8 fwk_status;
4368 u8 rsvd;
4369 __le32 reload_cnt;
4370 __le32 iqk_fail_cnt;
4371 __le32 lok_idac[2];
4372 __le32 lok_vbuf[2];
4373 __le32 rftxgain[2][4];
4374 __le32 rfrxgain[2][4];
4375 __le32 tx_xym[2][4];
4376 __le32 rx_xym[2][4];
4377} __packed;
4378
4379struct rtw89_c2h_rf_dpk_rpt_log {
4380 u8 ver;
4381 u8 idx[2];
4382 u8 band[2];
4383 u8 bw[2];
4384 u8 ch[2];
4385 u8 path_ok[2];
4386 u8 txagc[2];
4387 u8 ther[2];
4388 u8 gs[2];
4389 u8 dc_i[4];
4390 u8 dc_q[4];
4391 u8 corr_val[2];
4392 u8 corr_idx[2];
4393 u8 is_timeout[2];
4394 u8 rxbb_ov[2];
4395 u8 rsvd;
4396} __packed;
4397
4398struct rtw89_c2h_rf_dack_rpt_log {
4399 u8 fwdack_ver;
4400 u8 fwdack_info_ver;
4401 u8 msbk_d[2][2][16];
4402 u8 dadck_d[2][2];
4403 u8 cdack_d[2][2][2];
4404 u8 addck2_hd[2][2][2];
4405 u8 addck2_ld[2][2][2];
4406 u8 adgaink_d[2][2];
4407 u8 biask_hd[2][2];
4408 u8 biask_ld[2][2];
4409 u8 addck_timeout;
4410 u8 cdack_timeout;
4411 u8 dadck_timeout;
4412 u8 msbk_timeout;
4413 u8 adgaink_timeout;
4414 u8 wbadcdck_timeout;
4415 u8 drck_timeout;
4416 u8 dack_fail;
4417 u8 wbdck_d[2];
4418 u8 rck_d;
4419} __packed;
4420
4421struct rtw89_c2h_rf_rxdck_rpt_log {
4422 u8 ver;
4423 u8 band[2];
4424 u8 bw[2];
4425 u8 ch[2];
4426 u8 timeout[2];
4427} __packed;
4428
4429struct rtw89_c2h_rf_tssi_rpt_log {
4430 s8 alignment_power[2][2][4];
4431 u8 alignment_power_cw_h[2][2][4];
4432 u8 alignment_power_cw_l[2][2][4];
4433 u8 tssi_alimk_state[2][2];
4434 u8 default_txagc_offset[2][2];
4435} __packed;
4436
4437struct rtw89_c2h_rf_txgapk_rpt_log {
4438 __le32 r0x8010[2];
4439 __le32 chk_cnt;
4440 u8 track_d[2][17];
4441 u8 power_d[2][17];
4442 u8 is_txgapk_ok;
4443 u8 chk_id;
4444 u8 ver;
4445 u8 rsv1;
4446} __packed;
4447
4448struct rtw89_c2h_rfk_report {
4449 struct rtw89_c2h_hdr hdr;
4450 u8 state; /* enum rtw89_rfk_report_state */
4451 u8 version;
4452} __packed;
4453
4454#define RTW89_FW_RSVD_PLE_SIZE 0x800
4455
4456#define RTW89_FW_BACKTRACE_INFO_SIZE 8
4457#define RTW89_VALID_FW_BACKTRACE_SIZE(_size) \
4458 ((_size) % RTW89_FW_BACKTRACE_INFO_SIZE == 0)
4459
4460#define RTW89_FW_BACKTRACE_MAX_SIZE 512 /* 8 * 64 (entries) */
4461#define RTW89_FW_BACKTRACE_KEY 0xBACEBACE
4462
4463#define FWDL_WAIT_CNT 400000
4464
4465int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type);
4466int rtw89_fw_recognize(struct rtw89_dev *rtwdev);
4467int rtw89_fw_recognize_elements(struct rtw89_dev *rtwdev);
4468const struct firmware *
4469rtw89_early_fw_feature_recognize(struct device *device,
4470 const struct rtw89_chip_info *chip,
4471 struct rtw89_fw_info *early_fw,
4472 int *used_fw_format);
4473int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type,
4474 bool include_bb);
4475void rtw89_load_firmware_work(struct work_struct *work);
4476void rtw89_unload_firmware(struct rtw89_dev *rtwdev);
4477int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev);
4478int rtw89_fw_log_prepare(struct rtw89_dev *rtwdev);
4479void rtw89_fw_log_dump(struct rtw89_dev *rtwdev, u8 *buf, u32 len);
4480void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb,
4481 u8 type, u8 cat, u8 class, u8 func,
4482 bool rack, bool dack, u32 len);
4483int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev,
4484 struct rtw89_vif_link *rtwvif_link,
4485 struct rtw89_sta_link *rtwsta_link);
4486int rtw89_fw_h2c_default_cmac_tbl_g7(struct rtw89_dev *rtwdev,
4487 struct rtw89_vif_link *rtwvif_link,
4488 struct rtw89_sta_link *rtwsta_link);
4489int rtw89_fw_h2c_default_dmac_tbl_v2(struct rtw89_dev *rtwdev,
4490 struct rtw89_vif_link *rtwvif_link,
4491 struct rtw89_sta_link *rtwsta_link);
4492int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev,
4493 struct rtw89_vif_link *rtwvif_link,
4494 struct rtw89_sta_link *rtwsta_link);
4495int rtw89_fw_h2c_assoc_cmac_tbl_g7(struct rtw89_dev *rtwdev,
4496 struct rtw89_vif_link *rtwvif_link,
4497 struct rtw89_sta_link *rtwsta_link);
4498int rtw89_fw_h2c_ampdu_cmac_tbl_g7(struct rtw89_dev *rtwdev,
4499 struct rtw89_vif_link *rtwvif_link,
4500 struct rtw89_sta_link *rtwsta_link);
4501int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev,
4502 struct rtw89_sta_link *rtwsta_link);
4503int rtw89_fw_h2c_txpath_cmac_tbl(struct rtw89_dev *rtwdev,
4504 struct rtw89_sta_link *rtwsta_link);
4505int rtw89_fw_h2c_update_beacon(struct rtw89_dev *rtwdev,
4506 struct rtw89_vif_link *rtwvif_link);
4507int rtw89_fw_h2c_update_beacon_be(struct rtw89_dev *rtwdev,
4508 struct rtw89_vif_link *rtwvif_link);
4509int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif_link *vif,
4510 struct rtw89_sta_link *rtwsta_link, const u8 *scan_mac_addr);
4511int rtw89_fw_h2c_dctl_sec_cam_v1(struct rtw89_dev *rtwdev,
4512 struct rtw89_vif_link *rtwvif_link,
4513 struct rtw89_sta_link *rtwsta_link);
4514int rtw89_fw_h2c_dctl_sec_cam_v2(struct rtw89_dev *rtwdev,
4515 struct rtw89_vif_link *rtwvif_link,
4516 struct rtw89_sta_link *rtwsta_link);
4517void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h);
4518void rtw89_fw_c2h_work(struct work_struct *work);
4519int rtw89_fw_h2c_role_maintain(struct rtw89_dev *rtwdev,
4520 struct rtw89_vif_link *rtwvif_link,
4521 struct rtw89_sta_link *rtwsta_link,
4522 enum rtw89_upd_mode upd_mode);
4523int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4524 struct rtw89_sta_link *rtwsta_link, bool dis_conn);
4525int rtw89_fw_h2c_notify_dbcc(struct rtw89_dev *rtwdev, bool en);
4526int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp,
4527 bool pause);
4528int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4529 u8 ac, u32 val);
4530int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev);
4531int rtw89_fw_h2c_tx_duty(struct rtw89_dev *rtwdev, u8 lv);
4532int rtw89_fw_h2c_set_bcn_fltr_cfg(struct rtw89_dev *rtwdev,
4533 struct rtw89_vif_link *rtwvif_link,
4534 bool connect);
4535int rtw89_fw_h2c_rssi_offload(struct rtw89_dev *rtwdev,
4536 struct rtw89_rx_phy_ppdu *phy_ppdu);
4537int rtw89_fw_h2c_tp_offload(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
4538int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi);
4539int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev, u8 type);
4540int rtw89_fw_h2c_cxdrv_init_v7(struct rtw89_dev *rtwdev, u8 type);
4541int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev, u8 type);
4542int rtw89_fw_h2c_cxdrv_role_v1(struct rtw89_dev *rtwdev, u8 type);
4543int rtw89_fw_h2c_cxdrv_role_v2(struct rtw89_dev *rtwdev, u8 type);
4544int rtw89_fw_h2c_cxdrv_role_v7(struct rtw89_dev *rtwdev, u8 type);
4545int rtw89_fw_h2c_cxdrv_role_v8(struct rtw89_dev *rtwdev, u8 type);
4546int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev, u8 type);
4547int rtw89_fw_h2c_cxdrv_ctrl_v7(struct rtw89_dev *rtwdev, u8 type);
4548int rtw89_fw_h2c_cxdrv_trx(struct rtw89_dev *rtwdev, u8 type);
4549int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev, u8 type);
4550int rtw89_fw_h2c_del_pkt_offload(struct rtw89_dev *rtwdev, u8 id);
4551int rtw89_fw_h2c_add_pkt_offload(struct rtw89_dev *rtwdev, u8 *id,
4552 struct sk_buff *skb_ofld);
4553int rtw89_fw_h2c_scan_offload_ax(struct rtw89_dev *rtwdev,
4554 struct rtw89_scan_option *opt,
4555 struct rtw89_vif_link *vif,
4556 bool wowlan);
4557int rtw89_fw_h2c_scan_offload_be(struct rtw89_dev *rtwdev,
4558 struct rtw89_scan_option *opt,
4559 struct rtw89_vif_link *vif,
4560 bool wowlan);
4561int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev,
4562 struct rtw89_fw_h2c_rf_reg_info *info,
4563 u16 len, u8 page);
4564int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw89_dev *rtwdev);
4565int rtw89_fw_h2c_rf_pre_ntfy(struct rtw89_dev *rtwdev,
4566 enum rtw89_phy_idx phy_idx);
4567int rtw89_fw_h2c_rf_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4568 const struct rtw89_chan *chan, enum rtw89_tssi_mode tssi_mode);
4569int rtw89_fw_h2c_rf_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4570 const struct rtw89_chan *chan);
4571int rtw89_fw_h2c_rf_dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4572 const struct rtw89_chan *chan);
4573int rtw89_fw_h2c_rf_txgapk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4574 const struct rtw89_chan *chan);
4575int rtw89_fw_h2c_rf_dack(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4576 const struct rtw89_chan *chan);
4577int rtw89_fw_h2c_rf_rxdck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4578 const struct rtw89_chan *chan, bool is_chl_k);
4579int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev,
4580 u8 h2c_class, u8 h2c_func, u8 *buf, u16 len,
4581 bool rack, bool dack);
4582int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len);
4583void rtw89_fw_send_all_early_h2c(struct rtw89_dev *rtwdev);
4584void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev);
4585int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4586 u8 macid);
4587void rtw89_fw_release_general_pkt_list_vif(struct rtw89_dev *rtwdev,
4588 struct rtw89_vif_link *rtwvif_link,
4589 bool notify_fw);
4590void rtw89_fw_release_general_pkt_list(struct rtw89_dev *rtwdev, bool notify_fw);
4591int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev,
4592 struct rtw89_vif_link *rtwvif_link,
4593 struct rtw89_sta_link *rtwsta_link,
4594 bool valid, struct ieee80211_ampdu_params *params);
4595int rtw89_fw_h2c_ba_cam_v1(struct rtw89_dev *rtwdev,
4596 struct rtw89_vif_link *rtwvif_link,
4597 struct rtw89_sta_link *rtwsta_link,
4598 bool valid, struct ieee80211_ampdu_params *params);
4599void rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(struct rtw89_dev *rtwdev);
4600int rtw89_fw_h2c_init_ba_cam_users(struct rtw89_dev *rtwdev, u8 users,
4601 u8 offset, u8 mac_idx);
4602
4603int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev,
4604 struct rtw89_lps_parm *lps_param);
4605int rtw89_fw_h2c_lps_ch_info(struct rtw89_dev *rtwdev,
4606 struct rtw89_vif_link *rtwvif_link);
4607int rtw89_fw_h2c_fwips(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4608 bool enable);
4609struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(struct rtw89_dev *rtwdev, u32 len);
4610struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(struct rtw89_dev *rtwdev, u32 len);
4611int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev,
4612 struct rtw89_mac_h2c_info *h2c_info,
4613 struct rtw89_mac_c2h_info *c2h_info);
4614int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable);
4615void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev);
4616void rtw89_hw_scan_start(struct rtw89_dev *rtwdev,
4617 struct rtw89_vif_link *rtwvif_link,
4618 struct ieee80211_scan_request *scan_req);
4619void rtw89_hw_scan_complete(struct rtw89_dev *rtwdev,
4620 struct rtw89_vif_link *rtwvif_link,
4621 bool aborted);
4622int rtw89_hw_scan_offload(struct rtw89_dev *rtwdev,
4623 struct rtw89_vif_link *rtwvif_link,
4624 bool enable);
4625void rtw89_hw_scan_abort(struct rtw89_dev *rtwdev,
4626 struct rtw89_vif_link *rtwvif_link);
4627int rtw89_hw_scan_add_chan_list_ax(struct rtw89_dev *rtwdev,
4628 struct rtw89_vif_link *rtwvif_link, bool connected);
4629int rtw89_pno_scan_add_chan_list_ax(struct rtw89_dev *rtwdev,
4630 struct rtw89_vif_link *rtwvif_link);
4631int rtw89_hw_scan_add_chan_list_be(struct rtw89_dev *rtwdev,
4632 struct rtw89_vif_link *rtwvif_link, bool connected);
4633int rtw89_pno_scan_add_chan_list_be(struct rtw89_dev *rtwdev,
4634 struct rtw89_vif_link *rtwvif_link);
4635int rtw89_fw_h2c_trigger_cpu_exception(struct rtw89_dev *rtwdev);
4636int rtw89_fw_h2c_pkt_drop(struct rtw89_dev *rtwdev,
4637 const struct rtw89_pkt_drop_params *params);
4638int rtw89_fw_h2c_p2p_act(struct rtw89_dev *rtwdev,
4639 struct rtw89_vif_link *rtwvif_link,
4640 struct ieee80211_bss_conf *bss_conf,
4641 struct ieee80211_p2p_noa_desc *desc,
4642 u8 act, u8 noa_id);
4643int rtw89_fw_h2c_tsf32_toggle(struct rtw89_dev *rtwdev,
4644 struct rtw89_vif_link *rtwvif_link,
4645 bool en);
4646int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4647 bool enable);
4648int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
4649 struct rtw89_vif_link *rtwvif_link, bool enable);
4650int rtw89_fw_h2c_cfg_pno(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4651 bool enable);
4652int rtw89_fw_h2c_keep_alive(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4653 bool enable);
4654int rtw89_fw_h2c_arp_offload(struct rtw89_dev *rtwdev,
4655 struct rtw89_vif_link *rtwvif_link, bool enable);
4656int rtw89_fw_h2c_disconnect_detect(struct rtw89_dev *rtwdev,
4657 struct rtw89_vif_link *rtwvif_link, bool enable);
4658int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4659 bool enable);
4660int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
4661 struct rtw89_vif_link *rtwvif_link, bool enable);
4662int rtw89_fw_wow_cam_update(struct rtw89_dev *rtwdev,
4663 struct rtw89_wow_cam_info *cam_info);
4664int rtw89_fw_h2c_wow_gtk_ofld(struct rtw89_dev *rtwdev,
4665 struct rtw89_vif_link *rtwvif_link,
4666 bool enable);
4667int rtw89_fw_h2c_wow_request_aoac(struct rtw89_dev *rtwdev);
4668int rtw89_fw_h2c_add_mcc(struct rtw89_dev *rtwdev,
4669 const struct rtw89_fw_mcc_add_req *p);
4670int rtw89_fw_h2c_start_mcc(struct rtw89_dev *rtwdev,
4671 const struct rtw89_fw_mcc_start_req *p);
4672int rtw89_fw_h2c_stop_mcc(struct rtw89_dev *rtwdev, u8 group, u8 macid,
4673 bool prev_groups);
4674int rtw89_fw_h2c_del_mcc_group(struct rtw89_dev *rtwdev, u8 group,
4675 bool prev_groups);
4676int rtw89_fw_h2c_reset_mcc_group(struct rtw89_dev *rtwdev, u8 group);
4677int rtw89_fw_h2c_mcc_req_tsf(struct rtw89_dev *rtwdev,
4678 const struct rtw89_fw_mcc_tsf_req *req,
4679 struct rtw89_mac_mcc_tsf_rpt *rpt);
4680int rtw89_fw_h2c_mcc_macid_bitmap(struct rtw89_dev *rtwdev, u8 group, u8 macid,
4681 u8 *bitmap);
4682int rtw89_fw_h2c_mcc_sync(struct rtw89_dev *rtwdev, u8 group, u8 source,
4683 u8 target, u8 offset);
4684int rtw89_fw_h2c_mcc_set_duration(struct rtw89_dev *rtwdev,
4685 const struct rtw89_fw_mcc_duration *p);
4686int rtw89_fw_h2c_mrc_add(struct rtw89_dev *rtwdev,
4687 const struct rtw89_fw_mrc_add_arg *arg);
4688int rtw89_fw_h2c_mrc_start(struct rtw89_dev *rtwdev,
4689 const struct rtw89_fw_mrc_start_arg *arg);
4690int rtw89_fw_h2c_mrc_del(struct rtw89_dev *rtwdev, u8 sch_idx, u8 slot_idx);
4691int rtw89_fw_h2c_mrc_req_tsf(struct rtw89_dev *rtwdev,
4692 const struct rtw89_fw_mrc_req_tsf_arg *arg,
4693 struct rtw89_mac_mrc_tsf_rpt *rpt);
4694int rtw89_fw_h2c_mrc_upd_bitmap(struct rtw89_dev *rtwdev,
4695 const struct rtw89_fw_mrc_upd_bitmap_arg *arg);
4696int rtw89_fw_h2c_mrc_sync(struct rtw89_dev *rtwdev,
4697 const struct rtw89_fw_mrc_sync_arg *arg);
4698int rtw89_fw_h2c_mrc_upd_duration(struct rtw89_dev *rtwdev,
4699 const struct rtw89_fw_mrc_upd_duration_arg *arg);
4700
4701static inline void rtw89_fw_h2c_init_ba_cam(struct rtw89_dev *rtwdev)
4702{
4703 const struct rtw89_chip_info *chip = rtwdev->chip;
4704
4705 if (chip->bacam_ver == RTW89_BACAM_V0_EXT)
4706 rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(rtwdev);
4707}
4708
4709static inline int rtw89_chip_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev,
4710 struct rtw89_vif_link *rtwvif_link,
4711 struct rtw89_sta_link *rtwsta_link)
4712{
4713 const struct rtw89_chip_info *chip = rtwdev->chip;
4714
4715 return chip->ops->h2c_default_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
4716}
4717
4718static inline int rtw89_chip_h2c_default_dmac_tbl(struct rtw89_dev *rtwdev,
4719 struct rtw89_vif_link *rtwvif_link,
4720 struct rtw89_sta_link *rtwsta_link)
4721{
4722 const struct rtw89_chip_info *chip = rtwdev->chip;
4723
4724 if (chip->ops->h2c_default_dmac_tbl)
4725 return chip->ops->h2c_default_dmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
4726
4727 return 0;
4728}
4729
4730static inline int rtw89_chip_h2c_update_beacon(struct rtw89_dev *rtwdev,
4731 struct rtw89_vif_link *rtwvif_link)
4732{
4733 const struct rtw89_chip_info *chip = rtwdev->chip;
4734
4735 return chip->ops->h2c_update_beacon(rtwdev, rtwvif_link);
4736}
4737
4738static inline int rtw89_chip_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev,
4739 struct rtw89_vif_link *rtwvif_link,
4740 struct rtw89_sta_link *rtwsta_link)
4741{
4742 const struct rtw89_chip_info *chip = rtwdev->chip;
4743
4744 return chip->ops->h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
4745}
4746
4747static inline
4748int rtw89_chip_h2c_ampdu_link_cmac_tbl(struct rtw89_dev *rtwdev,
4749 struct rtw89_vif_link *rtwvif_link,
4750 struct rtw89_sta_link *rtwsta_link)
4751{
4752 const struct rtw89_chip_info *chip = rtwdev->chip;
4753
4754 if (chip->ops->h2c_ampdu_cmac_tbl)
4755 return chip->ops->h2c_ampdu_cmac_tbl(rtwdev, rtwvif_link,
4756 rtwsta_link);
4757
4758 return 0;
4759}
4760
4761static inline int rtw89_chip_h2c_ampdu_cmac_tbl(struct rtw89_dev *rtwdev,
4762 struct rtw89_vif *rtwvif,
4763 struct rtw89_sta *rtwsta)
4764{
4765 struct rtw89_vif_link *rtwvif_link;
4766 struct rtw89_sta_link *rtwsta_link;
4767 unsigned int link_id;
4768 int ret;
4769
4770 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) {
4771 rtwvif_link = rtwsta_link->rtwvif_link;
4772 ret = rtw89_chip_h2c_ampdu_link_cmac_tbl(rtwdev, rtwvif_link,
4773 rtwsta_link);
4774 if (ret)
4775 return ret;
4776 }
4777
4778 return 0;
4779}
4780
4781static inline
4782int rtw89_chip_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
4783 bool valid, struct ieee80211_ampdu_params *params)
4784{
4785 const struct rtw89_chip_info *chip = rtwdev->chip;
4786 struct rtw89_vif_link *rtwvif_link;
4787 struct rtw89_sta_link *rtwsta_link;
4788 unsigned int link_id;
4789 int ret;
4790
4791 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) {
4792 rtwvif_link = rtwsta_link->rtwvif_link;
4793 ret = chip->ops->h2c_ba_cam(rtwdev, rtwvif_link, rtwsta_link,
4794 valid, params);
4795 if (ret)
4796 return ret;
4797 }
4798
4799 return 0;
4800}
4801
4802/* must consider compatibility; don't insert new in the mid */
4803struct rtw89_fw_txpwr_byrate_entry {
4804 u8 band;
4805 u8 nss;
4806 u8 rs;
4807 u8 shf;
4808 u8 len;
4809 __le32 data;
4810 u8 bw;
4811 u8 ofdma;
4812} __packed;
4813
4814/* must consider compatibility; don't insert new in the mid */
4815struct rtw89_fw_txpwr_lmt_2ghz_entry {
4816 u8 bw;
4817 u8 nt;
4818 u8 rs;
4819 u8 bf;
4820 u8 regd;
4821 u8 ch_idx;
4822 s8 v;
4823} __packed;
4824
4825/* must consider compatibility; don't insert new in the mid */
4826struct rtw89_fw_txpwr_lmt_5ghz_entry {
4827 u8 bw;
4828 u8 nt;
4829 u8 rs;
4830 u8 bf;
4831 u8 regd;
4832 u8 ch_idx;
4833 s8 v;
4834} __packed;
4835
4836/* must consider compatibility; don't insert new in the mid */
4837struct rtw89_fw_txpwr_lmt_6ghz_entry {
4838 u8 bw;
4839 u8 nt;
4840 u8 rs;
4841 u8 bf;
4842 u8 regd;
4843 u8 reg_6ghz_power;
4844 u8 ch_idx;
4845 s8 v;
4846} __packed;
4847
4848/* must consider compatibility; don't insert new in the mid */
4849struct rtw89_fw_txpwr_lmt_ru_2ghz_entry {
4850 u8 ru;
4851 u8 nt;
4852 u8 regd;
4853 u8 ch_idx;
4854 s8 v;
4855} __packed;
4856
4857/* must consider compatibility; don't insert new in the mid */
4858struct rtw89_fw_txpwr_lmt_ru_5ghz_entry {
4859 u8 ru;
4860 u8 nt;
4861 u8 regd;
4862 u8 ch_idx;
4863 s8 v;
4864} __packed;
4865
4866/* must consider compatibility; don't insert new in the mid */
4867struct rtw89_fw_txpwr_lmt_ru_6ghz_entry {
4868 u8 ru;
4869 u8 nt;
4870 u8 regd;
4871 u8 reg_6ghz_power;
4872 u8 ch_idx;
4873 s8 v;
4874} __packed;
4875
4876/* must consider compatibility; don't insert new in the mid */
4877struct rtw89_fw_tx_shape_lmt_entry {
4878 u8 band;
4879 u8 tx_shape_rs;
4880 u8 regd;
4881 u8 v;
4882} __packed;
4883
4884/* must consider compatibility; don't insert new in the mid */
4885struct rtw89_fw_tx_shape_lmt_ru_entry {
4886 u8 band;
4887 u8 regd;
4888 u8 v;
4889} __packed;
4890
4891const struct rtw89_rfe_parms *
4892rtw89_load_rfe_data_from_fw(struct rtw89_dev *rtwdev,
4893 const struct rtw89_rfe_parms *init);
4894
4895enum rtw89_wow_wakeup_ver {
4896 RTW89_WOW_REASON_V0,
4897 RTW89_WOW_REASON_V1,
4898 RTW89_WOW_REASON_NUM,
4899};
4900
4901#endif