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1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5#ifndef __RTW89_CORE_H__
6#define __RTW89_CORE_H__
7
8#include <linux/average.h>
9#include <linux/bitfield.h>
10#include <linux/dmi.h>
11#include <linux/firmware.h>
12#include <linux/iopoll.h>
13#include <linux/workqueue.h>
14#include <net/mac80211.h>
15
16struct rtw89_dev;
17struct rtw89_pci_info;
18struct rtw89_mac_gen_def;
19struct rtw89_phy_gen_def;
20struct rtw89_efuse_block_cfg;
21struct rtw89_h2c_rf_tssi;
22struct rtw89_fw_txpwr_track_cfg;
23struct rtw89_phy_rfk_log_fmt;
24struct rtw89_debugfs;
25
26extern const struct ieee80211_ops rtw89_ops;
27
28#define MASKBYTE0 0xff
29#define MASKBYTE1 0xff00
30#define MASKBYTE2 0xff0000
31#define MASKBYTE3 0xff000000
32#define MASKBYTE4 0xff00000000ULL
33#define MASKHWORD 0xffff0000
34#define MASKLWORD 0x0000ffff
35#define MASKDWORD 0xffffffff
36#define RFREG_MASK 0xfffff
37#define INV_RF_DATA 0xffffffff
38#define BYPASS_CR_DATA 0xbabecafe
39
40#define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2)
41#define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4)
42#define CFO_TRACK_MAX_USER 64
43#define MAX_RSSI 110
44#define RSSI_FACTOR 1
45#define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI)
46#define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR)
47#define DELTA_SWINGIDX_SIZE 30
48
49#define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he)
50#define RTW89_RADIOTAP_ROOM_EHT \
51 (sizeof(struct ieee80211_radiotap_tlv) + \
52 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \
53 sizeof(struct ieee80211_radiotap_tlv) + \
54 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4))
55#define RTW89_RADIOTAP_ROOM \
56 ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64)
57
58#define RTW89_HTC_MASK_VARIANT GENMASK(1, 0)
59#define RTW89_HTC_VARIANT_HE 3
60#define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2)
61#define RTW89_HTC_VARIANT_HE_CID_OM 1
62#define RTW89_HTC_VARIANT_HE_CID_CAS 6
63#define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6)
64
65#define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6)
66enum htc_om_channel_width {
67 HTC_OM_CHANNEL_WIDTH_20 = 0,
68 HTC_OM_CHANNEL_WIDTH_40 = 1,
69 HTC_OM_CHANNEL_WIDTH_80 = 2,
70 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3,
71};
72#define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9)
73#define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11)
74#define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12)
75#define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15)
76#define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16)
77#define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17)
78
79#define RTW89_TF_PAD GENMASK(11, 0)
80#define RTW89_TF_BASIC_USER_INFO_SZ 6
81
82#define RTW89_GET_TF_USER_INFO_AID12(data) \
83 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0))
84#define RTW89_GET_TF_USER_INFO_RUA(data) \
85 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12))
86#define RTW89_GET_TF_USER_INFO_UL_MCS(data) \
87 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21))
88
89enum rtw89_subband {
90 RTW89_CH_2G = 0,
91 RTW89_CH_5G_BAND_1 = 1,
92 /* RTW89_CH_5G_BAND_2 = 2, unused */
93 RTW89_CH_5G_BAND_3 = 3,
94 RTW89_CH_5G_BAND_4 = 4,
95
96 RTW89_CH_6G_BAND_IDX0, /* Low */
97 RTW89_CH_6G_BAND_IDX1, /* Low */
98 RTW89_CH_6G_BAND_IDX2, /* Mid */
99 RTW89_CH_6G_BAND_IDX3, /* Mid */
100 RTW89_CH_6G_BAND_IDX4, /* High */
101 RTW89_CH_6G_BAND_IDX5, /* High */
102 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */
103 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */
104
105 RTW89_SUBBAND_NR,
106 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1,
107};
108
109enum rtw89_gain_offset {
110 RTW89_GAIN_OFFSET_2G_CCK,
111 RTW89_GAIN_OFFSET_2G_OFDM,
112 RTW89_GAIN_OFFSET_5G_LOW,
113 RTW89_GAIN_OFFSET_5G_MID,
114 RTW89_GAIN_OFFSET_5G_HIGH,
115 RTW89_GAIN_OFFSET_6G_L0,
116 RTW89_GAIN_OFFSET_6G_L1,
117 RTW89_GAIN_OFFSET_6G_M0,
118 RTW89_GAIN_OFFSET_6G_M1,
119 RTW89_GAIN_OFFSET_6G_H0,
120 RTW89_GAIN_OFFSET_6G_H1,
121 RTW89_GAIN_OFFSET_6G_UH0,
122 RTW89_GAIN_OFFSET_6G_UH1,
123
124 RTW89_GAIN_OFFSET_NR,
125};
126
127enum rtw89_hci_type {
128 RTW89_HCI_TYPE_PCIE,
129 RTW89_HCI_TYPE_USB,
130 RTW89_HCI_TYPE_SDIO,
131};
132
133enum rtw89_core_chip_id {
134 RTL8852A,
135 RTL8852B,
136 RTL8852BT,
137 RTL8852C,
138 RTL8851B,
139 RTL8922A,
140};
141
142enum rtw89_chip_gen {
143 RTW89_CHIP_AX,
144 RTW89_CHIP_BE,
145
146 RTW89_CHIP_GEN_NUM,
147};
148
149enum rtw89_cv {
150 CHIP_CAV,
151 CHIP_CBV,
152 CHIP_CCV,
153 CHIP_CDV,
154 CHIP_CEV,
155 CHIP_CFV,
156 CHIP_CV_MAX,
157 CHIP_CV_INVALID = CHIP_CV_MAX,
158};
159
160enum rtw89_bacam_ver {
161 RTW89_BACAM_V0,
162 RTW89_BACAM_V1,
163
164 RTW89_BACAM_V0_EXT = 99,
165};
166
167enum rtw89_core_tx_type {
168 RTW89_CORE_TX_TYPE_DATA,
169 RTW89_CORE_TX_TYPE_MGMT,
170 RTW89_CORE_TX_TYPE_FWCMD,
171};
172
173enum rtw89_core_rx_type {
174 RTW89_CORE_RX_TYPE_WIFI = 0,
175 RTW89_CORE_RX_TYPE_PPDU_STAT = 1,
176 RTW89_CORE_RX_TYPE_CHAN_INFO = 2,
177 RTW89_CORE_RX_TYPE_BB_SCOPE = 3,
178 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4,
179 RTW89_CORE_RX_TYPE_SS2FW = 5,
180 RTW89_CORE_RX_TYPE_TX_REPORT = 6,
181 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7,
182 RTW89_CORE_RX_TYPE_DFS_REPORT = 8,
183 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9,
184 RTW89_CORE_RX_TYPE_C2H = 10,
185 RTW89_CORE_RX_TYPE_CSI = 11,
186 RTW89_CORE_RX_TYPE_CQI = 12,
187 RTW89_CORE_RX_TYPE_H2C = 13,
188 RTW89_CORE_RX_TYPE_FWDL = 14,
189};
190
191enum rtw89_txq_flags {
192 RTW89_TXQ_F_AMPDU = 0,
193 RTW89_TXQ_F_BLOCK_BA = 1,
194 RTW89_TXQ_F_FORBID_BA = 2,
195};
196
197enum rtw89_net_type {
198 RTW89_NET_TYPE_NO_LINK = 0,
199 RTW89_NET_TYPE_AD_HOC = 1,
200 RTW89_NET_TYPE_INFRA = 2,
201 RTW89_NET_TYPE_AP_MODE = 3,
202};
203
204enum rtw89_wifi_role {
205 RTW89_WIFI_ROLE_NONE,
206 RTW89_WIFI_ROLE_STATION,
207 RTW89_WIFI_ROLE_AP,
208 RTW89_WIFI_ROLE_AP_VLAN,
209 RTW89_WIFI_ROLE_ADHOC,
210 RTW89_WIFI_ROLE_ADHOC_MASTER,
211 RTW89_WIFI_ROLE_MESH_POINT,
212 RTW89_WIFI_ROLE_MONITOR,
213 RTW89_WIFI_ROLE_P2P_DEVICE,
214 RTW89_WIFI_ROLE_P2P_CLIENT,
215 RTW89_WIFI_ROLE_P2P_GO,
216 RTW89_WIFI_ROLE_NAN,
217 RTW89_WIFI_ROLE_MLME_MAX
218};
219
220enum rtw89_upd_mode {
221 RTW89_ROLE_CREATE,
222 RTW89_ROLE_REMOVE,
223 RTW89_ROLE_TYPE_CHANGE,
224 RTW89_ROLE_INFO_CHANGE,
225 RTW89_ROLE_CON_DISCONN,
226 RTW89_ROLE_BAND_SW,
227 RTW89_ROLE_FW_RESTORE,
228};
229
230enum rtw89_self_role {
231 RTW89_SELF_ROLE_CLIENT,
232 RTW89_SELF_ROLE_AP,
233 RTW89_SELF_ROLE_AP_CLIENT
234};
235
236enum rtw89_msk_sO_el {
237 RTW89_NO_MSK,
238 RTW89_SMA,
239 RTW89_TMA,
240 RTW89_BSSID
241};
242
243enum rtw89_sch_tx_sel {
244 RTW89_SCH_TX_SEL_ALL,
245 RTW89_SCH_TX_SEL_HIQ,
246 RTW89_SCH_TX_SEL_MG0,
247 RTW89_SCH_TX_SEL_MACID,
248};
249
250/* RTW89_ADDR_CAM_SEC_NONE : not enabled
251 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast
252 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP
253 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP
254 */
255enum rtw89_add_cam_sec_mode {
256 RTW89_ADDR_CAM_SEC_NONE = 0,
257 RTW89_ADDR_CAM_SEC_ALL_UNI = 1,
258 RTW89_ADDR_CAM_SEC_NORMAL = 2,
259 RTW89_ADDR_CAM_SEC_4GROUP = 3,
260};
261
262enum rtw89_sec_key_type {
263 RTW89_SEC_KEY_TYPE_NONE = 0,
264 RTW89_SEC_KEY_TYPE_WEP40 = 1,
265 RTW89_SEC_KEY_TYPE_WEP104 = 2,
266 RTW89_SEC_KEY_TYPE_TKIP = 3,
267 RTW89_SEC_KEY_TYPE_WAPI = 4,
268 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5,
269 RTW89_SEC_KEY_TYPE_CCMP128 = 6,
270 RTW89_SEC_KEY_TYPE_CCMP256 = 7,
271 RTW89_SEC_KEY_TYPE_GCMP128 = 8,
272 RTW89_SEC_KEY_TYPE_GCMP256 = 9,
273 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10,
274};
275
276enum rtw89_port {
277 RTW89_PORT_0 = 0,
278 RTW89_PORT_1 = 1,
279 RTW89_PORT_2 = 2,
280 RTW89_PORT_3 = 3,
281 RTW89_PORT_4 = 4,
282 RTW89_PORT_NUM
283};
284
285enum rtw89_band {
286 RTW89_BAND_2G = 0,
287 RTW89_BAND_5G = 1,
288 RTW89_BAND_6G = 2,
289 RTW89_BAND_NUM,
290};
291
292enum rtw89_hw_rate {
293 RTW89_HW_RATE_CCK1 = 0x0,
294 RTW89_HW_RATE_CCK2 = 0x1,
295 RTW89_HW_RATE_CCK5_5 = 0x2,
296 RTW89_HW_RATE_CCK11 = 0x3,
297 RTW89_HW_RATE_OFDM6 = 0x4,
298 RTW89_HW_RATE_OFDM9 = 0x5,
299 RTW89_HW_RATE_OFDM12 = 0x6,
300 RTW89_HW_RATE_OFDM18 = 0x7,
301 RTW89_HW_RATE_OFDM24 = 0x8,
302 RTW89_HW_RATE_OFDM36 = 0x9,
303 RTW89_HW_RATE_OFDM48 = 0xA,
304 RTW89_HW_RATE_OFDM54 = 0xB,
305 RTW89_HW_RATE_MCS0 = 0x80,
306 RTW89_HW_RATE_MCS1 = 0x81,
307 RTW89_HW_RATE_MCS2 = 0x82,
308 RTW89_HW_RATE_MCS3 = 0x83,
309 RTW89_HW_RATE_MCS4 = 0x84,
310 RTW89_HW_RATE_MCS5 = 0x85,
311 RTW89_HW_RATE_MCS6 = 0x86,
312 RTW89_HW_RATE_MCS7 = 0x87,
313 RTW89_HW_RATE_MCS8 = 0x88,
314 RTW89_HW_RATE_MCS9 = 0x89,
315 RTW89_HW_RATE_MCS10 = 0x8A,
316 RTW89_HW_RATE_MCS11 = 0x8B,
317 RTW89_HW_RATE_MCS12 = 0x8C,
318 RTW89_HW_RATE_MCS13 = 0x8D,
319 RTW89_HW_RATE_MCS14 = 0x8E,
320 RTW89_HW_RATE_MCS15 = 0x8F,
321 RTW89_HW_RATE_MCS16 = 0x90,
322 RTW89_HW_RATE_MCS17 = 0x91,
323 RTW89_HW_RATE_MCS18 = 0x92,
324 RTW89_HW_RATE_MCS19 = 0x93,
325 RTW89_HW_RATE_MCS20 = 0x94,
326 RTW89_HW_RATE_MCS21 = 0x95,
327 RTW89_HW_RATE_MCS22 = 0x96,
328 RTW89_HW_RATE_MCS23 = 0x97,
329 RTW89_HW_RATE_MCS24 = 0x98,
330 RTW89_HW_RATE_MCS25 = 0x99,
331 RTW89_HW_RATE_MCS26 = 0x9A,
332 RTW89_HW_RATE_MCS27 = 0x9B,
333 RTW89_HW_RATE_MCS28 = 0x9C,
334 RTW89_HW_RATE_MCS29 = 0x9D,
335 RTW89_HW_RATE_MCS30 = 0x9E,
336 RTW89_HW_RATE_MCS31 = 0x9F,
337 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100,
338 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101,
339 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102,
340 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103,
341 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104,
342 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105,
343 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106,
344 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107,
345 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108,
346 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109,
347 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110,
348 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111,
349 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112,
350 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113,
351 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114,
352 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115,
353 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116,
354 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117,
355 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118,
356 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119,
357 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120,
358 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121,
359 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122,
360 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123,
361 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124,
362 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125,
363 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126,
364 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127,
365 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128,
366 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129,
367 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130,
368 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131,
369 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132,
370 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133,
371 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134,
372 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135,
373 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136,
374 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137,
375 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138,
376 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139,
377 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180,
378 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181,
379 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182,
380 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183,
381 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184,
382 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185,
383 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186,
384 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187,
385 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188,
386 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189,
387 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A,
388 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B,
389 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190,
390 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191,
391 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192,
392 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193,
393 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194,
394 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195,
395 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196,
396 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197,
397 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198,
398 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199,
399 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A,
400 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B,
401 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0,
402 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1,
403 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2,
404 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3,
405 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4,
406 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5,
407 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6,
408 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7,
409 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8,
410 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9,
411 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA,
412 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB,
413 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0,
414 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1,
415 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2,
416 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3,
417 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4,
418 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5,
419 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6,
420 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7,
421 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8,
422 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9,
423 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA,
424 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB,
425
426 RTW89_HW_RATE_V1_MCS0 = 0x100,
427 RTW89_HW_RATE_V1_MCS1 = 0x101,
428 RTW89_HW_RATE_V1_MCS2 = 0x102,
429 RTW89_HW_RATE_V1_MCS3 = 0x103,
430 RTW89_HW_RATE_V1_MCS4 = 0x104,
431 RTW89_HW_RATE_V1_MCS5 = 0x105,
432 RTW89_HW_RATE_V1_MCS6 = 0x106,
433 RTW89_HW_RATE_V1_MCS7 = 0x107,
434 RTW89_HW_RATE_V1_MCS8 = 0x108,
435 RTW89_HW_RATE_V1_MCS9 = 0x109,
436 RTW89_HW_RATE_V1_MCS10 = 0x10A,
437 RTW89_HW_RATE_V1_MCS11 = 0x10B,
438 RTW89_HW_RATE_V1_MCS12 = 0x10C,
439 RTW89_HW_RATE_V1_MCS13 = 0x10D,
440 RTW89_HW_RATE_V1_MCS14 = 0x10E,
441 RTW89_HW_RATE_V1_MCS15 = 0x10F,
442 RTW89_HW_RATE_V1_MCS16 = 0x110,
443 RTW89_HW_RATE_V1_MCS17 = 0x111,
444 RTW89_HW_RATE_V1_MCS18 = 0x112,
445 RTW89_HW_RATE_V1_MCS19 = 0x113,
446 RTW89_HW_RATE_V1_MCS20 = 0x114,
447 RTW89_HW_RATE_V1_MCS21 = 0x115,
448 RTW89_HW_RATE_V1_MCS22 = 0x116,
449 RTW89_HW_RATE_V1_MCS23 = 0x117,
450 RTW89_HW_RATE_V1_MCS24 = 0x118,
451 RTW89_HW_RATE_V1_MCS25 = 0x119,
452 RTW89_HW_RATE_V1_MCS26 = 0x11A,
453 RTW89_HW_RATE_V1_MCS27 = 0x11B,
454 RTW89_HW_RATE_V1_MCS28 = 0x11C,
455 RTW89_HW_RATE_V1_MCS29 = 0x11D,
456 RTW89_HW_RATE_V1_MCS30 = 0x11E,
457 RTW89_HW_RATE_V1_MCS31 = 0x11F,
458 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200,
459 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201,
460 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202,
461 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203,
462 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204,
463 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205,
464 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206,
465 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207,
466 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208,
467 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209,
468 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A,
469 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B,
470 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220,
471 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221,
472 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222,
473 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223,
474 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224,
475 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225,
476 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226,
477 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227,
478 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228,
479 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229,
480 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A,
481 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B,
482 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240,
483 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241,
484 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242,
485 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243,
486 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244,
487 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245,
488 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246,
489 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247,
490 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248,
491 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249,
492 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A,
493 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B,
494 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260,
495 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261,
496 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262,
497 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263,
498 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264,
499 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265,
500 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266,
501 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267,
502 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268,
503 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269,
504 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A,
505 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B,
506 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300,
507 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301,
508 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302,
509 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303,
510 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304,
511 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305,
512 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306,
513 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307,
514 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308,
515 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309,
516 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A,
517 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B,
518 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320,
519 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321,
520 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322,
521 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323,
522 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324,
523 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325,
524 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326,
525 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327,
526 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328,
527 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329,
528 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A,
529 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B,
530 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340,
531 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341,
532 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342,
533 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343,
534 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344,
535 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345,
536 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346,
537 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347,
538 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348,
539 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349,
540 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A,
541 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B,
542 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360,
543 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361,
544 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362,
545 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363,
546 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364,
547 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365,
548 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366,
549 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367,
550 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368,
551 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369,
552 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A,
553 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B,
554 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400,
555 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401,
556 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402,
557 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403,
558 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404,
559 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405,
560 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406,
561 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407,
562 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408,
563 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409,
564 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A,
565 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B,
566 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C,
567 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D,
568 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E,
569 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F,
570 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420,
571 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421,
572 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422,
573 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423,
574 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424,
575 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425,
576 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426,
577 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427,
578 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428,
579 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429,
580 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A,
581 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B,
582 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C,
583 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D,
584 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440,
585 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441,
586 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442,
587 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443,
588 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444,
589 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445,
590 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446,
591 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447,
592 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448,
593 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449,
594 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A,
595 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B,
596 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C,
597 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D,
598 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460,
599 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461,
600 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462,
601 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463,
602 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464,
603 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465,
604 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466,
605 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467,
606 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468,
607 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469,
608 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A,
609 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B,
610 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C,
611 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D,
612
613 RTW89_HW_RATE_NR,
614 RTW89_HW_RATE_INVAL,
615
616 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7),
617 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0),
618 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8),
619 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0),
620};
621
622/* 2G channels,
623 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
624 */
625#define RTW89_2G_CH_NUM 14
626
627/* 5G channels,
628 * 36, 38, 40, 42, 44, 46, 48, 50,
629 * 52, 54, 56, 58, 60, 62, 64,
630 * 100, 102, 104, 106, 108, 110, 112, 114,
631 * 116, 118, 120, 122, 124, 126, 128, 130,
632 * 132, 134, 136, 138, 140, 142, 144,
633 * 149, 151, 153, 155, 157, 159, 161, 163,
634 * 165, 167, 169, 171, 173, 175, 177
635 */
636#define RTW89_5G_CH_NUM 53
637
638/* 6G channels,
639 * 1, 3, 5, 7, 9, 11, 13, 15,
640 * 17, 19, 21, 23, 25, 27, 29, 33,
641 * 35, 37, 39, 41, 43, 45, 47, 49,
642 * 51, 53, 55, 57, 59, 61, 65, 67,
643 * 69, 71, 73, 75, 77, 79, 81, 83,
644 * 85, 87, 89, 91, 93, 97, 99, 101,
645 * 103, 105, 107, 109, 111, 113, 115, 117,
646 * 119, 121, 123, 125, 129, 131, 133, 135,
647 * 137, 139, 141, 143, 145, 147, 149, 151,
648 * 153, 155, 157, 161, 163, 165, 167, 169,
649 * 171, 173, 175, 177, 179, 181, 183, 185,
650 * 187, 189, 193, 195, 197, 199, 201, 203,
651 * 205, 207, 209, 211, 213, 215, 217, 219,
652 * 221, 225, 227, 229, 231, 233, 235, 237,
653 * 239, 241, 243, 245, 247, 249, 251, 253,
654 */
655#define RTW89_6G_CH_NUM 120
656
657enum rtw89_rate_section {
658 RTW89_RS_CCK,
659 RTW89_RS_OFDM,
660 RTW89_RS_MCS, /* for HT/VHT/HE */
661 RTW89_RS_HEDCM,
662 RTW89_RS_OFFSET,
663 RTW89_RS_NUM,
664 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1,
665 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1,
666};
667
668enum rtw89_rate_offset_indexes {
669 RTW89_RATE_OFFSET_HE,
670 RTW89_RATE_OFFSET_VHT,
671 RTW89_RATE_OFFSET_HT,
672 RTW89_RATE_OFFSET_OFDM,
673 RTW89_RATE_OFFSET_CCK,
674 RTW89_RATE_OFFSET_DLRU_EHT,
675 RTW89_RATE_OFFSET_DLRU_HE,
676 RTW89_RATE_OFFSET_EHT,
677 __RTW89_RATE_OFFSET_NUM,
678
679 RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1,
680 RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1,
681};
682
683enum rtw89_rate_num {
684 RTW89_RATE_CCK_NUM = 4,
685 RTW89_RATE_OFDM_NUM = 8,
686 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */
687
688 RTW89_RATE_MCS_NUM_AX = 12,
689 RTW89_RATE_MCS_NUM_BE = 16,
690 __RTW89_RATE_MCS_NUM = 16,
691};
692
693enum rtw89_nss {
694 RTW89_NSS_1 = 0,
695 RTW89_NSS_2 = 1,
696 /* HE DCM only support 1ss and 2ss */
697 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1,
698 RTW89_NSS_3 = 2,
699 RTW89_NSS_4 = 3,
700 RTW89_NSS_NUM,
701};
702
703enum rtw89_ntx {
704 RTW89_1TX = 0,
705 RTW89_2TX = 1,
706 RTW89_NTX_NUM,
707};
708
709enum rtw89_beamforming_type {
710 RTW89_NONBF = 0,
711 RTW89_BF = 1,
712 RTW89_BF_NUM,
713};
714
715enum rtw89_ofdma_type {
716 RTW89_NON_OFDMA = 0,
717 RTW89_OFDMA = 1,
718 RTW89_OFDMA_NUM,
719};
720
721enum rtw89_regulation_type {
722 RTW89_WW = 0,
723 RTW89_ETSI = 1,
724 RTW89_FCC = 2,
725 RTW89_MKK = 3,
726 RTW89_NA = 4,
727 RTW89_IC = 5,
728 RTW89_KCC = 6,
729 RTW89_ACMA = 7,
730 RTW89_NCC = 8,
731 RTW89_MEXICO = 9,
732 RTW89_CHILE = 10,
733 RTW89_UKRAINE = 11,
734 RTW89_CN = 12,
735 RTW89_QATAR = 13,
736 RTW89_UK = 14,
737 RTW89_THAILAND = 15,
738 RTW89_REGD_NUM,
739};
740
741enum rtw89_reg_6ghz_power {
742 RTW89_REG_6GHZ_POWER_VLP = 0,
743 RTW89_REG_6GHZ_POWER_LPI = 1,
744 RTW89_REG_6GHZ_POWER_STD = 2,
745
746 NUM_OF_RTW89_REG_6GHZ_POWER,
747 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP,
748};
749
750#define RTW89_MIN_VALID_POWER_CONSTRAINT (-10) /* unit: dBm */
751
752/* calculate based on ieee80211 Transmit Power Envelope */
753struct rtw89_reg_6ghz_tpe {
754 bool valid;
755 s8 constraint; /* unit: dBm */
756};
757
758enum rtw89_fw_pkt_ofld_type {
759 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0,
760 RTW89_PKT_OFLD_TYPE_PS_POLL = 1,
761 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2,
762 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3,
763 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4,
764 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5,
765 RTW89_PKT_OFLD_TYPE_NDP = 6,
766 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7,
767 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8,
768 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12,
769 RTW89_PKT_OFLD_TYPE_NUM,
770};
771
772struct rtw89_txpwr_byrate {
773 s8 cck[RTW89_RATE_CCK_NUM];
774 s8 ofdm[RTW89_RATE_OFDM_NUM];
775 s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM];
776 s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM];
777 s8 offset[__RTW89_RATE_OFFSET_NUM];
778 s8 trap;
779};
780
781struct rtw89_rate_desc {
782 enum rtw89_nss nss;
783 enum rtw89_rate_section rs;
784 enum rtw89_ofdma_type ofdma;
785 u8 idx;
786};
787
788#define PHY_STS_HDR_LEN 8
789#define RF_PATH_MAX 4
790#define RTW89_MAX_PPDU_CNT 8
791struct rtw89_rx_phy_ppdu {
792 void *buf;
793 u32 len;
794 u8 rssi_avg;
795 u8 rssi[RF_PATH_MAX];
796 u8 mac_id;
797 u8 chan_idx;
798 u8 ie;
799 u16 rate;
800 u8 rpl_avg;
801 u8 rpl_path[RF_PATH_MAX];
802 u8 rpl_fd[RF_PATH_MAX];
803 u8 bw_idx;
804 u8 rx_path_en;
805 struct {
806 bool has;
807 u8 avg_snr;
808 u8 evm_max;
809 u8 evm_min;
810 } ofdm;
811 bool has_data;
812 bool has_bcn;
813 bool ldpc;
814 bool stbc;
815 bool to_self;
816 bool valid;
817 bool hdr_2_en;
818};
819
820enum rtw89_mac_idx {
821 RTW89_MAC_0 = 0,
822 RTW89_MAC_1 = 1,
823 RTW89_MAC_NUM,
824};
825
826enum rtw89_phy_idx {
827 RTW89_PHY_0 = 0,
828 RTW89_PHY_1 = 1,
829 RTW89_PHY_MAX
830};
831
832#define __RTW89_MLD_MAX_LINK_NUM 2
833
834enum rtw89_chanctx_idx {
835 RTW89_CHANCTX_0 = 0,
836 RTW89_CHANCTX_1 = 1,
837
838 NUM_OF_RTW89_CHANCTX,
839 RTW89_CHANCTX_IDLE = NUM_OF_RTW89_CHANCTX,
840};
841
842enum rtw89_rf_path {
843 RF_PATH_A = 0,
844 RF_PATH_B = 1,
845 RF_PATH_C = 2,
846 RF_PATH_D = 3,
847 RF_PATH_AB,
848 RF_PATH_AC,
849 RF_PATH_AD,
850 RF_PATH_BC,
851 RF_PATH_BD,
852 RF_PATH_CD,
853 RF_PATH_ABC,
854 RF_PATH_ABD,
855 RF_PATH_ACD,
856 RF_PATH_BCD,
857 RF_PATH_ABCD,
858};
859
860enum rtw89_rf_path_bit {
861 RF_A = BIT(0),
862 RF_B = BIT(1),
863 RF_C = BIT(2),
864 RF_D = BIT(3),
865
866 RF_AB = (RF_A | RF_B),
867 RF_AC = (RF_A | RF_C),
868 RF_AD = (RF_A | RF_D),
869 RF_BC = (RF_B | RF_C),
870 RF_BD = (RF_B | RF_D),
871 RF_CD = (RF_C | RF_D),
872
873 RF_ABC = (RF_A | RF_B | RF_C),
874 RF_ABD = (RF_A | RF_B | RF_D),
875 RF_ACD = (RF_A | RF_C | RF_D),
876 RF_BCD = (RF_B | RF_C | RF_D),
877
878 RF_ABCD = (RF_A | RF_B | RF_C | RF_D),
879};
880
881enum rtw89_bandwidth {
882 RTW89_CHANNEL_WIDTH_20 = 0,
883 RTW89_CHANNEL_WIDTH_40 = 1,
884 RTW89_CHANNEL_WIDTH_80 = 2,
885 RTW89_CHANNEL_WIDTH_160 = 3,
886 RTW89_CHANNEL_WIDTH_320 = 4,
887
888 /* keep index order above */
889 RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5,
890
891 RTW89_CHANNEL_WIDTH_80_80 = 5,
892 RTW89_CHANNEL_WIDTH_5 = 6,
893 RTW89_CHANNEL_WIDTH_10 = 7,
894};
895
896enum rtw89_ps_mode {
897 RTW89_PS_MODE_NONE = 0,
898 RTW89_PS_MODE_RFOFF = 1,
899 RTW89_PS_MODE_CLK_GATED = 2,
900 RTW89_PS_MODE_PWR_GATED = 3,
901};
902
903#define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1)
904#define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1)
905#define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1)
906#define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1)
907#define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1)
908
909enum rtw89_pe_duration {
910 RTW89_PE_DURATION_0 = 0,
911 RTW89_PE_DURATION_8 = 1,
912 RTW89_PE_DURATION_16 = 2,
913 RTW89_PE_DURATION_16_20 = 3,
914};
915
916enum rtw89_ru_bandwidth {
917 RTW89_RU26 = 0,
918 RTW89_RU52 = 1,
919 RTW89_RU106 = 2,
920 RTW89_RU52_26 = 3,
921 RTW89_RU106_26 = 4,
922 RTW89_RU_NUM,
923};
924
925enum rtw89_sc_offset {
926 RTW89_SC_DONT_CARE = 0,
927 RTW89_SC_20_UPPER = 1,
928 RTW89_SC_20_LOWER = 2,
929 RTW89_SC_20_UPMOST = 3,
930 RTW89_SC_20_LOWEST = 4,
931 RTW89_SC_20_UP2X = 5,
932 RTW89_SC_20_LOW2X = 6,
933 RTW89_SC_20_UP3X = 7,
934 RTW89_SC_20_LOW3X = 8,
935 RTW89_SC_40_UPPER = 9,
936 RTW89_SC_40_LOWER = 10,
937};
938
939/* only mgd features can be added to the enum */
940enum rtw89_wow_flags {
941 RTW89_WOW_FLAG_EN_MAGIC_PKT,
942 RTW89_WOW_FLAG_EN_REKEY_PKT,
943 RTW89_WOW_FLAG_EN_DISCONNECT,
944 RTW89_WOW_FLAG_EN_PATTERN,
945 RTW89_WOW_FLAG_NUM,
946};
947
948struct rtw89_chan {
949 u8 channel;
950 u8 primary_channel;
951 enum rtw89_band band_type;
952 enum rtw89_bandwidth band_width;
953
954 /* The follow-up are derived from the above. We must ensure that it
955 * is assigned correctly in rtw89_chan_create() if new one is added.
956 */
957 u32 freq;
958 enum rtw89_subband subband_type;
959 enum rtw89_sc_offset pri_ch_idx;
960 u8 pri_sb_idx;
961};
962
963struct rtw89_chan_rcd {
964 u8 prev_primary_channel;
965 enum rtw89_band prev_band_type;
966 bool band_changed;
967};
968
969struct rtw89_channel_help_params {
970 u32 tx_en;
971};
972
973struct rtw89_port_reg {
974 u32 port_cfg;
975 u32 tbtt_prohib;
976 u32 bcn_area;
977 u32 bcn_early;
978 u32 tbtt_early;
979 u32 tbtt_agg;
980 u32 bcn_space;
981 u32 bcn_forcetx;
982 u32 bcn_err_cnt;
983 u32 bcn_err_flag;
984 u32 dtim_ctrl;
985 u32 tbtt_shift;
986 u32 bcn_cnt_tmr;
987 u32 tsftr_l;
988 u32 tsftr_h;
989 u32 md_tsft;
990 u32 bss_color;
991 u32 mbssid;
992 u32 mbssid_drop;
993 u32 tsf_sync;
994 u32 ptcl_dbg;
995 u32 ptcl_dbg_info;
996 u32 bcn_drop_all;
997 u32 hiq_win[RTW89_PORT_NUM];
998};
999
1000struct rtw89_txwd_body {
1001 __le32 dword0;
1002 __le32 dword1;
1003 __le32 dword2;
1004 __le32 dword3;
1005 __le32 dword4;
1006 __le32 dword5;
1007} __packed;
1008
1009struct rtw89_txwd_body_v1 {
1010 __le32 dword0;
1011 __le32 dword1;
1012 __le32 dword2;
1013 __le32 dword3;
1014 __le32 dword4;
1015 __le32 dword5;
1016 __le32 dword6;
1017 __le32 dword7;
1018} __packed;
1019
1020struct rtw89_txwd_body_v2 {
1021 __le32 dword0;
1022 __le32 dword1;
1023 __le32 dword2;
1024 __le32 dword3;
1025 __le32 dword4;
1026 __le32 dword5;
1027 __le32 dword6;
1028 __le32 dword7;
1029} __packed;
1030
1031struct rtw89_txwd_info {
1032 __le32 dword0;
1033 __le32 dword1;
1034 __le32 dword2;
1035 __le32 dword3;
1036 __le32 dword4;
1037 __le32 dword5;
1038} __packed;
1039
1040struct rtw89_txwd_info_v2 {
1041 __le32 dword0;
1042 __le32 dword1;
1043 __le32 dword2;
1044 __le32 dword3;
1045 __le32 dword4;
1046 __le32 dword5;
1047 __le32 dword6;
1048 __le32 dword7;
1049} __packed;
1050
1051struct rtw89_rx_desc_info {
1052 u16 pkt_size;
1053 u8 pkt_type;
1054 u8 drv_info_size;
1055 u8 phy_rpt_size;
1056 u8 hdr_cnv_size;
1057 u8 shift;
1058 u8 wl_hd_iv_len;
1059 bool long_rxdesc;
1060 bool bb_sel;
1061 bool mac_info_valid;
1062 u16 data_rate;
1063 u8 gi_ltf;
1064 u8 bw;
1065 u32 free_run_cnt;
1066 u8 user_id;
1067 bool sr_en;
1068 u8 ppdu_cnt;
1069 u8 ppdu_type;
1070 bool icv_err;
1071 bool crc32_err;
1072 bool hw_dec;
1073 bool sw_dec;
1074 bool addr1_match;
1075 u8 frag;
1076 u16 seq;
1077 u8 frame_type;
1078 u8 rx_pl_id;
1079 bool addr_cam_valid;
1080 u8 addr_cam_id;
1081 u8 sec_cam_id;
1082 u8 mac_id;
1083 u16 offset;
1084 u16 rxd_len;
1085 bool ready;
1086};
1087
1088struct rtw89_rxdesc_short {
1089 __le32 dword0;
1090 __le32 dword1;
1091 __le32 dword2;
1092 __le32 dword3;
1093} __packed;
1094
1095struct rtw89_rxdesc_short_v2 {
1096 __le32 dword0;
1097 __le32 dword1;
1098 __le32 dword2;
1099 __le32 dword3;
1100 __le32 dword4;
1101 __le32 dword5;
1102} __packed;
1103
1104struct rtw89_rxdesc_long {
1105 __le32 dword0;
1106 __le32 dword1;
1107 __le32 dword2;
1108 __le32 dword3;
1109 __le32 dword4;
1110 __le32 dword5;
1111 __le32 dword6;
1112 __le32 dword7;
1113} __packed;
1114
1115struct rtw89_rxdesc_long_v2 {
1116 __le32 dword0;
1117 __le32 dword1;
1118 __le32 dword2;
1119 __le32 dword3;
1120 __le32 dword4;
1121 __le32 dword5;
1122 __le32 dword6;
1123 __le32 dword7;
1124 __le32 dword8;
1125 __le32 dword9;
1126} __packed;
1127
1128struct rtw89_tx_desc_info {
1129 u16 pkt_size;
1130 u8 wp_offset;
1131 u8 mac_id;
1132 u8 qsel;
1133 u8 ch_dma;
1134 u8 hdr_llc_len;
1135 bool is_bmc;
1136 bool en_wd_info;
1137 bool wd_page;
1138 bool use_rate;
1139 bool dis_data_fb;
1140 bool tid_indicate;
1141 bool agg_en;
1142 bool bk;
1143 u8 ampdu_density;
1144 u8 ampdu_num;
1145 bool sec_en;
1146 u8 addr_info_nr;
1147 u8 sec_keyid;
1148 u8 sec_type;
1149 u8 sec_cam_idx;
1150 u8 sec_seq[6];
1151 u16 data_rate;
1152 u16 data_retry_lowest_rate;
1153 bool fw_dl;
1154 u16 seq;
1155 bool a_ctrl_bsr;
1156 u8 hw_ssn_sel;
1157#define RTW89_MGMT_HW_SSN_SEL 1
1158 u8 hw_seq_mode;
1159#define RTW89_MGMT_HW_SEQ_MODE 1
1160 bool hiq;
1161 u8 port;
1162 bool er_cap;
1163 bool stbc;
1164 bool ldpc;
1165 bool upd_wlan_hdr;
1166 bool mlo;
1167};
1168
1169struct rtw89_core_tx_request {
1170 enum rtw89_core_tx_type tx_type;
1171
1172 struct sk_buff *skb;
1173 struct ieee80211_vif *vif;
1174 struct ieee80211_sta *sta;
1175 struct rtw89_vif_link *rtwvif_link;
1176 struct rtw89_sta_link *rtwsta_link;
1177 struct rtw89_tx_desc_info desc_info;
1178};
1179
1180struct rtw89_txq {
1181 struct list_head list;
1182 unsigned long flags;
1183 int wait_cnt;
1184};
1185
1186struct rtw89_mac_ax_gnt {
1187 u8 gnt_bt_sw_en;
1188 u8 gnt_bt;
1189 u8 gnt_wl_sw_en;
1190 u8 gnt_wl;
1191} __packed;
1192
1193struct rtw89_mac_ax_wl_act {
1194 u8 wlan_act_en;
1195 u8 wlan_act;
1196};
1197
1198#define RTW89_MAC_AX_COEX_GNT_NR 2
1199struct rtw89_mac_ax_coex_gnt {
1200 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR];
1201 struct rtw89_mac_ax_wl_act bt[RTW89_MAC_AX_COEX_GNT_NR];
1202};
1203
1204enum rtw89_btc_ncnt {
1205 BTC_NCNT_POWER_ON = 0x0,
1206 BTC_NCNT_POWER_OFF,
1207 BTC_NCNT_INIT_COEX,
1208 BTC_NCNT_SCAN_START,
1209 BTC_NCNT_SCAN_FINISH,
1210 BTC_NCNT_SPECIAL_PACKET,
1211 BTC_NCNT_SWITCH_BAND,
1212 BTC_NCNT_RFK_TIMEOUT,
1213 BTC_NCNT_SHOW_COEX_INFO,
1214 BTC_NCNT_ROLE_INFO,
1215 BTC_NCNT_CONTROL,
1216 BTC_NCNT_RADIO_STATE,
1217 BTC_NCNT_CUSTOMERIZE,
1218 BTC_NCNT_WL_RFK,
1219 BTC_NCNT_WL_STA,
1220 BTC_NCNT_WL_STA_LAST,
1221 BTC_NCNT_FWINFO,
1222 BTC_NCNT_TIMER,
1223 BTC_NCNT_SWITCH_CHBW,
1224 BTC_NCNT_RESUME_DL_FW,
1225 BTC_NCNT_COUNTRYCODE,
1226 BTC_NCNT_NUM,
1227};
1228
1229enum rtw89_btc_btinfo {
1230 BTC_BTINFO_L0 = 0,
1231 BTC_BTINFO_L1,
1232 BTC_BTINFO_L2,
1233 BTC_BTINFO_L3,
1234 BTC_BTINFO_H0,
1235 BTC_BTINFO_H1,
1236 BTC_BTINFO_H2,
1237 BTC_BTINFO_H3,
1238 BTC_BTINFO_MAX
1239};
1240
1241enum rtw89_btc_dcnt {
1242 BTC_DCNT_RUN = 0x0,
1243 BTC_DCNT_CX_RUNINFO,
1244 BTC_DCNT_RPT,
1245 BTC_DCNT_RPT_HANG,
1246 BTC_DCNT_CYCLE,
1247 BTC_DCNT_CYCLE_HANG,
1248 BTC_DCNT_W1,
1249 BTC_DCNT_W1_HANG,
1250 BTC_DCNT_B1,
1251 BTC_DCNT_B1_HANG,
1252 BTC_DCNT_TDMA_NONSYNC,
1253 BTC_DCNT_SLOT_NONSYNC,
1254 BTC_DCNT_BTCNT_HANG,
1255 BTC_DCNT_BTTX_HANG,
1256 BTC_DCNT_WL_SLOT_DRIFT,
1257 BTC_DCNT_WL_STA_LAST,
1258 BTC_DCNT_BT_SLOT_DRIFT,
1259 BTC_DCNT_BT_SLOT_FLOOD,
1260 BTC_DCNT_FDDT_TRIG,
1261 BTC_DCNT_E2G,
1262 BTC_DCNT_E2G_HANG,
1263 BTC_DCNT_WL_FW_VER_MATCH,
1264 BTC_DCNT_NULL_TX_FAIL,
1265 BTC_DCNT_WL_STA_NTFY,
1266 BTC_DCNT_NUM,
1267};
1268
1269enum rtw89_btc_wl_state_cnt {
1270 BTC_WCNT_SCANAP = 0x0,
1271 BTC_WCNT_DHCP,
1272 BTC_WCNT_EAPOL,
1273 BTC_WCNT_ARP,
1274 BTC_WCNT_SCBDUPDATE,
1275 BTC_WCNT_RFK_REQ,
1276 BTC_WCNT_RFK_GO,
1277 BTC_WCNT_RFK_REJECT,
1278 BTC_WCNT_RFK_TIMEOUT,
1279 BTC_WCNT_CH_UPDATE,
1280 BTC_WCNT_DBCC_ALL_2G,
1281 BTC_WCNT_DBCC_CHG,
1282 BTC_WCNT_RX_OK_LAST,
1283 BTC_WCNT_RX_OK_LAST2S,
1284 BTC_WCNT_RX_ERR_LAST,
1285 BTC_WCNT_RX_ERR_LAST2S,
1286 BTC_WCNT_RX_LAST,
1287 BTC_WCNT_NUM
1288};
1289
1290enum rtw89_btc_bt_state_cnt {
1291 BTC_BCNT_RETRY = 0x0,
1292 BTC_BCNT_REINIT,
1293 BTC_BCNT_REENABLE,
1294 BTC_BCNT_SCBDREAD,
1295 BTC_BCNT_RELINK,
1296 BTC_BCNT_IGNOWL,
1297 BTC_BCNT_INQPAG,
1298 BTC_BCNT_INQ,
1299 BTC_BCNT_PAGE,
1300 BTC_BCNT_ROLESW,
1301 BTC_BCNT_AFH,
1302 BTC_BCNT_INFOUPDATE,
1303 BTC_BCNT_INFOSAME,
1304 BTC_BCNT_SCBDUPDATE,
1305 BTC_BCNT_HIPRI_TX,
1306 BTC_BCNT_HIPRI_RX,
1307 BTC_BCNT_LOPRI_TX,
1308 BTC_BCNT_LOPRI_RX,
1309 BTC_BCNT_POLUT,
1310 BTC_BCNT_POLUT_NOW,
1311 BTC_BCNT_POLUT_DIFF,
1312 BTC_BCNT_RATECHG,
1313 BTC_BCNT_NUM,
1314};
1315
1316enum rtw89_btc_bt_profile {
1317 BTC_BT_NOPROFILE = 0,
1318 BTC_BT_HFP = BIT(0),
1319 BTC_BT_HID = BIT(1),
1320 BTC_BT_A2DP = BIT(2),
1321 BTC_BT_PAN = BIT(3),
1322 BTC_PROFILE_MAX = 4,
1323};
1324
1325struct rtw89_btc_ant_info {
1326 u8 type; /* shared, dedicated */
1327 u8 num;
1328 u8 isolation;
1329
1330 u8 single_pos: 1;/* Single antenna at S0 or S1 */
1331 u8 diversity: 1;
1332 u8 btg_pos: 2;
1333 u8 stream_cnt: 4;
1334};
1335
1336struct rtw89_btc_ant_info_v7 {
1337 u8 type; /* shared, dedicated(non-shared) */
1338 u8 num; /* antenna count */
1339 u8 isolation;
1340 u8 single_pos;/* wifi 1ss-1ant at 0:S0 or 1:S1 */
1341
1342 u8 diversity; /* only for wifi use 1-antenna */
1343 u8 btg_pos; /* btg-circuit at 0:S0/1:S1/others:all */
1344 u8 stream_cnt; /* spatial_stream count */
1345 u8 rsvd;
1346} __packed;
1347
1348enum rtw89_tfc_dir {
1349 RTW89_TFC_UL,
1350 RTW89_TFC_DL,
1351};
1352
1353struct rtw89_btc_wl_smap {
1354 u32 busy: 1;
1355 u32 scan: 1;
1356 u32 connecting: 1;
1357 u32 roaming: 1;
1358 u32 dbccing: 1;
1359 u32 _4way: 1;
1360 u32 rf_off: 1;
1361 u32 lps: 2;
1362 u32 ips: 1;
1363 u32 init_ok: 1;
1364 u32 traffic_dir : 2;
1365 u32 rf_off_pre: 1;
1366 u32 lps_pre: 2;
1367 u32 lps_exiting: 1;
1368 u32 emlsr: 1;
1369};
1370
1371enum rtw89_tfc_lv {
1372 RTW89_TFC_IDLE,
1373 RTW89_TFC_ULTRA_LOW,
1374 RTW89_TFC_LOW,
1375 RTW89_TFC_MID,
1376 RTW89_TFC_HIGH,
1377};
1378
1379#define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */
1380DECLARE_EWMA(tp, 10, 2);
1381
1382struct rtw89_traffic_stats {
1383 /* units in bytes */
1384 u64 tx_unicast;
1385 u64 rx_unicast;
1386 u32 tx_avg_len;
1387 u32 rx_avg_len;
1388
1389 /* count for packets */
1390 u64 tx_cnt;
1391 u64 rx_cnt;
1392
1393 /* units in Mbps */
1394 u32 tx_throughput;
1395 u32 rx_throughput;
1396 u32 tx_throughput_raw;
1397 u32 rx_throughput_raw;
1398
1399 u32 rx_tf_acc;
1400 u32 rx_tf_periodic;
1401
1402 enum rtw89_tfc_lv tx_tfc_lv;
1403 enum rtw89_tfc_lv rx_tfc_lv;
1404 struct ewma_tp tx_ewma_tp;
1405 struct ewma_tp rx_ewma_tp;
1406
1407 u16 tx_rate;
1408 u16 rx_rate;
1409};
1410
1411struct rtw89_btc_chdef {
1412 u8 center_ch;
1413 u8 band;
1414 u8 chan;
1415 enum rtw89_sc_offset offset;
1416 enum rtw89_bandwidth bw;
1417};
1418
1419struct rtw89_btc_statistic {
1420 u8 rssi; /* 0%~110% (dBm = rssi -110) */
1421 struct rtw89_traffic_stats traffic;
1422};
1423
1424#define BTC_WL_RSSI_THMAX 4
1425
1426struct rtw89_btc_wl_link_info {
1427 struct rtw89_btc_chdef chdef;
1428 struct rtw89_btc_statistic stat;
1429 enum rtw89_tfc_dir dir;
1430 u8 rssi_state[BTC_WL_RSSI_THMAX];
1431 u8 mac_addr[ETH_ALEN];
1432 u8 busy;
1433 u8 ch;
1434 u8 bw;
1435 u8 band;
1436 u8 role;
1437 u8 pid;
1438 u8 phy;
1439 u8 dtim_period;
1440 u8 mode;
1441 u8 tx_1ss_limit;
1442
1443 u8 mac_id;
1444 u8 tx_retry;
1445
1446 u32 bcn_period;
1447 u32 busy_t;
1448 u32 tx_time;
1449 u32 client_cnt;
1450 u32 rx_rate_drop_cnt;
1451 u32 noa_duration;
1452
1453 u32 active: 1;
1454 u32 noa: 1;
1455 u32 client_ps: 1;
1456 u32 connected: 2;
1457};
1458
1459union rtw89_btc_wl_state_map {
1460 u32 val;
1461 struct rtw89_btc_wl_smap map;
1462};
1463
1464struct rtw89_btc_bt_hfp_desc {
1465 u32 exist: 1;
1466 u32 type: 2;
1467 u32 rsvd: 29;
1468};
1469
1470struct rtw89_btc_bt_hid_desc {
1471 u32 exist: 1;
1472 u32 slot_info: 2;
1473 u32 pair_cnt: 2;
1474 u32 type: 8;
1475 u32 rsvd: 19;
1476};
1477
1478struct rtw89_btc_bt_a2dp_desc {
1479 u8 exist: 1;
1480 u8 exist_last: 1;
1481 u8 play_latency: 1;
1482 u8 type: 3;
1483 u8 active: 1;
1484 u8 sink: 1;
1485 u32 handle_update: 1;
1486 u32 devinfo_query: 1;
1487 u32 no_empty_streak_2s: 8;
1488 u32 no_empty_streak_max: 8;
1489 u32 rsvd: 6;
1490
1491 u8 bitpool;
1492 u16 vendor_id;
1493 u32 device_name;
1494 u32 flush_time;
1495};
1496
1497struct rtw89_btc_bt_pan_desc {
1498 u32 exist: 1;
1499 u32 type: 1;
1500 u32 active: 1;
1501 u32 rsvd: 29;
1502};
1503
1504struct rtw89_btc_bt_rfk_info {
1505 u32 run: 1;
1506 u32 req: 1;
1507 u32 timeout: 1;
1508 u32 rsvd: 29;
1509};
1510
1511union rtw89_btc_bt_rfk_info_map {
1512 u32 val;
1513 struct rtw89_btc_bt_rfk_info map;
1514};
1515
1516struct rtw89_btc_bt_ver_info {
1517 u32 fw_coex; /* match with which coex_ver */
1518 u32 fw;
1519};
1520
1521struct rtw89_btc_bool_sta_chg {
1522 u32 now: 1;
1523 u32 last: 1;
1524 u32 remain: 1;
1525 u32 srvd: 29;
1526};
1527
1528struct rtw89_btc_u8_sta_chg {
1529 u8 now;
1530 u8 last;
1531 u8 remain;
1532 u8 rsvd;
1533};
1534
1535struct rtw89_btc_wl_scan_info {
1536 u8 band[RTW89_PHY_MAX];
1537 u8 phy_map;
1538 u8 rsvd;
1539};
1540
1541struct rtw89_btc_wl_dbcc_info {
1542 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */
1543 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */
1544 u8 real_band[RTW89_PHY_MAX];
1545 u8 role[RTW89_PHY_MAX]; /* role in each phy */
1546};
1547
1548struct rtw89_btc_wl_active_role {
1549 u8 connected: 1;
1550 u8 pid: 3;
1551 u8 phy: 1;
1552 u8 noa: 1;
1553 u8 band: 2;
1554
1555 u8 client_ps: 1;
1556 u8 bw: 7;
1557
1558 u8 role;
1559 u8 ch;
1560
1561 u16 tx_lvl;
1562 u16 rx_lvl;
1563 u16 tx_rate;
1564 u16 rx_rate;
1565};
1566
1567struct rtw89_btc_wl_active_role_v1 {
1568 u8 connected: 1;
1569 u8 pid: 3;
1570 u8 phy: 1;
1571 u8 noa: 1;
1572 u8 band: 2;
1573
1574 u8 client_ps: 1;
1575 u8 bw: 7;
1576
1577 u8 role;
1578 u8 ch;
1579
1580 u16 tx_lvl;
1581 u16 rx_lvl;
1582 u16 tx_rate;
1583 u16 rx_rate;
1584
1585 u32 noa_duration; /* ms */
1586};
1587
1588struct rtw89_btc_wl_active_role_v2 {
1589 u8 connected: 1;
1590 u8 pid: 3;
1591 u8 phy: 1;
1592 u8 noa: 1;
1593 u8 band: 2;
1594
1595 u8 client_ps: 1;
1596 u8 bw: 7;
1597
1598 u8 role;
1599 u8 ch;
1600
1601 u32 noa_duration; /* ms */
1602};
1603
1604struct rtw89_btc_wl_active_role_v7 {
1605 u8 connected;
1606 u8 pid;
1607 u8 phy;
1608 u8 noa;
1609
1610 u8 band;
1611 u8 client_ps;
1612 u8 bw;
1613 u8 role;
1614
1615 u8 ch;
1616 u8 noa_dur;
1617 u8 client_cnt;
1618 u8 rsvd2;
1619} __packed;
1620
1621struct rtw89_btc_wl_role_info_bpos {
1622 u16 none: 1;
1623 u16 station: 1;
1624 u16 ap: 1;
1625 u16 vap: 1;
1626 u16 adhoc: 1;
1627 u16 adhoc_master: 1;
1628 u16 mesh: 1;
1629 u16 moniter: 1;
1630 u16 p2p_device: 1;
1631 u16 p2p_gc: 1;
1632 u16 p2p_go: 1;
1633 u16 nan: 1;
1634};
1635
1636struct rtw89_btc_wl_scc_ctrl {
1637 u8 null_role1;
1638 u8 null_role2;
1639 u8 ebt_null; /* if tx null at EBT slot */
1640};
1641
1642union rtw89_btc_wl_role_info_map {
1643 u16 val;
1644 struct rtw89_btc_wl_role_info_bpos role;
1645};
1646
1647struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */
1648 u8 connect_cnt;
1649 u8 link_mode;
1650 union rtw89_btc_wl_role_info_map role_map;
1651 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM];
1652};
1653
1654struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */
1655 u8 connect_cnt;
1656 u8 link_mode;
1657 union rtw89_btc_wl_role_info_map role_map;
1658 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM];
1659 u32 mrole_type; /* btc_wl_mrole_type */
1660 u32 mrole_noa_duration; /* ms */
1661
1662 u32 dbcc_en: 1;
1663 u32 dbcc_chg: 1;
1664 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1665 u32 link_mode_chg: 1;
1666 u32 rsvd: 27;
1667};
1668
1669struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */
1670 u8 connect_cnt;
1671 u8 link_mode;
1672 union rtw89_btc_wl_role_info_map role_map;
1673 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM];
1674 u32 mrole_type; /* btc_wl_mrole_type */
1675 u32 mrole_noa_duration; /* ms */
1676
1677 u32 dbcc_en: 1;
1678 u32 dbcc_chg: 1;
1679 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1680 u32 link_mode_chg: 1;
1681 u32 rsvd: 27;
1682};
1683
1684struct rtw89_btc_wl_rlink { /* H2C info, struct size must be n*4 bytes */
1685 u8 connected;
1686 u8 pid;
1687 u8 phy;
1688 u8 noa;
1689
1690 u8 rf_band; /* enum band_type RF band: 2.4G/5G/6G */
1691 u8 active; /* 0:rlink is under doze */
1692 u8 bw; /* enum channel_width */
1693 u8 role; /*enum role_type */
1694
1695 u8 ch;
1696 u8 noa_dur; /* ms */
1697 u8 client_cnt; /* for Role = P2P-Go/AP */
1698 u8 mode; /* wifi protocol */
1699} __packed;
1700
1701#define RTW89_BE_BTC_WL_MAX_ROLE_NUMBER 6
1702struct rtw89_btc_wl_role_info_v7 { /* struct size must be n*4 bytes */
1703 u8 connect_cnt;
1704 u8 link_mode;
1705 u8 link_mode_chg;
1706 u8 p2p_2g;
1707
1708 struct rtw89_btc_wl_active_role_v7 active_role[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER];
1709
1710 u32 role_map;
1711 u32 mrole_type; /* btc_wl_mrole_type */
1712 u32 mrole_noa_duration; /* ms */
1713 u32 dbcc_en;
1714 u32 dbcc_chg;
1715 u32 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1716} __packed;
1717
1718struct rtw89_btc_wl_role_info_v8 { /* H2C info, struct size must be n*4 bytes */
1719 u8 connect_cnt;
1720 u8 link_mode;
1721 u8 link_mode_chg;
1722 u8 p2p_2g;
1723
1724 u8 pta_req_band;
1725 u8 dbcc_en; /* 1+1 and 2.4G-included */
1726 u8 dbcc_chg;
1727 u8 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1728
1729 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM];
1730
1731 u32 role_map;
1732 u32 mrole_type; /* btc_wl_mrole_type */
1733 u32 mrole_noa_duration; /* ms */
1734} __packed;
1735
1736struct rtw89_btc_wl_ver_info {
1737 u32 fw_coex; /* match with which coex_ver */
1738 u32 fw;
1739 u32 mac;
1740 u32 bb;
1741 u32 rf;
1742};
1743
1744struct rtw89_btc_wl_afh_info {
1745 u8 en;
1746 u8 ch;
1747 u8 bw;
1748 u8 rsvd;
1749} __packed;
1750
1751struct rtw89_btc_wl_rfk_info {
1752 u32 state: 2;
1753 u32 path_map: 4;
1754 u32 phy_map: 2;
1755 u32 band: 2;
1756 u32 type: 8;
1757 u32 rsvd: 14;
1758
1759 u32 start_time;
1760 u32 proc_time;
1761};
1762
1763struct rtw89_btc_bt_smap {
1764 u32 connect: 1;
1765 u32 ble_connect: 1;
1766 u32 acl_busy: 1;
1767 u32 sco_busy: 1;
1768 u32 mesh_busy: 1;
1769 u32 inq_pag: 1;
1770};
1771
1772union rtw89_btc_bt_state_map {
1773 u32 val;
1774 struct rtw89_btc_bt_smap map;
1775};
1776
1777#define BTC_BT_RSSI_THMAX 4
1778#define BTC_BT_AFH_GROUP 12
1779#define BTC_BT_AFH_LE_GROUP 5
1780
1781struct rtw89_btc_bt_link_info {
1782 struct rtw89_btc_u8_sta_chg profile_cnt;
1783 struct rtw89_btc_bool_sta_chg multi_link;
1784 struct rtw89_btc_bool_sta_chg relink;
1785 struct rtw89_btc_bt_hfp_desc hfp_desc;
1786 struct rtw89_btc_bt_hid_desc hid_desc;
1787 struct rtw89_btc_bt_a2dp_desc a2dp_desc;
1788 struct rtw89_btc_bt_pan_desc pan_desc;
1789 union rtw89_btc_bt_state_map status;
1790
1791 u8 sut_pwr_level[BTC_PROFILE_MAX];
1792 u8 golden_rx_shift[BTC_PROFILE_MAX];
1793 u8 rssi_state[BTC_BT_RSSI_THMAX];
1794 u8 afh_map[BTC_BT_AFH_GROUP];
1795 u8 afh_map_le[BTC_BT_AFH_LE_GROUP];
1796
1797 u32 role_sw: 1;
1798 u32 slave_role: 1;
1799 u32 afh_update: 1;
1800 u32 cqddr: 1;
1801 u32 rssi: 8;
1802 u32 tx_3m: 1;
1803 u32 rsvd: 19;
1804};
1805
1806struct rtw89_btc_3rdcx_info {
1807 u8 type; /* 0: none, 1:zigbee, 2:LTE */
1808 u8 hw_coex;
1809 u16 rsvd;
1810};
1811
1812struct rtw89_btc_dm_emap {
1813 u32 init: 1;
1814 u32 pta_owner: 1;
1815 u32 wl_rfk_timeout: 1;
1816 u32 bt_rfk_timeout: 1;
1817 u32 wl_fw_hang: 1;
1818 u32 cycle_hang: 1;
1819 u32 w1_hang: 1;
1820 u32 b1_hang: 1;
1821 u32 tdma_no_sync: 1;
1822 u32 slot_no_sync: 1;
1823 u32 wl_slot_drift: 1;
1824 u32 bt_slot_drift: 1;
1825 u32 role_num_mismatch: 1;
1826 u32 null1_tx_late: 1;
1827 u32 bt_afh_conflict: 1;
1828 u32 bt_leafh_conflict: 1;
1829 u32 bt_slot_flood: 1;
1830 u32 wl_e2g_hang: 1;
1831 u32 wl_ver_mismatch: 1;
1832 u32 bt_ver_mismatch: 1;
1833 u32 rfe_type0: 1;
1834 u32 h2c_buffer_over: 1;
1835 u32 bt_tx_hang: 1; /* for SNR too low bug, BT has no Tx req*/
1836 u32 wl_no_sta_ntfy: 1;
1837
1838 u32 h2c_bmap_mismatch: 1;
1839 u32 c2h_bmap_mismatch: 1;
1840 u32 h2c_struct_invalid: 1;
1841 u32 c2h_struct_invalid: 1;
1842 u32 h2c_c2h_buffer_mismatch: 1;
1843};
1844
1845union rtw89_btc_dm_error_map {
1846 u32 val;
1847 struct rtw89_btc_dm_emap map;
1848};
1849
1850struct rtw89_btc_rf_para {
1851 u32 tx_pwr_freerun;
1852 u32 rx_gain_freerun;
1853 u32 tx_pwr_perpkt;
1854 u32 rx_gain_perpkt;
1855};
1856
1857struct rtw89_btc_wl_nhm {
1858 u8 instant_wl_nhm_dbm;
1859 u8 instant_wl_nhm_per_mhz;
1860 u16 valid_record_times;
1861 s8 record_pwr[16];
1862 u8 record_ratio[16];
1863 s8 pwr; /* dbm_per_MHz */
1864 u8 ratio;
1865 u8 current_status;
1866 u8 refresh;
1867 bool start_flag;
1868 s8 pwr_max;
1869 s8 pwr_min;
1870};
1871
1872struct rtw89_btc_wl_info {
1873 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM];
1874 struct rtw89_btc_wl_link_info rlink_info[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM];
1875 struct rtw89_btc_wl_rfk_info rfk_info;
1876 struct rtw89_btc_wl_ver_info ver_info;
1877 struct rtw89_btc_wl_afh_info afh_info;
1878 struct rtw89_btc_wl_role_info role_info;
1879 struct rtw89_btc_wl_role_info_v1 role_info_v1;
1880 struct rtw89_btc_wl_role_info_v2 role_info_v2;
1881 struct rtw89_btc_wl_role_info_v7 role_info_v7;
1882 struct rtw89_btc_wl_role_info_v8 role_info_v8;
1883 struct rtw89_btc_wl_scan_info scan_info;
1884 struct rtw89_btc_wl_dbcc_info dbcc_info;
1885 struct rtw89_btc_rf_para rf_para;
1886 struct rtw89_btc_wl_nhm nhm;
1887 union rtw89_btc_wl_state_map status;
1888
1889 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX];
1890 u8 rssi_level;
1891 u8 cn_report;
1892 u8 coex_mode;
1893 u8 pta_req_mac;
1894 u8 bt_polut_type[RTW89_PHY_MAX]; /* BT polluted WL-Tx type for phy0/1 */
1895
1896 bool is_5g_hi_channel;
1897 bool pta_reg_mac_chg;
1898 bool bg_mode;
1899 bool he_mode;
1900 bool scbd_change;
1901 bool fw_ver_mismatch;
1902 bool client_cnt_inc_2g;
1903 u32 scbd;
1904};
1905
1906struct rtw89_btc_module {
1907 struct rtw89_btc_ant_info ant;
1908 u8 rfe_type;
1909 u8 cv;
1910
1911 u8 bt_solo: 1;
1912 u8 bt_pos: 1;
1913 u8 switch_type: 1;
1914 u8 wa_type: 3;
1915
1916 u8 kt_ver_adie;
1917};
1918
1919struct rtw89_btc_module_v7 {
1920 u8 rfe_type;
1921 u8 kt_ver;
1922 u8 bt_solo;
1923 u8 bt_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/
1924
1925 u8 switch_type; /* WL/BT switch type: 0: internal, 1: external */
1926 u8 wa_type; /* WA type: 0:none, 1: 51B 5G_Hi-Ch_Rx */
1927 u8 kt_ver_adie;
1928 u8 rsvd;
1929
1930 struct rtw89_btc_ant_info_v7 ant;
1931} __packed;
1932
1933union rtw89_btc_module_info {
1934 struct rtw89_btc_module md;
1935 struct rtw89_btc_module_v7 md_v7;
1936};
1937
1938#define RTW89_BTC_DM_MAXSTEP 30
1939#define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8)
1940
1941struct rtw89_btc_dm_step {
1942 u16 step[RTW89_BTC_DM_MAXSTEP];
1943 u8 step_pos;
1944 bool step_ov;
1945};
1946
1947struct rtw89_btc_init_info {
1948 struct rtw89_btc_module module;
1949 u8 wl_guard_ch;
1950
1951 u8 wl_only: 1;
1952 u8 wl_init_ok: 1;
1953 u8 dbcc_en: 1;
1954 u8 cx_other: 1;
1955 u8 bt_only: 1;
1956
1957 u16 rsvd;
1958};
1959
1960struct rtw89_btc_init_info_v7 {
1961 u8 wl_guard_ch;
1962 u8 wl_only;
1963 u8 wl_init_ok;
1964 u8 rsvd3;
1965
1966 u8 cx_other;
1967 u8 bt_only;
1968 u8 pta_mode;
1969 u8 pta_direction;
1970
1971 struct rtw89_btc_module_v7 module;
1972} __packed;
1973
1974union rtw89_btc_init_info_u {
1975 struct rtw89_btc_init_info init;
1976 struct rtw89_btc_init_info_v7 init_v7;
1977};
1978
1979struct rtw89_btc_wl_tx_limit_para {
1980 u16 enable;
1981 u32 tx_time; /* unit: us */
1982 u16 tx_retry;
1983};
1984
1985enum rtw89_btc_bt_scan_type {
1986 BTC_SCAN_INQ = 0,
1987 BTC_SCAN_PAGE,
1988 BTC_SCAN_BLE,
1989 BTC_SCAN_INIT,
1990 BTC_SCAN_TV,
1991 BTC_SCAN_ADV,
1992 BTC_SCAN_MAX1,
1993};
1994
1995enum rtw89_btc_ble_scan_type {
1996 CXSCAN_BG = 0,
1997 CXSCAN_INIT,
1998 CXSCAN_LE,
1999 CXSCAN_MAX
2000};
2001
2002#define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0)
2003#define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1)
2004
2005struct rtw89_btc_bt_scan_info_v1 {
2006 __le16 win;
2007 __le16 intvl;
2008 __le32 flags;
2009} __packed;
2010
2011struct rtw89_btc_bt_scan_info_v2 {
2012 __le16 win;
2013 __le16 intvl;
2014} __packed;
2015
2016struct rtw89_btc_fbtc_btscan_v1 {
2017 u8 fver; /* btc_ver::fcxbtscan */
2018 u8 rsvd;
2019 __le16 rsvd2;
2020 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1];
2021} __packed;
2022
2023struct rtw89_btc_fbtc_btscan_v2 {
2024 u8 fver; /* btc_ver::fcxbtscan */
2025 u8 type;
2026 __le16 rsvd2;
2027 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX];
2028} __packed;
2029
2030struct rtw89_btc_fbtc_btscan_v7 {
2031 u8 fver; /* btc_ver::fcxbtscan */
2032 u8 type;
2033 u8 rsvd0;
2034 u8 rsvd1;
2035 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX];
2036} __packed;
2037
2038union rtw89_btc_fbtc_btscan {
2039 struct rtw89_btc_fbtc_btscan_v1 v1;
2040 struct rtw89_btc_fbtc_btscan_v2 v2;
2041 struct rtw89_btc_fbtc_btscan_v7 v7;
2042};
2043
2044struct rtw89_btc_bt_info {
2045 struct rtw89_btc_bt_link_info link_info;
2046 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1];
2047 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX];
2048 struct rtw89_btc_bt_ver_info ver_info;
2049 struct rtw89_btc_bool_sta_chg enable;
2050 struct rtw89_btc_bool_sta_chg inq_pag;
2051 struct rtw89_btc_rf_para rf_para;
2052 union rtw89_btc_bt_rfk_info_map rfk_info;
2053
2054 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */
2055 u8 rssi_level;
2056
2057 u32 scbd;
2058 u32 feature;
2059
2060 u32 mbx_avl: 1;
2061 u32 whql_test: 1;
2062 u32 igno_wl: 1;
2063 u32 reinit: 1;
2064 u32 ble_scan_en: 1;
2065 u32 btg_type: 1;
2066 u32 inq: 1;
2067 u32 pag: 1;
2068 u32 run_patch_code: 1;
2069 u32 hi_lna_rx: 1;
2070 u32 scan_rx_low_pri: 1;
2071 u32 scan_info_update: 1;
2072 u32 lna_constrain: 3;
2073 u32 rsvd: 17;
2074};
2075
2076struct rtw89_btc_cx {
2077 struct rtw89_btc_wl_info wl;
2078 struct rtw89_btc_bt_info bt;
2079 struct rtw89_btc_3rdcx_info other;
2080 u32 state_map;
2081 u32 cnt_bt[BTC_BCNT_NUM];
2082 u32 cnt_wl[BTC_WCNT_NUM];
2083};
2084
2085struct rtw89_btc_fbtc_tdma {
2086 u8 type; /* btc_ver::fcxtdma */
2087 u8 rxflctrl;
2088 u8 txpause;
2089 u8 wtgle_n;
2090 u8 leak_n;
2091 u8 ext_ctrl;
2092 u8 rxflctrl_role;
2093 u8 option_ctrl;
2094} __packed;
2095
2096struct rtw89_btc_fbtc_tdma_v3 {
2097 u8 fver; /* btc_ver::fcxtdma */
2098 u8 rsvd;
2099 __le16 rsvd1;
2100 struct rtw89_btc_fbtc_tdma tdma;
2101} __packed;
2102
2103union rtw89_btc_fbtc_tdma_le32 {
2104 struct rtw89_btc_fbtc_tdma v1;
2105 struct rtw89_btc_fbtc_tdma_v3 v3;
2106};
2107
2108#define CXMREG_MAX 30
2109#define CXMREG_MAX_V2 20
2110#define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/
2111#define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */
2112
2113enum rtw89_btc_bt_sta_counter {
2114 BTC_BCNT_RFK_REQ = 0,
2115 BTC_BCNT_RFK_GO = 1,
2116 BTC_BCNT_RFK_REJECT = 2,
2117 BTC_BCNT_RFK_FAIL = 3,
2118 BTC_BCNT_RFK_TIMEOUT = 4,
2119 BTC_BCNT_HI_TX = 5,
2120 BTC_BCNT_HI_RX = 6,
2121 BTC_BCNT_LO_TX = 7,
2122 BTC_BCNT_LO_RX = 8,
2123 BTC_BCNT_POLLUTED = 9,
2124 BTC_BCNT_STA_MAX
2125};
2126
2127enum rtw89_btc_bt_sta_counter_v105 {
2128 BTC_BCNT_RFK_REQ_V105 = 0,
2129 BTC_BCNT_HI_TX_V105 = 1,
2130 BTC_BCNT_HI_RX_V105 = 2,
2131 BTC_BCNT_LO_TX_V105 = 3,
2132 BTC_BCNT_LO_RX_V105 = 4,
2133 BTC_BCNT_POLLUTED_V105 = 5,
2134 BTC_BCNT_STA_MAX_V105
2135};
2136
2137struct rtw89_btc_fbtc_rpt_ctrl_v1 {
2138 u16 fver; /* btc_ver::fcxbtcrpt */
2139 u16 rpt_cnt; /* tmr counters */
2140 u32 wl_fw_coex_ver; /* match which driver's coex version */
2141 u32 wl_fw_cx_offload;
2142 u32 wl_fw_ver;
2143 u32 rpt_enable;
2144 u32 rpt_para; /* ms */
2145 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */
2146 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */
2147 u32 mb_recv_cnt; /* fw recv mailbox counter */
2148 u32 mb_a2dp_empty_cnt; /* a2dp empty count */
2149 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */
2150 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */
2151 u32 bt_rfk_cnt[BTC_BCNT_HI_TX];
2152 u32 c2h_cnt; /* fw send c2h counter */
2153 u32 h2c_cnt; /* fw recv h2c counter */
2154} __packed;
2155
2156struct rtw89_btc_fbtc_rpt_ctrl_info {
2157 __le32 cnt; /* fw report counter */
2158 __le32 en; /* report map */
2159 __le32 para; /* not used */
2160
2161 __le32 cnt_c2h; /* fw send c2h counter */
2162 __le32 cnt_h2c; /* fw recv h2c counter */
2163 __le32 len_c2h; /* The total length of the last C2H */
2164
2165 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */
2166 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
2167} __packed;
2168
2169struct rtw89_btc_fbtc_rpt_ctrl_info_v5 {
2170 __le32 cx_ver; /* match which driver's coex version */
2171 __le32 fw_ver;
2172 __le32 en; /* report map */
2173
2174 __le16 cnt; /* fw report counter */
2175 __le16 cnt_c2h; /* fw send c2h counter */
2176 __le16 cnt_h2c; /* fw recv h2c counter */
2177 __le16 len_c2h; /* The total length of the last C2H */
2178
2179 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */
2180 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
2181} __packed;
2182
2183struct rtw89_btc_fbtc_rpt_ctrl_info_v8 {
2184 __le16 cnt; /* fw report counter */
2185 __le16 cnt_c2h; /* fw send c2h counter */
2186 __le16 cnt_h2c; /* fw recv h2c counter */
2187 __le16 len_c2h; /* The total length of the last C2H */
2188
2189 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */
2190 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
2191
2192 __le32 cx_ver; /* match which driver's coex version */
2193 __le32 fw_ver;
2194 __le32 en; /* report map */
2195} __packed;
2196
2197struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info {
2198 __le32 cx_ver; /* match which driver's coex version */
2199 __le32 cx_offload;
2200 __le32 fw_ver;
2201} __packed;
2202
2203struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty {
2204 __le32 cnt_empty; /* a2dp empty count */
2205 __le32 cnt_flowctrl; /* a2dp empty flow control counter */
2206 __le32 cnt_tx;
2207 __le32 cnt_ack;
2208 __le32 cnt_nack;
2209} __packed;
2210
2211struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox {
2212 __le32 cnt_send_ok; /* fw send mailbox ok counter */
2213 __le32 cnt_send_fail; /* fw send mailbox fail counter */
2214 __le32 cnt_recv; /* fw recv mailbox counter */
2215 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp;
2216} __packed;
2217
2218struct rtw89_btc_fbtc_rpt_ctrl_v4 {
2219 u8 fver;
2220 u8 rsvd;
2221 __le16 rsvd1;
2222 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info;
2223 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info;
2224 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2225 __le32 bt_cnt[BTC_BCNT_STA_MAX];
2226 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX];
2227} __packed;
2228
2229struct rtw89_btc_fbtc_rpt_ctrl_v5 {
2230 u8 fver;
2231 u8 rsvd;
2232 __le16 rsvd1;
2233
2234 u8 gnt_val[RTW89_PHY_MAX][4];
2235 __le16 bt_cnt[BTC_BCNT_STA_MAX];
2236
2237 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info;
2238 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2239} __packed;
2240
2241struct rtw89_btc_fbtc_rpt_ctrl_v105 {
2242 u8 fver;
2243 u8 rsvd;
2244 __le16 rsvd1;
2245
2246 u8 gnt_val[RTW89_PHY_MAX][4];
2247 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105];
2248
2249 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info;
2250 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2251} __packed;
2252
2253struct rtw89_btc_fbtc_rpt_ctrl_v7 {
2254 u8 fver;
2255 u8 rsvd0;
2256 u8 rsvd1;
2257 u8 rsvd2;
2258
2259 u8 gnt_val[RTW89_PHY_MAX][4];
2260 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105];
2261
2262 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info;
2263 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2264} __packed;
2265
2266struct rtw89_btc_fbtc_rpt_ctrl_v8 {
2267 u8 fver;
2268 u8 rsvd0;
2269 u8 rpt_len_max_l; /* BTC_RPT_MAX bit0~7 */
2270 u8 rpt_len_max_h; /* BTC_RPT_MAX bit8~15 */
2271
2272 u8 gnt_val[RTW89_PHY_MAX][4];
2273 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105];
2274
2275 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info;
2276 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2277} __packed;
2278
2279union rtw89_btc_fbtc_rpt_ctrl_ver_info {
2280 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1;
2281 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4;
2282 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5;
2283 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105;
2284 struct rtw89_btc_fbtc_rpt_ctrl_v7 v7;
2285 struct rtw89_btc_fbtc_rpt_ctrl_v8 v8;
2286};
2287
2288enum rtw89_fbtc_ext_ctrl_type {
2289 CXECTL_OFF = 0x0, /* tdma off */
2290 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */
2291 CXECTL_EXT = 0x2,
2292 CXECTL_MAX
2293};
2294
2295union rtw89_btc_fbtc_rxflct {
2296 u8 val;
2297 u8 type: 3;
2298 u8 tgln_n: 5;
2299};
2300
2301enum rtw89_btc_cxst_state {
2302 CXST_OFF = 0x0,
2303 CXST_B2W = 0x1,
2304 CXST_W1 = 0x2,
2305 CXST_W2 = 0x3,
2306 CXST_W2B = 0x4,
2307 CXST_B1 = 0x5,
2308 CXST_B2 = 0x6,
2309 CXST_B3 = 0x7,
2310 CXST_B4 = 0x8,
2311 CXST_LK = 0x9,
2312 CXST_BLK = 0xa,
2313 CXST_E2G = 0xb,
2314 CXST_E5G = 0xc,
2315 CXST_EBT = 0xd,
2316 CXST_ENULL = 0xe,
2317 CXST_WLK = 0xf,
2318 CXST_W1FDD = 0x10,
2319 CXST_B1FDD = 0x11,
2320 CXST_MAX = 0x12,
2321};
2322
2323enum rtw89_btc_cxevnt {
2324 CXEVNT_TDMA_ENTRY = 0x0,
2325 CXEVNT_WL_TMR,
2326 CXEVNT_B1_TMR,
2327 CXEVNT_B2_TMR,
2328 CXEVNT_B3_TMR,
2329 CXEVNT_B4_TMR,
2330 CXEVNT_W2B_TMR,
2331 CXEVNT_B2W_TMR,
2332 CXEVNT_BCN_EARLY,
2333 CXEVNT_A2DP_EMPTY,
2334 CXEVNT_LK_END,
2335 CXEVNT_RX_ISR,
2336 CXEVNT_RX_FC0,
2337 CXEVNT_RX_FC1,
2338 CXEVNT_BT_RELINK,
2339 CXEVNT_BT_RETRY,
2340 CXEVNT_E2G,
2341 CXEVNT_E5G,
2342 CXEVNT_EBT,
2343 CXEVNT_ENULL,
2344 CXEVNT_DRV_WLK,
2345 CXEVNT_BCN_OK,
2346 CXEVNT_BT_CHANGE,
2347 CXEVNT_EBT_EXTEND,
2348 CXEVNT_E2G_NULL1,
2349 CXEVNT_B1FDD_TMR,
2350 CXEVNT_MAX
2351};
2352
2353enum {
2354 CXBCN_ALL = 0x0,
2355 CXBCN_ALL_OK,
2356 CXBCN_BT_SLOT,
2357 CXBCN_BT_OK,
2358 CXBCN_MAX
2359};
2360
2361enum btc_slot_type {
2362 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */
2363 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/
2364 CXSTYPE_NUM,
2365};
2366
2367enum { /* TIME */
2368 CXT_BT = 0x0,
2369 CXT_WL = 0x1,
2370 CXT_MAX
2371};
2372
2373enum { /* TIME-A2DP */
2374 CXT_FLCTRL_OFF = 0x0,
2375 CXT_FLCTRL_ON = 0x1,
2376 CXT_FLCTRL_MAX
2377};
2378
2379enum { /* STEP TYPE */
2380 CXSTEP_NONE = 0x0,
2381 CXSTEP_EVNT = 0x1,
2382 CXSTEP_SLOT = 0x2,
2383 CXSTEP_MAX,
2384};
2385
2386enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */
2387 RPT_BT_AFH_SEQ_LEGACY = 0x10,
2388 RPT_BT_AFH_SEQ_LE = 0x20
2389};
2390
2391#define BTC_DBG_MAX1 32
2392struct rtw89_btc_fbtc_gpio_dbg_v1 {
2393 u8 fver; /* btc_ver::fcxgpiodbg */
2394 u8 rsvd;
2395 __le16 rsvd2;
2396 __le32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */
2397 __le32 pre_state; /* the debug signal is 1 or 0 */
2398 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */
2399} __packed;
2400
2401struct rtw89_btc_fbtc_gpio_dbg_v7 {
2402 u8 fver;
2403 u8 rsvd0;
2404 u8 rsvd1;
2405 u8 rsvd2;
2406
2407 u8 gpio_map[BTC_DBG_MAX1];
2408
2409 __le32 en_map;
2410 __le32 pre_state;
2411} __packed;
2412
2413union rtw89_btc_fbtc_gpio_dbg {
2414 struct rtw89_btc_fbtc_gpio_dbg_v1 v1;
2415 struct rtw89_btc_fbtc_gpio_dbg_v7 v7;
2416};
2417
2418struct rtw89_btc_fbtc_mreg_val_v1 {
2419 u8 fver; /* btc_ver::fcxmreg */
2420 u8 reg_num;
2421 __le16 rsvd;
2422 __le32 mreg_val[CXMREG_MAX];
2423} __packed;
2424
2425struct rtw89_btc_fbtc_mreg_val_v2 {
2426 u8 fver; /* btc_ver::fcxmreg */
2427 u8 reg_num;
2428 __le16 rsvd;
2429 __le32 mreg_val[CXMREG_MAX_V2];
2430} __packed;
2431
2432struct rtw89_btc_fbtc_mreg_val_v7 {
2433 u8 fver;
2434 u8 reg_num;
2435 u8 rsvd0;
2436 u8 rsvd1;
2437 __le32 mreg_val[CXMREG_MAX_V2];
2438} __packed;
2439
2440union rtw89_btc_fbtc_mreg_val {
2441 struct rtw89_btc_fbtc_mreg_val_v1 v1;
2442 struct rtw89_btc_fbtc_mreg_val_v2 v2;
2443 struct rtw89_btc_fbtc_mreg_val_v7 v7;
2444};
2445
2446#define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \
2447 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \
2448 .offset = cpu_to_le32(__offset), }
2449
2450struct rtw89_btc_fbtc_mreg {
2451 __le16 type;
2452 __le16 bytes;
2453 __le32 offset;
2454} __packed;
2455
2456struct rtw89_btc_fbtc_slot {
2457 __le16 dur;
2458 __le32 cxtbl;
2459 __le16 cxtype;
2460} __packed;
2461
2462struct rtw89_btc_fbtc_slots {
2463 u8 fver; /* btc_ver::fcxslots */
2464 u8 tbl_num;
2465 __le16 rsvd;
2466 __le32 update_map;
2467 struct rtw89_btc_fbtc_slot slot[CXST_MAX];
2468} __packed;
2469
2470struct rtw89_btc_fbtc_slot_v7 {
2471 __le16 dur; /* slot duration */
2472 __le16 cxtype;
2473 __le32 cxtbl;
2474} __packed;
2475
2476struct rtw89_btc_fbtc_slot_u16 {
2477 __le16 dur; /* slot duration */
2478 __le16 cxtype;
2479 __le16 cxtbl_l16; /* coex table [15:0] */
2480 __le16 cxtbl_h16; /* coex table [31:16] */
2481} __packed;
2482
2483struct rtw89_btc_fbtc_1slot_v7 {
2484 u8 fver;
2485 u8 sid; /* slot id */
2486 __le16 rsvd;
2487 struct rtw89_btc_fbtc_slot_v7 slot;
2488} __packed;
2489
2490struct rtw89_btc_fbtc_slots_v7 {
2491 u8 fver;
2492 u8 slot_cnt;
2493 u8 rsvd0;
2494 u8 rsvd1;
2495 struct rtw89_btc_fbtc_slot_u16 slot[CXST_MAX];
2496 __le32 update_map;
2497} __packed;
2498
2499union rtw89_btc_fbtc_slots_info {
2500 struct rtw89_btc_fbtc_slots v1;
2501 struct rtw89_btc_fbtc_slots_v7 v7;
2502} __packed;
2503
2504struct rtw89_btc_fbtc_step {
2505 u8 type;
2506 u8 val;
2507 __le16 difft;
2508} __packed;
2509
2510struct rtw89_btc_fbtc_steps_v2 {
2511 u8 fver; /* btc_ver::fcxstep */
2512 u8 rsvd;
2513 __le16 cnt;
2514 __le16 pos_old;
2515 __le16 pos_new;
2516 struct rtw89_btc_fbtc_step step[FCXMAX_STEP];
2517} __packed;
2518
2519struct rtw89_btc_fbtc_steps_v3 {
2520 u8 fver;
2521 u8 en;
2522 __le16 rsvd;
2523 __le32 cnt;
2524 struct rtw89_btc_fbtc_step step[FCXMAX_STEP];
2525} __packed;
2526
2527union rtw89_btc_fbtc_steps_info {
2528 struct rtw89_btc_fbtc_steps_v2 v2;
2529 struct rtw89_btc_fbtc_steps_v3 v3;
2530};
2531
2532struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */
2533 u8 fver; /* btc_ver::fcxcysta */
2534 u8 rsvd;
2535 __le16 cycles; /* total cycle number */
2536 __le16 cycles_a2dp[CXT_FLCTRL_MAX];
2537 __le16 a2dpept; /* a2dp empty cnt */
2538 __le16 a2dpeptto; /* a2dp empty timeout cnt*/
2539 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */
2540 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */
2541 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
2542 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */
2543 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */
2544 __le16 tavg_a2dpept; /* avg a2dp empty time */
2545 __le16 tmax_a2dpept; /* max a2dp empty time */
2546 __le16 tavg_lk; /* avg leak-slot time */
2547 __le16 tmax_lk; /* max leak-slot time */
2548 __le32 slot_cnt[CXST_MAX]; /* slot count */
2549 __le32 bcn_cnt[CXBCN_MAX];
2550 __le32 leakrx_cnt; /* the rximr occur at leak slot */
2551 __le32 collision_cnt; /* counter for event/timer occur at same time */
2552 __le32 skip_cnt;
2553 __le32 exception;
2554 __le32 except_cnt;
2555 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX];
2556} __packed;
2557
2558struct rtw89_btc_fbtc_fdd_try_info {
2559 __le16 cycles[CXT_FLCTRL_MAX];
2560 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */
2561 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */
2562} __packed;
2563
2564struct rtw89_btc_fbtc_cycle_time_info {
2565 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
2566 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */
2567 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
2568} __packed;
2569
2570struct rtw89_btc_fbtc_cycle_time_info_v5 {
2571 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
2572 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */
2573} __packed;
2574
2575struct rtw89_btc_fbtc_a2dp_trx_stat {
2576 u8 empty_cnt;
2577 u8 retry_cnt;
2578 u8 tx_rate;
2579 u8 tx_cnt;
2580 u8 ack_cnt;
2581 u8 nack_cnt;
2582 u8 rsvd1;
2583 u8 rsvd2;
2584} __packed;
2585
2586struct rtw89_btc_fbtc_a2dp_trx_stat_v4 {
2587 u8 empty_cnt;
2588 u8 retry_cnt;
2589 u8 tx_rate;
2590 u8 tx_cnt;
2591 u8 ack_cnt;
2592 u8 nack_cnt;
2593 u8 no_empty_cnt;
2594 u8 rsvd;
2595} __packed;
2596
2597struct rtw89_btc_fbtc_cycle_a2dp_empty_info {
2598 __le16 cnt; /* a2dp empty cnt */
2599 __le16 cnt_timeout; /* a2dp empty timeout cnt*/
2600 __le16 tavg; /* avg a2dp empty time */
2601 __le16 tmax; /* max a2dp empty time */
2602} __packed;
2603
2604struct rtw89_btc_fbtc_cycle_leak_info {
2605 __le32 cnt_rximr; /* the rximr occur at leak slot */
2606 __le16 tavg; /* avg leak-slot time */
2607 __le16 tmax; /* max leak-slot time */
2608} __packed;
2609
2610struct rtw89_btc_fbtc_cycle_leak_info_v7 {
2611 __le16 tavg;
2612 __le16 tamx;
2613 __le32 cnt_rximr;
2614} __packed;
2615
2616#define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0)
2617#define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10)
2618
2619struct rtw89_btc_fbtc_cycle_fddt_info {
2620 __le16 train_cycle;
2621 __le16 tp;
2622
2623 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2624 s8 bt_tx_power; /* decrease Tx power (dB) */
2625 s8 bt_rx_gain; /* LNA constrain level */
2626 u8 no_empty_cnt;
2627
2628 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */
2629 u8 cn; /* condition_num */
2630 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */
2631 u8 train_result; /* refer to enum btc_fddt_check_map */
2632} __packed;
2633
2634#define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0)
2635#define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4)
2636
2637struct rtw89_btc_fbtc_cycle_fddt_info_v5 {
2638 __le16 train_cycle;
2639 __le16 tp;
2640
2641 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2642 s8 bt_tx_power; /* decrease Tx power (dB) */
2643 s8 bt_rx_gain; /* LNA constrain level */
2644 u8 no_empty_cnt;
2645
2646 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */
2647 u8 cn; /* condition_num */
2648 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */
2649 u8 train_result; /* refer to enum btc_fddt_check_map */
2650} __packed;
2651
2652struct rtw89_btc_fbtc_fddt_cell_status {
2653 s8 wl_tx_pwr;
2654 s8 bt_tx_pwr;
2655 s8 bt_rx_gain;
2656 u8 state_phase; /* [0:3] train state, [4:7] train phase */
2657} __packed;
2658
2659struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */
2660 u8 fver;
2661 u8 rsvd;
2662 __le16 cycles; /* total cycle number */
2663 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX];
2664 struct rtw89_btc_fbtc_cycle_time_info cycle_time;
2665 struct rtw89_btc_fbtc_fdd_try_info fdd_try;
2666 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2667 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX];
2668 struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2669 __le32 slot_cnt[CXST_MAX]; /* slot count */
2670 __le32 bcn_cnt[CXBCN_MAX];
2671 __le32 collision_cnt; /* counter for event/timer occur at the same time */
2672 __le32 skip_cnt;
2673 __le32 except_cnt;
2674 __le32 except_map;
2675} __packed;
2676
2677#define FDD_TRAIN_WL_DIRECTION 2
2678#define FDD_TRAIN_WL_RSSI_LEVEL 5
2679#define FDD_TRAIN_BT_RSSI_LEVEL 5
2680
2681struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */
2682 u8 fver;
2683 u8 rsvd;
2684 u8 collision_cnt; /* counter for event/timer occur at the same time */
2685 u8 except_cnt;
2686
2687 __le16 skip_cnt;
2688 __le16 cycles; /* total cycle number */
2689
2690 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2691 __le16 slot_cnt[CXST_MAX]; /* slot count */
2692 __le16 bcn_cnt[CXBCN_MAX];
2693 struct rtw89_btc_fbtc_cycle_time_info cycle_time;
2694 struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2695 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2696 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2697 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX];
2698 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION]
2699 [FDD_TRAIN_WL_RSSI_LEVEL]
2700 [FDD_TRAIN_BT_RSSI_LEVEL];
2701 __le32 except_map;
2702} __packed;
2703
2704struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */
2705 u8 fver;
2706 u8 rsvd;
2707 u8 collision_cnt; /* counter for event/timer occur at the same time */
2708 u8 except_cnt;
2709 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX];
2710
2711 __le16 skip_cnt;
2712 __le16 cycles; /* total cycle number */
2713
2714 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2715 __le16 slot_cnt[CXST_MAX]; /* slot count */
2716 __le16 bcn_cnt[CXBCN_MAX];
2717 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time;
2718 struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2719 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2720 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2721 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX];
2722 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION]
2723 [FDD_TRAIN_WL_RSSI_LEVEL]
2724 [FDD_TRAIN_BT_RSSI_LEVEL];
2725 __le32 except_map;
2726} __packed;
2727
2728struct rtw89_btc_fbtc_cysta_v7 { /* statistics for cycles */
2729 u8 fver;
2730 u8 rsvd;
2731 u8 collision_cnt; /* counter for event/timer occur at the same time */
2732 u8 except_cnt;
2733
2734 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX];
2735
2736 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2737
2738 __le16 skip_cnt;
2739 __le16 cycles; /* total cycle number */
2740
2741 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2742 __le16 slot_cnt[CXST_MAX]; /* slot count */
2743 __le16 bcn_cnt[CXBCN_MAX];
2744
2745 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time;
2746 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2747 struct rtw89_btc_fbtc_cycle_leak_info_v7 leak_slot;
2748
2749 __le32 except_map;
2750} __packed;
2751
2752union rtw89_btc_fbtc_cysta_info {
2753 struct rtw89_btc_fbtc_cysta_v2 v2;
2754 struct rtw89_btc_fbtc_cysta_v3 v3;
2755 struct rtw89_btc_fbtc_cysta_v4 v4;
2756 struct rtw89_btc_fbtc_cysta_v5 v5;
2757 struct rtw89_btc_fbtc_cysta_v7 v7;
2758};
2759
2760struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */
2761 u8 fver; /* btc_ver::fcxnullsta */
2762 u8 rsvd;
2763 __le16 rsvd2;
2764 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */
2765 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
2766 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */
2767} __packed;
2768
2769struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */
2770 u8 fver; /* btc_ver::fcxnullsta */
2771 u8 rsvd;
2772 __le16 rsvd2;
2773 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */
2774 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
2775 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */
2776} __packed;
2777
2778struct rtw89_btc_fbtc_cynullsta_v7 { /* cycle null statistics */
2779 u8 fver;
2780 u8 rsvd0;
2781 u8 rsvd1;
2782 u8 rsvd2;
2783
2784 __le32 tmax[2];
2785 __le32 tavg[2];
2786 __le32 result[2][5];
2787} __packed;
2788
2789union rtw89_btc_fbtc_cynullsta_info {
2790 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */
2791 struct rtw89_btc_fbtc_cynullsta_v2 v2;
2792 struct rtw89_btc_fbtc_cynullsta_v7 v7;
2793};
2794
2795struct rtw89_btc_fbtc_btver_v1 {
2796 u8 fver; /* btc_ver::fcxbtver */
2797 u8 rsvd;
2798 __le16 rsvd2;
2799 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */
2800 __le32 fw_ver;
2801 __le32 feature;
2802} __packed;
2803
2804struct rtw89_btc_fbtc_btver_v7 {
2805 u8 fver;
2806 u8 rsvd0;
2807 u8 rsvd1;
2808 u8 rsvd2;
2809
2810 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */
2811 __le32 fw_ver;
2812 __le32 feature;
2813} __packed;
2814
2815union rtw89_btc_fbtc_btver {
2816 struct rtw89_btc_fbtc_btver_v1 v1;
2817 struct rtw89_btc_fbtc_btver_v7 v7;
2818} __packed;
2819
2820struct rtw89_btc_fbtc_btafh {
2821 u8 fver; /* btc_ver::fcxbtafh */
2822 u8 rsvd;
2823 __le16 rsvd2;
2824 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */
2825 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */
2826 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */
2827} __packed;
2828
2829struct rtw89_btc_fbtc_btafh_v2 {
2830 u8 fver; /* btc_ver::fcxbtafh */
2831 u8 rsvd;
2832 u8 rsvd2;
2833 u8 map_type;
2834 u8 afh_l[4];
2835 u8 afh_m[4];
2836 u8 afh_h[4];
2837 u8 afh_le_a[4];
2838 u8 afh_le_b[4];
2839} __packed;
2840
2841struct rtw89_btc_fbtc_btafh_v7 {
2842 u8 fver;
2843 u8 map_type;
2844 u8 rsvd0;
2845 u8 rsvd1;
2846 u8 afh_l[4]; /*bit0:2402, bit1:2403.... bit31:2433 */
2847 u8 afh_m[4]; /*bit0:2434, bit1:2435.... bit31:2465 */
2848 u8 afh_h[4]; /*bit0:2466, bit1:2467.....bit14:2480 */
2849 u8 afh_le_a[4];
2850 u8 afh_le_b[4];
2851} __packed;
2852
2853struct rtw89_btc_fbtc_btdevinfo {
2854 u8 fver; /* btc_ver::fcxbtdevinfo */
2855 u8 rsvd;
2856 __le16 vendor_id;
2857 __le32 dev_name; /* only 24 bits valid */
2858 __le32 flush_time;
2859} __packed;
2860
2861#define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0)
2862struct rtw89_btc_rf_trx_para {
2863 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2864 u32 wl_rx_gain; /* rx gain table index (TBD.) */
2865 u8 bt_tx_power; /* decrease Tx power (dB) */
2866 u8 bt_rx_gain; /* LNA constrain level */
2867};
2868
2869struct rtw89_btc_trx_info {
2870 u8 tx_lvl;
2871 u8 rx_lvl;
2872 u8 wl_rssi;
2873 u8 bt_rssi;
2874
2875 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2876 s8 rx_gain; /* rx gain table index (TBD.) */
2877 s8 bt_tx_power; /* decrease Tx power (dB) */
2878 s8 bt_rx_gain; /* LNA constrain level */
2879
2880 u8 cn; /* condition_num */
2881 s8 nhm;
2882 u8 bt_profile;
2883 u8 rsvd2;
2884
2885 u16 tx_rate;
2886 u16 rx_rate;
2887
2888 u32 tx_tp;
2889 u32 rx_tp;
2890 u32 rx_err_ratio;
2891};
2892
2893union rtw89_btc_fbtc_slot_u {
2894 struct rtw89_btc_fbtc_slot v1[CXST_MAX];
2895 struct rtw89_btc_fbtc_slot_v7 v7[CXST_MAX];
2896};
2897
2898struct rtw89_btc_dm {
2899 union rtw89_btc_fbtc_slot_u slot;
2900 union rtw89_btc_fbtc_slot_u slot_now;
2901 struct rtw89_btc_fbtc_tdma tdma;
2902 struct rtw89_btc_fbtc_tdma tdma_now;
2903 struct rtw89_mac_ax_coex_gnt gnt;
2904 union rtw89_btc_init_info_u init_info; /* pass to wl_fw if offload */
2905 struct rtw89_btc_rf_trx_para rf_trx_para;
2906 struct rtw89_btc_wl_tx_limit_para wl_tx_limit;
2907 struct rtw89_btc_dm_step dm_step;
2908 struct rtw89_btc_wl_scc_ctrl wl_scc;
2909 struct rtw89_btc_trx_info trx_info;
2910 union rtw89_btc_dm_error_map error;
2911 u32 cnt_dm[BTC_DCNT_NUM];
2912 u32 cnt_notify[BTC_NCNT_NUM];
2913
2914 u32 update_slot_map;
2915 u32 set_ant_path;
2916 u32 e2g_slot_limit;
2917 u32 e2g_slot_nulltx_time;
2918
2919 u32 wl_only: 1;
2920 u32 wl_fw_cx_offload: 1;
2921 u32 freerun: 1;
2922 u32 fddt_train: 1;
2923 u32 wl_ps_ctrl: 2;
2924 u32 wl_mimo_ps: 1;
2925 u32 leak_ap: 1;
2926 u32 noisy_level: 3;
2927 u32 coex_info_map: 8;
2928 u32 bt_only: 1;
2929 u32 wl_btg_rx: 2;
2930 u32 trx_para_level: 8;
2931 u32 wl_stb_chg: 1;
2932 u32 pta_owner: 1;
2933
2934 u32 tdma_instant_excute: 1;
2935 u32 wl_btg_rx_rb: 2;
2936
2937 u16 slot_dur[CXST_MAX];
2938 u16 bt_slot_flood;
2939
2940 u8 run_reason;
2941 u8 run_action;
2942
2943 u8 wl_pre_agc: 2;
2944 u8 wl_lna2: 1;
2945 u8 freerun_chk: 1;
2946 u8 wl_pre_agc_rb: 2;
2947 u8 bt_select: 2; /* 0:s0, 1:s1, 2:s0 & s1, refer to enum btc_bt_index */
2948 u8 slot_req_more: 1;
2949};
2950
2951struct rtw89_btc_ctrl {
2952 u32 manual: 1;
2953 u32 igno_bt: 1;
2954 u32 always_freerun: 1;
2955 u32 trace_step: 16;
2956 u32 rsvd: 12;
2957};
2958
2959struct rtw89_btc_ctrl_v7 {
2960 u8 manual;
2961 u8 igno_bt;
2962 u8 always_freerun;
2963 u8 rsvd;
2964} __packed;
2965
2966union rtw89_btc_ctrl_list {
2967 struct rtw89_btc_ctrl ctrl;
2968 struct rtw89_btc_ctrl_v7 ctrl_v7;
2969};
2970
2971struct rtw89_btc_dbg {
2972 /* cmd "rb" */
2973 bool rb_done;
2974 u32 rb_val;
2975};
2976
2977enum rtw89_btc_btf_fw_event {
2978 BTF_EVNT_RPT = 0,
2979 BTF_EVNT_BT_INFO = 1,
2980 BTF_EVNT_BT_SCBD = 2,
2981 BTF_EVNT_BT_REG = 3,
2982 BTF_EVNT_CX_RUNINFO = 4,
2983 BTF_EVNT_BT_PSD = 5,
2984 BTF_EVNT_BT_DEV_INFO = 6, /* fwc2hfunc > 0 */
2985 BTF_EVNT_BT_LEAUDIO_INFO = 7, /* fwc2hfunc > 1 */
2986 BTF_EVNT_BUF_OVERFLOW,
2987 BTF_EVNT_C2H_LOOPBACK,
2988 BTF_EVNT_MAX,
2989};
2990
2991enum btf_fw_event_report {
2992 BTC_RPT_TYPE_CTRL = 0x0,
2993 BTC_RPT_TYPE_TDMA,
2994 BTC_RPT_TYPE_SLOT,
2995 BTC_RPT_TYPE_CYSTA,
2996 BTC_RPT_TYPE_STEP,
2997 BTC_RPT_TYPE_NULLSTA,
2998 BTC_RPT_TYPE_FDDT, /* added by ver->fwevntrptl == 1 */
2999 BTC_RPT_TYPE_MREG,
3000 BTC_RPT_TYPE_GPIO_DBG,
3001 BTC_RPT_TYPE_BT_VER,
3002 BTC_RPT_TYPE_BT_SCAN,
3003 BTC_RPT_TYPE_BT_AFH,
3004 BTC_RPT_TYPE_BT_DEVICE,
3005 BTC_RPT_TYPE_TEST,
3006 BTC_RPT_TYPE_MAX = 31,
3007
3008 __BTC_RPT_TYPE_V0_SAME = BTC_RPT_TYPE_NULLSTA,
3009 __BTC_RPT_TYPE_V0_MAX = 12,
3010};
3011
3012enum rtw_btc_btf_reg_type {
3013 REG_MAC = 0x0,
3014 REG_BB = 0x1,
3015 REG_RF = 0x2,
3016 REG_BT_RF = 0x3,
3017 REG_BT_MODEM = 0x4,
3018 REG_BT_BLUEWIZE = 0x5,
3019 REG_BT_VENDOR = 0x6,
3020 REG_BT_LE = 0x7,
3021 REG_MAX_TYPE,
3022};
3023
3024struct rtw89_btc_rpt_cmn_info {
3025 u32 rx_cnt;
3026 u32 rx_len;
3027 u32 req_len; /* expected rsp len */
3028 u8 req_fver; /* expected rsp fver */
3029 u8 rsp_fver; /* fver from fw */
3030 u8 valid;
3031} __packed;
3032
3033union rtw89_btc_fbtc_btafh_info {
3034 struct rtw89_btc_fbtc_btafh v1;
3035 struct rtw89_btc_fbtc_btafh_v2 v2;
3036};
3037
3038struct rtw89_btc_report_ctrl_state {
3039 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3040 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo;
3041};
3042
3043struct rtw89_btc_rpt_fbtc_tdma {
3044 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3045 union rtw89_btc_fbtc_tdma_le32 finfo;
3046};
3047
3048struct rtw89_btc_rpt_fbtc_slots {
3049 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3050 union rtw89_btc_fbtc_slots_info finfo; /* info from fw */
3051};
3052
3053struct rtw89_btc_rpt_fbtc_cysta {
3054 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3055 union rtw89_btc_fbtc_cysta_info finfo;
3056};
3057
3058struct rtw89_btc_rpt_fbtc_step {
3059 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3060 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */
3061};
3062
3063struct rtw89_btc_rpt_fbtc_nullsta {
3064 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3065 union rtw89_btc_fbtc_cynullsta_info finfo;
3066};
3067
3068struct rtw89_btc_rpt_fbtc_mreg {
3069 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3070 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */
3071};
3072
3073struct rtw89_btc_rpt_fbtc_gpio_dbg {
3074 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3075 union rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */
3076};
3077
3078struct rtw89_btc_rpt_fbtc_btver {
3079 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3080 union rtw89_btc_fbtc_btver finfo; /* info from fw */
3081};
3082
3083struct rtw89_btc_rpt_fbtc_btscan {
3084 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3085 union rtw89_btc_fbtc_btscan finfo; /* info from fw */
3086};
3087
3088struct rtw89_btc_rpt_fbtc_btafh {
3089 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3090 union rtw89_btc_fbtc_btafh_info finfo;
3091};
3092
3093struct rtw89_btc_rpt_fbtc_btdev {
3094 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3095 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */
3096};
3097
3098enum rtw89_btc_btfre_type {
3099 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */
3100 BTFRE_UNDEF_TYPE,
3101 BTFRE_EXCEPTION,
3102 BTFRE_MAX,
3103};
3104
3105struct rtw89_btc_btf_fwinfo {
3106 u32 cnt_c2h;
3107 u32 cnt_h2c;
3108 u32 cnt_h2c_fail;
3109 u32 event[BTF_EVNT_MAX];
3110
3111 u32 err[BTFRE_MAX];
3112 u32 len_mismch;
3113 u32 fver_mismch;
3114 u32 rpt_en_map;
3115
3116 struct rtw89_btc_report_ctrl_state rpt_ctrl;
3117 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma;
3118 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots;
3119 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta;
3120 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step;
3121 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta;
3122 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval;
3123 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg;
3124 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver;
3125 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan;
3126 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh;
3127 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev;
3128};
3129
3130struct rtw89_btc_ver {
3131 enum rtw89_core_chip_id chip_id;
3132 u32 fw_ver_code;
3133
3134 u8 fcxbtcrpt;
3135 u8 fcxtdma;
3136 u8 fcxslots;
3137 u8 fcxcysta;
3138 u8 fcxstep;
3139 u8 fcxnullsta;
3140 u8 fcxmreg;
3141 u8 fcxgpiodbg;
3142 u8 fcxbtver;
3143 u8 fcxbtscan;
3144 u8 fcxbtafh;
3145 u8 fcxbtdevinfo;
3146 u8 fwlrole;
3147 u8 frptmap;
3148 u8 fcxctrl;
3149 u8 fcxinit;
3150
3151 u8 fwevntrptl;
3152 u8 fwc2hfunc;
3153 u8 drvinfo_type;
3154 u16 info_buf;
3155 u8 max_role_num;
3156};
3157
3158#define RTW89_BTC_POLICY_MAXLEN 512
3159
3160struct rtw89_btc {
3161 const struct rtw89_btc_ver *ver;
3162
3163 struct rtw89_btc_cx cx;
3164 struct rtw89_btc_dm dm;
3165 union rtw89_btc_ctrl_list ctrl;
3166 union rtw89_btc_module_info mdinfo;
3167 struct rtw89_btc_btf_fwinfo fwinfo;
3168 struct rtw89_btc_dbg dbg;
3169
3170 struct work_struct eapol_notify_work;
3171 struct work_struct arp_notify_work;
3172 struct work_struct dhcp_notify_work;
3173 struct work_struct icmp_notify_work;
3174
3175 u32 bt_req_len;
3176
3177 u8 policy[RTW89_BTC_POLICY_MAXLEN];
3178 u8 ant_type;
3179 u8 btg_pos;
3180 u16 policy_len;
3181 u16 policy_type;
3182 u32 hubmsg_cnt;
3183 bool bt_req_en;
3184 bool update_policy_force;
3185 bool lps;
3186 bool manual_ctrl;
3187};
3188
3189enum rtw89_btc_hmsg {
3190 RTW89_BTC_HMSG_TMR_EN = 0x0,
3191 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1,
3192 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2,
3193 RTW89_BTC_HMSG_FW_EV = 0x3,
3194 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4,
3195 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5,
3196
3197 NUM_OF_RTW89_BTC_HMSG,
3198};
3199
3200enum rtw89_ra_mode {
3201 RTW89_RA_MODE_CCK = BIT(0),
3202 RTW89_RA_MODE_OFDM = BIT(1),
3203 RTW89_RA_MODE_HT = BIT(2),
3204 RTW89_RA_MODE_VHT = BIT(3),
3205 RTW89_RA_MODE_HE = BIT(4),
3206 RTW89_RA_MODE_EHT = BIT(5),
3207};
3208
3209enum rtw89_ra_report_mode {
3210 RTW89_RA_RPT_MODE_LEGACY,
3211 RTW89_RA_RPT_MODE_HT,
3212 RTW89_RA_RPT_MODE_VHT,
3213 RTW89_RA_RPT_MODE_HE,
3214 RTW89_RA_RPT_MODE_EHT,
3215};
3216
3217enum rtw89_dig_noisy_level {
3218 RTW89_DIG_NOISY_LEVEL0 = -1,
3219 RTW89_DIG_NOISY_LEVEL1 = 0,
3220 RTW89_DIG_NOISY_LEVEL2 = 1,
3221 RTW89_DIG_NOISY_LEVEL3 = 2,
3222 RTW89_DIG_NOISY_LEVEL_MAX = 3,
3223};
3224
3225enum rtw89_gi_ltf {
3226 RTW89_GILTF_LGI_4XHE32 = 0,
3227 RTW89_GILTF_SGI_4XHE08 = 1,
3228 RTW89_GILTF_2XHE16 = 2,
3229 RTW89_GILTF_2XHE08 = 3,
3230 RTW89_GILTF_1XHE16 = 4,
3231 RTW89_GILTF_1XHE08 = 5,
3232 RTW89_GILTF_MAX
3233};
3234
3235enum rtw89_rx_frame_type {
3236 RTW89_RX_TYPE_MGNT = 0,
3237 RTW89_RX_TYPE_CTRL = 1,
3238 RTW89_RX_TYPE_DATA = 2,
3239 RTW89_RX_TYPE_RSVD = 3,
3240};
3241
3242enum rtw89_efuse_block {
3243 RTW89_EFUSE_BLOCK_SYS = 0,
3244 RTW89_EFUSE_BLOCK_RF = 1,
3245 RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2,
3246 RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3,
3247 RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4,
3248 RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5,
3249 RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6,
3250 RTW89_EFUSE_BLOCK_ADIE = 7,
3251
3252 RTW89_EFUSE_BLOCK_NUM,
3253 RTW89_EFUSE_BLOCK_IGNORE,
3254};
3255
3256struct rtw89_ra_info {
3257 u8 is_dis_ra:1;
3258 /* Bit0 : CCK
3259 * Bit1 : OFDM
3260 * Bit2 : HT
3261 * Bit3 : VHT
3262 * Bit4 : HE
3263 * Bit5 : EHT
3264 */
3265 u8 mode_ctrl:6;
3266 u8 bw_cap:3; /* enum rtw89_bandwidth */
3267 u8 macid;
3268 u8 dcm_cap:1;
3269 u8 er_cap:1;
3270 u8 init_rate_lv:2;
3271 u8 upd_all:1;
3272 u8 en_sgi:1;
3273 u8 ldpc_cap:1;
3274 u8 stbc_cap:1;
3275 u8 ss_num:3;
3276 u8 giltf:3;
3277 u8 upd_bw_nss_mask:1;
3278 u8 upd_mask:1;
3279 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */
3280 /* BFee CSI */
3281 u8 band_num;
3282 u8 ra_csi_rate_en:1;
3283 u8 fixed_csi_rate_en:1;
3284 u8 cr_tbl_sel:1;
3285 u8 fix_giltf_en:1;
3286 u8 fix_giltf:3;
3287 u8 rsvd2:1;
3288 u8 csi_mcs_ss_idx;
3289 u8 csi_mode:2;
3290 u8 csi_gi_ltf:3;
3291 u8 csi_bw:3;
3292};
3293
3294#define RTW89_PPDU_MAC_INFO_USR_SIZE 4
3295#define RTW89_PPDU_MAC_INFO_SIZE 8
3296#define RTW89_PPDU_MAC_RX_CNT_SIZE 96
3297#define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128
3298
3299#define RTW89_MAX_RX_AGG_NUM 64
3300#define RTW89_MAX_TX_AGG_NUM 128
3301
3302struct rtw89_ampdu_params {
3303 u16 agg_num;
3304 bool amsdu;
3305};
3306
3307struct rtw89_ra_report {
3308 struct rate_info txrate;
3309 u32 bit_rate;
3310 u16 hw_rate;
3311 bool might_fallback_legacy;
3312};
3313
3314DECLARE_EWMA(rssi, 10, 16);
3315DECLARE_EWMA(evm, 10, 16);
3316DECLARE_EWMA(snr, 10, 16);
3317
3318struct rtw89_ba_cam_entry {
3319 struct list_head list;
3320 u8 tid;
3321};
3322
3323#define RTW89_MAX_ADDR_CAM_NUM 128
3324#define RTW89_MAX_BSSID_CAM_NUM 20
3325#define RTW89_MAX_SEC_CAM_NUM 128
3326#define RTW89_MAX_BA_CAM_NUM 24
3327#define RTW89_SEC_CAM_IN_ADDR_CAM 7
3328
3329struct rtw89_addr_cam_entry {
3330 u8 addr_cam_idx;
3331 u8 offset;
3332 u8 len;
3333 u8 valid : 1;
3334 u8 addr_mask : 6;
3335 u8 wapi : 1;
3336 u8 mask_sel : 2;
3337 u8 bssid_cam_idx: 6;
3338
3339 u8 sec_ent_mode;
3340 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM);
3341 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM];
3342 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM];
3343};
3344
3345struct rtw89_bssid_cam_entry {
3346 u8 bssid[ETH_ALEN];
3347 u8 phy_idx;
3348 u8 bssid_cam_idx;
3349 u8 offset;
3350 u8 len;
3351 u8 valid : 1;
3352 u8 num;
3353};
3354
3355struct rtw89_sec_cam_entry {
3356 u8 sec_cam_idx;
3357 u8 offset;
3358 u8 len;
3359 u8 type : 4;
3360 u8 ext_key : 1;
3361 u8 spp_mode : 1;
3362 /* 256 bits */
3363 u8 key[32];
3364};
3365
3366struct rtw89_sta_link {
3367 struct rtw89_sta *rtwsta;
3368 unsigned int link_id;
3369
3370 u8 mac_id;
3371 bool er_cap;
3372 struct rtw89_vif_link *rtwvif_link;
3373 struct rtw89_ra_info ra;
3374 struct rtw89_ra_report ra_report;
3375 int max_agg_wait;
3376 u8 prev_rssi;
3377 struct ewma_rssi avg_rssi;
3378 struct ewma_rssi rssi[RF_PATH_MAX];
3379 struct ewma_snr avg_snr;
3380 struct ewma_evm evm_1ss;
3381 struct ewma_evm evm_min[RF_PATH_MAX];
3382 struct ewma_evm evm_max[RF_PATH_MAX];
3383 struct ieee80211_rx_status rx_status;
3384 u16 rx_hw_rate;
3385 __le32 htc_template;
3386 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */
3387 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */
3388 struct list_head ba_cam_list;
3389
3390 bool use_cfg_mask;
3391 struct cfg80211_bitrate_mask mask;
3392
3393 bool cctl_tx_time;
3394 u32 ampdu_max_time:4;
3395 bool cctl_tx_retry_limit;
3396 u32 data_tx_cnt_lmt:6;
3397};
3398
3399struct rtw89_efuse {
3400 bool valid;
3401 bool power_k_valid;
3402 u8 xtal_cap;
3403 u8 addr[ETH_ALEN];
3404 u8 rfe_type;
3405 char country_code[2];
3406};
3407
3408struct rtw89_phy_rate_pattern {
3409 u64 ra_mask;
3410 u16 rate;
3411 u8 ra_mode;
3412 bool enable;
3413};
3414
3415struct rtw89_tx_wait_info {
3416 struct rcu_head rcu_head;
3417 struct completion completion;
3418 bool tx_done;
3419};
3420
3421struct rtw89_tx_skb_data {
3422 struct rtw89_tx_wait_info __rcu *wait;
3423 u8 hci_priv[];
3424};
3425
3426#define RTW89_ROC_IDLE_TIMEOUT 500
3427#define RTW89_ROC_TX_TIMEOUT 30
3428enum rtw89_roc_state {
3429 RTW89_ROC_IDLE,
3430 RTW89_ROC_NORMAL,
3431 RTW89_ROC_MGMT,
3432};
3433
3434#define RTW89_ROC_BY_LINK_INDEX 0
3435
3436struct rtw89_roc {
3437 struct ieee80211_channel chan;
3438 struct delayed_work roc_work;
3439 enum ieee80211_roc_type type;
3440 enum rtw89_roc_state state;
3441 int duration;
3442};
3443
3444#define RTW89_P2P_MAX_NOA_NUM 2
3445
3446struct rtw89_p2p_ie_head {
3447 u8 eid;
3448 u8 ie_len;
3449 u8 oui[3];
3450 u8 oui_type;
3451} __packed;
3452
3453struct rtw89_noa_attr_head {
3454 u8 attr_type;
3455 __le16 attr_len;
3456 u8 index;
3457 u8 oppps_ctwindow;
3458} __packed;
3459
3460struct rtw89_p2p_noa_ie {
3461 struct rtw89_p2p_ie_head p2p_head;
3462 struct rtw89_noa_attr_head noa_head;
3463 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM];
3464} __packed;
3465
3466struct rtw89_p2p_noa_setter {
3467 struct rtw89_p2p_noa_ie ie;
3468 u8 noa_count;
3469 u8 noa_index;
3470};
3471
3472struct rtw89_vif_link {
3473 struct rtw89_vif *rtwvif;
3474 unsigned int link_id;
3475
3476 bool chanctx_assigned; /* only valid when running with chanctx_ops */
3477 enum rtw89_chanctx_idx chanctx_idx;
3478 enum rtw89_reg_6ghz_power reg_6ghz_power;
3479 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe;
3480
3481 u8 mac_id;
3482 u8 port;
3483 u8 mac_addr[ETH_ALEN];
3484 u8 bssid[ETH_ALEN];
3485 u8 phy_idx;
3486 u8 mac_idx;
3487 u8 net_type;
3488 u8 wifi_role;
3489 u8 self_role;
3490 u8 wmm;
3491 u8 bcn_hit_cond;
3492 u8 hit_rule;
3493 u8 last_noa_nr;
3494 u64 sync_bcn_tsf;
3495 bool trigger;
3496 bool lsig_txop;
3497 u8 tgt_ind;
3498 u8 frm_tgt_ind;
3499 bool wowlan_pattern;
3500 bool wowlan_uc;
3501 bool wowlan_magic;
3502 bool is_hesta;
3503 bool last_a_ctrl;
3504 bool dyn_tb_bedge_en;
3505 bool pre_pwr_diff_en;
3506 bool pwr_diff_en;
3507 u8 def_tri_idx;
3508 struct work_struct update_beacon_work;
3509 struct rtw89_addr_cam_entry addr_cam;
3510 struct rtw89_bssid_cam_entry bssid_cam;
3511 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS];
3512 struct rtw89_phy_rate_pattern rate_pattern;
3513 struct list_head general_pkt_list;
3514 struct rtw89_p2p_noa_setter p2p_noa;
3515};
3516
3517enum rtw89_lv1_rcvy_step {
3518 RTW89_LV1_RCVY_STEP_1,
3519 RTW89_LV1_RCVY_STEP_2,
3520};
3521
3522struct rtw89_hci_ops {
3523 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req);
3524 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch);
3525 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop);
3526 void (*reset)(struct rtw89_dev *rtwdev);
3527 int (*start)(struct rtw89_dev *rtwdev);
3528 void (*stop)(struct rtw89_dev *rtwdev);
3529 void (*pause)(struct rtw89_dev *rtwdev, bool pause);
3530 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power);
3531 void (*recalc_int_mit)(struct rtw89_dev *rtwdev);
3532
3533 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr);
3534 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr);
3535 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr);
3536 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data);
3537 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data);
3538 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data);
3539
3540 int (*mac_pre_init)(struct rtw89_dev *rtwdev);
3541 int (*mac_pre_deinit)(struct rtw89_dev *rtwdev);
3542 int (*mac_post_init)(struct rtw89_dev *rtwdev);
3543 int (*deinit)(struct rtw89_dev *rtwdev);
3544
3545 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch);
3546 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step);
3547 void (*dump_err_status)(struct rtw89_dev *rtwdev);
3548 int (*napi_poll)(struct napi_struct *napi, int budget);
3549
3550 /* Deal with locks inside recovery_start and recovery_complete callbacks
3551 * by hci instance, and handle things which need to consider under SER.
3552 * e.g. turn on/off interrupts except for the one for halt notification.
3553 */
3554 void (*recovery_start)(struct rtw89_dev *rtwdev);
3555 void (*recovery_complete)(struct rtw89_dev *rtwdev);
3556
3557 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable);
3558 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable);
3559 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable);
3560 int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev);
3561 void (*clr_idx_all)(struct rtw89_dev *rtwdev);
3562 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev);
3563 void (*disable_intr)(struct rtw89_dev *rtwdev);
3564 void (*enable_intr)(struct rtw89_dev *rtwdev);
3565 int (*rst_bdram)(struct rtw89_dev *rtwdev);
3566};
3567
3568struct rtw89_hci_info {
3569 const struct rtw89_hci_ops *ops;
3570 enum rtw89_hci_type type;
3571 u32 rpwm_addr;
3572 u32 cpwm_addr;
3573 bool paused;
3574};
3575
3576struct rtw89_chip_ops {
3577 int (*enable_bb_rf)(struct rtw89_dev *rtwdev);
3578 int (*disable_bb_rf)(struct rtw89_dev *rtwdev);
3579 void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
3580 void (*bb_postinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
3581 void (*bb_reset)(struct rtw89_dev *rtwdev,
3582 enum rtw89_phy_idx phy_idx);
3583 void (*bb_sethw)(struct rtw89_dev *rtwdev);
3584 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3585 u32 addr, u32 mask);
3586 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3587 u32 addr, u32 mask, u32 data);
3588 void (*set_channel)(struct rtw89_dev *rtwdev,
3589 const struct rtw89_chan *chan,
3590 enum rtw89_mac_idx mac_idx,
3591 enum rtw89_phy_idx phy_idx);
3592 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter,
3593 struct rtw89_channel_help_params *p,
3594 const struct rtw89_chan *chan,
3595 enum rtw89_mac_idx mac_idx,
3596 enum rtw89_phy_idx phy_idx);
3597 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map,
3598 enum rtw89_efuse_block block);
3599 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map);
3600 void (*fem_setup)(struct rtw89_dev *rtwdev);
3601 void (*rfe_gpio)(struct rtw89_dev *rtwdev);
3602 void (*rfk_hw_init)(struct rtw89_dev *rtwdev);
3603 void (*rfk_init)(struct rtw89_dev *rtwdev);
3604 void (*rfk_init_late)(struct rtw89_dev *rtwdev);
3605 void (*rfk_channel)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
3606 void (*rfk_band_changed)(struct rtw89_dev *rtwdev,
3607 enum rtw89_phy_idx phy_idx,
3608 const struct rtw89_chan *chan);
3609 void (*rfk_scan)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
3610 bool start);
3611 void (*rfk_track)(struct rtw89_dev *rtwdev);
3612 void (*power_trim)(struct rtw89_dev *rtwdev);
3613 void (*set_txpwr)(struct rtw89_dev *rtwdev,
3614 const struct rtw89_chan *chan,
3615 enum rtw89_phy_idx phy_idx);
3616 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev,
3617 enum rtw89_phy_idx phy_idx);
3618 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
3619 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path);
3620 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en,
3621 enum rtw89_phy_idx phy_idx);
3622 void (*query_ppdu)(struct rtw89_dev *rtwdev,
3623 struct rtw89_rx_phy_ppdu *phy_ppdu,
3624 struct ieee80211_rx_status *status);
3625 void (*convert_rpl_to_rssi)(struct rtw89_dev *rtwdev,
3626 struct rtw89_rx_phy_ppdu *phy_ppdu);
3627 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en,
3628 enum rtw89_phy_idx phy_idx);
3629 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev);
3630 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev,
3631 s8 pw_ofst, enum rtw89_mac_idx mac_idx);
3632 void (*digital_pwr_comp)(struct rtw89_dev *rtwdev,
3633 enum rtw89_phy_idx phy_idx);
3634 int (*pwr_on_func)(struct rtw89_dev *rtwdev);
3635 int (*pwr_off_func)(struct rtw89_dev *rtwdev);
3636 void (*query_rxdesc)(struct rtw89_dev *rtwdev,
3637 struct rtw89_rx_desc_info *desc_info,
3638 u8 *data, u32 data_offset);
3639 void (*fill_txdesc)(struct rtw89_dev *rtwdev,
3640 struct rtw89_tx_desc_info *desc_info,
3641 void *txdesc);
3642 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev,
3643 struct rtw89_tx_desc_info *desc_info,
3644 void *txdesc);
3645 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl);
3646 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev,
3647 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
3648 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx,
3649 u32 *tx_en, enum rtw89_sch_tx_sel sel);
3650 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
3651 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev,
3652 struct rtw89_vif_link *rtwvif_link,
3653 struct rtw89_sta_link *rtwsta_link);
3654 int (*h2c_default_cmac_tbl)(struct rtw89_dev *rtwdev,
3655 struct rtw89_vif_link *rtwvif_link,
3656 struct rtw89_sta_link *rtwsta_link);
3657 int (*h2c_assoc_cmac_tbl)(struct rtw89_dev *rtwdev,
3658 struct rtw89_vif_link *rtwvif_link,
3659 struct rtw89_sta_link *rtwsta_link);
3660 int (*h2c_ampdu_cmac_tbl)(struct rtw89_dev *rtwdev,
3661 struct rtw89_vif_link *rtwvif_link,
3662 struct rtw89_sta_link *rtwsta_link);
3663 int (*h2c_default_dmac_tbl)(struct rtw89_dev *rtwdev,
3664 struct rtw89_vif_link *rtwvif_link,
3665 struct rtw89_sta_link *rtwsta_link);
3666 int (*h2c_update_beacon)(struct rtw89_dev *rtwdev,
3667 struct rtw89_vif_link *rtwvif_link);
3668 int (*h2c_ba_cam)(struct rtw89_dev *rtwdev,
3669 struct rtw89_vif_link *rtwvif_link,
3670 struct rtw89_sta_link *rtwsta_link,
3671 bool valid, struct ieee80211_ampdu_params *params);
3672
3673 void (*btc_set_rfe)(struct rtw89_dev *rtwdev);
3674 void (*btc_init_cfg)(struct rtw89_dev *rtwdev);
3675 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state);
3676 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val);
3677 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val);
3678 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev);
3679 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state);
3680 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type);
3681 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level);
3682};
3683
3684enum rtw89_dma_ch {
3685 RTW89_DMA_ACH0 = 0,
3686 RTW89_DMA_ACH1 = 1,
3687 RTW89_DMA_ACH2 = 2,
3688 RTW89_DMA_ACH3 = 3,
3689 RTW89_DMA_ACH4 = 4,
3690 RTW89_DMA_ACH5 = 5,
3691 RTW89_DMA_ACH6 = 6,
3692 RTW89_DMA_ACH7 = 7,
3693 RTW89_DMA_B0MG = 8,
3694 RTW89_DMA_B0HI = 9,
3695 RTW89_DMA_B1MG = 10,
3696 RTW89_DMA_B1HI = 11,
3697 RTW89_DMA_H2C = 12,
3698 RTW89_DMA_CH_NUM = 13
3699};
3700
3701#define MLO_MODE_FOR_BB0_BB1_RF(bb0, bb1, rf) ((rf) << 12 | (bb1) << 4 | (bb0))
3702
3703enum rtw89_mlo_dbcc_mode {
3704 MLO_DBCC_NOT_SUPPORT = 1,
3705 MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1),
3706 MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2),
3707 MLO_1_PLUS_1_1RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 1),
3708 MLO_1_PLUS_1_2RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 2),
3709 MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1),
3710 MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2),
3711 MLO_2_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 2, 2),
3712 DBCC_LEGACY = 0xffffffff,
3713};
3714
3715enum rtw89_scan_be_operation {
3716 RTW89_SCAN_OP_STOP,
3717 RTW89_SCAN_OP_START,
3718 RTW89_SCAN_OP_SETPARM,
3719 RTW89_SCAN_OP_GETRPT,
3720 RTW89_SCAN_OP_NUM
3721};
3722
3723enum rtw89_scan_be_mode {
3724 RTW89_SCAN_MODE_SA,
3725 RTW89_SCAN_MODE_MACC,
3726 RTW89_SCAN_MODE_NUM
3727};
3728
3729enum rtw89_scan_be_opmode {
3730 RTW89_SCAN_OPMODE_NONE,
3731 RTW89_SCAN_OPMODE_TBTT,
3732 RTW89_SCAN_OPMODE_INTV,
3733 RTW89_SCAN_OPMODE_CNT,
3734 RTW89_SCAN_OPMODE_NUM,
3735};
3736
3737struct rtw89_scan_option {
3738 bool enable;
3739 bool target_ch_mode;
3740 u8 num_macc_role;
3741 u8 num_opch;
3742 u8 repeat;
3743 u16 norm_pd;
3744 u16 slow_pd;
3745 u16 norm_cy;
3746 u8 opch_end;
3747 u16 delay;
3748 u64 prohib_chan;
3749 enum rtw89_phy_idx band;
3750 enum rtw89_scan_be_operation operation;
3751 enum rtw89_scan_be_mode scan_mode;
3752 enum rtw89_mlo_dbcc_mode mlo_mode;
3753};
3754
3755enum rtw89_qta_mode {
3756 RTW89_QTA_SCC,
3757 RTW89_QTA_DBCC,
3758 RTW89_QTA_DLFW,
3759 RTW89_QTA_WOW,
3760
3761 /* keep last */
3762 RTW89_QTA_INVALID,
3763};
3764
3765struct rtw89_hfc_ch_cfg {
3766 u16 min;
3767 u16 max;
3768#define grp_0 0
3769#define grp_1 1
3770#define grp_num 2
3771 u8 grp;
3772};
3773
3774struct rtw89_hfc_ch_info {
3775 u16 aval;
3776 u16 used;
3777};
3778
3779struct rtw89_hfc_pub_cfg {
3780 u16 grp0;
3781 u16 grp1;
3782 u16 pub_max;
3783 u16 wp_thrd;
3784};
3785
3786struct rtw89_hfc_pub_info {
3787 u16 g0_used;
3788 u16 g1_used;
3789 u16 g0_aval;
3790 u16 g1_aval;
3791 u16 pub_aval;
3792 u16 wp_aval;
3793};
3794
3795struct rtw89_hfc_prec_cfg {
3796 u16 ch011_prec;
3797 u16 h2c_prec;
3798 u16 wp_ch07_prec;
3799 u16 wp_ch811_prec;
3800 u8 ch011_full_cond;
3801 u8 h2c_full_cond;
3802 u8 wp_ch07_full_cond;
3803 u8 wp_ch811_full_cond;
3804};
3805
3806struct rtw89_hfc_param {
3807 bool en;
3808 bool h2c_en;
3809 u8 mode;
3810 const struct rtw89_hfc_ch_cfg *ch_cfg;
3811 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM];
3812 struct rtw89_hfc_pub_cfg pub_cfg;
3813 struct rtw89_hfc_pub_info pub_info;
3814 struct rtw89_hfc_prec_cfg prec_cfg;
3815};
3816
3817struct rtw89_hfc_param_ini {
3818 const struct rtw89_hfc_ch_cfg *ch_cfg;
3819 const struct rtw89_hfc_pub_cfg *pub_cfg;
3820 const struct rtw89_hfc_prec_cfg *prec_cfg;
3821 u8 mode;
3822};
3823
3824struct rtw89_dle_size {
3825 u16 pge_size;
3826 u16 lnk_pge_num;
3827 u16 unlnk_pge_num;
3828 /* for WiFi 7 chips below */
3829 u32 srt_ofst;
3830};
3831
3832struct rtw89_wde_quota {
3833 u16 hif;
3834 u16 wcpu;
3835 u16 pkt_in;
3836 u16 cpu_io;
3837};
3838
3839struct rtw89_ple_quota {
3840 u16 cma0_tx;
3841 u16 cma1_tx;
3842 u16 c2h;
3843 u16 h2c;
3844 u16 wcpu;
3845 u16 mpdu_proc;
3846 u16 cma0_dma;
3847 u16 cma1_dma;
3848 u16 bb_rpt;
3849 u16 wd_rel;
3850 u16 cpu_io;
3851 u16 tx_rpt;
3852 /* for WiFi 7 chips below */
3853 u16 h2d;
3854};
3855
3856struct rtw89_rsvd_quota {
3857 u16 mpdu_info_tbl;
3858 u16 b0_csi;
3859 u16 b1_csi;
3860 u16 b0_lmr;
3861 u16 b1_lmr;
3862 u16 b0_ftm;
3863 u16 b1_ftm;
3864 u16 b0_smr;
3865 u16 b1_smr;
3866 u16 others;
3867};
3868
3869struct rtw89_dle_rsvd_size {
3870 u32 srt_ofst;
3871 u32 size;
3872};
3873
3874struct rtw89_dle_mem {
3875 enum rtw89_qta_mode mode;
3876 const struct rtw89_dle_size *wde_size;
3877 const struct rtw89_dle_size *ple_size;
3878 const struct rtw89_wde_quota *wde_min_qt;
3879 const struct rtw89_wde_quota *wde_max_qt;
3880 const struct rtw89_ple_quota *ple_min_qt;
3881 const struct rtw89_ple_quota *ple_max_qt;
3882 /* for WiFi 7 chips below */
3883 const struct rtw89_rsvd_quota *rsvd_qt;
3884 const struct rtw89_dle_rsvd_size *rsvd0_size;
3885 const struct rtw89_dle_rsvd_size *rsvd1_size;
3886};
3887
3888struct rtw89_reg_def {
3889 u32 addr;
3890 u32 mask;
3891};
3892
3893struct rtw89_reg2_def {
3894 u32 addr;
3895 u32 data;
3896};
3897
3898struct rtw89_reg3_def {
3899 u32 addr;
3900 u32 mask;
3901 u32 data;
3902};
3903
3904struct rtw89_reg5_def {
3905 u8 flag; /* recognized by parsers */
3906 u8 path;
3907 u32 addr;
3908 u32 mask;
3909 u32 data;
3910};
3911
3912struct rtw89_reg_imr {
3913 u32 addr;
3914 u32 clr;
3915 u32 set;
3916};
3917
3918struct rtw89_phy_table {
3919 const struct rtw89_reg2_def *regs;
3920 u32 n_regs;
3921 enum rtw89_rf_path rf_path;
3922 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg,
3923 enum rtw89_rf_path rf_path, void *data);
3924};
3925
3926struct rtw89_txpwr_table {
3927 const void *data;
3928 u32 size;
3929 void (*load)(struct rtw89_dev *rtwdev,
3930 const struct rtw89_txpwr_table *tbl);
3931};
3932
3933struct rtw89_txpwr_rule_2ghz {
3934 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
3935 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3936 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
3937 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
3938 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
3939};
3940
3941struct rtw89_txpwr_rule_5ghz {
3942 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
3943 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3944 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
3945 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
3946 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
3947};
3948
3949struct rtw89_txpwr_rule_6ghz {
3950 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM]
3951 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3952 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
3953 [RTW89_6G_CH_NUM];
3954 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
3955 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
3956 [RTW89_6G_CH_NUM];
3957};
3958
3959struct rtw89_tx_shape {
3960 const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM];
3961 const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM];
3962};
3963
3964struct rtw89_rfe_parms {
3965 const struct rtw89_txpwr_table *byr_tbl;
3966 struct rtw89_txpwr_rule_2ghz rule_2ghz;
3967 struct rtw89_txpwr_rule_5ghz rule_5ghz;
3968 struct rtw89_txpwr_rule_6ghz rule_6ghz;
3969 struct rtw89_tx_shape tx_shape;
3970};
3971
3972struct rtw89_rfe_parms_conf {
3973 const struct rtw89_rfe_parms *rfe_parms;
3974 u8 rfe_type;
3975};
3976
3977#define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0
3978
3979struct rtw89_txpwr_conf {
3980 u8 rfe_type;
3981 u8 ent_sz;
3982 u32 num_ents;
3983 const void *data;
3984};
3985
3986static inline bool rtw89_txpwr_entcpy(void *entry, const void *cursor, u8 size,
3987 const struct rtw89_txpwr_conf *conf)
3988{
3989 u8 valid_size = min(size, conf->ent_sz);
3990
3991 memcpy(entry, cursor, valid_size);
3992 return true;
3993}
3994
3995#define rtw89_txpwr_conf_valid(conf) (!!(conf)->data)
3996
3997#define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \
3998 for (typecheck(const void *, cursor), (cursor) = (conf)->data; \
3999 (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \
4000 (cursor) += (conf)->ent_sz) \
4001 if (rtw89_txpwr_entcpy(&(entry), cursor, sizeof(entry), conf))
4002
4003struct rtw89_txpwr_byrate_data {
4004 struct rtw89_txpwr_conf conf;
4005 struct rtw89_txpwr_table tbl;
4006};
4007
4008struct rtw89_txpwr_lmt_2ghz_data {
4009 struct rtw89_txpwr_conf conf;
4010 s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
4011 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
4012 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
4013};
4014
4015struct rtw89_txpwr_lmt_5ghz_data {
4016 struct rtw89_txpwr_conf conf;
4017 s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
4018 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
4019 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
4020};
4021
4022struct rtw89_txpwr_lmt_6ghz_data {
4023 struct rtw89_txpwr_conf conf;
4024 s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM]
4025 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
4026 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
4027 [RTW89_6G_CH_NUM];
4028};
4029
4030struct rtw89_txpwr_lmt_ru_2ghz_data {
4031 struct rtw89_txpwr_conf conf;
4032 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
4033 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
4034};
4035
4036struct rtw89_txpwr_lmt_ru_5ghz_data {
4037 struct rtw89_txpwr_conf conf;
4038 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
4039 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
4040};
4041
4042struct rtw89_txpwr_lmt_ru_6ghz_data {
4043 struct rtw89_txpwr_conf conf;
4044 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
4045 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
4046 [RTW89_6G_CH_NUM];
4047};
4048
4049struct rtw89_tx_shape_lmt_data {
4050 struct rtw89_txpwr_conf conf;
4051 u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM];
4052};
4053
4054struct rtw89_tx_shape_lmt_ru_data {
4055 struct rtw89_txpwr_conf conf;
4056 u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM];
4057};
4058
4059struct rtw89_rfe_data {
4060 struct rtw89_txpwr_byrate_data byrate;
4061 struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz;
4062 struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz;
4063 struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz;
4064 struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz;
4065 struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz;
4066 struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz;
4067 struct rtw89_tx_shape_lmt_data tx_shape_lmt;
4068 struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru;
4069 struct rtw89_rfe_parms rfe_parms;
4070};
4071
4072struct rtw89_page_regs {
4073 u32 hci_fc_ctrl;
4074 u32 ch_page_ctrl;
4075 u32 ach_page_ctrl;
4076 u32 ach_page_info;
4077 u32 pub_page_info3;
4078 u32 pub_page_ctrl1;
4079 u32 pub_page_ctrl2;
4080 u32 pub_page_info1;
4081 u32 pub_page_info2;
4082 u32 wp_page_ctrl1;
4083 u32 wp_page_ctrl2;
4084 u32 wp_page_info1;
4085};
4086
4087struct rtw89_imr_info {
4088 u32 wdrls_imr_set;
4089 u32 wsec_imr_reg;
4090 u32 wsec_imr_set;
4091 u32 mpdu_tx_imr_set;
4092 u32 mpdu_rx_imr_set;
4093 u32 sta_sch_imr_set;
4094 u32 txpktctl_imr_b0_reg;
4095 u32 txpktctl_imr_b0_clr;
4096 u32 txpktctl_imr_b0_set;
4097 u32 txpktctl_imr_b1_reg;
4098 u32 txpktctl_imr_b1_clr;
4099 u32 txpktctl_imr_b1_set;
4100 u32 wde_imr_clr;
4101 u32 wde_imr_set;
4102 u32 ple_imr_clr;
4103 u32 ple_imr_set;
4104 u32 host_disp_imr_clr;
4105 u32 host_disp_imr_set;
4106 u32 cpu_disp_imr_clr;
4107 u32 cpu_disp_imr_set;
4108 u32 other_disp_imr_clr;
4109 u32 other_disp_imr_set;
4110 u32 bbrpt_com_err_imr_reg;
4111 u32 bbrpt_chinfo_err_imr_reg;
4112 u32 bbrpt_err_imr_set;
4113 u32 bbrpt_dfs_err_imr_reg;
4114 u32 ptcl_imr_clr;
4115 u32 ptcl_imr_set;
4116 u32 cdma_imr_0_reg;
4117 u32 cdma_imr_0_clr;
4118 u32 cdma_imr_0_set;
4119 u32 cdma_imr_1_reg;
4120 u32 cdma_imr_1_clr;
4121 u32 cdma_imr_1_set;
4122 u32 phy_intf_imr_reg;
4123 u32 phy_intf_imr_clr;
4124 u32 phy_intf_imr_set;
4125 u32 rmac_imr_reg;
4126 u32 rmac_imr_clr;
4127 u32 rmac_imr_set;
4128 u32 tmac_imr_reg;
4129 u32 tmac_imr_clr;
4130 u32 tmac_imr_set;
4131};
4132
4133struct rtw89_imr_table {
4134 const struct rtw89_reg_imr *regs;
4135 u32 n_regs;
4136};
4137
4138struct rtw89_xtal_info {
4139 u32 xcap_reg;
4140 u32 sc_xo_mask;
4141 u32 sc_xi_mask;
4142};
4143
4144struct rtw89_rrsr_cfgs {
4145 struct rtw89_reg3_def ref_rate;
4146 struct rtw89_reg3_def rsc;
4147};
4148
4149struct rtw89_rfkill_regs {
4150 struct rtw89_reg3_def pinmux;
4151 struct rtw89_reg3_def mode;
4152};
4153
4154struct rtw89_dig_regs {
4155 u32 seg0_pd_reg;
4156 u32 pd_lower_bound_mask;
4157 u32 pd_spatial_reuse_en;
4158 u32 bmode_pd_reg;
4159 u32 bmode_cca_rssi_limit_en;
4160 u32 bmode_pd_lower_bound_reg;
4161 u32 bmode_rssi_nocca_low_th_mask;
4162 struct rtw89_reg_def p0_lna_init;
4163 struct rtw89_reg_def p1_lna_init;
4164 struct rtw89_reg_def p0_tia_init;
4165 struct rtw89_reg_def p1_tia_init;
4166 struct rtw89_reg_def p0_rxb_init;
4167 struct rtw89_reg_def p1_rxb_init;
4168 struct rtw89_reg_def p0_p20_pagcugc_en;
4169 struct rtw89_reg_def p0_s20_pagcugc_en;
4170 struct rtw89_reg_def p1_p20_pagcugc_en;
4171 struct rtw89_reg_def p1_s20_pagcugc_en;
4172};
4173
4174struct rtw89_edcca_regs {
4175 u32 edcca_level;
4176 u32 edcca_mask;
4177 u32 edcca_p_mask;
4178 u32 ppdu_level;
4179 u32 ppdu_mask;
4180 u32 rpt_a;
4181 u32 rpt_b;
4182 u32 rpt_sel;
4183 u32 rpt_sel_mask;
4184 u32 rpt_sel_be;
4185 u32 rpt_sel_be_mask;
4186 u32 tx_collision_t2r_st;
4187 u32 tx_collision_t2r_st_mask;
4188};
4189
4190struct rtw89_phy_ul_tb_info {
4191 bool dyn_tb_tri_en;
4192 u8 def_if_bandedge;
4193};
4194
4195struct rtw89_antdiv_stats {
4196 struct ewma_rssi cck_rssi_avg;
4197 struct ewma_rssi ofdm_rssi_avg;
4198 struct ewma_rssi non_legacy_rssi_avg;
4199 u16 pkt_cnt_cck;
4200 u16 pkt_cnt_ofdm;
4201 u16 pkt_cnt_non_legacy;
4202 u32 evm;
4203};
4204
4205struct rtw89_antdiv_info {
4206 struct rtw89_antdiv_stats target_stats;
4207 struct rtw89_antdiv_stats main_stats;
4208 struct rtw89_antdiv_stats aux_stats;
4209 u8 training_count;
4210 u8 rssi_pre;
4211 bool get_stats;
4212};
4213
4214enum rtw89_chanctx_state {
4215 RTW89_CHANCTX_STATE_MCC_START,
4216 RTW89_CHANCTX_STATE_MCC_STOP,
4217};
4218
4219enum rtw89_chanctx_callbacks {
4220 RTW89_CHANCTX_CALLBACK_PLACEHOLDER,
4221 RTW89_CHANCTX_CALLBACK_RFK,
4222
4223 NUM_OF_RTW89_CHANCTX_CALLBACKS,
4224};
4225
4226struct rtw89_chanctx_listener {
4227 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS])
4228 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state);
4229};
4230
4231struct rtw89_chip_info {
4232 enum rtw89_core_chip_id chip_id;
4233 enum rtw89_chip_gen chip_gen;
4234 const struct rtw89_chip_ops *ops;
4235 const struct rtw89_mac_gen_def *mac_def;
4236 const struct rtw89_phy_gen_def *phy_def;
4237 const char *fw_basename;
4238 u8 fw_format_max;
4239 bool try_ce_fw;
4240 u8 bbmcu_nr;
4241 u32 needed_fw_elms;
4242 u32 fifo_size;
4243 bool small_fifo_size;
4244 u32 dle_scc_rsvd_size;
4245 u16 max_amsdu_limit;
4246 bool dis_2g_40m_ul_ofdma;
4247 u32 rsvd_ple_ofst;
4248 const struct rtw89_hfc_param_ini *hfc_param_ini;
4249 const struct rtw89_dle_mem *dle_mem;
4250 u8 wde_qempty_acq_grpnum;
4251 u8 wde_qempty_mgq_grpsel;
4252 u32 rf_base_addr[2];
4253 u8 thermal_th[2];
4254 u8 support_macid_num;
4255 u8 support_link_num;
4256 u8 support_chanctx_num;
4257 u8 support_bands;
4258 u16 support_bandwidths;
4259 bool support_unii4;
4260 bool support_rnr;
4261 bool ul_tb_waveform_ctrl;
4262 bool ul_tb_pwr_diff;
4263 bool hw_sec_hdr;
4264 bool hw_mgmt_tx_encrypt;
4265 u8 rf_path_num;
4266 u8 tx_nss;
4267 u8 rx_nss;
4268 u8 acam_num;
4269 u8 bcam_num;
4270 u8 scam_num;
4271 u8 bacam_num;
4272 u8 bacam_dynamic_num;
4273 enum rtw89_bacam_ver bacam_ver;
4274 u8 ppdu_max_usr;
4275
4276 u8 sec_ctrl_efuse_size;
4277 u32 physical_efuse_size;
4278 u32 logical_efuse_size;
4279 u32 limit_efuse_size;
4280 u32 dav_phy_efuse_size;
4281 u32 dav_log_efuse_size;
4282 u32 phycap_addr;
4283 u32 phycap_size;
4284 const struct rtw89_efuse_block_cfg *efuse_blocks;
4285
4286 const struct rtw89_pwr_cfg * const *pwr_on_seq;
4287 const struct rtw89_pwr_cfg * const *pwr_off_seq;
4288 const struct rtw89_phy_table *bb_table;
4289 const struct rtw89_phy_table *bb_gain_table;
4290 const struct rtw89_phy_table *rf_table[RF_PATH_MAX];
4291 const struct rtw89_phy_table *nctl_table;
4292 const struct rtw89_rfk_tbl *nctl_post_table;
4293 const struct rtw89_phy_dig_gain_table *dig_table;
4294 const struct rtw89_dig_regs *dig_regs;
4295 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table;
4296
4297 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */
4298 const struct rtw89_rfe_parms_conf *rfe_parms_conf;
4299 const struct rtw89_rfe_parms *dflt_parms;
4300 const struct rtw89_chanctx_listener *chanctx_listener;
4301
4302 u8 txpwr_factor_rf;
4303 u8 txpwr_factor_mac;
4304
4305 u32 para_ver;
4306 u32 wlcx_desired;
4307 u8 btcx_desired;
4308 u8 scbd;
4309 u8 mailbox;
4310
4311 u8 afh_guard_ch;
4312 const u8 *wl_rssi_thres;
4313 const u8 *bt_rssi_thres;
4314 u8 rssi_tol;
4315
4316 u8 mon_reg_num;
4317 const struct rtw89_btc_fbtc_mreg *mon_reg;
4318 u8 rf_para_ulink_num;
4319 const struct rtw89_btc_rf_trx_para *rf_para_ulink;
4320 u8 rf_para_dlink_num;
4321 const struct rtw89_btc_rf_trx_para *rf_para_dlink;
4322 u8 ps_mode_supported;
4323 u8 low_power_hci_modes;
4324
4325 u32 h2c_cctl_func_id;
4326 u32 hci_func_en_addr;
4327 u32 h2c_desc_size;
4328 u32 txwd_body_size;
4329 u32 txwd_info_size;
4330 u32 h2c_ctrl_reg;
4331 const u32 *h2c_regs;
4332 struct rtw89_reg_def h2c_counter_reg;
4333 u32 c2h_ctrl_reg;
4334 const u32 *c2h_regs;
4335 struct rtw89_reg_def c2h_counter_reg;
4336 const struct rtw89_page_regs *page_regs;
4337 const u32 *wow_reason_reg;
4338 bool cfo_src_fd;
4339 bool cfo_hw_comp;
4340 const struct rtw89_reg_def *dcfo_comp;
4341 u8 dcfo_comp_sft;
4342 const struct rtw89_imr_info *imr_info;
4343 const struct rtw89_imr_table *imr_dmac_table;
4344 const struct rtw89_imr_table *imr_cmac_table;
4345 const struct rtw89_rrsr_cfgs *rrsr_cfgs;
4346 struct rtw89_reg_def bss_clr_vld;
4347 u32 bss_clr_map_reg;
4348 const struct rtw89_rfkill_regs *rfkill_init;
4349 struct rtw89_reg_def rfkill_get;
4350 u32 dma_ch_mask;
4351 const struct rtw89_edcca_regs *edcca_regs;
4352 const struct wiphy_wowlan_support *wowlan_stub;
4353 const struct rtw89_xtal_info *xtal_info;
4354};
4355
4356union rtw89_bus_info {
4357 const struct rtw89_pci_info *pci;
4358};
4359
4360struct rtw89_driver_info {
4361 const struct rtw89_chip_info *chip;
4362 const struct dmi_system_id *quirks;
4363 union rtw89_bus_info bus;
4364};
4365
4366enum rtw89_hcifc_mode {
4367 RTW89_HCIFC_POH = 0,
4368 RTW89_HCIFC_STF = 1,
4369 RTW89_HCIFC_SDIO = 2,
4370
4371 /* keep last */
4372 RTW89_HCIFC_MODE_INVALID,
4373};
4374
4375struct rtw89_dle_info {
4376 const struct rtw89_rsvd_quota *rsvd_qt;
4377 enum rtw89_qta_mode qta_mode;
4378 u16 ple_pg_size;
4379 u16 ple_free_pg;
4380 u16 c0_rx_qta;
4381 u16 c1_rx_qta;
4382};
4383
4384enum rtw89_host_rpr_mode {
4385 RTW89_RPR_MODE_POH = 0,
4386 RTW89_RPR_MODE_STF
4387};
4388
4389#define RTW89_COMPLETION_BUF_SIZE 40
4390#define RTW89_WAIT_COND_IDLE UINT_MAX
4391
4392struct rtw89_completion_data {
4393 bool err;
4394 u8 buf[RTW89_COMPLETION_BUF_SIZE];
4395};
4396
4397struct rtw89_wait_info {
4398 atomic_t cond;
4399 struct completion completion;
4400 struct rtw89_completion_data data;
4401};
4402
4403#define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100)
4404
4405static inline void rtw89_init_wait(struct rtw89_wait_info *wait)
4406{
4407 init_completion(&wait->completion);
4408 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE);
4409}
4410
4411struct rtw89_mac_info {
4412 struct rtw89_dle_info dle_info;
4413 struct rtw89_hfc_param hfc_param;
4414 enum rtw89_qta_mode qta_mode;
4415 u8 rpwm_seq_num;
4416 u8 cpwm_seq_num;
4417
4418 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */
4419 struct rtw89_wait_info fw_ofld_wait;
4420 /* see RTW89_PS_WAIT_COND series for wait condition */
4421 struct rtw89_wait_info ps_wait;
4422};
4423
4424enum rtw89_fwdl_check_type {
4425 RTW89_FWDL_CHECK_FREERTOS_DONE,
4426 RTW89_FWDL_CHECK_WCPU_FWDL_DONE,
4427 RTW89_FWDL_CHECK_DCPU_FWDL_DONE,
4428 RTW89_FWDL_CHECK_BB0_FWDL_DONE,
4429 RTW89_FWDL_CHECK_BB1_FWDL_DONE,
4430};
4431
4432enum rtw89_fw_type {
4433 RTW89_FW_NORMAL = 1,
4434 RTW89_FW_WOWLAN = 3,
4435 RTW89_FW_NORMAL_CE = 5,
4436 RTW89_FW_BBMCU0 = 64,
4437 RTW89_FW_BBMCU1 = 65,
4438 RTW89_FW_LOGFMT = 255,
4439};
4440
4441enum rtw89_fw_feature {
4442 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT,
4443 RTW89_FW_FEATURE_SCAN_OFFLOAD,
4444 RTW89_FW_FEATURE_TX_WAKE,
4445 RTW89_FW_FEATURE_CRASH_TRIGGER,
4446 RTW89_FW_FEATURE_NO_PACKET_DROP,
4447 RTW89_FW_FEATURE_NO_DEEP_PS,
4448 RTW89_FW_FEATURE_NO_LPS_PG,
4449 RTW89_FW_FEATURE_BEACON_FILTER,
4450 RTW89_FW_FEATURE_MACID_PAUSE_SLEEP,
4451 RTW89_FW_FEATURE_SCAN_OFFLOAD_BE_V0,
4452 RTW89_FW_FEATURE_WOW_REASON_V1,
4453 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V0,
4454 RTW89_FW_FEATURE_RFK_RXDCK_V0,
4455 RTW89_FW_FEATURE_NO_WOW_CPU_IO_RX,
4456};
4457
4458struct rtw89_fw_suit {
4459 enum rtw89_fw_type type;
4460 const u8 *data;
4461 u32 size;
4462 u8 major_ver;
4463 u8 minor_ver;
4464 u8 sub_ver;
4465 u8 sub_idex;
4466 u16 build_year;
4467 u16 build_mon;
4468 u16 build_date;
4469 u16 build_hour;
4470 u16 build_min;
4471 u8 cmd_ver;
4472 u8 hdr_ver;
4473 u32 commitid;
4474};
4475
4476#define RTW89_FW_VER_CODE(major, minor, sub, idx) \
4477 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx))
4478#define RTW89_FW_SUIT_VER_CODE(s) \
4479 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex)
4480
4481#define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \
4482 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \
4483 (mfw_hdr)->ver.minor, \
4484 (mfw_hdr)->ver.sub, \
4485 (mfw_hdr)->ver.idx)
4486
4487#define RTW89_FW_HDR_VER_CODE(fw_hdr) \
4488 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \
4489 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \
4490 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \
4491 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX))
4492
4493struct rtw89_fw_req_info {
4494 const struct firmware *firmware;
4495 struct completion completion;
4496};
4497
4498struct rtw89_fw_log {
4499 struct rtw89_fw_suit suit;
4500 bool enable;
4501 u32 last_fmt_id;
4502 u32 fmt_count;
4503 const __le32 *fmt_ids;
4504 const char *(*fmts)[];
4505};
4506
4507struct rtw89_fw_elm_info {
4508 struct rtw89_phy_table *bb_tbl;
4509 struct rtw89_phy_table *bb_gain;
4510 struct rtw89_phy_table *rf_radio[RF_PATH_MAX];
4511 struct rtw89_phy_table *rf_nctl;
4512 struct rtw89_fw_txpwr_track_cfg *txpwr_trk;
4513 struct rtw89_phy_rfk_log_fmt *rfk_log_fmt;
4514};
4515
4516enum rtw89_fw_mss_dev_type {
4517 RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF = 0xF,
4518 RTW89_FW_MSS_DEV_TYPE_FWSEC_INV = 0xFF,
4519};
4520
4521struct rtw89_fw_secure {
4522 bool secure_boot: 1;
4523 bool can_mss_v1: 1;
4524 bool can_mss_v0: 1;
4525 u32 sb_sel_mgn;
4526 u8 mss_dev_type;
4527 u8 mss_cust_idx;
4528 u8 mss_key_num;
4529 u8 mss_idx; /* v0 */
4530};
4531
4532struct rtw89_fw_info {
4533 struct rtw89_fw_req_info req;
4534 int fw_format;
4535 u8 h2c_seq;
4536 u8 rec_seq;
4537 u8 h2c_counter;
4538 u8 c2h_counter;
4539 struct rtw89_fw_suit normal;
4540 struct rtw89_fw_suit wowlan;
4541 struct rtw89_fw_suit bbmcu0;
4542 struct rtw89_fw_suit bbmcu1;
4543 struct rtw89_fw_log log;
4544 u32 feature_map;
4545 struct rtw89_fw_elm_info elm_info;
4546 struct rtw89_fw_secure sec;
4547};
4548
4549#define RTW89_CHK_FW_FEATURE(_feat, _fw) \
4550 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat)))
4551
4552#define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \
4553 ((_fw)->feature_map |= BIT(_fw_feature))
4554
4555struct rtw89_cam_info {
4556 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM);
4557 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM);
4558 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM);
4559 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM);
4560 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM];
4561 const struct rtw89_sec_cam_entry *sec_entries[RTW89_MAX_SEC_CAM_NUM];
4562};
4563
4564enum rtw89_sar_sources {
4565 RTW89_SAR_SOURCE_NONE,
4566 RTW89_SAR_SOURCE_COMMON,
4567
4568 RTW89_SAR_SOURCE_NR,
4569};
4570
4571enum rtw89_sar_subband {
4572 RTW89_SAR_2GHZ_SUBBAND,
4573 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */
4574 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */
4575 RTW89_SAR_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */
4576 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */
4577 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */
4578 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */
4579 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */
4580 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */
4581 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */
4582
4583 RTW89_SAR_SUBBAND_NR,
4584};
4585
4586struct rtw89_sar_cfg_common {
4587 bool set[RTW89_SAR_SUBBAND_NR];
4588 s32 cfg[RTW89_SAR_SUBBAND_NR];
4589};
4590
4591struct rtw89_sar_info {
4592 /* used to decide how to acces SAR cfg union */
4593 enum rtw89_sar_sources src;
4594
4595 /* reserved for different knids of SAR cfg struct.
4596 * supposed that a single cfg struct cannot handle various SAR sources.
4597 */
4598 union {
4599 struct rtw89_sar_cfg_common cfg_common;
4600 };
4601};
4602
4603enum rtw89_tas_state {
4604 RTW89_TAS_STATE_DPR_OFF,
4605 RTW89_TAS_STATE_DPR_ON,
4606 RTW89_TAS_STATE_DPR_FORBID,
4607};
4608
4609#define RTW89_TAS_MAX_WINDOW 50
4610struct rtw89_tas_info {
4611 s16 txpwr_history[RTW89_TAS_MAX_WINDOW];
4612 s32 total_txpwr;
4613 u8 cur_idx;
4614 s8 dpr_gap;
4615 s8 delta;
4616 enum rtw89_tas_state state;
4617 bool enable;
4618};
4619
4620struct rtw89_chanctx_cfg {
4621 enum rtw89_chanctx_idx idx;
4622 int ref_count;
4623};
4624
4625enum rtw89_chanctx_changes {
4626 RTW89_CHANCTX_REMOTE_STA_CHANGE,
4627 RTW89_CHANCTX_BCN_OFFSET_CHANGE,
4628 RTW89_CHANCTX_P2P_PS_CHANGE,
4629 RTW89_CHANCTX_BT_SLOT_CHANGE,
4630 RTW89_CHANCTX_TSF32_TOGGLE_CHANGE,
4631
4632 NUM_OF_RTW89_CHANCTX_CHANGES,
4633 RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES,
4634};
4635
4636enum rtw89_entity_mode {
4637 RTW89_ENTITY_MODE_SCC_OR_SMLD,
4638 RTW89_ENTITY_MODE_MCC_PREPARE,
4639 RTW89_ENTITY_MODE_MCC,
4640
4641 NUM_OF_RTW89_ENTITY_MODE,
4642 RTW89_ENTITY_MODE_INVALID = -EINVAL,
4643 RTW89_ENTITY_MODE_UNHANDLED = -ESRCH,
4644};
4645
4646#define RTW89_MAX_INTERFACE_NUM 2
4647
4648/* only valid when running with chanctx_ops */
4649struct rtw89_entity_mgnt {
4650 struct list_head active_list;
4651 struct rtw89_vif *active_roles[RTW89_MAX_INTERFACE_NUM];
4652 enum rtw89_chanctx_idx chanctx_tbl[RTW89_MAX_INTERFACE_NUM]
4653 [__RTW89_MLD_MAX_LINK_NUM];
4654};
4655
4656struct rtw89_chanctx {
4657 struct cfg80211_chan_def chandef;
4658 struct rtw89_chan chan;
4659 struct rtw89_chan_rcd rcd;
4660
4661 /* only assigned when running with chanctx_ops */
4662 struct rtw89_chanctx_cfg *cfg;
4663};
4664
4665struct rtw89_edcca_bak {
4666 u8 a;
4667 u8 p;
4668 u8 ppdu;
4669 u8 th_old;
4670};
4671
4672enum rtw89_dm_type {
4673 RTW89_DM_DYNAMIC_EDCCA,
4674 RTW89_DM_THERMAL_PROTECT,
4675};
4676
4677#define RTW89_THERMAL_PROT_LV_MAX 5
4678#define RTW89_THERMAL_PROT_STEP 19 /* -19% for each level */
4679
4680struct rtw89_hal {
4681 u32 rx_fltr;
4682 u8 cv;
4683 u8 acv;
4684 u32 antenna_tx;
4685 u32 antenna_rx;
4686 u8 tx_nss;
4687 u8 rx_nss;
4688 bool tx_path_diversity;
4689 bool ant_diversity;
4690 bool ant_diversity_fixed;
4691 bool support_cckpd;
4692 bool support_igi;
4693 atomic_t roc_chanctx_idx;
4694
4695 DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES);
4696 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_CHANCTX);
4697 struct rtw89_chanctx chanctx[NUM_OF_RTW89_CHANCTX];
4698 struct cfg80211_chan_def roc_chandef;
4699
4700 bool entity_active[RTW89_PHY_MAX];
4701 bool entity_pause;
4702 enum rtw89_entity_mode entity_mode;
4703 struct rtw89_entity_mgnt entity_mgnt;
4704
4705 struct rtw89_edcca_bak edcca_bak;
4706 u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */
4707
4708 u8 thermal_prot_th;
4709 u8 thermal_prot_lv; /* 0 ~ RTW89_THERMAL_PROT_LV_MAX */
4710};
4711
4712#define RTW89_MAX_MAC_ID_NUM 128
4713#define RTW89_MAX_PKT_OFLD_NUM 255
4714
4715enum rtw89_flags {
4716 RTW89_FLAG_POWERON,
4717 RTW89_FLAG_DMAC_FUNC,
4718 RTW89_FLAG_CMAC0_FUNC,
4719 RTW89_FLAG_CMAC1_FUNC,
4720 RTW89_FLAG_FW_RDY,
4721 RTW89_FLAG_RUNNING,
4722 RTW89_FLAG_PROBE_DONE,
4723 RTW89_FLAG_BFEE_MON,
4724 RTW89_FLAG_BFEE_EN,
4725 RTW89_FLAG_BFEE_TIMER_KEEP,
4726 RTW89_FLAG_NAPI_RUNNING,
4727 RTW89_FLAG_LEISURE_PS,
4728 RTW89_FLAG_LOW_POWER_MODE,
4729 RTW89_FLAG_INACTIVE_PS,
4730 RTW89_FLAG_CRASH_SIMULATING,
4731 RTW89_FLAG_SER_HANDLING,
4732 RTW89_FLAG_WOWLAN,
4733 RTW89_FLAG_FORBIDDEN_TRACK_WROK,
4734 RTW89_FLAG_CHANGING_INTERFACE,
4735 RTW89_FLAG_HW_RFKILL_STATE,
4736
4737 NUM_OF_RTW89_FLAGS,
4738};
4739
4740enum rtw89_quirks {
4741 RTW89_QUIRK_PCI_BER,
4742 RTW89_QUIRK_THERMAL_PROT_120C,
4743 RTW89_QUIRK_THERMAL_PROT_110C,
4744
4745 NUM_OF_RTW89_QUIRKS,
4746};
4747
4748enum rtw89_custid {
4749 RTW89_CUSTID_NONE,
4750 RTW89_CUSTID_ACER,
4751 RTW89_CUSTID_AMD,
4752 RTW89_CUSTID_ASUS,
4753 RTW89_CUSTID_DELL,
4754 RTW89_CUSTID_HP,
4755 RTW89_CUSTID_LENOVO,
4756};
4757
4758enum rtw89_pkt_drop_sel {
4759 RTW89_PKT_DROP_SEL_MACID_BE_ONCE,
4760 RTW89_PKT_DROP_SEL_MACID_BK_ONCE,
4761 RTW89_PKT_DROP_SEL_MACID_VI_ONCE,
4762 RTW89_PKT_DROP_SEL_MACID_VO_ONCE,
4763 RTW89_PKT_DROP_SEL_MACID_ALL,
4764 RTW89_PKT_DROP_SEL_MG0_ONCE,
4765 RTW89_PKT_DROP_SEL_HIQ_ONCE,
4766 RTW89_PKT_DROP_SEL_HIQ_PORT,
4767 RTW89_PKT_DROP_SEL_HIQ_MBSSID,
4768 RTW89_PKT_DROP_SEL_BAND,
4769 RTW89_PKT_DROP_SEL_BAND_ONCE,
4770 RTW89_PKT_DROP_SEL_REL_MACID,
4771 RTW89_PKT_DROP_SEL_REL_HIQ_PORT,
4772 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID,
4773};
4774
4775struct rtw89_pkt_drop_params {
4776 enum rtw89_pkt_drop_sel sel;
4777 enum rtw89_mac_idx mac_band;
4778 u8 macid;
4779 u8 port;
4780 u8 mbssid;
4781 bool tf_trs;
4782 u32 macid_band_sel[4];
4783};
4784
4785struct rtw89_pkt_stat {
4786 u16 beacon_nr;
4787 u32 rx_rate_cnt[RTW89_HW_RATE_NR];
4788};
4789
4790DECLARE_EWMA(thermal, 4, 4);
4791
4792struct rtw89_phy_stat {
4793 struct ewma_thermal avg_thermal[RF_PATH_MAX];
4794 u8 last_thermal_max;
4795 struct ewma_rssi bcn_rssi;
4796 struct rtw89_pkt_stat cur_pkt_stat;
4797 struct rtw89_pkt_stat last_pkt_stat;
4798};
4799
4800enum rtw89_rfk_report_state {
4801 RTW89_RFK_STATE_START = 0x0,
4802 RTW89_RFK_STATE_OK = 0x1,
4803 RTW89_RFK_STATE_FAIL = 0x2,
4804 RTW89_RFK_STATE_TIMEOUT = 0x3,
4805 RTW89_RFK_STATE_H2C_CMD_ERR = 0x4,
4806};
4807
4808struct rtw89_rfk_wait_info {
4809 struct completion completion;
4810 ktime_t start_time;
4811 enum rtw89_rfk_report_state state;
4812 u8 version;
4813};
4814
4815#define RTW89_DACK_PATH_NR 2
4816#define RTW89_DACK_IDX_NR 2
4817#define RTW89_DACK_MSBK_NR 16
4818struct rtw89_dack_info {
4819 bool dack_done;
4820 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR];
4821 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
4822 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
4823 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
4824 u32 dack_cnt;
4825 bool addck_timeout[RTW89_DACK_PATH_NR];
4826 bool dadck_timeout[RTW89_DACK_PATH_NR];
4827 bool msbk_timeout[RTW89_DACK_PATH_NR];
4828};
4829
4830enum rtw89_rfk_chs_nrs {
4831 __RTW89_RFK_CHS_NR_V0 = 2,
4832 __RTW89_RFK_CHS_NR_V1 = 3,
4833
4834 RTW89_RFK_CHS_NR = __RTW89_RFK_CHS_NR_V1,
4835};
4836
4837struct rtw89_rfk_mcc_info_data {
4838 u8 ch[RTW89_RFK_CHS_NR];
4839 u8 band[RTW89_RFK_CHS_NR];
4840 u8 bw[RTW89_RFK_CHS_NR];
4841 u8 table_idx;
4842};
4843
4844struct rtw89_rfk_mcc_info {
4845 struct rtw89_rfk_mcc_info_data data[2];
4846};
4847
4848#define RTW89_IQK_CHS_NR 2
4849#define RTW89_IQK_PATH_NR 4
4850
4851struct rtw89_lck_info {
4852 u8 thermal[RF_PATH_MAX];
4853};
4854
4855struct rtw89_rx_dck_info {
4856 u8 thermal[RF_PATH_MAX];
4857};
4858
4859struct rtw89_iqk_info {
4860 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4861 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4862 bool lok_fail[RTW89_IQK_PATH_NR];
4863 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4864 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4865 u32 iqk_fail_cnt;
4866 bool is_iqk_init;
4867 u32 iqk_channel[RTW89_IQK_CHS_NR];
4868 u8 iqk_band[RTW89_IQK_PATH_NR];
4869 u8 iqk_ch[RTW89_IQK_PATH_NR];
4870 u8 iqk_bw[RTW89_IQK_PATH_NR];
4871 u8 iqk_times;
4872 u8 version;
4873 u32 nb_txcfir[RTW89_IQK_PATH_NR];
4874 u32 nb_rxcfir[RTW89_IQK_PATH_NR];
4875 u32 bp_txkresult[RTW89_IQK_PATH_NR];
4876 u32 bp_rxkresult[RTW89_IQK_PATH_NR];
4877 u32 bp_iqkenable[RTW89_IQK_PATH_NR];
4878 bool is_wb_txiqk[RTW89_IQK_PATH_NR];
4879 bool is_wb_rxiqk[RTW89_IQK_PATH_NR];
4880 bool is_nbiqk;
4881 bool iqk_fft_en;
4882 bool iqk_xym_en;
4883 bool iqk_sram_en;
4884 bool iqk_cfir_en;
4885 u32 syn1to2;
4886 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4887 u8 iqk_table_idx[RTW89_IQK_PATH_NR];
4888 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4889 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4890};
4891
4892#define RTW89_DPK_RF_PATH 2
4893#define RTW89_DPK_AVG_THERMAL_NUM 8
4894#define RTW89_DPK_BKUP_NUM 2
4895struct rtw89_dpk_bkup_para {
4896 enum rtw89_band band;
4897 enum rtw89_bandwidth bw;
4898 u8 ch;
4899 bool path_ok;
4900 u8 mdpd_en;
4901 u8 txagc_dpk;
4902 u8 ther_dpk;
4903 u8 gs;
4904 u16 pwsf;
4905};
4906
4907struct rtw89_dpk_info {
4908 bool is_dpk_enable;
4909 bool is_dpk_reload_en;
4910 u8 dpk_gs[RTW89_PHY_MAX];
4911 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
4912 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
4913 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
4914 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
4915 u8 cur_idx[RTW89_DPK_RF_PATH];
4916 u8 cur_k_set;
4917 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
4918 u8 max_dpk_txagc[RTW89_DPK_RF_PATH];
4919 u32 dpk_order[RTW89_DPK_RF_PATH];
4920};
4921
4922struct rtw89_fem_info {
4923 bool elna_2g;
4924 bool elna_5g;
4925 bool epa_2g;
4926 bool epa_5g;
4927 bool epa_6g;
4928};
4929
4930struct rtw89_phy_ch_info {
4931 u8 rssi_min;
4932 u16 rssi_min_macid;
4933 u8 pre_rssi_min;
4934 u8 rssi_max;
4935 u16 rssi_max_macid;
4936 u8 rxsc_160;
4937 u8 rxsc_80;
4938 u8 rxsc_40;
4939 u8 rxsc_20;
4940 u8 rxsc_l;
4941 u8 is_noisy;
4942};
4943
4944struct rtw89_agc_gaincode_set {
4945 u8 lna_idx;
4946 u8 tia_idx;
4947 u8 rxb_idx;
4948};
4949
4950#define IGI_RSSI_TH_NUM 5
4951#define FA_TH_NUM 4
4952#define TIA_LNA_OP1DB_NUM 8
4953#define LNA_GAIN_NUM 7
4954#define TIA_GAIN_NUM 2
4955struct rtw89_dig_info {
4956 struct rtw89_agc_gaincode_set cur_gaincode;
4957 bool force_gaincode_idx_en;
4958 struct rtw89_agc_gaincode_set force_gaincode;
4959 u8 igi_rssi_th[IGI_RSSI_TH_NUM];
4960 u16 fa_th[FA_TH_NUM];
4961 u8 igi_rssi;
4962 u8 igi_fa_rssi;
4963 u8 fa_rssi_ofst;
4964 u8 dyn_igi_max;
4965 u8 dyn_igi_min;
4966 bool dyn_pd_th_en;
4967 u8 dyn_pd_th_max;
4968 u8 pd_low_th_ofst;
4969 u8 ib_pbk;
4970 s8 ib_pkpwr;
4971 s8 lna_gain_a[LNA_GAIN_NUM];
4972 s8 lna_gain_g[LNA_GAIN_NUM];
4973 s8 *lna_gain;
4974 s8 tia_gain_a[TIA_GAIN_NUM];
4975 s8 tia_gain_g[TIA_GAIN_NUM];
4976 s8 *tia_gain;
4977 bool is_linked_pre;
4978 bool bypass_dig;
4979};
4980
4981enum rtw89_multi_cfo_mode {
4982 RTW89_PKT_BASED_AVG_MODE = 0,
4983 RTW89_ENTRY_BASED_AVG_MODE = 1,
4984 RTW89_TP_BASED_AVG_MODE = 2,
4985};
4986
4987enum rtw89_phy_cfo_status {
4988 RTW89_PHY_DCFO_STATE_NORMAL = 0,
4989 RTW89_PHY_DCFO_STATE_ENHANCE = 1,
4990 RTW89_PHY_DCFO_STATE_HOLD = 2,
4991 RTW89_PHY_DCFO_STATE_MAX
4992};
4993
4994enum rtw89_phy_cfo_ul_ofdma_acc_mode {
4995 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0,
4996 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1
4997};
4998
4999struct rtw89_cfo_tracking_info {
5000 u16 cfo_timer_ms;
5001 bool cfo_trig_by_timer_en;
5002 enum rtw89_phy_cfo_status phy_cfo_status;
5003 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode;
5004 u8 phy_cfo_trk_cnt;
5005 bool is_adjust;
5006 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode;
5007 bool apply_compensation;
5008 u8 crystal_cap;
5009 u8 crystal_cap_default;
5010 u8 def_x_cap;
5011 s8 x_cap_ofst;
5012 u32 sta_cfo_tolerance;
5013 s32 cfo_tail[CFO_TRACK_MAX_USER];
5014 u16 cfo_cnt[CFO_TRACK_MAX_USER];
5015 s32 cfo_avg_pre;
5016 s32 cfo_avg[CFO_TRACK_MAX_USER];
5017 s32 pre_cfo_avg[CFO_TRACK_MAX_USER];
5018 s32 dcfo_avg;
5019 s32 dcfo_avg_pre;
5020 u32 packet_count;
5021 u32 packet_count_pre;
5022 s32 residual_cfo_acc;
5023 u8 phy_cfotrk_state;
5024 u8 phy_cfotrk_cnt;
5025 bool divergence_lock_en;
5026 u8 x_cap_lb;
5027 u8 x_cap_ub;
5028 u8 lock_cnt;
5029};
5030
5031enum rtw89_tssi_mode {
5032 RTW89_TSSI_NORMAL = 0,
5033 RTW89_TSSI_SCAN = 1,
5034};
5035
5036enum rtw89_tssi_alimk_band {
5037 TSSI_ALIMK_2G = 0,
5038 TSSI_ALIMK_5GL,
5039 TSSI_ALIMK_5GM,
5040 TSSI_ALIMK_5GH,
5041 TSSI_ALIMK_MAX
5042};
5043
5044/* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */
5045#define TSSI_TRIM_CH_GROUP_NUM 8
5046#define TSSI_TRIM_CH_GROUP_NUM_6G 16
5047
5048#define TSSI_CCK_CH_GROUP_NUM 6
5049#define TSSI_MCS_2G_CH_GROUP_NUM 5
5050#define TSSI_MCS_5G_CH_GROUP_NUM 14
5051#define TSSI_MCS_6G_CH_GROUP_NUM 32
5052#define TSSI_MCS_CH_GROUP_NUM \
5053 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM)
5054#define TSSI_MAX_CH_NUM 67
5055#define TSSI_ALIMK_VALUE_NUM 8
5056
5057struct rtw89_tssi_info {
5058 u8 thermal[RF_PATH_MAX];
5059 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM];
5060 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G];
5061 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM];
5062 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM];
5063 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM];
5064 s8 extra_ofst[RF_PATH_MAX];
5065 bool tssi_tracking_check[RF_PATH_MAX];
5066 u8 default_txagc_offset[RF_PATH_MAX];
5067 u32 base_thermal[RF_PATH_MAX];
5068 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM];
5069 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM];
5070 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM];
5071 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX];
5072 u32 tssi_alimk_time;
5073};
5074
5075struct rtw89_power_trim_info {
5076 bool pg_thermal_trim;
5077 bool pg_pa_bias_trim;
5078 u8 thermal_trim[RF_PATH_MAX];
5079 u8 pa_bias_trim[RF_PATH_MAX];
5080 u8 pad_bias_trim[RF_PATH_MAX];
5081};
5082
5083struct rtw89_regd {
5084 char alpha2[3];
5085 u8 txpwr_regd[RTW89_BAND_NUM];
5086};
5087
5088#define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX
5089#define RTW89_5GHZ_UNII4_CHANNEL_NUM 3
5090#define RTW89_5GHZ_UNII4_START_INDEX 25
5091
5092struct rtw89_regulatory_info {
5093 const struct rtw89_regd *regd;
5094 enum rtw89_reg_6ghz_power reg_6ghz_power;
5095 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe;
5096 DECLARE_BITMAP(block_unii4, RTW89_REGD_MAX_COUNTRY_NUM);
5097 DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM);
5098 DECLARE_BITMAP(block_6ghz_sp, RTW89_REGD_MAX_COUNTRY_NUM);
5099};
5100
5101enum rtw89_ifs_clm_application {
5102 RTW89_IFS_CLM_INIT = 0,
5103 RTW89_IFS_CLM_BACKGROUND = 1,
5104 RTW89_IFS_CLM_ACS = 2,
5105 RTW89_IFS_CLM_DIG = 3,
5106 RTW89_IFS_CLM_TDMA_DIG = 4,
5107 RTW89_IFS_CLM_DBG = 5,
5108 RTW89_IFS_CLM_DBG_MANUAL = 6
5109};
5110
5111enum rtw89_env_racing_lv {
5112 RTW89_RAC_RELEASE = 0,
5113 RTW89_RAC_LV_1 = 1,
5114 RTW89_RAC_LV_2 = 2,
5115 RTW89_RAC_LV_3 = 3,
5116 RTW89_RAC_LV_4 = 4,
5117 RTW89_RAC_MAX_NUM = 5
5118};
5119
5120struct rtw89_ccx_para_info {
5121 enum rtw89_env_racing_lv rac_lv;
5122 u16 mntr_time;
5123 u8 nhm_manual_th_ofst;
5124 u8 nhm_manual_th0;
5125 enum rtw89_ifs_clm_application ifs_clm_app;
5126 u32 ifs_clm_manual_th_times;
5127 u32 ifs_clm_manual_th0;
5128 u8 fahm_manual_th_ofst;
5129 u8 fahm_manual_th0;
5130 u8 fahm_numer_opt;
5131 u8 fahm_denom_opt;
5132};
5133
5134enum rtw89_ccx_edcca_opt_sc_idx {
5135 RTW89_CCX_EDCCA_SEG0_P0 = 0,
5136 RTW89_CCX_EDCCA_SEG0_S1 = 1,
5137 RTW89_CCX_EDCCA_SEG0_S2 = 2,
5138 RTW89_CCX_EDCCA_SEG0_S3 = 3,
5139 RTW89_CCX_EDCCA_SEG1_P0 = 4,
5140 RTW89_CCX_EDCCA_SEG1_S1 = 5,
5141 RTW89_CCX_EDCCA_SEG1_S2 = 6,
5142 RTW89_CCX_EDCCA_SEG1_S3 = 7
5143};
5144
5145enum rtw89_ccx_edcca_opt_bw_idx {
5146 RTW89_CCX_EDCCA_BW20_0 = 0,
5147 RTW89_CCX_EDCCA_BW20_1 = 1,
5148 RTW89_CCX_EDCCA_BW20_2 = 2,
5149 RTW89_CCX_EDCCA_BW20_3 = 3,
5150 RTW89_CCX_EDCCA_BW20_4 = 4,
5151 RTW89_CCX_EDCCA_BW20_5 = 5,
5152 RTW89_CCX_EDCCA_BW20_6 = 6,
5153 RTW89_CCX_EDCCA_BW20_7 = 7
5154};
5155
5156#define RTW89_NHM_TH_NUM 11
5157#define RTW89_FAHM_TH_NUM 11
5158#define RTW89_NHM_RPT_NUM 12
5159#define RTW89_FAHM_RPT_NUM 12
5160#define RTW89_IFS_CLM_NUM 4
5161struct rtw89_env_monitor_info {
5162 u8 ccx_watchdog_result;
5163 bool ccx_ongoing;
5164 u8 ccx_rac_lv;
5165 bool ccx_manual_ctrl;
5166 u16 ifs_clm_mntr_time;
5167 enum rtw89_ifs_clm_application ifs_clm_app;
5168 u16 ccx_period;
5169 u8 ccx_unit_idx;
5170 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM];
5171 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM];
5172 u16 ifs_clm_tx;
5173 u16 ifs_clm_edcca_excl_cca;
5174 u16 ifs_clm_ofdmfa;
5175 u16 ifs_clm_ofdmcca_excl_fa;
5176 u16 ifs_clm_cckfa;
5177 u16 ifs_clm_cckcca_excl_fa;
5178 u16 ifs_clm_total_ifs;
5179 u8 ifs_clm_his[RTW89_IFS_CLM_NUM];
5180 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM];
5181 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM];
5182 u8 ifs_clm_tx_ratio;
5183 u8 ifs_clm_edcca_excl_cca_ratio;
5184 u8 ifs_clm_cck_fa_ratio;
5185 u8 ifs_clm_ofdm_fa_ratio;
5186 u8 ifs_clm_cck_cca_excl_fa_ratio;
5187 u8 ifs_clm_ofdm_cca_excl_fa_ratio;
5188 u16 ifs_clm_cck_fa_permil;
5189 u16 ifs_clm_ofdm_fa_permil;
5190 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM];
5191 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM];
5192};
5193
5194enum rtw89_ser_rcvy_step {
5195 RTW89_SER_DRV_STOP_TX,
5196 RTW89_SER_DRV_STOP_RX,
5197 RTW89_SER_DRV_STOP_RUN,
5198 RTW89_SER_HAL_STOP_DMA,
5199 RTW89_SER_SUPPRESS_LOG,
5200 RTW89_NUM_OF_SER_FLAGS
5201};
5202
5203struct rtw89_ser {
5204 u8 state;
5205 u8 alarm_event;
5206 bool prehandle_l1;
5207
5208 struct work_struct ser_hdl_work;
5209 struct delayed_work ser_alarm_work;
5210 const struct state_ent *st_tbl;
5211 const struct event_ent *ev_tbl;
5212 struct list_head msg_q;
5213 spinlock_t msg_q_lock; /* lock when read/write ser msg */
5214 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS);
5215};
5216
5217enum rtw89_mac_ax_ps_mode {
5218 RTW89_MAC_AX_PS_MODE_ACTIVE = 0,
5219 RTW89_MAC_AX_PS_MODE_LEGACY = 1,
5220 RTW89_MAC_AX_PS_MODE_WMMPS = 2,
5221 RTW89_MAC_AX_PS_MODE_MAX = 3,
5222};
5223
5224enum rtw89_last_rpwm_mode {
5225 RTW89_LAST_RPWM_PS = 0x0,
5226 RTW89_LAST_RPWM_ACTIVE = 0x6,
5227};
5228
5229struct rtw89_lps_parm {
5230 u8 macid;
5231 u8 psmode; /* enum rtw89_mac_ax_ps_mode */
5232 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */
5233};
5234
5235struct rtw89_ppdu_sts_info {
5236 struct sk_buff_head rx_queue[RTW89_PHY_MAX];
5237 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX];
5238};
5239
5240struct rtw89_early_h2c {
5241 struct list_head list;
5242 u8 *h2c;
5243 u16 h2c_len;
5244};
5245
5246struct rtw89_hw_scan_info {
5247 struct rtw89_vif_link *scanning_vif;
5248 struct list_head pkt_list[NUM_NL80211_BANDS];
5249 struct rtw89_chan op_chan;
5250 bool abort;
5251 u32 last_chan_idx;
5252};
5253
5254enum rtw89_phy_bb_gain_band {
5255 RTW89_BB_GAIN_BAND_2G = 0,
5256 RTW89_BB_GAIN_BAND_5G_L = 1,
5257 RTW89_BB_GAIN_BAND_5G_M = 2,
5258 RTW89_BB_GAIN_BAND_5G_H = 3,
5259 RTW89_BB_GAIN_BAND_6G_L = 4,
5260 RTW89_BB_GAIN_BAND_6G_M = 5,
5261 RTW89_BB_GAIN_BAND_6G_H = 6,
5262 RTW89_BB_GAIN_BAND_6G_UH = 7,
5263
5264 RTW89_BB_GAIN_BAND_NR,
5265};
5266
5267enum rtw89_phy_gain_band_be {
5268 RTW89_BB_GAIN_BAND_2G_BE = 0,
5269 RTW89_BB_GAIN_BAND_5G_L_BE = 1,
5270 RTW89_BB_GAIN_BAND_5G_M_BE = 2,
5271 RTW89_BB_GAIN_BAND_5G_H_BE = 3,
5272 RTW89_BB_GAIN_BAND_6G_L0_BE = 4,
5273 RTW89_BB_GAIN_BAND_6G_L1_BE = 5,
5274 RTW89_BB_GAIN_BAND_6G_M0_BE = 6,
5275 RTW89_BB_GAIN_BAND_6G_M1_BE = 7,
5276 RTW89_BB_GAIN_BAND_6G_H0_BE = 8,
5277 RTW89_BB_GAIN_BAND_6G_H1_BE = 9,
5278 RTW89_BB_GAIN_BAND_6G_UH0_BE = 10,
5279 RTW89_BB_GAIN_BAND_6G_UH1_BE = 11,
5280
5281 RTW89_BB_GAIN_BAND_NR_BE,
5282};
5283
5284enum rtw89_phy_bb_bw_be {
5285 RTW89_BB_BW_20_40 = 0,
5286 RTW89_BB_BW_80_160_320 = 1,
5287
5288 RTW89_BB_BW_NR_BE,
5289};
5290
5291enum rtw89_bw20_sc {
5292 RTW89_BW20_SC_20M = 1,
5293 RTW89_BW20_SC_40M = 2,
5294 RTW89_BW20_SC_80M = 4,
5295 RTW89_BW20_SC_160M = 8,
5296 RTW89_BW20_SC_320M = 16,
5297};
5298
5299enum rtw89_cmac_table_bw {
5300 RTW89_CMAC_BW_20M = 0,
5301 RTW89_CMAC_BW_40M = 1,
5302 RTW89_CMAC_BW_80M = 2,
5303 RTW89_CMAC_BW_160M = 3,
5304 RTW89_CMAC_BW_320M = 4,
5305
5306 RTW89_CMAC_BW_NR,
5307};
5308
5309enum rtw89_phy_bb_rxsc_num {
5310 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */
5311 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */
5312 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */
5313};
5314
5315struct rtw89_phy_bb_gain_info {
5316 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
5317 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM];
5318 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
5319 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
5320 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5321 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */
5322 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX];
5323 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5324 [RTW89_BB_RXSC_NUM_40];
5325 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5326 [RTW89_BB_RXSC_NUM_80];
5327 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5328 [RTW89_BB_RXSC_NUM_160];
5329};
5330
5331struct rtw89_phy_bb_gain_info_be {
5332 s8 lna_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX]
5333 [LNA_GAIN_NUM];
5334 s8 tia_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX]
5335 [TIA_GAIN_NUM];
5336 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE]
5337 [RF_PATH_MAX][LNA_GAIN_NUM];
5338 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE]
5339 [RF_PATH_MAX][LNA_GAIN_NUM];
5340 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE]
5341 [RF_PATH_MAX][LNA_GAIN_NUM + 1];
5342 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5343 [RTW89_BW20_SC_20M];
5344 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5345 [RTW89_BW20_SC_40M];
5346 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5347 [RTW89_BW20_SC_80M];
5348 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5349 [RTW89_BW20_SC_160M];
5350};
5351
5352struct rtw89_phy_efuse_gain {
5353 bool offset_valid;
5354 bool comp_valid;
5355 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */
5356 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */
5357 s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */
5358 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */
5359};
5360
5361#define RTW89_MAX_PATTERN_NUM 18
5362#define RTW89_MAX_PATTERN_MASK_SIZE 4
5363#define RTW89_MAX_PATTERN_SIZE 128
5364
5365struct rtw89_wow_cam_info {
5366 bool r_w;
5367 u8 idx;
5368 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE];
5369 u16 crc;
5370 bool negative_pattern_match;
5371 bool skip_mac_hdr;
5372 bool uc;
5373 bool mc;
5374 bool bc;
5375 bool valid;
5376};
5377
5378struct rtw89_wow_key_info {
5379 u8 ptk_tx_iv[8];
5380 u8 valid_check;
5381 u8 symbol_check_en;
5382 u8 gtk_keyidx;
5383 u8 rsvd[5];
5384 u8 ptk_rx_iv[8];
5385 u8 gtk_rx_iv[4][8];
5386} __packed;
5387
5388struct rtw89_wow_gtk_info {
5389 u8 kck[32];
5390 u8 kek[32];
5391 u8 tk1[16];
5392 u8 txmickey[8];
5393 u8 rxmickey[8];
5394 __le32 igtk_keyid;
5395 __le64 ipn;
5396 u8 igtk[2][32];
5397 u8 psk[32];
5398} __packed;
5399
5400struct rtw89_wow_aoac_report {
5401 u8 rpt_ver;
5402 u8 sec_type;
5403 u8 key_idx;
5404 u8 pattern_idx;
5405 u8 rekey_ok;
5406 u8 ptk_tx_iv[8];
5407 u8 eapol_key_replay_count[8];
5408 u8 gtk[32];
5409 u8 ptk_rx_iv[8];
5410 u8 gtk_rx_iv[4][8];
5411 u64 igtk_key_id;
5412 u64 igtk_ipn;
5413 u8 igtk[32];
5414 u8 csa_pri_ch;
5415 u8 csa_bw;
5416 u8 csa_ch_offset;
5417 u8 csa_chsw_failed;
5418 u8 csa_ch_band;
5419};
5420
5421struct rtw89_wow_param {
5422 struct rtw89_vif_link *rtwvif_link;
5423 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM);
5424 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM];
5425 struct rtw89_wow_key_info key_info;
5426 struct rtw89_wow_gtk_info gtk_info;
5427 struct rtw89_wow_aoac_report aoac_rpt;
5428 u8 pattern_cnt;
5429 u8 ptk_alg;
5430 u8 gtk_alg;
5431 u8 ptk_keyidx;
5432 u8 akm;
5433
5434 /* see RTW89_WOW_WAIT_COND series for wait condition */
5435 struct rtw89_wait_info wait;
5436
5437 bool pno_inited;
5438 struct list_head pno_pkt_list;
5439 struct cfg80211_sched_scan_request *nd_config;
5440};
5441
5442struct rtw89_mcc_limit {
5443 bool enable;
5444 u16 max_tob; /* TU; max time offset behind */
5445 u16 max_toa; /* TU; max time offset ahead */
5446 u16 max_dur; /* TU */
5447};
5448
5449struct rtw89_mcc_policy {
5450 u8 c2h_rpt;
5451 u8 tx_null_early;
5452 u8 dis_tx_null;
5453 u8 in_curr_ch;
5454 u8 dis_sw_retry;
5455 u8 sw_retry_count;
5456};
5457
5458struct rtw89_mcc_role {
5459 struct rtw89_vif_link *rtwvif_link;
5460 struct rtw89_mcc_policy policy;
5461 struct rtw89_mcc_limit limit;
5462
5463 /* only valid when running with FW MRC mechanism */
5464 u8 slot_idx;
5465
5466 /* byte-array in LE order for FW */
5467 u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)];
5468
5469 u16 duration; /* TU */
5470 u16 beacon_interval; /* TU */
5471 bool is_2ghz;
5472 bool is_go;
5473 bool is_gc;
5474};
5475
5476struct rtw89_mcc_bt_role {
5477 u16 duration; /* TU */
5478};
5479
5480struct rtw89_mcc_courtesy {
5481 bool enable;
5482 u8 slot_num;
5483 u8 macid_src;
5484 u8 macid_tgt;
5485};
5486
5487enum rtw89_mcc_plan {
5488 RTW89_MCC_PLAN_TAIL_BT,
5489 RTW89_MCC_PLAN_MID_BT,
5490 RTW89_MCC_PLAN_NO_BT,
5491
5492 NUM_OF_RTW89_MCC_PLAN,
5493};
5494
5495struct rtw89_mcc_pattern {
5496 s16 tob_ref; /* TU; time offset behind of reference role */
5497 s16 toa_ref; /* TU; time offset ahead of reference role */
5498 s16 tob_aux; /* TU; time offset behind of auxiliary role */
5499 s16 toa_aux; /* TU; time offset ahead of auxiliary role */
5500
5501 enum rtw89_mcc_plan plan;
5502 struct rtw89_mcc_courtesy courtesy;
5503};
5504
5505struct rtw89_mcc_sync {
5506 bool enable;
5507 u16 offset; /* TU */
5508 u8 macid_src;
5509 u8 band_src;
5510 u8 port_src;
5511 u8 macid_tgt;
5512 u8 band_tgt;
5513 u8 port_tgt;
5514};
5515
5516struct rtw89_mcc_config {
5517 struct rtw89_mcc_pattern pattern;
5518 struct rtw89_mcc_sync sync;
5519 u64 start_tsf;
5520 u16 mcc_interval; /* TU */
5521 u16 beacon_offset; /* TU */
5522};
5523
5524enum rtw89_mcc_mode {
5525 RTW89_MCC_MODE_GO_STA,
5526 RTW89_MCC_MODE_GC_STA,
5527};
5528
5529struct rtw89_mcc_info {
5530 struct rtw89_wait_info wait;
5531
5532 u8 group;
5533 enum rtw89_mcc_mode mode;
5534 struct rtw89_mcc_role role_ref; /* reference role */
5535 struct rtw89_mcc_role role_aux; /* auxiliary role */
5536 struct rtw89_mcc_bt_role bt_role;
5537 struct rtw89_mcc_config config;
5538};
5539
5540struct rtw89_dev {
5541 struct ieee80211_hw *hw;
5542 struct device *dev;
5543 const struct ieee80211_ops *ops;
5544
5545 bool dbcc_en;
5546 bool support_mlo;
5547 enum rtw89_mlo_dbcc_mode mlo_dbcc_mode;
5548 struct rtw89_hw_scan_info scan_info;
5549 const struct rtw89_chip_info *chip;
5550 const struct rtw89_pci_info *pci_info;
5551 const struct rtw89_rfe_parms *rfe_parms;
5552 struct rtw89_hal hal;
5553 struct rtw89_mcc_info mcc;
5554 struct rtw89_mac_info mac;
5555 struct rtw89_fw_info fw;
5556 struct rtw89_hci_info hci;
5557 struct rtw89_efuse efuse;
5558 struct rtw89_traffic_stats stats;
5559 struct rtw89_rfe_data *rfe_data;
5560 enum rtw89_custid custid;
5561
5562 /* ensures exclusive access from mac80211 callbacks */
5563 struct mutex mutex;
5564 struct list_head rtwvifs_list;
5565 /* used to protect rf read write */
5566 struct mutex rf_mutex;
5567 struct workqueue_struct *txq_wq;
5568 struct work_struct txq_work;
5569 struct delayed_work txq_reinvoke_work;
5570 /* used to protect ba_list and forbid_ba_list */
5571 spinlock_t ba_lock;
5572 /* txqs to setup ba session */
5573 struct list_head ba_list;
5574 /* txqs to forbid ba session */
5575 struct list_head forbid_ba_list;
5576 struct work_struct ba_work;
5577 /* used to protect rpwm */
5578 spinlock_t rpwm_lock;
5579
5580 struct rtw89_cam_info cam_info;
5581
5582 struct sk_buff_head c2h_queue;
5583 struct work_struct c2h_work;
5584 struct work_struct ips_work;
5585 struct work_struct load_firmware_work;
5586 struct work_struct cancel_6ghz_probe_work;
5587
5588 struct list_head early_h2c_list;
5589
5590 struct rtw89_ser ser;
5591
5592 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM);
5593 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM);
5594 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS);
5595 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM);
5596 DECLARE_BITMAP(quirks, NUM_OF_RTW89_QUIRKS);
5597
5598 struct rtw89_phy_stat phystat;
5599 struct rtw89_rfk_wait_info rfk_wait;
5600 struct rtw89_dack_info dack;
5601 struct rtw89_iqk_info iqk;
5602 struct rtw89_dpk_info dpk;
5603 struct rtw89_rfk_mcc_info rfk_mcc;
5604 struct rtw89_lck_info lck;
5605 struct rtw89_rx_dck_info rx_dck;
5606 bool is_tssi_mode[RF_PATH_MAX];
5607 bool is_bt_iqk_timeout;
5608
5609 struct rtw89_fem_info fem;
5610 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM];
5611 struct rtw89_tssi_info tssi;
5612 struct rtw89_power_trim_info pwr_trim;
5613
5614 struct rtw89_cfo_tracking_info cfo_tracking;
5615 struct rtw89_env_monitor_info env_monitor;
5616 struct rtw89_dig_info dig;
5617 struct rtw89_phy_ch_info ch_info;
5618 union {
5619 struct rtw89_phy_bb_gain_info ax;
5620 struct rtw89_phy_bb_gain_info_be be;
5621 } bb_gain;
5622 struct rtw89_phy_efuse_gain efuse_gain;
5623 struct rtw89_phy_ul_tb_info ul_tb_info;
5624 struct rtw89_antdiv_info antdiv;
5625
5626 struct delayed_work track_work;
5627 struct delayed_work chanctx_work;
5628 struct delayed_work coex_act1_work;
5629 struct delayed_work coex_bt_devinfo_work;
5630 struct delayed_work coex_rfk_chk_work;
5631 struct delayed_work cfo_track_work;
5632 struct delayed_work forbid_ba_work;
5633 struct delayed_work roc_work;
5634 struct delayed_work antdiv_work;
5635 struct rtw89_ppdu_sts_info ppdu_sts;
5636 u8 total_sta_assoc;
5637 bool scanning;
5638
5639 struct rtw89_regulatory_info regulatory;
5640 struct rtw89_sar_info sar;
5641 struct rtw89_tas_info tas;
5642
5643 struct rtw89_btc btc;
5644 enum rtw89_ps_mode ps_mode;
5645 bool lps_enabled;
5646
5647 struct rtw89_wow_param wow;
5648
5649 /* napi structure */
5650 struct net_device *netdev;
5651 struct napi_struct napi;
5652 int napi_budget_countdown;
5653
5654 struct rtw89_debugfs *debugfs;
5655
5656 /* HCI related data, keep last */
5657 u8 priv[] __aligned(sizeof(void *));
5658};
5659
5660struct rtw89_vif {
5661 struct rtw89_dev *rtwdev;
5662 struct list_head list;
5663 struct list_head mgnt_entry;
5664
5665 u8 mac_addr[ETH_ALEN];
5666 __be32 ip_addr;
5667
5668 struct rtw89_traffic_stats stats;
5669 u32 tdls_peer;
5670
5671 struct ieee80211_scan_ies *scan_ies;
5672 struct cfg80211_scan_request *scan_req;
5673
5674 struct rtw89_roc roc;
5675 bool offchan;
5676
5677 u8 links_inst_valid_num;
5678 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM);
5679 struct rtw89_vif_link *links[IEEE80211_MLD_MAX_NUM_LINKS];
5680 struct rtw89_vif_link links_inst[] __counted_by(links_inst_valid_num);
5681};
5682
5683static inline bool rtw89_vif_assign_link_is_valid(struct rtw89_vif_link **rtwvif_link,
5684 const struct rtw89_vif *rtwvif,
5685 unsigned int link_id)
5686{
5687 *rtwvif_link = rtwvif->links[link_id];
5688 return !!*rtwvif_link;
5689}
5690
5691#define rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) \
5692 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \
5693 if (rtw89_vif_assign_link_is_valid(&(rtwvif_link), rtwvif, link_id))
5694
5695struct rtw89_sta {
5696 struct rtw89_dev *rtwdev;
5697 struct rtw89_vif *rtwvif;
5698
5699 bool disassoc;
5700
5701 struct sk_buff_head roc_queue;
5702
5703 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS];
5704 DECLARE_BITMAP(ampdu_map, IEEE80211_NUM_TIDS);
5705
5706 u8 links_inst_valid_num;
5707 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM);
5708 struct rtw89_sta_link *links[IEEE80211_MLD_MAX_NUM_LINKS];
5709 struct rtw89_sta_link links_inst[] __counted_by(links_inst_valid_num);
5710};
5711
5712static inline bool rtw89_sta_assign_link_is_valid(struct rtw89_sta_link **rtwsta_link,
5713 const struct rtw89_sta *rtwsta,
5714 unsigned int link_id)
5715{
5716 *rtwsta_link = rtwsta->links[link_id];
5717 return !!*rtwsta_link;
5718}
5719
5720#define rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) \
5721 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \
5722 if (rtw89_sta_assign_link_is_valid(&(rtwsta_link), rtwsta, link_id))
5723
5724static inline u8 rtw89_vif_get_main_macid(struct rtw89_vif *rtwvif)
5725{
5726 /* const after init, so no need to check if active first */
5727 return rtwvif->links_inst[0].mac_id;
5728}
5729
5730static inline u8 rtw89_vif_get_main_port(struct rtw89_vif *rtwvif)
5731{
5732 /* const after init, so no need to check if active first */
5733 return rtwvif->links_inst[0].port;
5734}
5735
5736static inline struct rtw89_vif_link *
5737rtw89_vif_get_link_inst(struct rtw89_vif *rtwvif, u8 index)
5738{
5739 if (index >= rtwvif->links_inst_valid_num ||
5740 !test_bit(index, rtwvif->links_inst_map))
5741 return NULL;
5742 return &rtwvif->links_inst[index];
5743}
5744
5745static inline
5746u8 rtw89_vif_link_inst_get_index(struct rtw89_vif_link *rtwvif_link)
5747{
5748 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
5749
5750 return rtwvif_link - rtwvif->links_inst;
5751}
5752
5753static inline u8 rtw89_sta_get_main_macid(struct rtw89_sta *rtwsta)
5754{
5755 /* const after init, so no need to check if active first */
5756 return rtwsta->links_inst[0].mac_id;
5757}
5758
5759static inline struct rtw89_sta_link *
5760rtw89_sta_get_link_inst(struct rtw89_sta *rtwsta, u8 index)
5761{
5762 if (index >= rtwsta->links_inst_valid_num ||
5763 !test_bit(index, rtwsta->links_inst_map))
5764 return NULL;
5765 return &rtwsta->links_inst[index];
5766}
5767
5768static inline
5769u8 rtw89_sta_link_inst_get_index(struct rtw89_sta_link *rtwsta_link)
5770{
5771 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta;
5772
5773 return rtwsta_link - rtwsta->links_inst;
5774}
5775
5776static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev,
5777 struct rtw89_core_tx_request *tx_req)
5778{
5779 return rtwdev->hci.ops->tx_write(rtwdev, tx_req);
5780}
5781
5782static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev)
5783{
5784 rtwdev->hci.ops->reset(rtwdev);
5785}
5786
5787static inline int rtw89_hci_start(struct rtw89_dev *rtwdev)
5788{
5789 return rtwdev->hci.ops->start(rtwdev);
5790}
5791
5792static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev)
5793{
5794 rtwdev->hci.ops->stop(rtwdev);
5795}
5796
5797static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev)
5798{
5799 return rtwdev->hci.ops->deinit(rtwdev);
5800}
5801
5802static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause)
5803{
5804 rtwdev->hci.ops->pause(rtwdev, pause);
5805}
5806
5807static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power)
5808{
5809 rtwdev->hci.ops->switch_mode(rtwdev, low_power);
5810}
5811
5812static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev)
5813{
5814 rtwdev->hci.ops->recalc_int_mit(rtwdev);
5815}
5816
5817static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch)
5818{
5819 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch);
5820}
5821
5822static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch)
5823{
5824 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch);
5825}
5826
5827static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev)
5828{
5829 return rtwdev->hci.ops->mac_pre_deinit(rtwdev);
5830}
5831
5832static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues,
5833 bool drop)
5834{
5835 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
5836 return;
5837
5838 if (rtwdev->hci.ops->flush_queues)
5839 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop);
5840}
5841
5842static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev)
5843{
5844 if (rtwdev->hci.ops->recovery_start)
5845 rtwdev->hci.ops->recovery_start(rtwdev);
5846}
5847
5848static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev)
5849{
5850 if (rtwdev->hci.ops->recovery_complete)
5851 rtwdev->hci.ops->recovery_complete(rtwdev);
5852}
5853
5854static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev)
5855{
5856 if (rtwdev->hci.ops->enable_intr)
5857 rtwdev->hci.ops->enable_intr(rtwdev);
5858}
5859
5860static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev)
5861{
5862 if (rtwdev->hci.ops->disable_intr)
5863 rtwdev->hci.ops->disable_intr(rtwdev);
5864}
5865
5866static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable)
5867{
5868 if (rtwdev->hci.ops->ctrl_txdma_ch)
5869 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable);
5870}
5871
5872static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable)
5873{
5874 if (rtwdev->hci.ops->ctrl_txdma_fw_ch)
5875 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable);
5876}
5877
5878static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable)
5879{
5880 if (rtwdev->hci.ops->ctrl_trxhci)
5881 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable);
5882}
5883
5884static inline int rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev)
5885{
5886 int ret = 0;
5887
5888 if (rtwdev->hci.ops->poll_txdma_ch_idle)
5889 ret = rtwdev->hci.ops->poll_txdma_ch_idle(rtwdev);
5890 return ret;
5891}
5892
5893static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev)
5894{
5895 if (rtwdev->hci.ops->clr_idx_all)
5896 rtwdev->hci.ops->clr_idx_all(rtwdev);
5897}
5898
5899static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev)
5900{
5901 int ret = 0;
5902
5903 if (rtwdev->hci.ops->rst_bdram)
5904 ret = rtwdev->hci.ops->rst_bdram(rtwdev);
5905 return ret;
5906}
5907
5908static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev)
5909{
5910 if (rtwdev->hci.ops->clear)
5911 rtwdev->hci.ops->clear(rtwdev, pdev);
5912}
5913
5914static inline
5915struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb)
5916{
5917 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
5918
5919 return (struct rtw89_tx_skb_data *)info->status.status_driver_data;
5920}
5921
5922static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr)
5923{
5924 return rtwdev->hci.ops->read8(rtwdev, addr);
5925}
5926
5927static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr)
5928{
5929 return rtwdev->hci.ops->read16(rtwdev, addr);
5930}
5931
5932static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr)
5933{
5934 return rtwdev->hci.ops->read32(rtwdev, addr);
5935}
5936
5937static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data)
5938{
5939 rtwdev->hci.ops->write8(rtwdev, addr, data);
5940}
5941
5942static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data)
5943{
5944 rtwdev->hci.ops->write16(rtwdev, addr, data);
5945}
5946
5947static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data)
5948{
5949 rtwdev->hci.ops->write32(rtwdev, addr, data);
5950}
5951
5952static inline void
5953rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
5954{
5955 u8 val;
5956
5957 val = rtw89_read8(rtwdev, addr);
5958 rtw89_write8(rtwdev, addr, val | bit);
5959}
5960
5961static inline void
5962rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
5963{
5964 u16 val;
5965
5966 val = rtw89_read16(rtwdev, addr);
5967 rtw89_write16(rtwdev, addr, val | bit);
5968}
5969
5970static inline void
5971rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
5972{
5973 u32 val;
5974
5975 val = rtw89_read32(rtwdev, addr);
5976 rtw89_write32(rtwdev, addr, val | bit);
5977}
5978
5979static inline void
5980rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
5981{
5982 u8 val;
5983
5984 val = rtw89_read8(rtwdev, addr);
5985 rtw89_write8(rtwdev, addr, val & ~bit);
5986}
5987
5988static inline void
5989rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
5990{
5991 u16 val;
5992
5993 val = rtw89_read16(rtwdev, addr);
5994 rtw89_write16(rtwdev, addr, val & ~bit);
5995}
5996
5997static inline void
5998rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
5999{
6000 u32 val;
6001
6002 val = rtw89_read32(rtwdev, addr);
6003 rtw89_write32(rtwdev, addr, val & ~bit);
6004}
6005
6006static inline u32
6007rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
6008{
6009 u32 shift = __ffs(mask);
6010 u32 orig;
6011 u32 ret;
6012
6013 orig = rtw89_read32(rtwdev, addr);
6014 ret = (orig & mask) >> shift;
6015
6016 return ret;
6017}
6018
6019static inline u16
6020rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
6021{
6022 u32 shift = __ffs(mask);
6023 u32 orig;
6024 u32 ret;
6025
6026 orig = rtw89_read16(rtwdev, addr);
6027 ret = (orig & mask) >> shift;
6028
6029 return ret;
6030}
6031
6032static inline u8
6033rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
6034{
6035 u32 shift = __ffs(mask);
6036 u32 orig;
6037 u32 ret;
6038
6039 orig = rtw89_read8(rtwdev, addr);
6040 ret = (orig & mask) >> shift;
6041
6042 return ret;
6043}
6044
6045static inline void
6046rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data)
6047{
6048 u32 shift = __ffs(mask);
6049 u32 orig;
6050 u32 set;
6051
6052 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr);
6053
6054 orig = rtw89_read32(rtwdev, addr);
6055 set = (orig & ~mask) | ((data << shift) & mask);
6056 rtw89_write32(rtwdev, addr, set);
6057}
6058
6059static inline void
6060rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data)
6061{
6062 u32 shift;
6063 u16 orig, set;
6064
6065 mask &= 0xffff;
6066 shift = __ffs(mask);
6067
6068 orig = rtw89_read16(rtwdev, addr);
6069 set = (orig & ~mask) | ((data << shift) & mask);
6070 rtw89_write16(rtwdev, addr, set);
6071}
6072
6073static inline void
6074rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data)
6075{
6076 u32 shift;
6077 u8 orig, set;
6078
6079 mask &= 0xff;
6080 shift = __ffs(mask);
6081
6082 orig = rtw89_read8(rtwdev, addr);
6083 set = (orig & ~mask) | ((data << shift) & mask);
6084 rtw89_write8(rtwdev, addr, set);
6085}
6086
6087static inline u32
6088rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
6089 u32 addr, u32 mask)
6090{
6091 u32 val;
6092
6093 mutex_lock(&rtwdev->rf_mutex);
6094 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask);
6095 mutex_unlock(&rtwdev->rf_mutex);
6096
6097 return val;
6098}
6099
6100static inline void
6101rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
6102 u32 addr, u32 mask, u32 data)
6103{
6104 mutex_lock(&rtwdev->rf_mutex);
6105 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data);
6106 mutex_unlock(&rtwdev->rf_mutex);
6107}
6108
6109static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq)
6110{
6111 void *p = rtwtxq;
6112
6113 return container_of(p, struct ieee80211_txq, drv_priv);
6114}
6115
6116static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev,
6117 struct ieee80211_txq *txq)
6118{
6119 struct rtw89_txq *rtwtxq;
6120
6121 if (!txq)
6122 return;
6123
6124 rtwtxq = (struct rtw89_txq *)txq->drv_priv;
6125 INIT_LIST_HEAD(&rtwtxq->list);
6126}
6127
6128static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif)
6129{
6130 void *p = rtwvif;
6131
6132 return container_of(p, struct ieee80211_vif, drv_priv);
6133}
6134
6135static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif)
6136{
6137 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL;
6138}
6139
6140static inline
6141struct ieee80211_vif *rtwvif_link_to_vif(struct rtw89_vif_link *rtwvif_link)
6142{
6143 return rtwvif_to_vif(rtwvif_link->rtwvif);
6144}
6145
6146static inline
6147struct ieee80211_vif *rtwvif_link_to_vif_safe(struct rtw89_vif_link *rtwvif_link)
6148{
6149 return rtwvif_link ? rtwvif_link_to_vif(rtwvif_link) : NULL;
6150}
6151
6152static inline struct rtw89_vif *vif_to_rtwvif(struct ieee80211_vif *vif)
6153{
6154 return (struct rtw89_vif *)vif->drv_priv;
6155}
6156
6157static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif)
6158{
6159 return vif ? vif_to_rtwvif(vif) : NULL;
6160}
6161
6162static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta)
6163{
6164 void *p = rtwsta;
6165
6166 return container_of(p, struct ieee80211_sta, drv_priv);
6167}
6168
6169static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta)
6170{
6171 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL;
6172}
6173
6174static inline
6175struct ieee80211_sta *rtwsta_link_to_sta(struct rtw89_sta_link *rtwsta_link)
6176{
6177 return rtwsta_to_sta(rtwsta_link->rtwsta);
6178}
6179
6180static inline
6181struct ieee80211_sta *rtwsta_link_to_sta_safe(struct rtw89_sta_link *rtwsta_link)
6182{
6183 return rtwsta_link ? rtwsta_link_to_sta(rtwsta_link) : NULL;
6184}
6185
6186static inline struct rtw89_sta *sta_to_rtwsta(struct ieee80211_sta *sta)
6187{
6188 return (struct rtw89_sta *)sta->drv_priv;
6189}
6190
6191static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta)
6192{
6193 return sta ? sta_to_rtwsta(sta) : NULL;
6194}
6195
6196static inline struct ieee80211_bss_conf *
6197__rtw89_vif_rcu_dereference_link(struct rtw89_vif_link *rtwvif_link, bool *nolink)
6198{
6199 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
6200 struct ieee80211_bss_conf *bss_conf;
6201
6202 bss_conf = rcu_dereference(vif->link_conf[rtwvif_link->link_id]);
6203 if (unlikely(!bss_conf)) {
6204 *nolink = true;
6205 return &vif->bss_conf;
6206 }
6207
6208 *nolink = false;
6209 return bss_conf;
6210}
6211
6212#define rtw89_vif_rcu_dereference_link(rtwvif_link, assert) \
6213({ \
6214 typeof(rtwvif_link) p = rtwvif_link; \
6215 struct ieee80211_bss_conf *bss_conf; \
6216 bool nolink; \
6217 \
6218 bss_conf = __rtw89_vif_rcu_dereference_link(p, &nolink); \
6219 if (unlikely(nolink) && (assert)) \
6220 rtw89_err(p->rtwvif->rtwdev, \
6221 "%s: cannot find exact bss_conf for link_id %u\n",\
6222 __func__, p->link_id); \
6223 bss_conf; \
6224})
6225
6226static inline struct ieee80211_link_sta *
6227__rtw89_sta_rcu_dereference_link(struct rtw89_sta_link *rtwsta_link, bool *nolink)
6228{
6229 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
6230 struct ieee80211_link_sta *link_sta;
6231
6232 link_sta = rcu_dereference(sta->link[rtwsta_link->link_id]);
6233 if (unlikely(!link_sta)) {
6234 *nolink = true;
6235 return &sta->deflink;
6236 }
6237
6238 *nolink = false;
6239 return link_sta;
6240}
6241
6242#define rtw89_sta_rcu_dereference_link(rtwsta_link, assert) \
6243({ \
6244 typeof(rtwsta_link) p = rtwsta_link; \
6245 struct ieee80211_link_sta *link_sta; \
6246 bool nolink; \
6247 \
6248 link_sta = __rtw89_sta_rcu_dereference_link(p, &nolink); \
6249 if (unlikely(nolink) && (assert)) \
6250 rtw89_err(p->rtwsta->rtwdev, \
6251 "%s: cannot find exact link_sta for link_id %u\n",\
6252 __func__, p->link_id); \
6253 link_sta; \
6254})
6255
6256static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw)
6257{
6258 if (hw_bw == RTW89_CHANNEL_WIDTH_160)
6259 return RATE_INFO_BW_160;
6260 else if (hw_bw == RTW89_CHANNEL_WIDTH_80)
6261 return RATE_INFO_BW_80;
6262 else if (hw_bw == RTW89_CHANNEL_WIDTH_40)
6263 return RATE_INFO_BW_40;
6264 else
6265 return RATE_INFO_BW_20;
6266}
6267
6268static inline
6269enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band)
6270{
6271 switch (hw_band) {
6272 default:
6273 case RTW89_BAND_2G:
6274 return NL80211_BAND_2GHZ;
6275 case RTW89_BAND_5G:
6276 return NL80211_BAND_5GHZ;
6277 case RTW89_BAND_6G:
6278 return NL80211_BAND_6GHZ;
6279 }
6280}
6281
6282static inline
6283enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band)
6284{
6285 switch (nl_band) {
6286 default:
6287 case NL80211_BAND_2GHZ:
6288 return RTW89_BAND_2G;
6289 case NL80211_BAND_5GHZ:
6290 return RTW89_BAND_5G;
6291 case NL80211_BAND_6GHZ:
6292 return RTW89_BAND_6G;
6293 }
6294}
6295
6296static inline
6297enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width)
6298{
6299 switch (width) {
6300 default:
6301 WARN(1, "Not support bandwidth %d\n", width);
6302 fallthrough;
6303 case NL80211_CHAN_WIDTH_20_NOHT:
6304 case NL80211_CHAN_WIDTH_20:
6305 return RTW89_CHANNEL_WIDTH_20;
6306 case NL80211_CHAN_WIDTH_40:
6307 return RTW89_CHANNEL_WIDTH_40;
6308 case NL80211_CHAN_WIDTH_80:
6309 return RTW89_CHANNEL_WIDTH_80;
6310 case NL80211_CHAN_WIDTH_160:
6311 return RTW89_CHANNEL_WIDTH_160;
6312 }
6313}
6314
6315static inline
6316enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua)
6317{
6318 switch (rua) {
6319 default:
6320 WARN(1, "Invalid RU allocation: %d\n", rua);
6321 fallthrough;
6322 case 0 ... 36:
6323 return NL80211_RATE_INFO_HE_RU_ALLOC_26;
6324 case 37 ... 52:
6325 return NL80211_RATE_INFO_HE_RU_ALLOC_52;
6326 case 53 ... 60:
6327 return NL80211_RATE_INFO_HE_RU_ALLOC_106;
6328 case 61 ... 64:
6329 return NL80211_RATE_INFO_HE_RU_ALLOC_242;
6330 case 65 ... 66:
6331 return NL80211_RATE_INFO_HE_RU_ALLOC_484;
6332 case 67:
6333 return NL80211_RATE_INFO_HE_RU_ALLOC_996;
6334 case 68:
6335 return NL80211_RATE_INFO_HE_RU_ALLOC_2x996;
6336 }
6337}
6338
6339static inline
6340struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif_link *rtwvif_link,
6341 struct rtw89_sta_link *rtwsta_link)
6342{
6343 if (rtwsta_link) {
6344 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
6345
6346 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls)
6347 return &rtwsta_link->addr_cam;
6348 }
6349 return &rtwvif_link->addr_cam;
6350}
6351
6352static inline
6353struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif_link *rtwvif_link,
6354 struct rtw89_sta_link *rtwsta_link)
6355{
6356 if (rtwsta_link) {
6357 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
6358
6359 if (sta->tdls)
6360 return &rtwsta_link->bssid_cam;
6361 }
6362 return &rtwvif_link->bssid_cam;
6363}
6364
6365static inline
6366void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev,
6367 struct rtw89_channel_help_params *p,
6368 const struct rtw89_chan *chan,
6369 enum rtw89_mac_idx mac_idx,
6370 enum rtw89_phy_idx phy_idx)
6371{
6372 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan,
6373 mac_idx, phy_idx);
6374}
6375
6376static inline
6377void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev,
6378 struct rtw89_channel_help_params *p,
6379 const struct rtw89_chan *chan,
6380 enum rtw89_mac_idx mac_idx,
6381 enum rtw89_phy_idx phy_idx)
6382{
6383 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan,
6384 mac_idx, phy_idx);
6385}
6386
6387static inline
6388const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev,
6389 enum rtw89_chanctx_idx idx)
6390{
6391 struct rtw89_hal *hal = &rtwdev->hal;
6392 enum rtw89_chanctx_idx roc_idx = atomic_read(&hal->roc_chanctx_idx);
6393
6394 if (roc_idx == idx)
6395 return &hal->roc_chandef;
6396
6397 return &hal->chanctx[idx].chandef;
6398}
6399
6400static inline
6401const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev,
6402 enum rtw89_chanctx_idx idx)
6403{
6404 struct rtw89_hal *hal = &rtwdev->hal;
6405
6406 return &hal->chanctx[idx].chan;
6407}
6408
6409static inline
6410const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev,
6411 enum rtw89_chanctx_idx idx)
6412{
6413 struct rtw89_hal *hal = &rtwdev->hal;
6414
6415 return &hal->chanctx[idx].rcd;
6416}
6417
6418static inline
6419const struct rtw89_chan_rcd *rtw89_chan_rcd_get_by_chan(const struct rtw89_chan *chan)
6420{
6421 const struct rtw89_chanctx *chanctx =
6422 container_of_const(chan, struct rtw89_chanctx, chan);
6423
6424 return &chanctx->rcd;
6425}
6426
6427static inline
6428const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev)
6429{
6430 struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif;
6431
6432 if (rtwvif_link)
6433 return rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx);
6434 else
6435 return rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
6436}
6437
6438static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev)
6439{
6440 const struct rtw89_chip_info *chip = rtwdev->chip;
6441
6442 if (chip->ops->fem_setup)
6443 chip->ops->fem_setup(rtwdev);
6444}
6445
6446static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev)
6447{
6448 const struct rtw89_chip_info *chip = rtwdev->chip;
6449
6450 if (chip->ops->rfe_gpio)
6451 chip->ops->rfe_gpio(rtwdev);
6452}
6453
6454static inline void rtw89_chip_rfk_hw_init(struct rtw89_dev *rtwdev)
6455{
6456 const struct rtw89_chip_info *chip = rtwdev->chip;
6457
6458 if (chip->ops->rfk_hw_init)
6459 chip->ops->rfk_hw_init(rtwdev);
6460}
6461
6462static inline
6463void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
6464{
6465 const struct rtw89_chip_info *chip = rtwdev->chip;
6466
6467 if (chip->ops->bb_preinit)
6468 chip->ops->bb_preinit(rtwdev, phy_idx);
6469}
6470
6471static inline
6472void rtw89_chip_bb_postinit(struct rtw89_dev *rtwdev)
6473{
6474 const struct rtw89_chip_info *chip = rtwdev->chip;
6475
6476 if (!chip->ops->bb_postinit)
6477 return;
6478
6479 chip->ops->bb_postinit(rtwdev, RTW89_PHY_0);
6480
6481 if (rtwdev->dbcc_en)
6482 chip->ops->bb_postinit(rtwdev, RTW89_PHY_1);
6483}
6484
6485static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev)
6486{
6487 const struct rtw89_chip_info *chip = rtwdev->chip;
6488
6489 if (chip->ops->bb_sethw)
6490 chip->ops->bb_sethw(rtwdev);
6491}
6492
6493static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev)
6494{
6495 const struct rtw89_chip_info *chip = rtwdev->chip;
6496
6497 if (chip->ops->rfk_init)
6498 chip->ops->rfk_init(rtwdev);
6499}
6500
6501static inline void rtw89_chip_rfk_init_late(struct rtw89_dev *rtwdev)
6502{
6503 const struct rtw89_chip_info *chip = rtwdev->chip;
6504
6505 if (chip->ops->rfk_init_late)
6506 chip->ops->rfk_init_late(rtwdev);
6507}
6508
6509static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev,
6510 struct rtw89_vif_link *rtwvif_link)
6511{
6512 const struct rtw89_chip_info *chip = rtwdev->chip;
6513
6514 if (chip->ops->rfk_channel)
6515 chip->ops->rfk_channel(rtwdev, rtwvif_link);
6516}
6517
6518static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev,
6519 enum rtw89_phy_idx phy_idx,
6520 const struct rtw89_chan *chan)
6521{
6522 const struct rtw89_chip_info *chip = rtwdev->chip;
6523
6524 if (chip->ops->rfk_band_changed)
6525 chip->ops->rfk_band_changed(rtwdev, phy_idx, chan);
6526}
6527
6528static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev,
6529 struct rtw89_vif_link *rtwvif_link, bool start)
6530{
6531 const struct rtw89_chip_info *chip = rtwdev->chip;
6532
6533 if (chip->ops->rfk_scan)
6534 chip->ops->rfk_scan(rtwdev, rtwvif_link, start);
6535}
6536
6537static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev)
6538{
6539 const struct rtw89_chip_info *chip = rtwdev->chip;
6540
6541 if (chip->ops->rfk_track)
6542 chip->ops->rfk_track(rtwdev);
6543}
6544
6545static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev)
6546{
6547 const struct rtw89_chip_info *chip = rtwdev->chip;
6548
6549 if (!chip->ops->set_txpwr_ctrl)
6550 return;
6551
6552 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0);
6553 if (rtwdev->dbcc_en)
6554 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_1);
6555}
6556
6557static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev)
6558{
6559 const struct rtw89_chip_info *chip = rtwdev->chip;
6560
6561 if (chip->ops->power_trim)
6562 chip->ops->power_trim(rtwdev);
6563}
6564
6565static inline void __rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev,
6566 enum rtw89_phy_idx phy_idx)
6567{
6568 const struct rtw89_chip_info *chip = rtwdev->chip;
6569
6570 if (chip->ops->init_txpwr_unit)
6571 chip->ops->init_txpwr_unit(rtwdev, phy_idx);
6572}
6573
6574static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev)
6575{
6576 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0);
6577 if (rtwdev->dbcc_en)
6578 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_1);
6579}
6580
6581static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev,
6582 enum rtw89_rf_path rf_path)
6583{
6584 const struct rtw89_chip_info *chip = rtwdev->chip;
6585
6586 if (!chip->ops->get_thermal)
6587 return 0x10;
6588
6589 return chip->ops->get_thermal(rtwdev, rf_path);
6590}
6591
6592static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev,
6593 struct rtw89_rx_phy_ppdu *phy_ppdu,
6594 struct ieee80211_rx_status *status)
6595{
6596 const struct rtw89_chip_info *chip = rtwdev->chip;
6597
6598 if (chip->ops->query_ppdu)
6599 chip->ops->query_ppdu(rtwdev, phy_ppdu, status);
6600}
6601
6602static inline void rtw89_chip_convert_rpl_to_rssi(struct rtw89_dev *rtwdev,
6603 struct rtw89_rx_phy_ppdu *phy_ppdu)
6604{
6605 const struct rtw89_chip_info *chip = rtwdev->chip;
6606
6607 if (chip->ops->convert_rpl_to_rssi)
6608 chip->ops->convert_rpl_to_rssi(rtwdev, phy_ppdu);
6609}
6610
6611static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en,
6612 enum rtw89_phy_idx phy_idx)
6613{
6614 const struct rtw89_chip_info *chip = rtwdev->chip;
6615
6616 if (chip->ops->ctrl_nbtg_bt_tx)
6617 chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx);
6618}
6619
6620static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev)
6621{
6622 const struct rtw89_chip_info *chip = rtwdev->chip;
6623
6624 if (chip->ops->cfg_txrx_path)
6625 chip->ops->cfg_txrx_path(rtwdev);
6626}
6627
6628static inline void rtw89_chip_digital_pwr_comp(struct rtw89_dev *rtwdev,
6629 enum rtw89_phy_idx phy_idx)
6630{
6631 const struct rtw89_chip_info *chip = rtwdev->chip;
6632
6633 if (chip->ops->digital_pwr_comp)
6634 chip->ops->digital_pwr_comp(rtwdev, phy_idx);
6635}
6636
6637static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev,
6638 const struct rtw89_txpwr_table *tbl)
6639{
6640 tbl->load(rtwdev, tbl);
6641}
6642
6643static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band)
6644{
6645 const struct rtw89_regd *regd = rtwdev->regulatory.regd;
6646
6647 return regd->txpwr_regd[band];
6648}
6649
6650static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en,
6651 enum rtw89_phy_idx phy_idx)
6652{
6653 const struct rtw89_chip_info *chip = rtwdev->chip;
6654
6655 if (chip->ops->ctrl_btg_bt_rx)
6656 chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx);
6657}
6658
6659static inline
6660void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev,
6661 struct rtw89_rx_desc_info *desc_info,
6662 u8 *data, u32 data_offset)
6663{
6664 const struct rtw89_chip_info *chip = rtwdev->chip;
6665
6666 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset);
6667}
6668
6669static inline
6670void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev,
6671 struct rtw89_tx_desc_info *desc_info,
6672 void *txdesc)
6673{
6674 const struct rtw89_chip_info *chip = rtwdev->chip;
6675
6676 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc);
6677}
6678
6679static inline
6680void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev,
6681 struct rtw89_tx_desc_info *desc_info,
6682 void *txdesc)
6683{
6684 const struct rtw89_chip_info *chip = rtwdev->chip;
6685
6686 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc);
6687}
6688
6689static inline
6690void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev,
6691 const struct rtw89_mac_ax_coex_gnt *gnt_cfg)
6692{
6693 const struct rtw89_chip_info *chip = rtwdev->chip;
6694
6695 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg);
6696}
6697
6698static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl)
6699{
6700 const struct rtw89_chip_info *chip = rtwdev->chip;
6701
6702 chip->ops->cfg_ctrl_path(rtwdev, wl);
6703}
6704
6705static inline
6706int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,
6707 u32 *tx_en, enum rtw89_sch_tx_sel sel)
6708{
6709 const struct rtw89_chip_info *chip = rtwdev->chip;
6710
6711 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel);
6712}
6713
6714static inline
6715int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en)
6716{
6717 const struct rtw89_chip_info *chip = rtwdev->chip;
6718
6719 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en);
6720}
6721
6722static inline
6723int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev,
6724 struct rtw89_vif_link *rtwvif_link,
6725 struct rtw89_sta_link *rtwsta_link)
6726{
6727 const struct rtw89_chip_info *chip = rtwdev->chip;
6728
6729 if (!chip->ops->h2c_dctl_sec_cam)
6730 return 0;
6731 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif_link, rtwsta_link);
6732}
6733
6734static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr)
6735{
6736 __le16 fc = hdr->frame_control;
6737
6738 if (ieee80211_has_tods(fc))
6739 return hdr->addr1;
6740 else if (ieee80211_has_fromds(fc))
6741 return hdr->addr2;
6742 else
6743 return hdr->addr3;
6744}
6745
6746static inline
6747bool rtw89_sta_has_beamformer_cap(struct ieee80211_link_sta *link_sta)
6748{
6749 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) ||
6750 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) ||
6751 (link_sta->he_cap.he_cap_elem.phy_cap_info[3] &
6752 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) ||
6753 (link_sta->he_cap.he_cap_elem.phy_cap_info[4] &
6754 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER))
6755 return true;
6756 return false;
6757}
6758
6759static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev,
6760 enum rtw89_fw_type type)
6761{
6762 struct rtw89_fw_info *fw_info = &rtwdev->fw;
6763
6764 switch (type) {
6765 case RTW89_FW_WOWLAN:
6766 return &fw_info->wowlan;
6767 case RTW89_FW_LOGFMT:
6768 return &fw_info->log.suit;
6769 case RTW89_FW_BBMCU0:
6770 return &fw_info->bbmcu0;
6771 case RTW89_FW_BBMCU1:
6772 return &fw_info->bbmcu1;
6773 default:
6774 break;
6775 }
6776
6777 return &fw_info->normal;
6778}
6779
6780static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev,
6781 unsigned int length)
6782{
6783 struct sk_buff *skb;
6784
6785 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) {
6786 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM);
6787 if (!skb)
6788 return NULL;
6789
6790 skb_reserve(skb, RTW89_RADIOTAP_ROOM);
6791 return skb;
6792 }
6793
6794 return dev_alloc_skb(length);
6795}
6796
6797static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev,
6798 struct rtw89_tx_skb_data *skb_data,
6799 bool tx_done)
6800{
6801 struct rtw89_tx_wait_info *wait;
6802
6803 rcu_read_lock();
6804
6805 wait = rcu_dereference(skb_data->wait);
6806 if (!wait)
6807 goto out;
6808
6809 wait->tx_done = tx_done;
6810 complete(&wait->completion);
6811
6812out:
6813 rcu_read_unlock();
6814}
6815
6816static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev)
6817{
6818 switch (rtwdev->mlo_dbcc_mode) {
6819 case MLO_1_PLUS_1_1RF:
6820 case MLO_1_PLUS_1_2RF:
6821 case DBCC_LEGACY:
6822 return true;
6823 default:
6824 return false;
6825 }
6826}
6827
6828static inline bool rtw89_is_rtl885xb(struct rtw89_dev *rtwdev)
6829{
6830 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
6831
6832 if (chip_id == RTL8852B || chip_id == RTL8851B || chip_id == RTL8852BT)
6833 return true;
6834
6835 return false;
6836}
6837
6838int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
6839 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel);
6840int rtw89_h2c_tx(struct rtw89_dev *rtwdev,
6841 struct sk_buff *skb, bool fwdl);
6842void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel);
6843int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb,
6844 int qsel, unsigned int timeout);
6845void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev,
6846 struct rtw89_tx_desc_info *desc_info,
6847 void *txdesc);
6848void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev,
6849 struct rtw89_tx_desc_info *desc_info,
6850 void *txdesc);
6851void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev,
6852 struct rtw89_tx_desc_info *desc_info,
6853 void *txdesc);
6854void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev,
6855 struct rtw89_tx_desc_info *desc_info,
6856 void *txdesc);
6857void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev,
6858 struct rtw89_tx_desc_info *desc_info,
6859 void *txdesc);
6860void rtw89_core_rx(struct rtw89_dev *rtwdev,
6861 struct rtw89_rx_desc_info *desc_info,
6862 struct sk_buff *skb);
6863void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev,
6864 struct rtw89_rx_desc_info *desc_info,
6865 u8 *data, u32 data_offset);
6866void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev,
6867 struct rtw89_rx_desc_info *desc_info,
6868 u8 *data, u32 data_offset);
6869void rtw89_core_napi_start(struct rtw89_dev *rtwdev);
6870void rtw89_core_napi_stop(struct rtw89_dev *rtwdev);
6871int rtw89_core_napi_init(struct rtw89_dev *rtwdev);
6872void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev);
6873int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev,
6874 struct rtw89_vif_link *rtwvif_link,
6875 struct rtw89_sta_link *rtwsta_link);
6876int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev,
6877 struct rtw89_vif_link *rtwvif_link,
6878 struct rtw89_sta_link *rtwsta_link);
6879int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev,
6880 struct rtw89_vif_link *rtwvif_link,
6881 struct rtw89_sta_link *rtwsta_link);
6882int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev,
6883 struct rtw89_vif_link *rtwvif_link,
6884 struct rtw89_sta_link *rtwsta_link);
6885int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev,
6886 struct rtw89_vif_link *rtwvif_link,
6887 struct rtw89_sta_link *rtwsta_link);
6888void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
6889 struct ieee80211_sta *sta,
6890 struct cfg80211_tid_config *tid_config);
6891void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force);
6892void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks);
6893int rtw89_core_init(struct rtw89_dev *rtwdev);
6894void rtw89_core_deinit(struct rtw89_dev *rtwdev);
6895int rtw89_core_register(struct rtw89_dev *rtwdev);
6896void rtw89_core_unregister(struct rtw89_dev *rtwdev);
6897struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device,
6898 u32 bus_data_size,
6899 const struct rtw89_chip_info *chip);
6900void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev);
6901u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev);
6902void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id);
6903void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
6904 u8 mac_id, u8 port);
6905void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
6906 struct rtw89_sta *rtwsta, u8 mac_id);
6907struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif,
6908 unsigned int link_id);
6909void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id);
6910struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta,
6911 unsigned int link_id);
6912void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id);
6913void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev);
6914void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef);
6915void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef,
6916 struct rtw89_chan *chan);
6917int rtw89_set_channel(struct rtw89_dev *rtwdev);
6918u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size);
6919void rtw89_core_release_bit_map(unsigned long *addr, u8 bit);
6920void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits);
6921int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev,
6922 struct rtw89_sta_link *rtwsta_link, u8 tid,
6923 u8 *cam_idx);
6924int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev,
6925 struct rtw89_sta_link *rtwsta_link, u8 tid,
6926 u8 *cam_idx);
6927void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev,
6928 struct ieee80211_sta *sta);
6929void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev,
6930 struct ieee80211_sta *sta);
6931void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev,
6932 struct ieee80211_sta *sta);
6933void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc);
6934int rtw89_chip_info_setup(struct rtw89_dev *rtwdev);
6935void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
6936 struct rtw89_vif_link *rtwvif_link);
6937bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate);
6938int rtw89_regd_setup(struct rtw89_dev *rtwdev);
6939int rtw89_regd_init(struct rtw89_dev *rtwdev,
6940 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request));
6941void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request);
6942void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev,
6943 struct rtw89_traffic_stats *stats);
6944int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond);
6945void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond,
6946 const struct rtw89_completion_data *data);
6947int rtw89_core_start(struct rtw89_dev *rtwdev);
6948void rtw89_core_stop(struct rtw89_dev *rtwdev);
6949void rtw89_core_update_beacon_work(struct work_struct *work);
6950void rtw89_roc_work(struct work_struct *work);
6951void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
6952void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
6953void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
6954 const u8 *mac_addr, bool hw_scan);
6955void rtw89_core_scan_complete(struct rtw89_dev *rtwdev,
6956 struct rtw89_vif_link *rtwvif_link, bool hw_scan);
6957int rtw89_reg_6ghz_recalc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
6958 bool active);
6959void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev,
6960 struct rtw89_vif_link *rtwvif_link,
6961 struct ieee80211_bss_conf *bss_conf);
6962void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event);
6963
6964#endif