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1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19#include <linux/dma-mapping.h>
20#include <linux/slab.h>
21#include <linux/ath9k_platform.h>
22#include <linux/module.h>
23#include <linux/of.h>
24#include <linux/of_net.h>
25#include <linux/relay.h>
26#include <linux/dmi.h>
27#include <net/ieee80211_radiotap.h>
28
29#include "ath9k.h"
30
31struct ath9k_eeprom_ctx {
32 struct completion complete;
33 struct ath_hw *ah;
34};
35
36static char *dev_info = "ath9k";
37
38MODULE_AUTHOR("Atheros Communications");
39MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
40MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
41MODULE_LICENSE("Dual BSD/GPL");
42
43static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
44module_param_named(debug, ath9k_debug, uint, 0);
45MODULE_PARM_DESC(debug, "Debugging mask");
46
47int ath9k_modparam_nohwcrypt;
48module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444);
49MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
50
51int ath9k_led_blink;
52module_param_named(blink, ath9k_led_blink, int, 0444);
53MODULE_PARM_DESC(blink, "Enable LED blink on activity");
54
55static int ath9k_led_active_high = -1;
56module_param_named(led_active_high, ath9k_led_active_high, int, 0444);
57MODULE_PARM_DESC(led_active_high, "Invert LED polarity");
58
59static int ath9k_btcoex_enable;
60module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444);
61MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
62
63static int ath9k_bt_ant_diversity;
64module_param_named(bt_ant_diversity, ath9k_bt_ant_diversity, int, 0444);
65MODULE_PARM_DESC(bt_ant_diversity, "Enable WLAN/BT RX antenna diversity");
66
67static int ath9k_ps_enable;
68module_param_named(ps_enable, ath9k_ps_enable, int, 0444);
69MODULE_PARM_DESC(ps_enable, "Enable WLAN PowerSave");
70
71#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
72
73int ath9k_use_chanctx;
74module_param_named(use_chanctx, ath9k_use_chanctx, int, 0444);
75MODULE_PARM_DESC(use_chanctx, "Enable channel context for concurrency");
76
77#endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
78
79int ath9k_use_msi;
80module_param_named(use_msi, ath9k_use_msi, int, 0444);
81MODULE_PARM_DESC(use_msi, "Use MSI instead of INTx if possible");
82
83bool is_ath9k_unloaded;
84
85#ifdef CONFIG_MAC80211_LEDS
86static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = {
87 { .throughput = 0 * 1024, .blink_time = 334 },
88 { .throughput = 1 * 1024, .blink_time = 260 },
89 { .throughput = 5 * 1024, .blink_time = 220 },
90 { .throughput = 10 * 1024, .blink_time = 190 },
91 { .throughput = 20 * 1024, .blink_time = 170 },
92 { .throughput = 50 * 1024, .blink_time = 150 },
93 { .throughput = 70 * 1024, .blink_time = 130 },
94 { .throughput = 100 * 1024, .blink_time = 110 },
95 { .throughput = 200 * 1024, .blink_time = 80 },
96 { .throughput = 300 * 1024, .blink_time = 50 },
97};
98#endif
99
100static int __init set_use_msi(const struct dmi_system_id *dmi)
101{
102 ath9k_use_msi = 1;
103 return 1;
104}
105
106static const struct dmi_system_id ath9k_quirks[] __initconst = {
107 {
108 .callback = set_use_msi,
109 .ident = "Dell Inspiron 24-3460",
110 .matches = {
111 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
112 DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 24-3460"),
113 },
114 },
115 {
116 .callback = set_use_msi,
117 .ident = "Dell Vostro 3262",
118 .matches = {
119 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
120 DMI_MATCH(DMI_PRODUCT_NAME, "Vostro 3262"),
121 },
122 },
123 {
124 .callback = set_use_msi,
125 .ident = "Dell Inspiron 3472",
126 .matches = {
127 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
128 DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 3472"),
129 },
130 },
131 {
132 .callback = set_use_msi,
133 .ident = "Dell Vostro 15-3572",
134 .matches = {
135 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
136 DMI_MATCH(DMI_PRODUCT_NAME, "Vostro 15-3572"),
137 },
138 },
139 {
140 .callback = set_use_msi,
141 .ident = "Dell Inspiron 14-3473",
142 .matches = {
143 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
144 DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 14-3473"),
145 },
146 },
147 {}
148};
149
150static void ath9k_deinit_softc(struct ath_softc *sc);
151
152static void ath9k_op_ps_wakeup(struct ath_common *common)
153{
154 ath9k_ps_wakeup((struct ath_softc *) common->priv);
155}
156
157static void ath9k_op_ps_restore(struct ath_common *common)
158{
159 ath9k_ps_restore((struct ath_softc *) common->priv);
160}
161
162static const struct ath_ps_ops ath9k_ps_ops = {
163 .wakeup = ath9k_op_ps_wakeup,
164 .restore = ath9k_op_ps_restore,
165};
166
167/*
168 * Read and write, they both share the same lock. We do this to serialize
169 * reads and writes on Atheros 802.11n PCI devices only. This is required
170 * as the FIFO on these devices can only accept sanely 2 requests.
171 */
172
173static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
174{
175 struct ath_hw *ah = hw_priv;
176 struct ath_common *common = ath9k_hw_common(ah);
177 struct ath_softc *sc = (struct ath_softc *) common->priv;
178
179 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
180 unsigned long flags;
181 spin_lock_irqsave(&sc->sc_serial_rw, flags);
182 iowrite32(val, sc->mem + reg_offset);
183 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
184 } else
185 iowrite32(val, sc->mem + reg_offset);
186}
187
188static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
189{
190 struct ath_hw *ah = hw_priv;
191 struct ath_common *common = ath9k_hw_common(ah);
192 struct ath_softc *sc = (struct ath_softc *) common->priv;
193 u32 val;
194
195 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
196 unsigned long flags;
197 spin_lock_irqsave(&sc->sc_serial_rw, flags);
198 val = ioread32(sc->mem + reg_offset);
199 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
200 } else
201 val = ioread32(sc->mem + reg_offset);
202 return val;
203}
204
205static void ath9k_multi_ioread32(void *hw_priv, u32 *addr,
206 u32 *val, u16 count)
207{
208 int i;
209
210 for (i = 0; i < count; i++)
211 val[i] = ath9k_ioread32(hw_priv, addr[i]);
212}
213
214
215static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset,
216 u32 set, u32 clr)
217{
218 u32 val;
219
220 val = ioread32(sc->mem + reg_offset);
221 val &= ~clr;
222 val |= set;
223 iowrite32(val, sc->mem + reg_offset);
224
225 return val;
226}
227
228static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
229{
230 struct ath_hw *ah = hw_priv;
231 struct ath_common *common = ath9k_hw_common(ah);
232 struct ath_softc *sc = (struct ath_softc *) common->priv;
233 unsigned long uninitialized_var(flags);
234 u32 val;
235
236 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
237 spin_lock_irqsave(&sc->sc_serial_rw, flags);
238 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
239 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
240 } else
241 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
242
243 return val;
244}
245
246/**************************/
247/* Initialization */
248/**************************/
249
250static void ath9k_reg_notifier(struct wiphy *wiphy,
251 struct regulatory_request *request)
252{
253 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
254 struct ath_softc *sc = hw->priv;
255 struct ath_hw *ah = sc->sc_ah;
256 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
257
258 ath_reg_notifier_apply(wiphy, request, reg);
259
260 /* synchronize DFS detector if regulatory domain changed */
261 if (sc->dfs_detector != NULL)
262 sc->dfs_detector->set_dfs_domain(sc->dfs_detector,
263 request->dfs_region);
264
265 /* Set tx power */
266 if (!ah->curchan)
267 return;
268
269 sc->cur_chan->txpower = 2 * ah->curchan->chan->max_power;
270 ath9k_ps_wakeup(sc);
271 ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);
272 ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
273 sc->cur_chan->txpower,
274 &sc->cur_chan->cur_txpower);
275 ath9k_ps_restore(sc);
276}
277
278/*
279 * This function will allocate both the DMA descriptor structure, and the
280 * buffers it contains. These are used to contain the descriptors used
281 * by the system.
282*/
283int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
284 struct list_head *head, const char *name,
285 int nbuf, int ndesc, bool is_tx)
286{
287 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
288 u8 *ds;
289 int i, bsize, desc_len;
290
291 ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n",
292 name, nbuf, ndesc);
293
294 INIT_LIST_HEAD(head);
295
296 if (is_tx)
297 desc_len = sc->sc_ah->caps.tx_desc_len;
298 else
299 desc_len = sizeof(struct ath_desc);
300
301 /* ath_desc must be a multiple of DWORDs */
302 if ((desc_len % 4) != 0) {
303 ath_err(common, "ath_desc not DWORD aligned\n");
304 BUG_ON((desc_len % 4) != 0);
305 return -ENOMEM;
306 }
307
308 dd->dd_desc_len = desc_len * nbuf * ndesc;
309
310 /*
311 * Need additional DMA memory because we can't use
312 * descriptors that cross the 4K page boundary. Assume
313 * one skipped descriptor per 4K page.
314 */
315 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
316 u32 ndesc_skipped =
317 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
318 u32 dma_len;
319
320 while (ndesc_skipped) {
321 dma_len = ndesc_skipped * desc_len;
322 dd->dd_desc_len += dma_len;
323
324 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
325 }
326 }
327
328 /* allocate descriptors */
329 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
330 &dd->dd_desc_paddr, GFP_KERNEL);
331 if (!dd->dd_desc)
332 return -ENOMEM;
333
334 ds = dd->dd_desc;
335 ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
336 name, ds, (u32) dd->dd_desc_len,
337 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
338
339 /* allocate buffers */
340 if (is_tx) {
341 struct ath_buf *bf;
342
343 bsize = sizeof(struct ath_buf) * nbuf;
344 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);
345 if (!bf)
346 return -ENOMEM;
347
348 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
349 bf->bf_desc = ds;
350 bf->bf_daddr = DS2PHYS(dd, ds);
351
352 if (!(sc->sc_ah->caps.hw_caps &
353 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
354 /*
355 * Skip descriptor addresses which can cause 4KB
356 * boundary crossing (addr + length) with a 32 dword
357 * descriptor fetch.
358 */
359 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
360 BUG_ON((caddr_t) bf->bf_desc >=
361 ((caddr_t) dd->dd_desc +
362 dd->dd_desc_len));
363
364 ds += (desc_len * ndesc);
365 bf->bf_desc = ds;
366 bf->bf_daddr = DS2PHYS(dd, ds);
367 }
368 }
369 list_add_tail(&bf->list, head);
370 }
371 } else {
372 struct ath_rxbuf *bf;
373
374 bsize = sizeof(struct ath_rxbuf) * nbuf;
375 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);
376 if (!bf)
377 return -ENOMEM;
378
379 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
380 bf->bf_desc = ds;
381 bf->bf_daddr = DS2PHYS(dd, ds);
382
383 if (!(sc->sc_ah->caps.hw_caps &
384 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
385 /*
386 * Skip descriptor addresses which can cause 4KB
387 * boundary crossing (addr + length) with a 32 dword
388 * descriptor fetch.
389 */
390 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
391 BUG_ON((caddr_t) bf->bf_desc >=
392 ((caddr_t) dd->dd_desc +
393 dd->dd_desc_len));
394
395 ds += (desc_len * ndesc);
396 bf->bf_desc = ds;
397 bf->bf_daddr = DS2PHYS(dd, ds);
398 }
399 }
400 list_add_tail(&bf->list, head);
401 }
402 }
403 return 0;
404}
405
406static int ath9k_init_queues(struct ath_softc *sc)
407{
408 int i = 0;
409
410 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
411 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
412 ath_cabq_update(sc);
413
414 sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0);
415
416 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
417 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
418 sc->tx.txq_map[i]->mac80211_qnum = i;
419 }
420 return 0;
421}
422
423static void ath9k_init_misc(struct ath_softc *sc)
424{
425 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
426 int i = 0;
427
428 timer_setup(&common->ani.timer, ath_ani_calibrate, 0);
429
430 common->last_rssi = ATH_RSSI_DUMMY_MARKER;
431 eth_broadcast_addr(common->bssidmask);
432 sc->beacon.slottime = 9;
433
434 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
435 sc->beacon.bslot[i] = NULL;
436
437 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
438 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT;
439
440 sc->spec_priv.ah = sc->sc_ah;
441 sc->spec_priv.spec_config.enabled = 0;
442 sc->spec_priv.spec_config.short_repeat = true;
443 sc->spec_priv.spec_config.count = 8;
444 sc->spec_priv.spec_config.endless = false;
445 sc->spec_priv.spec_config.period = 0xFF;
446 sc->spec_priv.spec_config.fft_period = 0xF;
447}
448
449static void ath9k_init_pcoem_platform(struct ath_softc *sc)
450{
451 struct ath_hw *ah = sc->sc_ah;
452 struct ath9k_hw_capabilities *pCap = &ah->caps;
453 struct ath_common *common = ath9k_hw_common(ah);
454
455 if (!IS_ENABLED(CONFIG_ATH9K_PCOEM))
456 return;
457
458 if (common->bus_ops->ath_bus_type != ATH_PCI)
459 return;
460
461 if (sc->driver_data & (ATH9K_PCI_CUS198 |
462 ATH9K_PCI_CUS230)) {
463 ah->config.xlna_gpio = 9;
464 ah->config.xatten_margin_cfg = true;
465 ah->config.alt_mingainidx = true;
466 ah->config.ant_ctrl_comm2g_switch_enable = 0x000BBB88;
467 sc->ant_comb.low_rssi_thresh = 20;
468 sc->ant_comb.fast_div_bias = 3;
469
470 ath_info(common, "Set parameters for %s\n",
471 (sc->driver_data & ATH9K_PCI_CUS198) ?
472 "CUS198" : "CUS230");
473 }
474
475 if (sc->driver_data & ATH9K_PCI_CUS217)
476 ath_info(common, "CUS217 card detected\n");
477
478 if (sc->driver_data & ATH9K_PCI_CUS252)
479 ath_info(common, "CUS252 card detected\n");
480
481 if (sc->driver_data & ATH9K_PCI_AR9565_1ANT)
482 ath_info(common, "WB335 1-ANT card detected\n");
483
484 if (sc->driver_data & ATH9K_PCI_AR9565_2ANT)
485 ath_info(common, "WB335 2-ANT card detected\n");
486
487 if (sc->driver_data & ATH9K_PCI_KILLER)
488 ath_info(common, "Killer Wireless card detected\n");
489
490 /*
491 * Some WB335 cards do not support antenna diversity. Since
492 * we use a hardcoded value for AR9565 instead of using the
493 * EEPROM/OTP data, remove the combining feature from
494 * the HW capabilities bitmap.
495 */
496 if (sc->driver_data & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) {
497 if (!(sc->driver_data & ATH9K_PCI_BT_ANT_DIV))
498 pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB;
499 }
500
501 if (sc->driver_data & ATH9K_PCI_BT_ANT_DIV) {
502 pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV;
503 ath_info(common, "Set BT/WLAN RX diversity capability\n");
504 }
505
506 if (sc->driver_data & ATH9K_PCI_D3_L1_WAR) {
507 ah->config.pcie_waen = 0x0040473b;
508 ath_info(common, "Enable WAR for ASPM D3/L1\n");
509 }
510
511 /*
512 * The default value of pll_pwrsave is 1.
513 * For certain AR9485 cards, it is set to 0.
514 * For AR9462, AR9565 it's set to 7.
515 */
516 ah->config.pll_pwrsave = 1;
517
518 if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) {
519 ah->config.pll_pwrsave = 0;
520 ath_info(common, "Disable PLL PowerSave\n");
521 }
522
523 if (sc->driver_data & ATH9K_PCI_LED_ACT_HI)
524 ah->config.led_active_high = true;
525}
526
527static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob,
528 void *ctx)
529{
530 struct ath9k_eeprom_ctx *ec = ctx;
531
532 if (eeprom_blob)
533 ec->ah->eeprom_blob = eeprom_blob;
534
535 complete(&ec->complete);
536}
537
538static int ath9k_eeprom_request(struct ath_softc *sc, const char *name)
539{
540 struct ath9k_eeprom_ctx ec;
541 struct ath_hw *ah = sc->sc_ah;
542 int err;
543
544 /* try to load the EEPROM content asynchronously */
545 init_completion(&ec.complete);
546 ec.ah = sc->sc_ah;
547
548 err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL,
549 &ec, ath9k_eeprom_request_cb);
550 if (err < 0) {
551 ath_err(ath9k_hw_common(ah),
552 "EEPROM request failed\n");
553 return err;
554 }
555
556 wait_for_completion(&ec.complete);
557
558 if (!ah->eeprom_blob) {
559 ath_err(ath9k_hw_common(ah),
560 "Unable to load EEPROM file %s\n", name);
561 return -EINVAL;
562 }
563
564 return 0;
565}
566
567static void ath9k_eeprom_release(struct ath_softc *sc)
568{
569 release_firmware(sc->sc_ah->eeprom_blob);
570}
571
572static int ath9k_init_platform(struct ath_softc *sc)
573{
574 struct ath9k_platform_data *pdata = sc->dev->platform_data;
575 struct ath_hw *ah = sc->sc_ah;
576 struct ath_common *common = ath9k_hw_common(ah);
577 int ret;
578
579 if (!pdata)
580 return 0;
581
582 if (!pdata->use_eeprom) {
583 ah->ah_flags &= ~AH_USE_EEPROM;
584 ah->gpio_mask = pdata->gpio_mask;
585 ah->gpio_val = pdata->gpio_val;
586 ah->led_pin = pdata->led_pin;
587 ah->is_clk_25mhz = pdata->is_clk_25mhz;
588 ah->get_mac_revision = pdata->get_mac_revision;
589 ah->external_reset = pdata->external_reset;
590 ah->disable_2ghz = pdata->disable_2ghz;
591 ah->disable_5ghz = pdata->disable_5ghz;
592
593 if (!pdata->endian_check)
594 ah->ah_flags |= AH_NO_EEP_SWAP;
595 }
596
597 if (pdata->eeprom_name) {
598 ret = ath9k_eeprom_request(sc, pdata->eeprom_name);
599 if (ret)
600 return ret;
601 }
602
603 if (pdata->led_active_high)
604 ah->config.led_active_high = true;
605
606 if (pdata->tx_gain_buffalo)
607 ah->config.tx_gain_buffalo = true;
608
609 if (pdata->macaddr)
610 ether_addr_copy(common->macaddr, pdata->macaddr);
611
612 return 0;
613}
614
615static int ath9k_of_init(struct ath_softc *sc)
616{
617 struct device_node *np = sc->dev->of_node;
618 struct ath_hw *ah = sc->sc_ah;
619 struct ath_common *common = ath9k_hw_common(ah);
620 enum ath_bus_type bus_type = common->bus_ops->ath_bus_type;
621 const char *mac;
622 char eeprom_name[100];
623 int ret;
624
625 if (!of_device_is_available(np))
626 return 0;
627
628 ath_dbg(common, CONFIG, "parsing configuration from OF node\n");
629
630 if (of_property_read_bool(np, "qca,no-eeprom")) {
631 /* ath9k-eeprom-<bus>-<id>.bin */
632 scnprintf(eeprom_name, sizeof(eeprom_name),
633 "ath9k-eeprom-%s-%s.bin",
634 ath_bus_type_to_string(bus_type), dev_name(ah->dev));
635
636 ret = ath9k_eeprom_request(sc, eeprom_name);
637 if (ret)
638 return ret;
639 }
640
641 mac = of_get_mac_address(np);
642 if (mac)
643 ether_addr_copy(common->macaddr, mac);
644
645 ah->ah_flags &= ~AH_USE_EEPROM;
646 ah->ah_flags |= AH_NO_EEP_SWAP;
647
648 return 0;
649}
650
651static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
652 const struct ath_bus_ops *bus_ops)
653{
654 struct ath_hw *ah = NULL;
655 struct ath9k_hw_capabilities *pCap;
656 struct ath_common *common;
657 int ret = 0, i;
658 int csz = 0;
659
660 ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL);
661 if (!ah)
662 return -ENOMEM;
663
664 ah->dev = sc->dev;
665 ah->hw = sc->hw;
666 ah->hw_version.devid = devid;
667 ah->ah_flags |= AH_USE_EEPROM;
668 ah->led_pin = -1;
669 ah->reg_ops.read = ath9k_ioread32;
670 ah->reg_ops.multi_read = ath9k_multi_ioread32;
671 ah->reg_ops.write = ath9k_iowrite32;
672 ah->reg_ops.rmw = ath9k_reg_rmw;
673 pCap = &ah->caps;
674
675 common = ath9k_hw_common(ah);
676
677 /* Will be cleared in ath9k_start() */
678 set_bit(ATH_OP_INVALID, &common->op_flags);
679 sc->airtime_flags = (AIRTIME_USE_TX | AIRTIME_USE_RX |
680 AIRTIME_USE_NEW_QUEUES);
681
682 sc->sc_ah = ah;
683 sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET);
684 sc->tx99_power = MAX_RATE_POWER + 1;
685 init_waitqueue_head(&sc->tx_wait);
686 sc->cur_chan = &sc->chanctx[0];
687 if (!ath9k_is_chanctx_enabled())
688 sc->cur_chan->hw_queue_base = 0;
689
690 common->ops = &ah->reg_ops;
691 common->bus_ops = bus_ops;
692 common->ps_ops = &ath9k_ps_ops;
693 common->ah = ah;
694 common->hw = sc->hw;
695 common->priv = sc;
696 common->debug_mask = ath9k_debug;
697 common->btcoex_enabled = ath9k_btcoex_enable == 1;
698 common->disable_ani = false;
699
700 /*
701 * Platform quirks.
702 */
703 ath9k_init_pcoem_platform(sc);
704
705 ret = ath9k_init_platform(sc);
706 if (ret)
707 return ret;
708
709 ret = ath9k_of_init(sc);
710 if (ret)
711 return ret;
712
713 if (ath9k_led_active_high != -1)
714 ah->config.led_active_high = ath9k_led_active_high == 1;
715
716 /*
717 * Enable WLAN/BT RX Antenna diversity only when:
718 *
719 * - BTCOEX is disabled.
720 * - the user manually requests the feature.
721 * - the HW cap is set using the platform data.
722 */
723 if (!common->btcoex_enabled && ath9k_bt_ant_diversity &&
724 (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV))
725 common->bt_ant_diversity = 1;
726
727 spin_lock_init(&common->cc_lock);
728 spin_lock_init(&sc->intr_lock);
729 spin_lock_init(&sc->sc_serial_rw);
730 spin_lock_init(&sc->sc_pm_lock);
731 spin_lock_init(&sc->chan_lock);
732 mutex_init(&sc->mutex);
733 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
734 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
735 (unsigned long)sc);
736
737 timer_setup(&sc->sleep_timer, ath_ps_full_sleep, 0);
738 INIT_WORK(&sc->hw_reset_work, ath_reset_work);
739 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
740 INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work);
741 INIT_DELAYED_WORK(&sc->hw_check_work, ath_hw_check_work);
742
743 ath9k_init_channel_context(sc);
744
745 /*
746 * Cache line size is used to size and align various
747 * structures used to communicate with the hardware.
748 */
749 ath_read_cachesize(common, &csz);
750 common->cachelsz = csz << 2; /* convert to bytes */
751
752 /* Initializes the hardware for all supported chipsets */
753 ret = ath9k_hw_init(ah);
754 if (ret)
755 goto err_hw;
756
757 ret = ath9k_init_queues(sc);
758 if (ret)
759 goto err_queues;
760
761 ret = ath9k_init_btcoex(sc);
762 if (ret)
763 goto err_btcoex;
764
765 ret = ath9k_cmn_init_channels_rates(common);
766 if (ret)
767 goto err_btcoex;
768
769 ret = ath9k_init_p2p(sc);
770 if (ret)
771 goto err_btcoex;
772
773 ath9k_cmn_init_crypto(sc->sc_ah);
774 ath9k_init_misc(sc);
775 ath_chanctx_init(sc);
776 ath9k_offchannel_init(sc);
777
778 if (common->bus_ops->aspm_init)
779 common->bus_ops->aspm_init(common);
780
781 return 0;
782
783err_btcoex:
784 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
785 if (ATH_TXQ_SETUP(sc, i))
786 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
787err_queues:
788 ath9k_hw_deinit(ah);
789err_hw:
790 ath9k_eeprom_release(sc);
791 dev_kfree_skb_any(sc->tx99_skb);
792 return ret;
793}
794
795static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
796{
797 struct ieee80211_supported_band *sband;
798 struct ieee80211_channel *chan;
799 struct ath_hw *ah = sc->sc_ah;
800 struct ath_common *common = ath9k_hw_common(ah);
801 struct cfg80211_chan_def chandef;
802 int i;
803
804 sband = &common->sbands[band];
805 for (i = 0; i < sband->n_channels; i++) {
806 chan = &sband->channels[i];
807 ah->curchan = &ah->channels[chan->hw_value];
808 cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_HT20);
809 ath9k_cmn_get_channel(sc->hw, ah, &chandef);
810 ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true);
811 }
812}
813
814static void ath9k_init_txpower_limits(struct ath_softc *sc)
815{
816 struct ath_hw *ah = sc->sc_ah;
817 struct ath9k_channel *curchan = ah->curchan;
818
819 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
820 ath9k_init_band_txpower(sc, NL80211_BAND_2GHZ);
821 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
822 ath9k_init_band_txpower(sc, NL80211_BAND_5GHZ);
823
824 ah->curchan = curchan;
825}
826
827static const struct ieee80211_iface_limit if_limits[] = {
828 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) },
829 { .max = 8, .types =
830#ifdef CONFIG_MAC80211_MESH
831 BIT(NL80211_IFTYPE_MESH_POINT) |
832#endif
833 BIT(NL80211_IFTYPE_AP) },
834 { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_CLIENT) |
835 BIT(NL80211_IFTYPE_P2P_GO) },
836};
837
838#ifdef CONFIG_WIRELESS_WDS
839static const struct ieee80211_iface_limit wds_limits[] = {
840 { .max = 2048, .types = BIT(NL80211_IFTYPE_WDS) },
841};
842#endif
843
844#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
845
846static const struct ieee80211_iface_limit if_limits_multi[] = {
847 { .max = 2, .types = BIT(NL80211_IFTYPE_STATION) |
848 BIT(NL80211_IFTYPE_AP) |
849 BIT(NL80211_IFTYPE_P2P_CLIENT) |
850 BIT(NL80211_IFTYPE_P2P_GO) },
851 { .max = 1, .types = BIT(NL80211_IFTYPE_ADHOC) },
852 { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_DEVICE) },
853};
854
855static const struct ieee80211_iface_combination if_comb_multi[] = {
856 {
857 .limits = if_limits_multi,
858 .n_limits = ARRAY_SIZE(if_limits_multi),
859 .max_interfaces = 3,
860 .num_different_channels = 2,
861 .beacon_int_infra_match = true,
862 },
863};
864
865#endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
866
867static const struct ieee80211_iface_combination if_comb[] = {
868 {
869 .limits = if_limits,
870 .n_limits = ARRAY_SIZE(if_limits),
871 .max_interfaces = 2048,
872 .num_different_channels = 1,
873 .beacon_int_infra_match = true,
874#ifdef CONFIG_ATH9K_DFS_CERTIFIED
875 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
876 BIT(NL80211_CHAN_WIDTH_20) |
877 BIT(NL80211_CHAN_WIDTH_40),
878#endif
879 },
880#ifdef CONFIG_WIRELESS_WDS
881 {
882 .limits = wds_limits,
883 .n_limits = ARRAY_SIZE(wds_limits),
884 .max_interfaces = 2048,
885 .num_different_channels = 1,
886 .beacon_int_infra_match = true,
887 },
888#endif
889};
890
891#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
892static void ath9k_set_mcc_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
893{
894 struct ath_hw *ah = sc->sc_ah;
895 struct ath_common *common = ath9k_hw_common(ah);
896
897 if (!ath9k_is_chanctx_enabled())
898 return;
899
900 ieee80211_hw_set(hw, QUEUE_CONTROL);
901 hw->queues = ATH9K_NUM_TX_QUEUES;
902 hw->offchannel_tx_hw_queue = hw->queues - 1;
903 hw->wiphy->interface_modes &= ~ BIT(NL80211_IFTYPE_WDS);
904 hw->wiphy->iface_combinations = if_comb_multi;
905 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb_multi);
906 hw->wiphy->max_scan_ssids = 255;
907 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
908 hw->wiphy->max_remain_on_channel_duration = 10000;
909 hw->chanctx_data_size = sizeof(void *);
910 hw->extra_beacon_tailroom =
911 sizeof(struct ieee80211_p2p_noa_attr) + 9;
912
913 ath_dbg(common, CHAN_CTX, "Use channel contexts\n");
914}
915#endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
916
917static void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
918{
919 struct ath_hw *ah = sc->sc_ah;
920 struct ath_common *common = ath9k_hw_common(ah);
921
922 ieee80211_hw_set(hw, SUPPORTS_HT_CCK_RATES);
923 ieee80211_hw_set(hw, SUPPORTS_RC_TABLE);
924 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
925 ieee80211_hw_set(hw, SPECTRUM_MGMT);
926 ieee80211_hw_set(hw, PS_NULLFUNC_STACK);
927 ieee80211_hw_set(hw, SIGNAL_DBM);
928 ieee80211_hw_set(hw, RX_INCLUDES_FCS);
929 ieee80211_hw_set(hw, HOST_BROADCAST_PS_BUFFERING);
930 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
931 ieee80211_hw_set(hw, SUPPORTS_CLONED_SKBS);
932
933 if (ath9k_ps_enable)
934 ieee80211_hw_set(hw, SUPPORTS_PS);
935
936 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
937 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
938
939 if (AR_SREV_9280_20_OR_LATER(ah))
940 hw->radiotap_mcs_details |=
941 IEEE80211_RADIOTAP_MCS_HAVE_STBC;
942 }
943
944 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt)
945 ieee80211_hw_set(hw, MFP_CAPABLE);
946
947 hw->wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR |
948 NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE |
949 NL80211_FEATURE_P2P_GO_CTWIN;
950
951 if (!IS_ENABLED(CONFIG_ATH9K_TX99)) {
952 hw->wiphy->interface_modes =
953 BIT(NL80211_IFTYPE_P2P_GO) |
954 BIT(NL80211_IFTYPE_P2P_CLIENT) |
955 BIT(NL80211_IFTYPE_AP) |
956 BIT(NL80211_IFTYPE_STATION) |
957 BIT(NL80211_IFTYPE_ADHOC) |
958 BIT(NL80211_IFTYPE_MESH_POINT) |
959#ifdef CONFIG_WIRELESS_WDS
960 BIT(NL80211_IFTYPE_WDS) |
961#endif
962 BIT(NL80211_IFTYPE_OCB);
963
964 if (ath9k_is_chanctx_enabled())
965 hw->wiphy->interface_modes |=
966 BIT(NL80211_IFTYPE_P2P_DEVICE);
967
968 hw->wiphy->iface_combinations = if_comb;
969 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
970 }
971
972 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
973
974 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
975 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
976 hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
977 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ;
978 hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
979 hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD;
980
981 hw->queues = 4;
982 hw->max_rates = 4;
983 hw->max_listen_interval = 10;
984 hw->max_rate_tries = 10;
985 hw->sta_data_size = sizeof(struct ath_node);
986 hw->vif_data_size = sizeof(struct ath_vif);
987 hw->txq_data_size = sizeof(struct ath_atx_tid);
988 hw->extra_tx_headroom = 4;
989
990 hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1;
991 hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1;
992
993 /* single chain devices with rx diversity */
994 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
995 hw->wiphy->available_antennas_rx = BIT(0) | BIT(1);
996
997 sc->ant_rx = hw->wiphy->available_antennas_rx;
998 sc->ant_tx = hw->wiphy->available_antennas_tx;
999
1000 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
1001 hw->wiphy->bands[NL80211_BAND_2GHZ] =
1002 &common->sbands[NL80211_BAND_2GHZ];
1003 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
1004 hw->wiphy->bands[NL80211_BAND_5GHZ] =
1005 &common->sbands[NL80211_BAND_5GHZ];
1006
1007#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1008 ath9k_set_mcc_capab(sc, hw);
1009#endif
1010 ath9k_init_wow(hw);
1011 ath9k_cmn_reload_chainmask(ah);
1012
1013 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
1014
1015 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
1016}
1017
1018int ath9k_init_device(u16 devid, struct ath_softc *sc,
1019 const struct ath_bus_ops *bus_ops)
1020{
1021 struct ieee80211_hw *hw = sc->hw;
1022 struct ath_common *common;
1023 struct ath_hw *ah;
1024 int error = 0;
1025 struct ath_regulatory *reg;
1026
1027 /* Bring up device */
1028 error = ath9k_init_softc(devid, sc, bus_ops);
1029 if (error)
1030 return error;
1031
1032 ah = sc->sc_ah;
1033 common = ath9k_hw_common(ah);
1034 ath9k_set_hw_capab(sc, hw);
1035
1036 /* Initialize regulatory */
1037 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
1038 ath9k_reg_notifier);
1039 if (error)
1040 goto deinit;
1041
1042 reg = &common->regulatory;
1043
1044 /* Setup TX DMA */
1045 error = ath_tx_init(sc, ATH_TXBUF);
1046 if (error != 0)
1047 goto deinit;
1048
1049 /* Setup RX DMA */
1050 error = ath_rx_init(sc, ATH_RXBUF);
1051 if (error != 0)
1052 goto deinit;
1053
1054 ath9k_init_txpower_limits(sc);
1055
1056#ifdef CONFIG_MAC80211_LEDS
1057 /* must be initialized before ieee80211_register_hw */
1058 sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw,
1059 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink,
1060 ARRAY_SIZE(ath9k_tpt_blink));
1061#endif
1062
1063 /* Register with mac80211 */
1064 error = ieee80211_register_hw(hw);
1065 if (error)
1066 goto rx_cleanup;
1067
1068 error = ath9k_init_debug(ah);
1069 if (error) {
1070 ath_err(common, "Unable to create debugfs files\n");
1071 goto unregister;
1072 }
1073
1074 /* Handle world regulatory */
1075 if (!ath_is_world_regd(reg)) {
1076 error = regulatory_hint(hw->wiphy, reg->alpha2);
1077 if (error)
1078 goto debug_cleanup;
1079 }
1080
1081 ath_init_leds(sc);
1082 ath_start_rfkill_poll(sc);
1083
1084 return 0;
1085
1086debug_cleanup:
1087 ath9k_deinit_debug(sc);
1088unregister:
1089 ieee80211_unregister_hw(hw);
1090rx_cleanup:
1091 ath_rx_cleanup(sc);
1092deinit:
1093 ath9k_deinit_softc(sc);
1094 return error;
1095}
1096
1097/*****************************/
1098/* De-Initialization */
1099/*****************************/
1100
1101static void ath9k_deinit_softc(struct ath_softc *sc)
1102{
1103 int i = 0;
1104
1105 ath9k_deinit_p2p(sc);
1106 ath9k_deinit_btcoex(sc);
1107
1108 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1109 if (ATH_TXQ_SETUP(sc, i))
1110 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1111
1112 del_timer_sync(&sc->sleep_timer);
1113 ath9k_hw_deinit(sc->sc_ah);
1114 if (sc->dfs_detector != NULL)
1115 sc->dfs_detector->exit(sc->dfs_detector);
1116
1117 ath9k_eeprom_release(sc);
1118}
1119
1120void ath9k_deinit_device(struct ath_softc *sc)
1121{
1122 struct ieee80211_hw *hw = sc->hw;
1123
1124 ath9k_ps_wakeup(sc);
1125
1126 wiphy_rfkill_stop_polling(sc->hw->wiphy);
1127 ath_deinit_leds(sc);
1128
1129 ath9k_ps_restore(sc);
1130
1131 ath9k_deinit_debug(sc);
1132 ath9k_deinit_wow(hw);
1133 ieee80211_unregister_hw(hw);
1134 ath_rx_cleanup(sc);
1135 ath9k_deinit_softc(sc);
1136}
1137
1138/************************/
1139/* Module Hooks */
1140/************************/
1141
1142static int __init ath9k_init(void)
1143{
1144 int error;
1145
1146 error = ath_pci_init();
1147 if (error < 0) {
1148 pr_err("No PCI devices found, driver not installed\n");
1149 error = -ENODEV;
1150 goto err_out;
1151 }
1152
1153 error = ath_ahb_init();
1154 if (error < 0) {
1155 error = -ENODEV;
1156 goto err_pci_exit;
1157 }
1158
1159 dmi_check_system(ath9k_quirks);
1160
1161 return 0;
1162
1163 err_pci_exit:
1164 ath_pci_exit();
1165 err_out:
1166 return error;
1167}
1168module_init(ath9k_init);
1169
1170static void __exit ath9k_exit(void)
1171{
1172 is_ath9k_unloaded = true;
1173 ath_ahb_exit();
1174 ath_pci_exit();
1175 pr_info("%s: Driver unloaded\n", dev_info);
1176}
1177module_exit(ath9k_exit);
1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19#include <linux/dma-mapping.h>
20#include <linux/slab.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/of_net.h>
24#include <linux/nvmem-consumer.h>
25#include <linux/relay.h>
26#include <linux/dmi.h>
27#include <net/ieee80211_radiotap.h>
28
29#include "ath9k.h"
30
31struct ath9k_eeprom_ctx {
32 struct completion complete;
33 struct ath_hw *ah;
34};
35
36static char *dev_info = "ath9k";
37
38MODULE_AUTHOR("Atheros Communications");
39MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
40MODULE_LICENSE("Dual BSD/GPL");
41
42static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
43module_param_named(debug, ath9k_debug, uint, 0);
44MODULE_PARM_DESC(debug, "Debugging mask");
45
46int ath9k_modparam_nohwcrypt;
47module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444);
48MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
49
50int ath9k_led_blink;
51module_param_named(blink, ath9k_led_blink, int, 0444);
52MODULE_PARM_DESC(blink, "Enable LED blink on activity");
53
54static int ath9k_led_active_high = -1;
55module_param_named(led_active_high, ath9k_led_active_high, int, 0444);
56MODULE_PARM_DESC(led_active_high, "Invert LED polarity");
57
58static int ath9k_btcoex_enable;
59module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444);
60MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
61
62static int ath9k_bt_ant_diversity;
63module_param_named(bt_ant_diversity, ath9k_bt_ant_diversity, int, 0444);
64MODULE_PARM_DESC(bt_ant_diversity, "Enable WLAN/BT RX antenna diversity");
65
66static int ath9k_ps_enable;
67module_param_named(ps_enable, ath9k_ps_enable, int, 0444);
68MODULE_PARM_DESC(ps_enable, "Enable WLAN PowerSave");
69
70#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
71
72int ath9k_use_chanctx;
73module_param_named(use_chanctx, ath9k_use_chanctx, int, 0444);
74MODULE_PARM_DESC(use_chanctx, "Enable channel context for concurrency");
75
76#endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
77
78int ath9k_use_msi;
79module_param_named(use_msi, ath9k_use_msi, int, 0444);
80MODULE_PARM_DESC(use_msi, "Use MSI instead of INTx if possible");
81
82bool is_ath9k_unloaded;
83
84#ifdef CONFIG_MAC80211_LEDS
85static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = {
86 { .throughput = 0 * 1024, .blink_time = 334 },
87 { .throughput = 1 * 1024, .blink_time = 260 },
88 { .throughput = 5 * 1024, .blink_time = 220 },
89 { .throughput = 10 * 1024, .blink_time = 190 },
90 { .throughput = 20 * 1024, .blink_time = 170 },
91 { .throughput = 50 * 1024, .blink_time = 150 },
92 { .throughput = 70 * 1024, .blink_time = 130 },
93 { .throughput = 100 * 1024, .blink_time = 110 },
94 { .throughput = 200 * 1024, .blink_time = 80 },
95 { .throughput = 300 * 1024, .blink_time = 50 },
96};
97#endif
98
99static int __init set_use_msi(const struct dmi_system_id *dmi)
100{
101 ath9k_use_msi = 1;
102 return 1;
103}
104
105static const struct dmi_system_id ath9k_quirks[] __initconst = {
106 {
107 .callback = set_use_msi,
108 .ident = "Dell Inspiron 24-3460",
109 .matches = {
110 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
111 DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 24-3460"),
112 },
113 },
114 {
115 .callback = set_use_msi,
116 .ident = "Dell Vostro 3262",
117 .matches = {
118 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
119 DMI_MATCH(DMI_PRODUCT_NAME, "Vostro 3262"),
120 },
121 },
122 {
123 .callback = set_use_msi,
124 .ident = "Dell Inspiron 3472",
125 .matches = {
126 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
127 DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 3472"),
128 },
129 },
130 {
131 .callback = set_use_msi,
132 .ident = "Dell Vostro 15-3572",
133 .matches = {
134 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
135 DMI_MATCH(DMI_PRODUCT_NAME, "Vostro 15-3572"),
136 },
137 },
138 {
139 .callback = set_use_msi,
140 .ident = "Dell Inspiron 14-3473",
141 .matches = {
142 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
143 DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 14-3473"),
144 },
145 },
146 {}
147};
148
149static void ath9k_deinit_softc(struct ath_softc *sc);
150
151static void ath9k_op_ps_wakeup(struct ath_common *common)
152{
153 ath9k_ps_wakeup(common->priv);
154}
155
156static void ath9k_op_ps_restore(struct ath_common *common)
157{
158 ath9k_ps_restore(common->priv);
159}
160
161static const struct ath_ps_ops ath9k_ps_ops = {
162 .wakeup = ath9k_op_ps_wakeup,
163 .restore = ath9k_op_ps_restore,
164};
165
166/*
167 * Read and write, they both share the same lock. We do this to serialize
168 * reads and writes on Atheros 802.11n PCI devices only. This is required
169 * as the FIFO on these devices can only accept sanely 2 requests.
170 */
171
172static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
173{
174 struct ath_hw *ah = hw_priv;
175 struct ath_common *common = ath9k_hw_common(ah);
176 struct ath_softc *sc = common->priv;
177
178 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
179 unsigned long flags;
180 spin_lock_irqsave(&sc->sc_serial_rw, flags);
181 iowrite32(val, sc->mem + reg_offset);
182 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
183 } else
184 iowrite32(val, sc->mem + reg_offset);
185}
186
187static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
188{
189 struct ath_hw *ah = hw_priv;
190 struct ath_common *common = ath9k_hw_common(ah);
191 struct ath_softc *sc = common->priv;
192 u32 val;
193
194 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
195 unsigned long flags;
196 spin_lock_irqsave(&sc->sc_serial_rw, flags);
197 val = ioread32(sc->mem + reg_offset);
198 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
199 } else
200 val = ioread32(sc->mem + reg_offset);
201 return val;
202}
203
204static void ath9k_multi_ioread32(void *hw_priv, u32 *addr,
205 u32 *val, u16 count)
206{
207 int i;
208
209 for (i = 0; i < count; i++)
210 val[i] = ath9k_ioread32(hw_priv, addr[i]);
211}
212
213
214static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset,
215 u32 set, u32 clr)
216{
217 u32 val;
218
219 val = ioread32(sc->mem + reg_offset);
220 val &= ~clr;
221 val |= set;
222 iowrite32(val, sc->mem + reg_offset);
223
224 return val;
225}
226
227static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
228{
229 struct ath_hw *ah = hw_priv;
230 struct ath_common *common = ath9k_hw_common(ah);
231 struct ath_softc *sc = common->priv;
232 unsigned long flags;
233 u32 val;
234
235 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
236 spin_lock_irqsave(&sc->sc_serial_rw, flags);
237 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
238 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
239 } else
240 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
241
242 return val;
243}
244
245/**************************/
246/* Initialization */
247/**************************/
248
249static void ath9k_reg_notifier(struct wiphy *wiphy,
250 struct regulatory_request *request)
251{
252 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
253 struct ath_softc *sc = hw->priv;
254 struct ath_hw *ah = sc->sc_ah;
255 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
256
257 ath_reg_notifier_apply(wiphy, request, reg);
258
259 /* synchronize DFS detector if regulatory domain changed */
260 if (sc->dfs_detector != NULL)
261 sc->dfs_detector->set_dfs_domain(sc->dfs_detector,
262 request->dfs_region);
263
264 /* Set tx power */
265 if (!ah->curchan)
266 return;
267
268 sc->cur_chan->txpower = 2 * ah->curchan->chan->max_power;
269 ath9k_ps_wakeup(sc);
270 ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);
271 ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
272 sc->cur_chan->txpower,
273 &sc->cur_chan->cur_txpower);
274 ath9k_ps_restore(sc);
275}
276
277/*
278 * This function will allocate both the DMA descriptor structure, and the
279 * buffers it contains. These are used to contain the descriptors used
280 * by the system.
281*/
282int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
283 struct list_head *head, const char *name,
284 int nbuf, int ndesc, bool is_tx)
285{
286 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
287 u8 *ds;
288 int i, bsize, desc_len;
289
290 ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n",
291 name, nbuf, ndesc);
292
293 INIT_LIST_HEAD(head);
294
295 if (is_tx)
296 desc_len = sc->sc_ah->caps.tx_desc_len;
297 else
298 desc_len = sizeof(struct ath_desc);
299
300 /* ath_desc must be a multiple of DWORDs */
301 if ((desc_len % 4) != 0) {
302 ath_err(common, "ath_desc not DWORD aligned\n");
303 BUG_ON((desc_len % 4) != 0);
304 return -ENOMEM;
305 }
306
307 dd->dd_desc_len = desc_len * nbuf * ndesc;
308
309 /*
310 * Need additional DMA memory because we can't use
311 * descriptors that cross the 4K page boundary. Assume
312 * one skipped descriptor per 4K page.
313 */
314 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
315 u32 ndesc_skipped =
316 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
317 u32 dma_len;
318
319 while (ndesc_skipped) {
320 dma_len = ndesc_skipped * desc_len;
321 dd->dd_desc_len += dma_len;
322
323 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
324 }
325 }
326
327 /* allocate descriptors */
328 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
329 &dd->dd_desc_paddr, GFP_KERNEL);
330 if (!dd->dd_desc)
331 return -ENOMEM;
332
333 ds = dd->dd_desc;
334 ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
335 name, ds, (u32) dd->dd_desc_len,
336 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
337
338 /* allocate buffers */
339 if (is_tx) {
340 struct ath_buf *bf;
341
342 bsize = sizeof(struct ath_buf) * nbuf;
343 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);
344 if (!bf)
345 return -ENOMEM;
346
347 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
348 bf->bf_desc = ds;
349 bf->bf_daddr = DS2PHYS(dd, ds);
350
351 if (!(sc->sc_ah->caps.hw_caps &
352 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
353 /*
354 * Skip descriptor addresses which can cause 4KB
355 * boundary crossing (addr + length) with a 32 dword
356 * descriptor fetch.
357 */
358 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
359 BUG_ON((caddr_t) bf->bf_desc >=
360 ((caddr_t) dd->dd_desc +
361 dd->dd_desc_len));
362
363 ds += (desc_len * ndesc);
364 bf->bf_desc = ds;
365 bf->bf_daddr = DS2PHYS(dd, ds);
366 }
367 }
368 list_add_tail(&bf->list, head);
369 }
370 } else {
371 struct ath_rxbuf *bf;
372
373 bsize = sizeof(struct ath_rxbuf) * nbuf;
374 bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);
375 if (!bf)
376 return -ENOMEM;
377
378 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
379 bf->bf_desc = ds;
380 bf->bf_daddr = DS2PHYS(dd, ds);
381
382 if (!(sc->sc_ah->caps.hw_caps &
383 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
384 /*
385 * Skip descriptor addresses which can cause 4KB
386 * boundary crossing (addr + length) with a 32 dword
387 * descriptor fetch.
388 */
389 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
390 BUG_ON((caddr_t) bf->bf_desc >=
391 ((caddr_t) dd->dd_desc +
392 dd->dd_desc_len));
393
394 ds += (desc_len * ndesc);
395 bf->bf_desc = ds;
396 bf->bf_daddr = DS2PHYS(dd, ds);
397 }
398 }
399 list_add_tail(&bf->list, head);
400 }
401 }
402 return 0;
403}
404
405static int ath9k_init_queues(struct ath_softc *sc)
406{
407 int i = 0;
408
409 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
410 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
411 ath_cabq_update(sc);
412
413 sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0);
414
415 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
416 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
417 sc->tx.txq_map[i]->mac80211_qnum = i;
418 }
419 return 0;
420}
421
422static void ath9k_init_misc(struct ath_softc *sc)
423{
424 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
425 int i = 0;
426
427 timer_setup(&common->ani.timer, ath_ani_calibrate, 0);
428
429 common->last_rssi = ATH_RSSI_DUMMY_MARKER;
430 eth_broadcast_addr(common->bssidmask);
431 sc->beacon.slottime = 9;
432
433 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
434 sc->beacon.bslot[i] = NULL;
435
436 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
437 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT;
438
439 sc->spec_priv.ah = sc->sc_ah;
440 sc->spec_priv.spec_config.enabled = 0;
441 sc->spec_priv.spec_config.short_repeat = true;
442 sc->spec_priv.spec_config.count = 8;
443 sc->spec_priv.spec_config.endless = false;
444 sc->spec_priv.spec_config.period = 0xFF;
445 sc->spec_priv.spec_config.fft_period = 0xF;
446}
447
448static void ath9k_init_pcoem_platform(struct ath_softc *sc)
449{
450 struct ath_hw *ah = sc->sc_ah;
451 struct ath9k_hw_capabilities *pCap = &ah->caps;
452 struct ath_common *common = ath9k_hw_common(ah);
453
454 if (!IS_ENABLED(CONFIG_ATH9K_PCOEM))
455 return;
456
457 if (common->bus_ops->ath_bus_type != ATH_PCI)
458 return;
459
460 if (sc->driver_data & (ATH9K_PCI_CUS198 |
461 ATH9K_PCI_CUS230)) {
462 ah->config.xlna_gpio = 9;
463 ah->config.xatten_margin_cfg = true;
464 ah->config.alt_mingainidx = true;
465 ah->config.ant_ctrl_comm2g_switch_enable = 0x000BBB88;
466 sc->ant_comb.low_rssi_thresh = 20;
467 sc->ant_comb.fast_div_bias = 3;
468
469 ath_info(common, "Set parameters for %s\n",
470 (sc->driver_data & ATH9K_PCI_CUS198) ?
471 "CUS198" : "CUS230");
472 }
473
474 if (sc->driver_data & ATH9K_PCI_CUS217)
475 ath_info(common, "CUS217 card detected\n");
476
477 if (sc->driver_data & ATH9K_PCI_CUS252)
478 ath_info(common, "CUS252 card detected\n");
479
480 if (sc->driver_data & ATH9K_PCI_AR9565_1ANT)
481 ath_info(common, "WB335 1-ANT card detected\n");
482
483 if (sc->driver_data & ATH9K_PCI_AR9565_2ANT)
484 ath_info(common, "WB335 2-ANT card detected\n");
485
486 if (sc->driver_data & ATH9K_PCI_KILLER)
487 ath_info(common, "Killer Wireless card detected\n");
488
489 /*
490 * Some WB335 cards do not support antenna diversity. Since
491 * we use a hardcoded value for AR9565 instead of using the
492 * EEPROM/OTP data, remove the combining feature from
493 * the HW capabilities bitmap.
494 */
495 if (sc->driver_data & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) {
496 if (!(sc->driver_data & ATH9K_PCI_BT_ANT_DIV))
497 pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB;
498 }
499
500 if (sc->driver_data & ATH9K_PCI_BT_ANT_DIV) {
501 pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV;
502 ath_info(common, "Set BT/WLAN RX diversity capability\n");
503 }
504
505 if (sc->driver_data & ATH9K_PCI_D3_L1_WAR) {
506 ah->config.pcie_waen = 0x0040473b;
507 ath_info(common, "Enable WAR for ASPM D3/L1\n");
508 }
509
510 /*
511 * The default value of pll_pwrsave is 1.
512 * For certain AR9485 cards, it is set to 0.
513 * For AR9462, AR9565 it's set to 7.
514 */
515 ah->config.pll_pwrsave = 1;
516
517 if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) {
518 ah->config.pll_pwrsave = 0;
519 ath_info(common, "Disable PLL PowerSave\n");
520 }
521
522 if (sc->driver_data & ATH9K_PCI_LED_ACT_HI)
523 ah->config.led_active_high = true;
524}
525
526static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob,
527 void *ctx)
528{
529 struct ath9k_eeprom_ctx *ec = ctx;
530
531 if (eeprom_blob)
532 ec->ah->eeprom_blob = eeprom_blob;
533
534 complete(&ec->complete);
535}
536
537static int ath9k_eeprom_request(struct ath_softc *sc, const char *name)
538{
539 struct ath9k_eeprom_ctx ec;
540 struct ath_hw *ah = sc->sc_ah;
541 int err;
542
543 /* try to load the EEPROM content asynchronously */
544 init_completion(&ec.complete);
545 ec.ah = sc->sc_ah;
546
547 err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL,
548 &ec, ath9k_eeprom_request_cb);
549 if (err < 0) {
550 ath_err(ath9k_hw_common(ah),
551 "EEPROM request failed\n");
552 return err;
553 }
554
555 wait_for_completion(&ec.complete);
556
557 if (!ah->eeprom_blob) {
558 ath_err(ath9k_hw_common(ah),
559 "Unable to load EEPROM file %s\n", name);
560 return -EINVAL;
561 }
562
563 return 0;
564}
565
566static void ath9k_eeprom_release(struct ath_softc *sc)
567{
568 release_firmware(sc->sc_ah->eeprom_blob);
569}
570
571static int ath9k_nvmem_request_eeprom(struct ath_softc *sc)
572{
573 struct ath_hw *ah = sc->sc_ah;
574 struct nvmem_cell *cell;
575 void *buf;
576 size_t len;
577 int err;
578
579 cell = devm_nvmem_cell_get(sc->dev, "calibration");
580 if (IS_ERR(cell)) {
581 err = PTR_ERR(cell);
582
583 /* nvmem cell might not be defined, or the nvmem
584 * subsystem isn't included. In this case, follow
585 * the established "just return 0;" convention
586 * to say:
587 * "All good. Nothing to see here. Please go on."
588 */
589 if (err == -ENOENT || err == -EOPNOTSUPP)
590 return 0;
591
592 return err;
593 }
594
595 buf = nvmem_cell_read(cell, &len);
596 if (IS_ERR(buf))
597 return PTR_ERR(buf);
598
599 /* run basic sanity checks on the returned nvram cell length.
600 * That length has to be a multiple of a "u16" (i.e.: & 1).
601 * Furthermore, it has to be more than "let's say" 512 bytes
602 * but less than the maximum of AR9300_EEPROM_SIZE (16kb).
603 */
604 if ((len & 1) == 1 || len < 512 || len >= AR9300_EEPROM_SIZE) {
605 kfree(buf);
606 return -EINVAL;
607 }
608
609 /* devres manages the calibration values release on shutdown */
610 ah->nvmem_blob = devm_kmemdup(sc->dev, buf, len, GFP_KERNEL);
611 kfree(buf);
612 if (!ah->nvmem_blob)
613 return -ENOMEM;
614
615 ah->nvmem_blob_len = len;
616 ah->ah_flags &= ~AH_USE_EEPROM;
617 ah->ah_flags |= AH_NO_EEP_SWAP;
618
619 return 0;
620}
621
622static int ath9k_of_init(struct ath_softc *sc)
623{
624 struct device_node *np = sc->dev->of_node;
625 struct ath_hw *ah = sc->sc_ah;
626 struct ath_common *common = ath9k_hw_common(ah);
627 enum ath_bus_type bus_type = common->bus_ops->ath_bus_type;
628 char eeprom_name[100];
629 int ret;
630
631 if (!of_device_is_available(np))
632 return 0;
633
634 ath_dbg(common, CONFIG, "parsing configuration from OF node\n");
635
636 if (of_property_read_bool(np, "qca,no-eeprom")) {
637 /* ath9k-eeprom-<bus>-<id>.bin */
638 scnprintf(eeprom_name, sizeof(eeprom_name),
639 "ath9k-eeprom-%s-%s.bin",
640 ath_bus_type_to_string(bus_type), dev_name(ah->dev));
641
642 ret = ath9k_eeprom_request(sc, eeprom_name);
643 if (ret)
644 return ret;
645
646 ah->ah_flags &= ~AH_USE_EEPROM;
647 ah->ah_flags |= AH_NO_EEP_SWAP;
648 }
649
650 of_get_mac_address(np, common->macaddr);
651
652 return 0;
653}
654
655static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
656 const struct ath_bus_ops *bus_ops)
657{
658 struct ath_hw *ah = NULL;
659 struct ath9k_hw_capabilities *pCap;
660 struct ath_common *common;
661 int ret = 0, i;
662 int csz = 0;
663
664 ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL);
665 if (!ah)
666 return -ENOMEM;
667
668 ah->dev = sc->dev;
669 ah->hw = sc->hw;
670 ah->hw_version.devid = devid;
671 ah->ah_flags |= AH_USE_EEPROM;
672 ah->led_pin = -1;
673 ah->reg_ops.read = ath9k_ioread32;
674 ah->reg_ops.multi_read = ath9k_multi_ioread32;
675 ah->reg_ops.write = ath9k_iowrite32;
676 ah->reg_ops.rmw = ath9k_reg_rmw;
677 pCap = &ah->caps;
678
679 common = ath9k_hw_common(ah);
680
681 /* Will be cleared in ath9k_start() */
682 set_bit(ATH_OP_INVALID, &common->op_flags);
683
684 sc->sc_ah = ah;
685 sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET);
686 sc->tx99_power = MAX_RATE_POWER + 1;
687 init_waitqueue_head(&sc->tx_wait);
688 sc->cur_chan = &sc->chanctx[0];
689 if (!ath9k_is_chanctx_enabled())
690 sc->cur_chan->hw_queue_base = 0;
691
692 common->ops = &ah->reg_ops;
693 common->bus_ops = bus_ops;
694 common->ps_ops = &ath9k_ps_ops;
695 common->ah = ah;
696 common->hw = sc->hw;
697 common->priv = sc;
698 common->debug_mask = ath9k_debug;
699 common->btcoex_enabled = ath9k_btcoex_enable == 1;
700 common->disable_ani = false;
701
702 /*
703 * Platform quirks.
704 */
705 ath9k_init_pcoem_platform(sc);
706
707 ret = ath9k_of_init(sc);
708 if (ret)
709 return ret;
710
711 ret = ath9k_nvmem_request_eeprom(sc);
712 if (ret)
713 return ret;
714
715 if (ath9k_led_active_high != -1)
716 ah->config.led_active_high = ath9k_led_active_high == 1;
717
718 /*
719 * Enable WLAN/BT RX Antenna diversity only when:
720 *
721 * - BTCOEX is disabled.
722 * - the user manually requests the feature.
723 * - the HW cap is set using the platform data.
724 */
725 if (!common->btcoex_enabled && ath9k_bt_ant_diversity &&
726 (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV))
727 common->bt_ant_diversity = 1;
728
729 spin_lock_init(&common->cc_lock);
730 spin_lock_init(&sc->intr_lock);
731 spin_lock_init(&sc->sc_serial_rw);
732 spin_lock_init(&sc->sc_pm_lock);
733 spin_lock_init(&sc->chan_lock);
734 mutex_init(&sc->mutex);
735 tasklet_setup(&sc->intr_tq, ath9k_tasklet);
736 tasklet_setup(&sc->bcon_tasklet, ath9k_beacon_tasklet);
737
738 timer_setup(&sc->sleep_timer, ath_ps_full_sleep, 0);
739 INIT_WORK(&sc->hw_reset_work, ath_reset_work);
740 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
741 INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work);
742 INIT_DELAYED_WORK(&sc->hw_check_work, ath_hw_check_work);
743
744 ath9k_init_channel_context(sc);
745
746 /*
747 * Cache line size is used to size and align various
748 * structures used to communicate with the hardware.
749 */
750 ath_read_cachesize(common, &csz);
751 common->cachelsz = csz << 2; /* convert to bytes */
752
753 /* Initializes the hardware for all supported chipsets */
754 ret = ath9k_hw_init(ah);
755 if (ret)
756 goto err_hw;
757
758 ret = ath9k_init_queues(sc);
759 if (ret)
760 goto err_queues;
761
762 ret = ath9k_init_btcoex(sc);
763 if (ret)
764 goto err_btcoex;
765
766 ret = ath9k_cmn_init_channels_rates(common);
767 if (ret)
768 goto err_btcoex;
769
770 ret = ath9k_init_p2p(sc);
771 if (ret)
772 goto err_btcoex;
773
774 ath9k_cmn_init_crypto(sc->sc_ah);
775 ath9k_init_misc(sc);
776 ath_chanctx_init(sc);
777 ath9k_offchannel_init(sc);
778
779 if (common->bus_ops->aspm_init)
780 common->bus_ops->aspm_init(common);
781
782 return 0;
783
784err_btcoex:
785 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
786 if (ATH_TXQ_SETUP(sc, i))
787 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
788err_queues:
789 ath9k_hw_deinit(ah);
790err_hw:
791 ath9k_eeprom_release(sc);
792 dev_kfree_skb_any(sc->tx99_skb);
793 return ret;
794}
795
796static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
797{
798 struct ieee80211_supported_band *sband;
799 struct ieee80211_channel *chan;
800 struct ath_hw *ah = sc->sc_ah;
801 struct ath_common *common = ath9k_hw_common(ah);
802 struct cfg80211_chan_def chandef;
803 int i;
804
805 sband = &common->sbands[band];
806 for (i = 0; i < sband->n_channels; i++) {
807 chan = &sband->channels[i];
808 ah->curchan = &ah->channels[chan->hw_value];
809 cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_HT20);
810 ath9k_cmn_get_channel(sc->hw, ah, &chandef);
811 ath9k_hw_set_txpowerlimit(ah, MAX_COMBINED_POWER, true);
812 }
813}
814
815static void ath9k_init_txpower_limits(struct ath_softc *sc)
816{
817 struct ath_hw *ah = sc->sc_ah;
818 struct ath9k_channel *curchan = ah->curchan;
819
820 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
821 ath9k_init_band_txpower(sc, NL80211_BAND_2GHZ);
822 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
823 ath9k_init_band_txpower(sc, NL80211_BAND_5GHZ);
824
825 ah->curchan = curchan;
826}
827
828static const struct ieee80211_iface_limit if_limits[] = {
829 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) },
830 { .max = 8, .types =
831#ifdef CONFIG_MAC80211_MESH
832 BIT(NL80211_IFTYPE_MESH_POINT) |
833#endif
834 BIT(NL80211_IFTYPE_AP) },
835 { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_CLIENT) |
836 BIT(NL80211_IFTYPE_P2P_GO) },
837};
838
839#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
840
841static const struct ieee80211_iface_limit if_limits_multi[] = {
842 { .max = 2, .types = BIT(NL80211_IFTYPE_STATION) |
843 BIT(NL80211_IFTYPE_AP) |
844 BIT(NL80211_IFTYPE_P2P_CLIENT) |
845 BIT(NL80211_IFTYPE_P2P_GO) },
846 { .max = 1, .types = BIT(NL80211_IFTYPE_ADHOC) },
847 { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_DEVICE) },
848};
849
850static const struct ieee80211_iface_combination if_comb_multi[] = {
851 {
852 .limits = if_limits_multi,
853 .n_limits = ARRAY_SIZE(if_limits_multi),
854 .max_interfaces = 3,
855 .num_different_channels = 2,
856 .beacon_int_infra_match = true,
857 },
858};
859
860#endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
861
862static const struct ieee80211_iface_combination if_comb[] = {
863 {
864 .limits = if_limits,
865 .n_limits = ARRAY_SIZE(if_limits),
866 .max_interfaces = 2048,
867 .num_different_channels = 1,
868 .beacon_int_infra_match = true,
869#ifdef CONFIG_ATH9K_DFS_CERTIFIED
870 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
871 BIT(NL80211_CHAN_WIDTH_20) |
872 BIT(NL80211_CHAN_WIDTH_40),
873#endif
874 },
875};
876
877#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
878static void ath9k_set_mcc_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
879{
880 struct ath_hw *ah = sc->sc_ah;
881 struct ath_common *common = ath9k_hw_common(ah);
882
883 if (!ath9k_is_chanctx_enabled())
884 return;
885
886 ieee80211_hw_set(hw, QUEUE_CONTROL);
887 hw->queues = ATH9K_NUM_TX_QUEUES;
888 hw->offchannel_tx_hw_queue = hw->queues - 1;
889 hw->wiphy->iface_combinations = if_comb_multi;
890 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb_multi);
891 hw->wiphy->max_scan_ssids = 255;
892 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
893 hw->wiphy->max_remain_on_channel_duration = 10000;
894 hw->chanctx_data_size = sizeof(void *);
895 hw->extra_beacon_tailroom =
896 sizeof(struct ieee80211_p2p_noa_attr) + 9;
897
898 ath_dbg(common, CHAN_CTX, "Use channel contexts\n");
899}
900#endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
901
902static void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
903{
904 struct ath_hw *ah = sc->sc_ah;
905 struct ath_common *common = ath9k_hw_common(ah);
906
907 ieee80211_hw_set(hw, SUPPORTS_HT_CCK_RATES);
908 ieee80211_hw_set(hw, SUPPORTS_RC_TABLE);
909 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
910 ieee80211_hw_set(hw, SPECTRUM_MGMT);
911 ieee80211_hw_set(hw, PS_NULLFUNC_STACK);
912 ieee80211_hw_set(hw, SIGNAL_DBM);
913 ieee80211_hw_set(hw, RX_INCLUDES_FCS);
914 ieee80211_hw_set(hw, HOST_BROADCAST_PS_BUFFERING);
915 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
916 ieee80211_hw_set(hw, SUPPORTS_CLONED_SKBS);
917
918 if (ath9k_ps_enable)
919 ieee80211_hw_set(hw, SUPPORTS_PS);
920
921 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
922 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
923
924 if (AR_SREV_9280_20_OR_LATER(ah))
925 hw->radiotap_mcs_details |=
926 IEEE80211_RADIOTAP_MCS_HAVE_STBC;
927 }
928
929 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt)
930 ieee80211_hw_set(hw, MFP_CAPABLE);
931
932 hw->wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR |
933 NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE |
934 NL80211_FEATURE_P2P_GO_CTWIN;
935
936 if (!IS_ENABLED(CONFIG_ATH9K_TX99)) {
937 hw->wiphy->interface_modes =
938 BIT(NL80211_IFTYPE_P2P_GO) |
939 BIT(NL80211_IFTYPE_P2P_CLIENT) |
940 BIT(NL80211_IFTYPE_AP) |
941 BIT(NL80211_IFTYPE_STATION) |
942 BIT(NL80211_IFTYPE_ADHOC) |
943 BIT(NL80211_IFTYPE_MESH_POINT) |
944 BIT(NL80211_IFTYPE_OCB);
945
946 if (ath9k_is_chanctx_enabled())
947 hw->wiphy->interface_modes |=
948 BIT(NL80211_IFTYPE_P2P_DEVICE);
949
950 hw->wiphy->iface_combinations = if_comb;
951 hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
952 }
953
954 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
955
956 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
957 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
958 hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
959 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ;
960 hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
961 hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD;
962
963 hw->queues = 4;
964 hw->max_rates = 4;
965 hw->max_listen_interval = 10;
966 hw->max_rate_tries = 10;
967 hw->sta_data_size = sizeof(struct ath_node);
968 hw->vif_data_size = sizeof(struct ath_vif);
969 hw->txq_data_size = sizeof(struct ath_atx_tid);
970 hw->extra_tx_headroom = 4;
971
972 hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1;
973 hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1;
974
975 /* single chain devices with rx diversity */
976 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
977 hw->wiphy->available_antennas_rx = BIT(0) | BIT(1);
978
979 sc->ant_rx = hw->wiphy->available_antennas_rx;
980 sc->ant_tx = hw->wiphy->available_antennas_tx;
981
982 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
983 hw->wiphy->bands[NL80211_BAND_2GHZ] =
984 &common->sbands[NL80211_BAND_2GHZ];
985 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
986 hw->wiphy->bands[NL80211_BAND_5GHZ] =
987 &common->sbands[NL80211_BAND_5GHZ];
988
989#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
990 ath9k_set_mcc_capab(sc, hw);
991#endif
992 ath9k_init_wow(hw);
993 ath9k_cmn_reload_chainmask(ah);
994
995 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
996
997 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
998 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_AIRTIME_FAIRNESS);
999 wiphy_ext_feature_set(hw->wiphy,
1000 NL80211_EXT_FEATURE_MULTICAST_REGISTRATIONS);
1001 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
1002}
1003
1004int ath9k_init_device(u16 devid, struct ath_softc *sc,
1005 const struct ath_bus_ops *bus_ops)
1006{
1007 struct ieee80211_hw *hw = sc->hw;
1008 struct ath_common *common;
1009 struct ath_hw *ah;
1010 int error = 0;
1011 struct ath_regulatory *reg;
1012
1013 /* Bring up device */
1014 error = ath9k_init_softc(devid, sc, bus_ops);
1015 if (error)
1016 return error;
1017
1018 ah = sc->sc_ah;
1019 common = ath9k_hw_common(ah);
1020 ath9k_set_hw_capab(sc, hw);
1021
1022 /* Initialize regulatory */
1023 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
1024 ath9k_reg_notifier);
1025 if (error)
1026 goto deinit;
1027
1028 reg = &common->regulatory;
1029
1030 /* Setup TX DMA */
1031 error = ath_tx_init(sc, ATH_TXBUF);
1032 if (error != 0)
1033 goto deinit;
1034
1035 /* Setup RX DMA */
1036 error = ath_rx_init(sc, ATH_RXBUF);
1037 if (error != 0)
1038 goto deinit;
1039
1040 ath9k_init_txpower_limits(sc);
1041
1042#ifdef CONFIG_MAC80211_LEDS
1043 /* must be initialized before ieee80211_register_hw */
1044 sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw,
1045 IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink,
1046 ARRAY_SIZE(ath9k_tpt_blink));
1047#endif
1048
1049 wiphy_read_of_freq_limits(hw->wiphy);
1050
1051 /* Register with mac80211 */
1052 error = ieee80211_register_hw(hw);
1053 if (error)
1054 goto rx_cleanup;
1055
1056 error = ath9k_init_debug(ah);
1057 if (error) {
1058 ath_err(common, "Unable to create debugfs files\n");
1059 goto unregister;
1060 }
1061
1062 /* Handle world regulatory */
1063 if (!ath_is_world_regd(reg)) {
1064 error = regulatory_hint(hw->wiphy, reg->alpha2);
1065 if (error)
1066 goto debug_cleanup;
1067 }
1068
1069 ath_init_leds(sc);
1070 ath_start_rfkill_poll(sc);
1071
1072 return 0;
1073
1074debug_cleanup:
1075 ath9k_deinit_debug(sc);
1076unregister:
1077 ieee80211_unregister_hw(hw);
1078rx_cleanup:
1079 ath_rx_cleanup(sc);
1080deinit:
1081 ath9k_deinit_softc(sc);
1082 return error;
1083}
1084
1085/*****************************/
1086/* De-Initialization */
1087/*****************************/
1088
1089static void ath9k_deinit_softc(struct ath_softc *sc)
1090{
1091 int i = 0;
1092
1093 ath9k_deinit_p2p(sc);
1094 ath9k_deinit_btcoex(sc);
1095
1096 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1097 if (ATH_TXQ_SETUP(sc, i))
1098 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1099
1100 del_timer_sync(&sc->sleep_timer);
1101 ath9k_hw_deinit(sc->sc_ah);
1102 if (sc->dfs_detector != NULL)
1103 sc->dfs_detector->exit(sc->dfs_detector);
1104
1105 ath9k_eeprom_release(sc);
1106}
1107
1108void ath9k_deinit_device(struct ath_softc *sc)
1109{
1110 struct ieee80211_hw *hw = sc->hw;
1111
1112 ath9k_ps_wakeup(sc);
1113
1114 wiphy_rfkill_stop_polling(sc->hw->wiphy);
1115 ath_deinit_leds(sc);
1116
1117 ath9k_ps_restore(sc);
1118
1119 ath9k_deinit_debug(sc);
1120 ath9k_deinit_wow(hw);
1121 ieee80211_unregister_hw(hw);
1122 ath_rx_cleanup(sc);
1123 ath9k_deinit_softc(sc);
1124}
1125
1126/************************/
1127/* Module Hooks */
1128/************************/
1129
1130static int __init ath9k_init(void)
1131{
1132 int error;
1133
1134 error = ath_pci_init();
1135 if (error < 0) {
1136 pr_err("No PCI devices found, driver not installed\n");
1137 error = -ENODEV;
1138 goto err_out;
1139 }
1140
1141 error = ath_ahb_init();
1142 if (error < 0) {
1143 error = -ENODEV;
1144 goto err_pci_exit;
1145 }
1146
1147 dmi_check_system(ath9k_quirks);
1148
1149 return 0;
1150
1151 err_pci_exit:
1152 ath_pci_exit();
1153 err_out:
1154 return error;
1155}
1156module_init(ath9k_init);
1157
1158static void __exit ath9k_exit(void)
1159{
1160 is_ath9k_unloaded = true;
1161 ath_ahb_exit();
1162 ath_pci_exit();
1163 pr_info("%s: Driver unloaded\n", dev_info);
1164}
1165module_exit(ath9k_exit);