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1/* SPDX-License-Identifier: GPL-2.0-only */
2/****************************************************************************
3 * Driver for Solarflare network controllers and boards
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2005-2013 Solarflare Communications Inc.
6 */
7
8/* Common definitions for all Efx net driver code */
9
10#ifndef EFX_NET_DRIVER_H
11#define EFX_NET_DRIVER_H
12
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/ethtool.h>
16#include <linux/if_vlan.h>
17#include <linux/timer.h>
18#include <linux/mdio.h>
19#include <linux/list.h>
20#include <linux/pci.h>
21#include <linux/device.h>
22#include <linux/highmem.h>
23#include <linux/workqueue.h>
24#include <linux/mutex.h>
25#include <linux/rwsem.h>
26#include <linux/vmalloc.h>
27#include <linux/mtd/mtd.h>
28#include <net/busy_poll.h>
29#include <net/xdp.h>
30
31#include "enum.h"
32#include "bitfield.h"
33#include "filter.h"
34
35/**************************************************************************
36 *
37 * Build definitions
38 *
39 **************************************************************************/
40
41#ifdef DEBUG
42#define EFX_WARN_ON_ONCE_PARANOID(x) WARN_ON_ONCE(x)
43#define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
44#else
45#define EFX_WARN_ON_ONCE_PARANOID(x) do {} while (0)
46#define EFX_WARN_ON_PARANOID(x) do {} while (0)
47#endif
48
49/**************************************************************************
50 *
51 * Efx data structures
52 *
53 **************************************************************************/
54
55#define EFX_MAX_CHANNELS 32U
56#define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
57#define EFX_EXTRA_CHANNEL_IOV 0
58#define EFX_EXTRA_CHANNEL_PTP 1
59#define EFX_MAX_EXTRA_CHANNELS 2U
60
61/* Checksum generation is a per-queue option in hardware, so each
62 * queue visible to the networking core is backed by two hardware TX
63 * queues. */
64#define EFX_MAX_TX_TC 2
65#define EFX_MAX_CORE_TX_QUEUES (EFX_MAX_TX_TC * EFX_MAX_CHANNELS)
66#define EFX_TXQ_TYPE_OUTER_CSUM 1 /* Outer checksum offload */
67#define EFX_TXQ_TYPE_INNER_CSUM 2 /* Inner checksum offload */
68#define EFX_TXQ_TYPE_HIGHPRI 4 /* High-priority (for TC) */
69#define EFX_TXQ_TYPES 8
70/* HIGHPRI is Siena-only, and INNER_CSUM is EF10, so no need for both */
71#define EFX_MAX_TXQ_PER_CHANNEL 4
72#define EFX_MAX_TX_QUEUES (EFX_MAX_TXQ_PER_CHANNEL * EFX_MAX_CHANNELS)
73
74/* Maximum possible MTU the driver supports */
75#define EFX_MAX_MTU (9 * 1024)
76
77/* Minimum MTU, from RFC791 (IP) */
78#define EFX_MIN_MTU 68
79
80/* Maximum total header length for TSOv2 */
81#define EFX_TSO2_MAX_HDRLEN 208
82
83/* Size of an RX scatter buffer. Small enough to pack 2 into a 4K page,
84 * and should be a multiple of the cache line size.
85 */
86#define EFX_RX_USR_BUF_SIZE (2048 - 256)
87
88/* If possible, we should ensure cache line alignment at start and end
89 * of every buffer. Otherwise, we just need to ensure 4-byte
90 * alignment of the network header.
91 */
92#if NET_IP_ALIGN == 0
93#define EFX_RX_BUF_ALIGNMENT L1_CACHE_BYTES
94#else
95#define EFX_RX_BUF_ALIGNMENT 4
96#endif
97
98/* Non-standard XDP_PACKET_HEADROOM and tailroom to satisfy XDP_REDIRECT and
99 * still fit two standard MTU size packets into a single 4K page.
100 */
101#define EFX_XDP_HEADROOM 128
102#define EFX_XDP_TAILROOM SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
103
104/* Forward declare Precision Time Protocol (PTP) support structure. */
105struct efx_ptp_data;
106struct hwtstamp_config;
107
108struct efx_self_tests;
109
110/**
111 * struct efx_buffer - A general-purpose DMA buffer
112 * @addr: host base address of the buffer
113 * @dma_addr: DMA base address of the buffer
114 * @len: Buffer length, in bytes
115 *
116 * The NIC uses these buffers for its interrupt status registers and
117 * MAC stats dumps.
118 */
119struct efx_buffer {
120 void *addr;
121 dma_addr_t dma_addr;
122 unsigned int len;
123};
124
125/**
126 * struct efx_special_buffer - DMA buffer entered into buffer table
127 * @buf: Standard &struct efx_buffer
128 * @index: Buffer index within controller;s buffer table
129 * @entries: Number of buffer table entries
130 *
131 * The NIC has a buffer table that maps buffers of size %EFX_BUF_SIZE.
132 * Event and descriptor rings are addressed via one or more buffer
133 * table entries (and so can be physically non-contiguous, although we
134 * currently do not take advantage of that). On Falcon and Siena we
135 * have to take care of allocating and initialising the entries
136 * ourselves. On later hardware this is managed by the firmware and
137 * @index and @entries are left as 0.
138 */
139struct efx_special_buffer {
140 struct efx_buffer buf;
141 unsigned int index;
142 unsigned int entries;
143};
144
145/**
146 * struct efx_tx_buffer - buffer state for a TX descriptor
147 * @skb: When @flags & %EFX_TX_BUF_SKB, the associated socket buffer to be
148 * freed when descriptor completes
149 * @xdpf: When @flags & %EFX_TX_BUF_XDP, the XDP frame information; its @data
150 * member is the associated buffer to drop a page reference on.
151 * @option: When @flags & %EFX_TX_BUF_OPTION, an EF10-specific option
152 * descriptor.
153 * @dma_addr: DMA address of the fragment.
154 * @flags: Flags for allocation and DMA mapping type
155 * @len: Length of this fragment.
156 * This field is zero when the queue slot is empty.
157 * @unmap_len: Length of this fragment to unmap
158 * @dma_offset: Offset of @dma_addr from the address of the backing DMA mapping.
159 * Only valid if @unmap_len != 0.
160 */
161struct efx_tx_buffer {
162 union {
163 const struct sk_buff *skb;
164 struct xdp_frame *xdpf;
165 };
166 union {
167 efx_qword_t option; /* EF10 */
168 dma_addr_t dma_addr;
169 };
170 unsigned short flags;
171 unsigned short len;
172 unsigned short unmap_len;
173 unsigned short dma_offset;
174};
175#define EFX_TX_BUF_CONT 1 /* not last descriptor of packet */
176#define EFX_TX_BUF_SKB 2 /* buffer is last part of skb */
177#define EFX_TX_BUF_MAP_SINGLE 8 /* buffer was mapped with dma_map_single() */
178#define EFX_TX_BUF_OPTION 0x10 /* empty buffer for option descriptor */
179#define EFX_TX_BUF_XDP 0x20 /* buffer was sent with XDP */
180#define EFX_TX_BUF_TSO_V3 0x40 /* empty buffer for a TSO_V3 descriptor */
181
182/**
183 * struct efx_tx_queue - An Efx TX queue
184 *
185 * This is a ring buffer of TX fragments.
186 * Since the TX completion path always executes on the same
187 * CPU and the xmit path can operate on different CPUs,
188 * performance is increased by ensuring that the completion
189 * path and the xmit path operate on different cache lines.
190 * This is particularly important if the xmit path is always
191 * executing on one CPU which is different from the completion
192 * path. There is also a cache line for members which are
193 * read but not written on the fast path.
194 *
195 * @efx: The associated Efx NIC
196 * @queue: DMA queue number
197 * @label: Label for TX completion events.
198 * Is our index within @channel->tx_queue array.
199 * @type: configuration type of this TX queue. A bitmask of %EFX_TXQ_TYPE_* flags.
200 * @tso_version: Version of TSO in use for this queue.
201 * @tso_encap: Is encapsulated TSO supported? Supported in TSOv2 on 8000 series.
202 * @channel: The associated channel
203 * @core_txq: The networking core TX queue structure
204 * @buffer: The software buffer ring
205 * @cb_page: Array of pages of copy buffers. Carved up according to
206 * %EFX_TX_CB_ORDER into %EFX_TX_CB_SIZE-sized chunks.
207 * @txd: The hardware descriptor ring
208 * @ptr_mask: The size of the ring minus 1.
209 * @piobuf: PIO buffer region for this TX queue (shared with its partner).
210 * @piobuf_offset: Buffer offset to be specified in PIO descriptors
211 * @initialised: Has hardware queue been initialised?
212 * @timestamping: Is timestamping enabled for this channel?
213 * @xdp_tx: Is this an XDP tx queue?
214 * @read_count: Current read pointer.
215 * This is the number of buffers that have been removed from both rings.
216 * @old_write_count: The value of @write_count when last checked.
217 * This is here for performance reasons. The xmit path will
218 * only get the up-to-date value of @write_count if this
219 * variable indicates that the queue is empty. This is to
220 * avoid cache-line ping-pong between the xmit path and the
221 * completion path.
222 * @merge_events: Number of TX merged completion events
223 * @completed_timestamp_major: Top part of the most recent tx timestamp.
224 * @completed_timestamp_minor: Low part of the most recent tx timestamp.
225 * @insert_count: Current insert pointer
226 * This is the number of buffers that have been added to the
227 * software ring.
228 * @write_count: Current write pointer
229 * This is the number of buffers that have been added to the
230 * hardware ring.
231 * @packet_write_count: Completable write pointer
232 * This is the write pointer of the last packet written.
233 * Normally this will equal @write_count, but as option descriptors
234 * don't produce completion events, they won't update this.
235 * Filled in iff @efx->type->option_descriptors; only used for PIO.
236 * Thus, this is written and used on EF10, and neither on farch.
237 * @old_read_count: The value of read_count when last checked.
238 * This is here for performance reasons. The xmit path will
239 * only get the up-to-date value of read_count if this
240 * variable indicates that the queue is full. This is to
241 * avoid cache-line ping-pong between the xmit path and the
242 * completion path.
243 * @tso_bursts: Number of times TSO xmit invoked by kernel
244 * @tso_long_headers: Number of packets with headers too long for standard
245 * blocks
246 * @tso_packets: Number of packets via the TSO xmit path
247 * @tso_fallbacks: Number of times TSO fallback used
248 * @pushes: Number of times the TX push feature has been used
249 * @pio_packets: Number of times the TX PIO feature has been used
250 * @xmit_pending: Are any packets waiting to be pushed to the NIC
251 * @cb_packets: Number of times the TX copybreak feature has been used
252 * @notify_count: Count of notified descriptors to the NIC
253 * @empty_read_count: If the completion path has seen the queue as empty
254 * and the transmission path has not yet checked this, the value of
255 * @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0.
256 */
257struct efx_tx_queue {
258 /* Members which don't change on the fast path */
259 struct efx_nic *efx ____cacheline_aligned_in_smp;
260 unsigned int queue;
261 unsigned int label;
262 unsigned int type;
263 unsigned int tso_version;
264 bool tso_encap;
265 struct efx_channel *channel;
266 struct netdev_queue *core_txq;
267 struct efx_tx_buffer *buffer;
268 struct efx_buffer *cb_page;
269 struct efx_special_buffer txd;
270 unsigned int ptr_mask;
271 void __iomem *piobuf;
272 unsigned int piobuf_offset;
273 bool initialised;
274 bool timestamping;
275 bool xdp_tx;
276
277 /* Members used mainly on the completion path */
278 unsigned int read_count ____cacheline_aligned_in_smp;
279 unsigned int old_write_count;
280 unsigned int merge_events;
281 unsigned int bytes_compl;
282 unsigned int pkts_compl;
283 u32 completed_timestamp_major;
284 u32 completed_timestamp_minor;
285
286 /* Members used only on the xmit path */
287 unsigned int insert_count ____cacheline_aligned_in_smp;
288 unsigned int write_count;
289 unsigned int packet_write_count;
290 unsigned int old_read_count;
291 unsigned int tso_bursts;
292 unsigned int tso_long_headers;
293 unsigned int tso_packets;
294 unsigned int tso_fallbacks;
295 unsigned int pushes;
296 unsigned int pio_packets;
297 bool xmit_pending;
298 unsigned int cb_packets;
299 unsigned int notify_count;
300 /* Statistics to supplement MAC stats */
301 unsigned long tx_packets;
302
303 /* Members shared between paths and sometimes updated */
304 unsigned int empty_read_count ____cacheline_aligned_in_smp;
305#define EFX_EMPTY_COUNT_VALID 0x80000000
306 atomic_t flush_outstanding;
307};
308
309#define EFX_TX_CB_ORDER 7
310#define EFX_TX_CB_SIZE (1 << EFX_TX_CB_ORDER) - NET_IP_ALIGN
311
312/**
313 * struct efx_rx_buffer - An Efx RX data buffer
314 * @dma_addr: DMA base address of the buffer
315 * @page: The associated page buffer.
316 * Will be %NULL if the buffer slot is currently free.
317 * @page_offset: If pending: offset in @page of DMA base address.
318 * If completed: offset in @page of Ethernet header.
319 * @len: If pending: length for DMA descriptor.
320 * If completed: received length, excluding hash prefix.
321 * @flags: Flags for buffer and packet state. These are only set on the
322 * first buffer of a scattered packet.
323 */
324struct efx_rx_buffer {
325 dma_addr_t dma_addr;
326 struct page *page;
327 u16 page_offset;
328 u16 len;
329 u16 flags;
330};
331#define EFX_RX_BUF_LAST_IN_PAGE 0x0001
332#define EFX_RX_PKT_CSUMMED 0x0002
333#define EFX_RX_PKT_DISCARD 0x0004
334#define EFX_RX_PKT_TCP 0x0040
335#define EFX_RX_PKT_PREFIX_LEN 0x0080 /* length is in prefix only */
336#define EFX_RX_PKT_CSUM_LEVEL 0x0200
337
338/**
339 * struct efx_rx_page_state - Page-based rx buffer state
340 *
341 * Inserted at the start of every page allocated for receive buffers.
342 * Used to facilitate sharing dma mappings between recycled rx buffers
343 * and those passed up to the kernel.
344 *
345 * @dma_addr: The dma address of this page.
346 */
347struct efx_rx_page_state {
348 dma_addr_t dma_addr;
349
350 unsigned int __pad[] ____cacheline_aligned;
351};
352
353/**
354 * struct efx_rx_queue - An Efx RX queue
355 * @efx: The associated Efx NIC
356 * @core_index: Index of network core RX queue. Will be >= 0 iff this
357 * is associated with a real RX queue.
358 * @buffer: The software buffer ring
359 * @rxd: The hardware descriptor ring
360 * @ptr_mask: The size of the ring minus 1.
361 * @refill_enabled: Enable refill whenever fill level is low
362 * @flush_pending: Set when a RX flush is pending. Has the same lifetime as
363 * @rxq_flush_pending.
364 * @added_count: Number of buffers added to the receive queue.
365 * @notified_count: Number of buffers given to NIC (<= @added_count).
366 * @removed_count: Number of buffers removed from the receive queue.
367 * @scatter_n: Used by NIC specific receive code.
368 * @scatter_len: Used by NIC specific receive code.
369 * @page_ring: The ring to store DMA mapped pages for reuse.
370 * @page_add: Counter to calculate the write pointer for the recycle ring.
371 * @page_remove: Counter to calculate the read pointer for the recycle ring.
372 * @page_recycle_count: The number of pages that have been recycled.
373 * @page_recycle_failed: The number of pages that couldn't be recycled because
374 * the kernel still held a reference to them.
375 * @page_recycle_full: The number of pages that were released because the
376 * recycle ring was full.
377 * @page_ptr_mask: The number of pages in the RX recycle ring minus 1.
378 * @max_fill: RX descriptor maximum fill level (<= ring size)
379 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
380 * (<= @max_fill)
381 * @min_fill: RX descriptor minimum non-zero fill level.
382 * This records the minimum fill level observed when a ring
383 * refill was triggered.
384 * @recycle_count: RX buffer recycle counter.
385 * @slow_fill: Timer used to defer efx_nic_generate_fill_event().
386 * @xdp_rxq_info: XDP specific RX queue information.
387 * @xdp_rxq_info_valid: Is xdp_rxq_info valid data?.
388 */
389struct efx_rx_queue {
390 struct efx_nic *efx;
391 int core_index;
392 struct efx_rx_buffer *buffer;
393 struct efx_special_buffer rxd;
394 unsigned int ptr_mask;
395 bool refill_enabled;
396 bool flush_pending;
397
398 unsigned int added_count;
399 unsigned int notified_count;
400 unsigned int removed_count;
401 unsigned int scatter_n;
402 unsigned int scatter_len;
403 struct page **page_ring;
404 unsigned int page_add;
405 unsigned int page_remove;
406 unsigned int page_recycle_count;
407 unsigned int page_recycle_failed;
408 unsigned int page_recycle_full;
409 unsigned int page_ptr_mask;
410 unsigned int max_fill;
411 unsigned int fast_fill_trigger;
412 unsigned int min_fill;
413 unsigned int min_overfill;
414 unsigned int recycle_count;
415 struct timer_list slow_fill;
416 unsigned int slow_fill_count;
417 /* Statistics to supplement MAC stats */
418 unsigned long rx_packets;
419 struct xdp_rxq_info xdp_rxq_info;
420 bool xdp_rxq_info_valid;
421};
422
423enum efx_sync_events_state {
424 SYNC_EVENTS_DISABLED = 0,
425 SYNC_EVENTS_QUIESCENT,
426 SYNC_EVENTS_REQUESTED,
427 SYNC_EVENTS_VALID,
428};
429
430/**
431 * struct efx_channel - An Efx channel
432 *
433 * A channel comprises an event queue, at least one TX queue, at least
434 * one RX queue, and an associated tasklet for processing the event
435 * queue.
436 *
437 * @efx: Associated Efx NIC
438 * @channel: Channel instance number
439 * @type: Channel type definition
440 * @eventq_init: Event queue initialised flag
441 * @enabled: Channel enabled indicator
442 * @irq: IRQ number (MSI and MSI-X only)
443 * @irq_moderation_us: IRQ moderation value (in microseconds)
444 * @napi_dev: Net device used with NAPI
445 * @napi_str: NAPI control structure
446 * @state: state for NAPI vs busy polling
447 * @state_lock: lock protecting @state
448 * @eventq: Event queue buffer
449 * @eventq_mask: Event queue pointer mask
450 * @eventq_read_ptr: Event queue read pointer
451 * @event_test_cpu: Last CPU to handle interrupt or test event for this channel
452 * @irq_count: Number of IRQs since last adaptive moderation decision
453 * @irq_mod_score: IRQ moderation score
454 * @rfs_filter_count: number of accelerated RFS filters currently in place;
455 * equals the count of @rps_flow_id slots filled
456 * @rfs_last_expiry: value of jiffies last time some accelerated RFS filters
457 * were checked for expiry
458 * @rfs_expire_index: next accelerated RFS filter ID to check for expiry
459 * @n_rfs_succeeded: number of successful accelerated RFS filter insertions
460 * @n_rfs_failed: number of failed accelerated RFS filter insertions
461 * @filter_work: Work item for efx_filter_rfs_expire()
462 * @rps_flow_id: Flow IDs of filters allocated for accelerated RFS,
463 * indexed by filter ID
464 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
465 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
466 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
467 * @n_rx_mcast_mismatch: Count of unmatched multicast frames
468 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
469 * @n_rx_overlength: Count of RX_OVERLENGTH errors
470 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
471 * @n_rx_nodesc_trunc: Number of RX packets truncated and then dropped due to
472 * lack of descriptors
473 * @n_rx_merge_events: Number of RX merged completion events
474 * @n_rx_merge_packets: Number of RX packets completed by merged events
475 * @n_rx_xdp_drops: Count of RX packets intentionally dropped due to XDP
476 * @n_rx_xdp_bad_drops: Count of RX packets dropped due to XDP errors
477 * @n_rx_xdp_tx: Count of RX packets retransmitted due to XDP
478 * @n_rx_xdp_redirect: Count of RX packets redirected to a different NIC by XDP
479 * @rx_pkt_n_frags: Number of fragments in next packet to be delivered by
480 * __efx_siena_rx_packet(), or zero if there is none
481 * @rx_pkt_index: Ring index of first buffer for next packet to be delivered
482 * by __efx_siena_rx_packet(), if @rx_pkt_n_frags != 0
483 * @rx_list: list of SKBs from current RX, awaiting processing
484 * @rx_queue: RX queue for this channel
485 * @tx_queue: TX queues for this channel
486 * @tx_queue_by_type: pointers into @tx_queue, or %NULL, indexed by txq type
487 * @sync_events_state: Current state of sync events on this channel
488 * @sync_timestamp_major: Major part of the last ptp sync event
489 * @sync_timestamp_minor: Minor part of the last ptp sync event
490 */
491struct efx_channel {
492 struct efx_nic *efx;
493 int channel;
494 const struct efx_channel_type *type;
495 bool eventq_init;
496 bool enabled;
497 int irq;
498 unsigned int irq_moderation_us;
499 struct net_device *napi_dev;
500 struct napi_struct napi_str;
501#ifdef CONFIG_NET_RX_BUSY_POLL
502 unsigned long busy_poll_state;
503#endif
504 struct efx_special_buffer eventq;
505 unsigned int eventq_mask;
506 unsigned int eventq_read_ptr;
507 int event_test_cpu;
508
509 unsigned int irq_count;
510 unsigned int irq_mod_score;
511#ifdef CONFIG_RFS_ACCEL
512 unsigned int rfs_filter_count;
513 unsigned int rfs_last_expiry;
514 unsigned int rfs_expire_index;
515 unsigned int n_rfs_succeeded;
516 unsigned int n_rfs_failed;
517 struct delayed_work filter_work;
518#define RPS_FLOW_ID_INVALID 0xFFFFFFFF
519 u32 *rps_flow_id;
520#endif
521
522 unsigned int n_rx_tobe_disc;
523 unsigned int n_rx_ip_hdr_chksum_err;
524 unsigned int n_rx_tcp_udp_chksum_err;
525 unsigned int n_rx_outer_ip_hdr_chksum_err;
526 unsigned int n_rx_outer_tcp_udp_chksum_err;
527 unsigned int n_rx_inner_ip_hdr_chksum_err;
528 unsigned int n_rx_inner_tcp_udp_chksum_err;
529 unsigned int n_rx_eth_crc_err;
530 unsigned int n_rx_mcast_mismatch;
531 unsigned int n_rx_frm_trunc;
532 unsigned int n_rx_overlength;
533 unsigned int n_skbuff_leaks;
534 unsigned int n_rx_nodesc_trunc;
535 unsigned int n_rx_merge_events;
536 unsigned int n_rx_merge_packets;
537 unsigned int n_rx_xdp_drops;
538 unsigned int n_rx_xdp_bad_drops;
539 unsigned int n_rx_xdp_tx;
540 unsigned int n_rx_xdp_redirect;
541
542 unsigned int rx_pkt_n_frags;
543 unsigned int rx_pkt_index;
544
545 struct list_head *rx_list;
546
547 struct efx_rx_queue rx_queue;
548 struct efx_tx_queue tx_queue[EFX_MAX_TXQ_PER_CHANNEL];
549 struct efx_tx_queue *tx_queue_by_type[EFX_TXQ_TYPES];
550
551 enum efx_sync_events_state sync_events_state;
552 u32 sync_timestamp_major;
553 u32 sync_timestamp_minor;
554};
555
556/**
557 * struct efx_msi_context - Context for each MSI
558 * @efx: The associated NIC
559 * @index: Index of the channel/IRQ
560 * @name: Name of the channel/IRQ
561 *
562 * Unlike &struct efx_channel, this is never reallocated and is always
563 * safe for the IRQ handler to access.
564 */
565struct efx_msi_context {
566 struct efx_nic *efx;
567 unsigned int index;
568 char name[IFNAMSIZ + 6];
569};
570
571/**
572 * struct efx_channel_type - distinguishes traffic and extra channels
573 * @handle_no_channel: Handle failure to allocate an extra channel
574 * @pre_probe: Set up extra state prior to initialisation
575 * @post_remove: Tear down extra state after finalisation, if allocated.
576 * May be called on channels that have not been probed.
577 * @get_name: Generate the channel's name (used for its IRQ handler)
578 * @copy: Copy the channel state prior to reallocation. May be %NULL if
579 * reallocation is not supported.
580 * @receive_skb: Handle an skb ready to be passed to netif_receive_skb()
581 * @want_txqs: Determine whether this channel should have TX queues
582 * created. If %NULL, TX queues are not created.
583 * @keep_eventq: Flag for whether event queue should be kept initialised
584 * while the device is stopped
585 * @want_pio: Flag for whether PIO buffers should be linked to this
586 * channel's TX queues.
587 */
588struct efx_channel_type {
589 void (*handle_no_channel)(struct efx_nic *);
590 int (*pre_probe)(struct efx_channel *);
591 void (*post_remove)(struct efx_channel *);
592 void (*get_name)(struct efx_channel *, char *buf, size_t len);
593 struct efx_channel *(*copy)(const struct efx_channel *);
594 bool (*receive_skb)(struct efx_channel *, struct sk_buff *);
595 bool (*want_txqs)(struct efx_channel *);
596 bool keep_eventq;
597 bool want_pio;
598};
599
600enum efx_led_mode {
601 EFX_LED_OFF = 0,
602 EFX_LED_ON = 1,
603 EFX_LED_DEFAULT = 2
604};
605
606#define STRING_TABLE_LOOKUP(val, member) \
607 ((val) < member ## _max) ? member ## _names[val] : "(invalid)"
608
609extern const char *const efx_siena_loopback_mode_names[];
610extern const unsigned int efx_siena_loopback_mode_max;
611#define LOOPBACK_MODE(efx) \
612 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_siena_loopback_mode)
613
614enum efx_int_mode {
615 /* Be careful if altering to correct macro below */
616 EFX_INT_MODE_MSIX = 0,
617 EFX_INT_MODE_MSI = 1,
618 EFX_INT_MODE_LEGACY = 2,
619 EFX_INT_MODE_MAX /* Insert any new items before this */
620};
621#define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
622
623enum nic_state {
624 STATE_UNINIT = 0, /* device being probed/removed or is frozen */
625 STATE_READY = 1, /* hardware ready and netdev registered */
626 STATE_DISABLED = 2, /* device disabled due to hardware errors */
627 STATE_RECOVERY = 3, /* device recovering from PCI error */
628};
629
630/* Forward declaration */
631struct efx_nic;
632
633/* Pseudo bit-mask flow control field */
634#define EFX_FC_RX FLOW_CTRL_RX
635#define EFX_FC_TX FLOW_CTRL_TX
636#define EFX_FC_AUTO 4
637
638/**
639 * struct efx_link_state - Current state of the link
640 * @up: Link is up
641 * @fd: Link is full-duplex
642 * @fc: Actual flow control flags
643 * @speed: Link speed (Mbps)
644 */
645struct efx_link_state {
646 bool up;
647 bool fd;
648 u8 fc;
649 unsigned int speed;
650};
651
652static inline bool efx_link_state_equal(const struct efx_link_state *left,
653 const struct efx_link_state *right)
654{
655 return left->up == right->up && left->fd == right->fd &&
656 left->fc == right->fc && left->speed == right->speed;
657}
658
659/**
660 * enum efx_phy_mode - PHY operating mode flags
661 * @PHY_MODE_NORMAL: on and should pass traffic
662 * @PHY_MODE_TX_DISABLED: on with TX disabled
663 * @PHY_MODE_LOW_POWER: set to low power through MDIO
664 * @PHY_MODE_OFF: switched off through external control
665 * @PHY_MODE_SPECIAL: on but will not pass traffic
666 */
667enum efx_phy_mode {
668 PHY_MODE_NORMAL = 0,
669 PHY_MODE_TX_DISABLED = 1,
670 PHY_MODE_LOW_POWER = 2,
671 PHY_MODE_OFF = 4,
672 PHY_MODE_SPECIAL = 8,
673};
674
675static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode)
676{
677 return !!(mode & ~PHY_MODE_TX_DISABLED);
678}
679
680/**
681 * struct efx_hw_stat_desc - Description of a hardware statistic
682 * @name: Name of the statistic as visible through ethtool, or %NULL if
683 * it should not be exposed
684 * @dma_width: Width in bits (0 for non-DMA statistics)
685 * @offset: Offset within stats (ignored for non-DMA statistics)
686 */
687struct efx_hw_stat_desc {
688 const char *name;
689 u16 dma_width;
690 u16 offset;
691};
692
693/* Number of bits used in a multicast filter hash address */
694#define EFX_MCAST_HASH_BITS 8
695
696/* Number of (single-bit) entries in a multicast filter hash */
697#define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
698
699/* An Efx multicast filter hash */
700union efx_multicast_hash {
701 u8 byte[EFX_MCAST_HASH_ENTRIES / 8];
702 efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8];
703};
704
705struct vfdi_status;
706
707/* The reserved RSS context value */
708#define EFX_MCDI_RSS_CONTEXT_INVALID 0xffffffff
709/**
710 * struct efx_rss_context - An RSS context for filtering
711 * @context_id: 0 if RSS is active, else %EFX_MCDI_RSS_CONTEXT_INVALID.
712 * @rx_hash_udp_4tuple: UDP 4-tuple hashing enabled
713 * @rx_hash_key: Toeplitz hash key for this RSS context
714 * @indir_table: Indirection table for this RSS context
715 */
716struct efx_rss_context {
717 u32 context_id;
718 bool rx_hash_udp_4tuple;
719 u8 rx_hash_key[40];
720 u32 rx_indir_table[128];
721};
722
723#ifdef CONFIG_RFS_ACCEL
724/* Order of these is important, since filter_id >= %EFX_ARFS_FILTER_ID_PENDING
725 * is used to test if filter does or will exist.
726 */
727#define EFX_ARFS_FILTER_ID_PENDING -1
728#define EFX_ARFS_FILTER_ID_ERROR -2
729#define EFX_ARFS_FILTER_ID_REMOVING -3
730/**
731 * struct efx_arfs_rule - record of an ARFS filter and its IDs
732 * @node: linkage into hash table
733 * @spec: details of the filter (used as key for hash table). Use efx->type to
734 * determine which member to use.
735 * @rxq_index: channel to which the filter will steer traffic.
736 * @arfs_id: filter ID which was returned to ARFS
737 * @filter_id: index in software filter table. May be
738 * %EFX_ARFS_FILTER_ID_PENDING if filter was not inserted yet,
739 * %EFX_ARFS_FILTER_ID_ERROR if filter insertion failed, or
740 * %EFX_ARFS_FILTER_ID_REMOVING if expiry is currently removing the filter.
741 */
742struct efx_arfs_rule {
743 struct hlist_node node;
744 struct efx_filter_spec spec;
745 u16 rxq_index;
746 u16 arfs_id;
747 s32 filter_id;
748};
749
750/* Size chosen so that the table is one page (4kB) */
751#define EFX_ARFS_HASH_TABLE_SIZE 512
752
753/**
754 * struct efx_async_filter_insertion - Request to asynchronously insert a filter
755 * @net_dev: Reference to the netdevice
756 * @spec: The filter to insert
757 * @work: Workitem for this request
758 * @rxq_index: Identifies the channel for which this request was made
759 * @flow_id: Identifies the kernel-side flow for which this request was made
760 */
761struct efx_async_filter_insertion {
762 struct net_device *net_dev;
763 struct efx_filter_spec spec;
764 struct work_struct work;
765 u16 rxq_index;
766 u32 flow_id;
767};
768
769/* Maximum number of ARFS workitems that may be in flight on an efx_nic */
770#define EFX_RPS_MAX_IN_FLIGHT 8
771#endif /* CONFIG_RFS_ACCEL */
772
773enum efx_xdp_tx_queues_mode {
774 EFX_XDP_TX_QUEUES_DEDICATED, /* one queue per core, locking not needed */
775 EFX_XDP_TX_QUEUES_SHARED, /* each queue used by more than 1 core */
776 EFX_XDP_TX_QUEUES_BORROWED /* queues borrowed from net stack */
777};
778
779/**
780 * struct efx_nic - an Efx NIC
781 * @name: Device name (net device name or bus id before net device registered)
782 * @pci_dev: The PCI device
783 * @node: List node for maintaning primary/secondary function lists
784 * @primary: &struct efx_nic instance for the primary function of this
785 * controller. May be the same structure, and may be %NULL if no
786 * primary function is bound. Serialised by rtnl_lock.
787 * @secondary_list: List of &struct efx_nic instances for the secondary PCI
788 * functions of the controller, if this is for the primary function.
789 * Serialised by rtnl_lock.
790 * @type: Controller type attributes
791 * @legacy_irq: IRQ number
792 * @workqueue: Workqueue for port reconfigures and the HW monitor.
793 * Work items do not hold and must not acquire RTNL.
794 * @workqueue_name: Name of workqueue
795 * @reset_work: Scheduled reset workitem
796 * @membase_phys: Memory BAR value as physical address
797 * @membase: Memory BAR value
798 * @vi_stride: step between per-VI registers / memory regions
799 * @interrupt_mode: Interrupt mode
800 * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds
801 * @timer_max_ns: Interrupt timer maximum value, in nanoseconds
802 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues
803 * @irqs_hooked: Channel interrupts are hooked
804 * @irq_rx_mod_step_us: Step size for IRQ moderation for RX event queues
805 * @irq_rx_moderation_us: IRQ moderation time for RX event queues
806 * @msg_enable: Log message enable flags
807 * @state: Device state number (%STATE_*). Serialised by the rtnl_lock.
808 * @reset_pending: Bitmask for pending resets
809 * @tx_queue: TX DMA queues
810 * @rx_queue: RX DMA queues
811 * @channel: Channels
812 * @msi_context: Context for each MSI
813 * @extra_channel_types: Types of extra (non-traffic) channels that
814 * should be allocated for this NIC
815 * @xdp_tx_queue_count: Number of entries in %xdp_tx_queues.
816 * @xdp_tx_queues: Array of pointers to tx queues used for XDP transmit.
817 * @xdp_txq_queues_mode: XDP TX queues sharing strategy.
818 * @rxq_entries: Size of receive queues requested by user.
819 * @txq_entries: Size of transmit queues requested by user.
820 * @txq_stop_thresh: TX queue fill level at or above which we stop it.
821 * @txq_wake_thresh: TX queue fill level at or below which we wake it.
822 * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches
823 * @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches
824 * @sram_lim_qw: Qword address limit of SRAM
825 * @next_buffer_table: First available buffer table id
826 * @n_channels: Number of channels in use
827 * @n_rx_channels: Number of channels used for RX (= number of RX queues)
828 * @n_tx_channels: Number of channels used for TX
829 * @n_extra_tx_channels: Number of extra channels with TX queues
830 * @tx_queues_per_channel: number of TX queues probed on each channel
831 * @n_xdp_channels: Number of channels used for XDP TX
832 * @xdp_channel_offset: Offset of zeroth channel used for XPD TX.
833 * @xdp_tx_per_channel: Max number of TX queues on an XDP TX channel.
834 * @rx_ip_align: RX DMA address offset to have IP header aligned in
835 * accordance with NET_IP_ALIGN
836 * @rx_dma_len: Current maximum RX DMA length
837 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
838 * @rx_buffer_truesize: Amortised allocation size of an RX buffer,
839 * for use in sk_buff::truesize
840 * @rx_prefix_size: Size of RX prefix before packet data
841 * @rx_packet_hash_offset: Offset of RX flow hash from start of packet data
842 * (valid only if @rx_prefix_size != 0; always negative)
843 * @rx_packet_len_offset: Offset of RX packet length from start of packet data
844 * (valid only for NICs that set %EFX_RX_PKT_PREFIX_LEN; always negative)
845 * @rx_packet_ts_offset: Offset of timestamp from start of packet data
846 * (valid only if channel->sync_timestamps_enabled; always negative)
847 * @rx_scatter: Scatter mode enabled for receives
848 * @rss_context: Main RSS context
849 * @vport_id: The function's vport ID, only relevant for PFs
850 * @int_error_count: Number of internal errors seen recently
851 * @int_error_expire: Time at which error count will be expired
852 * @must_realloc_vis: Flag: VIs have yet to be reallocated after MC reboot
853 * @irq_soft_enabled: Are IRQs soft-enabled? If not, IRQ handler will
854 * acknowledge but do nothing else.
855 * @irq_status: Interrupt status buffer
856 * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0
857 * @irq_level: IRQ level/index for IRQs not triggered by an event queue
858 * @selftest_work: Work item for asynchronous self-test
859 * @mtd_list: List of MTDs attached to the NIC
860 * @nic_data: Hardware dependent state
861 * @mcdi: Management-Controller-to-Driver Interface state
862 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,
863 * efx_monitor() and efx_siena_reconfigure_port()
864 * @port_enabled: Port enabled indicator.
865 * Serialises efx_siena_stop_all(), efx_siena_start_all(),
866 * efx_monitor() and efx_mac_work() with kernel interfaces.
867 * Safe to read under any one of the rtnl_lock, mac_lock, or netif_tx_lock,
868 * but all three must be held to modify it.
869 * @port_initialized: Port initialized?
870 * @net_dev: Operating system network device. Consider holding the rtnl lock
871 * @fixed_features: Features which cannot be turned off
872 * @num_mac_stats: Number of MAC stats reported by firmware (MAC_STATS_NUM_STATS
873 * field of %MC_CMD_GET_CAPABILITIES_V4 response, or %MC_CMD_MAC_NSTATS)
874 * @stats_buffer: DMA buffer for statistics
875 * @phy_type: PHY type
876 * @phy_data: PHY private data (including PHY-specific stats)
877 * @mdio: PHY MDIO interface
878 * @mdio_bus: PHY MDIO bus ID (only used by Siena)
879 * @phy_mode: PHY operating mode. Serialised by @mac_lock.
880 * @link_advertising: Autonegotiation advertising flags
881 * @fec_config: Forward Error Correction configuration flags. For bit positions
882 * see &enum ethtool_fec_config_bits.
883 * @link_state: Current state of the link
884 * @n_link_state_changes: Number of times the link has changed state
885 * @unicast_filter: Flag for Falcon-arch simple unicast filter.
886 * Protected by @mac_lock.
887 * @multicast_hash: Multicast hash table for Falcon-arch.
888 * Protected by @mac_lock.
889 * @wanted_fc: Wanted flow control flags
890 * @fc_disable: When non-zero flow control is disabled. Typically used to
891 * ensure that network back pressure doesn't delay dma queue flushes.
892 * Serialised by the rtnl lock.
893 * @mac_work: Work item for changing MAC promiscuity and multicast hash
894 * @loopback_mode: Loopback status
895 * @loopback_modes: Supported loopback mode bitmask
896 * @loopback_selftest: Offline self-test private state
897 * @xdp_prog: Current XDP programme for this interface
898 * @filter_sem: Filter table rw_semaphore, protects existence of @filter_state
899 * @filter_state: Architecture-dependent filter table state
900 * @rps_mutex: Protects RPS state of all channels
901 * @rps_slot_map: bitmap of in-flight entries in @rps_slot
902 * @rps_slot: array of ARFS insertion requests for efx_filter_rfs_work()
903 * @rps_hash_lock: Protects ARFS filter mapping state (@rps_hash_table and
904 * @rps_next_id).
905 * @rps_hash_table: Mapping between ARFS filters and their various IDs
906 * @rps_next_id: next arfs_id for an ARFS filter
907 * @active_queues: Count of RX and TX queues that haven't been flushed and drained.
908 * @rxq_flush_pending: Count of number of receive queues that need to be flushed.
909 * Decremented when the efx_flush_rx_queue() is called.
910 * @rxq_flush_outstanding: Count of number of RX flushes started but not yet
911 * completed (either success or failure). Not used when MCDI is used to
912 * flush receive queues.
913 * @flush_wq: wait queue used by efx_nic_flush_queues() to wait for flush completions.
914 * @vf_count: Number of VFs intended to be enabled.
915 * @vf_init_count: Number of VFs that have been fully initialised.
916 * @vi_scale: log2 number of vnics per VF.
917 * @ptp_data: PTP state data
918 * @ptp_warned: has this NIC seen and warned about unexpected PTP events?
919 * @vpd_sn: Serial number read from VPD
920 * @xdp_rxq_info_failed: Have any of the rx queues failed to initialise their
921 * xdp_rxq_info structures?
922 * @netdev_notifier: Netdevice notifier.
923 * @mem_bar: The BAR that is mapped into membase.
924 * @reg_base: Offset from the start of the bar to the function control window.
925 * @monitor_work: Hardware monitor workitem
926 * @biu_lock: BIU (bus interface unit) lock
927 * @last_irq_cpu: Last CPU to handle a possible test interrupt. This
928 * field is used by efx_test_interrupts() to verify that an
929 * interrupt has occurred.
930 * @stats_lock: Statistics update lock. Must be held when calling
931 * efx_nic_type::{update,start,stop}_stats.
932 * @n_rx_noskb_drops: Count of RX packets dropped due to failure to allocate an skb
933 *
934 * This is stored in the private area of the &struct net_device.
935 */
936struct efx_nic {
937 /* The following fields should be written very rarely */
938
939 char name[IFNAMSIZ];
940 struct list_head node;
941 struct efx_nic *primary;
942 struct list_head secondary_list;
943 struct pci_dev *pci_dev;
944 unsigned int port_num;
945 const struct efx_nic_type *type;
946 int legacy_irq;
947 bool eeh_disabled_legacy_irq;
948 struct workqueue_struct *workqueue;
949 char workqueue_name[16];
950 struct work_struct reset_work;
951 resource_size_t membase_phys;
952 void __iomem *membase;
953
954 unsigned int vi_stride;
955
956 enum efx_int_mode interrupt_mode;
957 unsigned int timer_quantum_ns;
958 unsigned int timer_max_ns;
959 bool irq_rx_adaptive;
960 bool irqs_hooked;
961 unsigned int irq_mod_step_us;
962 unsigned int irq_rx_moderation_us;
963 u32 msg_enable;
964
965 enum nic_state state;
966 unsigned long reset_pending;
967
968 struct efx_channel *channel[EFX_MAX_CHANNELS];
969 struct efx_msi_context msi_context[EFX_MAX_CHANNELS];
970 const struct efx_channel_type *
971 extra_channel_type[EFX_MAX_EXTRA_CHANNELS];
972
973 unsigned int xdp_tx_queue_count;
974 struct efx_tx_queue **xdp_tx_queues;
975 enum efx_xdp_tx_queues_mode xdp_txq_queues_mode;
976
977 unsigned rxq_entries;
978 unsigned txq_entries;
979 unsigned int txq_stop_thresh;
980 unsigned int txq_wake_thresh;
981
982 unsigned tx_dc_base;
983 unsigned rx_dc_base;
984 unsigned sram_lim_qw;
985 unsigned next_buffer_table;
986
987 unsigned int max_channels;
988 unsigned int max_vis;
989 unsigned int max_tx_channels;
990 unsigned n_channels;
991 unsigned n_rx_channels;
992 unsigned rss_spread;
993 unsigned tx_channel_offset;
994 unsigned n_tx_channels;
995 unsigned n_extra_tx_channels;
996 unsigned int tx_queues_per_channel;
997 unsigned int n_xdp_channels;
998 unsigned int xdp_channel_offset;
999 unsigned int xdp_tx_per_channel;
1000 unsigned int rx_ip_align;
1001 unsigned int rx_dma_len;
1002 unsigned int rx_buffer_order;
1003 unsigned int rx_buffer_truesize;
1004 unsigned int rx_page_buf_step;
1005 unsigned int rx_bufs_per_page;
1006 unsigned int rx_pages_per_batch;
1007 unsigned int rx_prefix_size;
1008 int rx_packet_hash_offset;
1009 int rx_packet_len_offset;
1010 int rx_packet_ts_offset;
1011 bool rx_scatter;
1012 struct efx_rss_context rss_context;
1013 u32 vport_id;
1014
1015 unsigned int_error_count;
1016 unsigned long int_error_expire;
1017
1018 bool must_realloc_vis;
1019 bool irq_soft_enabled;
1020 struct efx_buffer irq_status;
1021 unsigned irq_zero_count;
1022 unsigned irq_level;
1023 struct delayed_work selftest_work;
1024
1025#ifdef CONFIG_SFC_SIENA_MTD
1026 struct list_head mtd_list;
1027#endif
1028
1029 void *nic_data;
1030 struct efx_mcdi_data *mcdi;
1031
1032 struct mutex mac_lock;
1033 struct work_struct mac_work;
1034 bool port_enabled;
1035
1036 bool mc_bist_for_other_fn;
1037 bool port_initialized;
1038 struct net_device *net_dev;
1039
1040 netdev_features_t fixed_features;
1041
1042 u16 num_mac_stats;
1043 struct efx_buffer stats_buffer;
1044 u64 rx_nodesc_drops_total;
1045 u64 rx_nodesc_drops_while_down;
1046 bool rx_nodesc_drops_prev_state;
1047
1048 unsigned int phy_type;
1049 void *phy_data;
1050 struct mdio_if_info mdio;
1051 unsigned int mdio_bus;
1052 enum efx_phy_mode phy_mode;
1053
1054 __ETHTOOL_DECLARE_LINK_MODE_MASK(link_advertising);
1055 u32 fec_config;
1056 struct efx_link_state link_state;
1057 unsigned int n_link_state_changes;
1058
1059 bool unicast_filter;
1060 union efx_multicast_hash multicast_hash;
1061 u8 wanted_fc;
1062 unsigned fc_disable;
1063
1064 atomic_t rx_reset;
1065 enum efx_loopback_mode loopback_mode;
1066 u64 loopback_modes;
1067
1068 void *loopback_selftest;
1069 /* We access loopback_selftest immediately before running XDP,
1070 * so we want them next to each other.
1071 */
1072 struct bpf_prog __rcu *xdp_prog;
1073
1074 struct rw_semaphore filter_sem;
1075 void *filter_state;
1076#ifdef CONFIG_RFS_ACCEL
1077 struct mutex rps_mutex;
1078 unsigned long rps_slot_map;
1079 struct efx_async_filter_insertion rps_slot[EFX_RPS_MAX_IN_FLIGHT];
1080 spinlock_t rps_hash_lock;
1081 struct hlist_head *rps_hash_table;
1082 u32 rps_next_id;
1083#endif
1084
1085 atomic_t active_queues;
1086 atomic_t rxq_flush_pending;
1087 atomic_t rxq_flush_outstanding;
1088 wait_queue_head_t flush_wq;
1089
1090#ifdef CONFIG_SFC_SIENA_SRIOV
1091 unsigned vf_count;
1092 unsigned vf_init_count;
1093 unsigned vi_scale;
1094#endif
1095
1096 struct efx_ptp_data *ptp_data;
1097 bool ptp_warned;
1098
1099 char *vpd_sn;
1100 bool xdp_rxq_info_failed;
1101
1102 struct notifier_block netdev_notifier;
1103
1104 unsigned int mem_bar;
1105 u32 reg_base;
1106
1107 /* The following fields may be written more often */
1108
1109 struct delayed_work monitor_work ____cacheline_aligned_in_smp;
1110 spinlock_t biu_lock;
1111 int last_irq_cpu;
1112 spinlock_t stats_lock;
1113 atomic_t n_rx_noskb_drops;
1114};
1115
1116static inline int efx_dev_registered(struct efx_nic *efx)
1117{
1118 return efx->net_dev->reg_state == NETREG_REGISTERED;
1119}
1120
1121static inline unsigned int efx_port_num(struct efx_nic *efx)
1122{
1123 return efx->port_num;
1124}
1125
1126struct efx_mtd_partition {
1127 struct list_head node;
1128 struct mtd_info mtd;
1129 const char *dev_type_name;
1130 const char *type_name;
1131 char name[IFNAMSIZ + 20];
1132};
1133
1134struct efx_udp_tunnel {
1135#define TUNNEL_ENCAP_UDP_PORT_ENTRY_INVALID 0xffff
1136 u16 type; /* TUNNEL_ENCAP_UDP_PORT_ENTRY_foo, see mcdi_pcol.h */
1137 __be16 port;
1138};
1139
1140/**
1141 * struct efx_nic_type - Efx device type definition
1142 * @mem_bar: Get the memory BAR
1143 * @mem_map_size: Get memory BAR mapped size
1144 * @probe: Probe the controller
1145 * @remove: Free resources allocated by probe()
1146 * @init: Initialise the controller
1147 * @dimension_resources: Dimension controller resources (buffer table,
1148 * and VIs once the available interrupt resources are clear)
1149 * @fini: Shut down the controller
1150 * @monitor: Periodic function for polling link state and hardware monitor
1151 * @map_reset_reason: Map ethtool reset reason to a reset method
1152 * @map_reset_flags: Map ethtool reset flags to a reset method, if possible
1153 * @reset: Reset the controller hardware and possibly the PHY. This will
1154 * be called while the controller is uninitialised.
1155 * @probe_port: Probe the MAC and PHY
1156 * @remove_port: Free resources allocated by probe_port()
1157 * @handle_global_event: Handle a "global" event (may be %NULL)
1158 * @fini_dmaq: Flush and finalise DMA queues (RX and TX queues)
1159 * @prepare_flush: Prepare the hardware for flushing the DMA queues
1160 * (for Falcon architecture)
1161 * @finish_flush: Clean up after flushing the DMA queues (for Falcon
1162 * architecture)
1163 * @prepare_flr: Prepare for an FLR
1164 * @finish_flr: Clean up after an FLR
1165 * @describe_stats: Describe statistics for ethtool
1166 * @update_stats: Update statistics not provided by event handling.
1167 * Either argument may be %NULL.
1168 * @update_stats_atomic: Update statistics while in atomic context, if that
1169 * is more limiting than @update_stats. Otherwise, leave %NULL and
1170 * driver core will call @update_stats.
1171 * @start_stats: Start the regular fetching of statistics
1172 * @pull_stats: Pull stats from the NIC and wait until they arrive.
1173 * @stop_stats: Stop the regular fetching of statistics
1174 * @push_irq_moderation: Apply interrupt moderation value
1175 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY
1176 * @prepare_enable_fc_tx: Prepare MAC to enable pause frame TX (may be %NULL)
1177 * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings
1178 * to the hardware. Serialised by the mac_lock.
1179 * @check_mac_fault: Check MAC fault state. True if fault present.
1180 * @get_wol: Get WoL configuration from driver state
1181 * @set_wol: Push WoL configuration to the NIC
1182 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume)
1183 * @get_fec_stats: Get standard FEC statistics.
1184 * @test_chip: Test registers. May use efx_farch_test_registers(), and is
1185 * expected to reset the NIC.
1186 * @test_nvram: Test validity of NVRAM contents
1187 * @mcdi_request: Send an MCDI request with the given header and SDU.
1188 * The SDU length may be any value from 0 up to the protocol-
1189 * defined maximum, but its buffer will be padded to a multiple
1190 * of 4 bytes.
1191 * @mcdi_poll_response: Test whether an MCDI response is available.
1192 * @mcdi_read_response: Read the MCDI response PDU. The offset will
1193 * be a multiple of 4. The length may not be, but the buffer
1194 * will be padded so it is safe to round up.
1195 * @mcdi_poll_reboot: Test whether the MCDI has rebooted. If so,
1196 * return an appropriate error code for aborting any current
1197 * request; otherwise return 0.
1198 * @irq_enable_master: Enable IRQs on the NIC. Each event queue must
1199 * be separately enabled after this.
1200 * @irq_test_generate: Generate a test IRQ
1201 * @irq_disable_non_ev: Disable non-event IRQs on the NIC. Each event
1202 * queue must be separately disabled before this.
1203 * @irq_handle_msi: Handle MSI for a channel. The @dev_id argument is
1204 * a pointer to the &struct efx_msi_context for the channel.
1205 * @irq_handle_legacy: Handle legacy interrupt. The @dev_id argument
1206 * is a pointer to the &struct efx_nic.
1207 * @tx_probe: Allocate resources for TX queue (and select TXQ type)
1208 * @tx_init: Initialise TX queue on the NIC
1209 * @tx_remove: Free resources for TX queue
1210 * @tx_write: Write TX descriptors and doorbell
1211 * @tx_enqueue: Add an SKB to TX queue
1212 * @rx_push_rss_config: Write RSS hash key and indirection table to the NIC
1213 * @rx_pull_rss_config: Read RSS hash key and indirection table back from the NIC
1214 * @rx_probe: Allocate resources for RX queue
1215 * @rx_init: Initialise RX queue on the NIC
1216 * @rx_remove: Free resources for RX queue
1217 * @rx_write: Write RX descriptors and doorbell
1218 * @rx_defer_refill: Generate a refill reminder event
1219 * @rx_packet: Receive the queued RX buffer on a channel
1220 * @rx_buf_hash_valid: Determine whether the RX prefix contains a valid hash
1221 * @ev_probe: Allocate resources for event queue
1222 * @ev_init: Initialise event queue on the NIC
1223 * @ev_fini: Deinitialise event queue on the NIC
1224 * @ev_remove: Free resources for event queue
1225 * @ev_process: Process events for a queue, up to the given NAPI quota
1226 * @ev_read_ack: Acknowledge read events on a queue, rearming its IRQ
1227 * @ev_test_generate: Generate a test event
1228 * @filter_table_probe: Probe filter capabilities and set up filter software state
1229 * @filter_table_restore: Restore filters removed from hardware
1230 * @filter_table_remove: Remove filters from hardware and tear down software state
1231 * @filter_update_rx_scatter: Update filters after change to rx scatter setting
1232 * @filter_insert: add or replace a filter
1233 * @filter_remove_safe: remove a filter by ID, carefully
1234 * @filter_get_safe: retrieve a filter by ID, carefully
1235 * @filter_clear_rx: Remove all RX filters whose priority is less than or
1236 * equal to the given priority and is not %EFX_FILTER_PRI_AUTO
1237 * @filter_count_rx_used: Get the number of filters in use at a given priority
1238 * @filter_get_rx_id_limit: Get maximum value of a filter id, plus 1
1239 * @filter_get_rx_ids: Get list of RX filters at a given priority
1240 * @filter_rfs_expire_one: Consider expiring a filter inserted for RFS.
1241 * This must check whether the specified table entry is used by RFS
1242 * and that rps_may_expire_flow() returns true for it.
1243 * @mtd_probe: Probe and add MTD partitions associated with this net device,
1244 * using efx_siena_mtd_add()
1245 * @mtd_rename: Set an MTD partition name using the net device name
1246 * @mtd_read: Read from an MTD partition
1247 * @mtd_erase: Erase part of an MTD partition
1248 * @mtd_write: Write to an MTD partition
1249 * @mtd_sync: Wait for write-back to complete on MTD partition. This
1250 * also notifies the driver that a writer has finished using this
1251 * partition.
1252 * @ptp_write_host_time: Send host time to MC as part of sync protocol
1253 * @ptp_set_ts_sync_events: Enable or disable sync events for inline RX
1254 * timestamping, possibly only temporarily for the purposes of a reset.
1255 * @ptp_set_ts_config: Set hardware timestamp configuration. The flags
1256 * and tx_type will already have been validated but this operation
1257 * must validate and update rx_filter.
1258 * @get_phys_port_id: Get the underlying physical port id.
1259 * @set_mac_address: Set the MAC address of the device
1260 * @tso_versions: Returns mask of firmware-assisted TSO versions supported.
1261 * If %NULL, then device does not support any TSO version.
1262 * @udp_tnl_push_ports: Push the list of UDP tunnel ports to the NIC if required.
1263 * @udp_tnl_has_port: Check if a port has been added as UDP tunnel
1264 * @print_additional_fwver: Dump NIC-specific additional FW version info
1265 * @sensor_event: Handle a sensor event from MCDI
1266 * @rx_recycle_ring_size: Size of the RX recycle ring
1267 * @revision: Hardware architecture revision
1268 * @txd_ptr_tbl_base: TX descriptor ring base address
1269 * @rxd_ptr_tbl_base: RX descriptor ring base address
1270 * @buf_tbl_base: Buffer table base address
1271 * @evq_ptr_tbl_base: Event queue pointer table base address
1272 * @evq_rptr_tbl_base: Event queue read-pointer table base address
1273 * @max_dma_mask: Maximum possible DMA mask
1274 * @rx_prefix_size: Size of RX prefix before packet data
1275 * @rx_hash_offset: Offset of RX flow hash within prefix
1276 * @rx_ts_offset: Offset of timestamp within prefix
1277 * @rx_buffer_padding: Size of padding at end of RX packet
1278 * @can_rx_scatter: NIC is able to scatter packets to multiple buffers
1279 * @always_rx_scatter: NIC will always scatter packets to multiple buffers
1280 * @option_descriptors: NIC supports TX option descriptors
1281 * @min_interrupt_mode: Lowest capability interrupt mode supported
1282 * from &enum efx_int_mode.
1283 * @timer_period_max: Maximum period of interrupt timer (in ticks)
1284 * @offload_features: net_device feature flags for protocol offload
1285 * features implemented in hardware
1286 * @mcdi_max_ver: Maximum MCDI version supported
1287 * @hwtstamp_filters: Mask of hardware timestamp filter types supported
1288 */
1289struct efx_nic_type {
1290 bool is_vf;
1291 unsigned int (*mem_bar)(struct efx_nic *efx);
1292 unsigned int (*mem_map_size)(struct efx_nic *efx);
1293 int (*probe)(struct efx_nic *efx);
1294 void (*remove)(struct efx_nic *efx);
1295 int (*init)(struct efx_nic *efx);
1296 int (*dimension_resources)(struct efx_nic *efx);
1297 void (*fini)(struct efx_nic *efx);
1298 void (*monitor)(struct efx_nic *efx);
1299 enum reset_type (*map_reset_reason)(enum reset_type reason);
1300 int (*map_reset_flags)(u32 *flags);
1301 int (*reset)(struct efx_nic *efx, enum reset_type method);
1302 int (*probe_port)(struct efx_nic *efx);
1303 void (*remove_port)(struct efx_nic *efx);
1304 bool (*handle_global_event)(struct efx_channel *channel, efx_qword_t *);
1305 int (*fini_dmaq)(struct efx_nic *efx);
1306 void (*prepare_flush)(struct efx_nic *efx);
1307 void (*finish_flush)(struct efx_nic *efx);
1308 void (*prepare_flr)(struct efx_nic *efx);
1309 void (*finish_flr)(struct efx_nic *efx);
1310 size_t (*describe_stats)(struct efx_nic *efx, u8 **names);
1311 size_t (*update_stats)(struct efx_nic *efx, u64 *full_stats,
1312 struct rtnl_link_stats64 *core_stats);
1313 size_t (*update_stats_atomic)(struct efx_nic *efx, u64 *full_stats,
1314 struct rtnl_link_stats64 *core_stats);
1315 void (*start_stats)(struct efx_nic *efx);
1316 void (*pull_stats)(struct efx_nic *efx);
1317 void (*stop_stats)(struct efx_nic *efx);
1318 void (*push_irq_moderation)(struct efx_channel *channel);
1319 int (*reconfigure_port)(struct efx_nic *efx);
1320 void (*prepare_enable_fc_tx)(struct efx_nic *efx);
1321 int (*reconfigure_mac)(struct efx_nic *efx, bool mtu_only);
1322 bool (*check_mac_fault)(struct efx_nic *efx);
1323 void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol);
1324 int (*set_wol)(struct efx_nic *efx, u32 type);
1325 void (*resume_wol)(struct efx_nic *efx);
1326 void (*get_fec_stats)(struct efx_nic *efx,
1327 struct ethtool_fec_stats *fec_stats);
1328 unsigned int (*check_caps)(const struct efx_nic *efx,
1329 u8 flag,
1330 u32 offset);
1331 int (*test_chip)(struct efx_nic *efx, struct efx_self_tests *tests);
1332 int (*test_nvram)(struct efx_nic *efx);
1333 void (*mcdi_request)(struct efx_nic *efx,
1334 const efx_dword_t *hdr, size_t hdr_len,
1335 const efx_dword_t *sdu, size_t sdu_len);
1336 bool (*mcdi_poll_response)(struct efx_nic *efx);
1337 void (*mcdi_read_response)(struct efx_nic *efx, efx_dword_t *pdu,
1338 size_t pdu_offset, size_t pdu_len);
1339 int (*mcdi_poll_reboot)(struct efx_nic *efx);
1340 void (*mcdi_reboot_detected)(struct efx_nic *efx);
1341 void (*irq_enable_master)(struct efx_nic *efx);
1342 int (*irq_test_generate)(struct efx_nic *efx);
1343 void (*irq_disable_non_ev)(struct efx_nic *efx);
1344 irqreturn_t (*irq_handle_msi)(int irq, void *dev_id);
1345 irqreturn_t (*irq_handle_legacy)(int irq, void *dev_id);
1346 int (*tx_probe)(struct efx_tx_queue *tx_queue);
1347 void (*tx_init)(struct efx_tx_queue *tx_queue);
1348 void (*tx_remove)(struct efx_tx_queue *tx_queue);
1349 void (*tx_write)(struct efx_tx_queue *tx_queue);
1350 netdev_tx_t (*tx_enqueue)(struct efx_tx_queue *tx_queue, struct sk_buff *skb);
1351 unsigned int (*tx_limit_len)(struct efx_tx_queue *tx_queue,
1352 dma_addr_t dma_addr, unsigned int len);
1353 int (*rx_push_rss_config)(struct efx_nic *efx, bool user,
1354 const u32 *rx_indir_table, const u8 *key);
1355 int (*rx_pull_rss_config)(struct efx_nic *efx);
1356 int (*rx_probe)(struct efx_rx_queue *rx_queue);
1357 void (*rx_init)(struct efx_rx_queue *rx_queue);
1358 void (*rx_remove)(struct efx_rx_queue *rx_queue);
1359 void (*rx_write)(struct efx_rx_queue *rx_queue);
1360 void (*rx_defer_refill)(struct efx_rx_queue *rx_queue);
1361 void (*rx_packet)(struct efx_channel *channel);
1362 bool (*rx_buf_hash_valid)(const u8 *prefix);
1363 int (*ev_probe)(struct efx_channel *channel);
1364 int (*ev_init)(struct efx_channel *channel);
1365 void (*ev_fini)(struct efx_channel *channel);
1366 void (*ev_remove)(struct efx_channel *channel);
1367 int (*ev_process)(struct efx_channel *channel, int quota);
1368 void (*ev_read_ack)(struct efx_channel *channel);
1369 void (*ev_test_generate)(struct efx_channel *channel);
1370 int (*filter_table_probe)(struct efx_nic *efx);
1371 void (*filter_table_restore)(struct efx_nic *efx);
1372 void (*filter_table_remove)(struct efx_nic *efx);
1373 void (*filter_update_rx_scatter)(struct efx_nic *efx);
1374 s32 (*filter_insert)(struct efx_nic *efx,
1375 struct efx_filter_spec *spec, bool replace);
1376 int (*filter_remove_safe)(struct efx_nic *efx,
1377 enum efx_filter_priority priority,
1378 u32 filter_id);
1379 int (*filter_get_safe)(struct efx_nic *efx,
1380 enum efx_filter_priority priority,
1381 u32 filter_id, struct efx_filter_spec *);
1382 int (*filter_clear_rx)(struct efx_nic *efx,
1383 enum efx_filter_priority priority);
1384 u32 (*filter_count_rx_used)(struct efx_nic *efx,
1385 enum efx_filter_priority priority);
1386 u32 (*filter_get_rx_id_limit)(struct efx_nic *efx);
1387 s32 (*filter_get_rx_ids)(struct efx_nic *efx,
1388 enum efx_filter_priority priority,
1389 u32 *buf, u32 size);
1390#ifdef CONFIG_RFS_ACCEL
1391 bool (*filter_rfs_expire_one)(struct efx_nic *efx, u32 flow_id,
1392 unsigned int index);
1393#endif
1394#ifdef CONFIG_SFC_SIENA_MTD
1395 int (*mtd_probe)(struct efx_nic *efx);
1396 void (*mtd_rename)(struct efx_mtd_partition *part);
1397 int (*mtd_read)(struct mtd_info *mtd, loff_t start, size_t len,
1398 size_t *retlen, u8 *buffer);
1399 int (*mtd_erase)(struct mtd_info *mtd, loff_t start, size_t len);
1400 int (*mtd_write)(struct mtd_info *mtd, loff_t start, size_t len,
1401 size_t *retlen, const u8 *buffer);
1402 int (*mtd_sync)(struct mtd_info *mtd);
1403#endif
1404 void (*ptp_write_host_time)(struct efx_nic *efx, u32 host_time);
1405 int (*ptp_set_ts_sync_events)(struct efx_nic *efx, bool en, bool temp);
1406 int (*ptp_set_ts_config)(struct efx_nic *efx,
1407 struct kernel_hwtstamp_config *init);
1408 int (*sriov_configure)(struct efx_nic *efx, int num_vfs);
1409 int (*vlan_rx_add_vid)(struct efx_nic *efx, __be16 proto, u16 vid);
1410 int (*vlan_rx_kill_vid)(struct efx_nic *efx, __be16 proto, u16 vid);
1411 int (*get_phys_port_id)(struct efx_nic *efx,
1412 struct netdev_phys_item_id *ppid);
1413 int (*sriov_init)(struct efx_nic *efx);
1414 void (*sriov_fini)(struct efx_nic *efx);
1415 bool (*sriov_wanted)(struct efx_nic *efx);
1416 void (*sriov_reset)(struct efx_nic *efx);
1417 void (*sriov_flr)(struct efx_nic *efx, unsigned vf_i);
1418 int (*sriov_set_vf_mac)(struct efx_nic *efx, int vf_i, const u8 *mac);
1419 int (*sriov_set_vf_vlan)(struct efx_nic *efx, int vf_i, u16 vlan,
1420 u8 qos);
1421 int (*sriov_set_vf_spoofchk)(struct efx_nic *efx, int vf_i,
1422 bool spoofchk);
1423 int (*sriov_get_vf_config)(struct efx_nic *efx, int vf_i,
1424 struct ifla_vf_info *ivi);
1425 int (*sriov_set_vf_link_state)(struct efx_nic *efx, int vf_i,
1426 int link_state);
1427 int (*vswitching_probe)(struct efx_nic *efx);
1428 int (*vswitching_restore)(struct efx_nic *efx);
1429 void (*vswitching_remove)(struct efx_nic *efx);
1430 int (*get_mac_address)(struct efx_nic *efx, unsigned char *perm_addr);
1431 int (*set_mac_address)(struct efx_nic *efx);
1432 u32 (*tso_versions)(struct efx_nic *efx);
1433 int (*udp_tnl_push_ports)(struct efx_nic *efx);
1434 bool (*udp_tnl_has_port)(struct efx_nic *efx, __be16 port);
1435 size_t (*print_additional_fwver)(struct efx_nic *efx, char *buf,
1436 size_t len);
1437 void (*sensor_event)(struct efx_nic *efx, efx_qword_t *ev);
1438 unsigned int (*rx_recycle_ring_size)(const struct efx_nic *efx);
1439
1440 int revision;
1441 unsigned int txd_ptr_tbl_base;
1442 unsigned int rxd_ptr_tbl_base;
1443 unsigned int buf_tbl_base;
1444 unsigned int evq_ptr_tbl_base;
1445 unsigned int evq_rptr_tbl_base;
1446 u64 max_dma_mask;
1447 unsigned int rx_prefix_size;
1448 unsigned int rx_hash_offset;
1449 unsigned int rx_ts_offset;
1450 unsigned int rx_buffer_padding;
1451 bool can_rx_scatter;
1452 bool always_rx_scatter;
1453 bool option_descriptors;
1454 unsigned int min_interrupt_mode;
1455 unsigned int timer_period_max;
1456 netdev_features_t offload_features;
1457 int mcdi_max_ver;
1458 unsigned int max_rx_ip_filters;
1459 u32 hwtstamp_filters;
1460 unsigned int rx_hash_key_size;
1461};
1462
1463/**************************************************************************
1464 *
1465 * Prototypes and inline functions
1466 *
1467 *************************************************************************/
1468
1469static inline struct efx_channel *
1470efx_get_channel(struct efx_nic *efx, unsigned index)
1471{
1472 EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_channels);
1473 return efx->channel[index];
1474}
1475
1476/* Iterate over all used channels */
1477#define efx_for_each_channel(_channel, _efx) \
1478 for (_channel = (_efx)->channel[0]; \
1479 _channel; \
1480 _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \
1481 (_efx)->channel[_channel->channel + 1] : NULL)
1482
1483/* Iterate over all used channels in reverse */
1484#define efx_for_each_channel_rev(_channel, _efx) \
1485 for (_channel = (_efx)->channel[(_efx)->n_channels - 1]; \
1486 _channel; \
1487 _channel = _channel->channel ? \
1488 (_efx)->channel[_channel->channel - 1] : NULL)
1489
1490static inline struct efx_channel *
1491efx_get_tx_channel(struct efx_nic *efx, unsigned int index)
1492{
1493 EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_tx_channels);
1494 return efx->channel[efx->tx_channel_offset + index];
1495}
1496
1497static inline struct efx_channel *
1498efx_get_xdp_channel(struct efx_nic *efx, unsigned int index)
1499{
1500 EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_xdp_channels);
1501 return efx->channel[efx->xdp_channel_offset + index];
1502}
1503
1504static inline bool efx_channel_is_xdp_tx(struct efx_channel *channel)
1505{
1506 return channel->channel - channel->efx->xdp_channel_offset <
1507 channel->efx->n_xdp_channels;
1508}
1509
1510static inline bool efx_channel_has_tx_queues(struct efx_channel *channel)
1511{
1512 return channel && channel->channel >= channel->efx->tx_channel_offset;
1513}
1514
1515static inline unsigned int efx_channel_num_tx_queues(struct efx_channel *channel)
1516{
1517 if (efx_channel_is_xdp_tx(channel))
1518 return channel->efx->xdp_tx_per_channel;
1519 return channel->efx->tx_queues_per_channel;
1520}
1521
1522static inline struct efx_tx_queue *
1523efx_channel_get_tx_queue(struct efx_channel *channel, unsigned int type)
1524{
1525 EFX_WARN_ON_ONCE_PARANOID(type >= EFX_TXQ_TYPES);
1526 return channel->tx_queue_by_type[type];
1527}
1528
1529static inline struct efx_tx_queue *
1530efx_get_tx_queue(struct efx_nic *efx, unsigned int index, unsigned int type)
1531{
1532 struct efx_channel *channel = efx_get_tx_channel(efx, index);
1533
1534 return efx_channel_get_tx_queue(channel, type);
1535}
1536
1537/* Iterate over all TX queues belonging to a channel */
1538#define efx_for_each_channel_tx_queue(_tx_queue, _channel) \
1539 if (!efx_channel_has_tx_queues(_channel)) \
1540 ; \
1541 else \
1542 for (_tx_queue = (_channel)->tx_queue; \
1543 _tx_queue < (_channel)->tx_queue + \
1544 efx_channel_num_tx_queues(_channel); \
1545 _tx_queue++)
1546
1547static inline bool efx_channel_has_rx_queue(struct efx_channel *channel)
1548{
1549 return channel->rx_queue.core_index >= 0;
1550}
1551
1552static inline struct efx_rx_queue *
1553efx_channel_get_rx_queue(struct efx_channel *channel)
1554{
1555 EFX_WARN_ON_ONCE_PARANOID(!efx_channel_has_rx_queue(channel));
1556 return &channel->rx_queue;
1557}
1558
1559/* Iterate over all RX queues belonging to a channel */
1560#define efx_for_each_channel_rx_queue(_rx_queue, _channel) \
1561 if (!efx_channel_has_rx_queue(_channel)) \
1562 ; \
1563 else \
1564 for (_rx_queue = &(_channel)->rx_queue; \
1565 _rx_queue; \
1566 _rx_queue = NULL)
1567
1568static inline struct efx_channel *
1569efx_rx_queue_channel(struct efx_rx_queue *rx_queue)
1570{
1571 return container_of(rx_queue, struct efx_channel, rx_queue);
1572}
1573
1574static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue)
1575{
1576 return efx_rx_queue_channel(rx_queue)->channel;
1577}
1578
1579/* Returns a pointer to the specified receive buffer in the RX
1580 * descriptor queue.
1581 */
1582static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue,
1583 unsigned int index)
1584{
1585 return &rx_queue->buffer[index];
1586}
1587
1588static inline struct efx_rx_buffer *
1589efx_rx_buf_next(struct efx_rx_queue *rx_queue, struct efx_rx_buffer *rx_buf)
1590{
1591 if (unlikely(rx_buf == efx_rx_buffer(rx_queue, rx_queue->ptr_mask)))
1592 return efx_rx_buffer(rx_queue, 0);
1593 else
1594 return rx_buf + 1;
1595}
1596
1597/**
1598 * EFX_MAX_FRAME_LEN - calculate maximum frame length
1599 *
1600 * This calculates the maximum frame length that will be used for a
1601 * given MTU. The frame length will be equal to the MTU plus a
1602 * constant amount of header space and padding. This is the quantity
1603 * that the net driver will program into the MAC as the maximum frame
1604 * length.
1605 *
1606 * The 10G MAC requires 8-byte alignment on the frame
1607 * length, so we round up to the nearest 8.
1608 *
1609 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
1610 * XGMII cycle). If the frame length reaches the maximum value in the
1611 * same cycle, the XMAC can miss the IPG altogether. We work around
1612 * this by adding a further 16 bytes.
1613 */
1614#define EFX_FRAME_PAD 16
1615#define EFX_MAX_FRAME_LEN(mtu) \
1616 (ALIGN(((mtu) + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN + EFX_FRAME_PAD), 8))
1617
1618static inline bool efx_xmit_with_hwtstamp(struct sk_buff *skb)
1619{
1620 return skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP;
1621}
1622static inline void efx_xmit_hwtstamp_pending(struct sk_buff *skb)
1623{
1624 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1625}
1626
1627/* Get the max fill level of the TX queues on this channel */
1628static inline unsigned int
1629efx_channel_tx_fill_level(struct efx_channel *channel)
1630{
1631 struct efx_tx_queue *tx_queue;
1632 unsigned int fill_level = 0;
1633
1634 efx_for_each_channel_tx_queue(tx_queue, channel)
1635 fill_level = max(fill_level,
1636 tx_queue->insert_count - tx_queue->read_count);
1637
1638 return fill_level;
1639}
1640
1641/* Conservative approximation of efx_channel_tx_fill_level using cached value */
1642static inline unsigned int
1643efx_channel_tx_old_fill_level(struct efx_channel *channel)
1644{
1645 struct efx_tx_queue *tx_queue;
1646 unsigned int fill_level = 0;
1647
1648 efx_for_each_channel_tx_queue(tx_queue, channel)
1649 fill_level = max(fill_level,
1650 tx_queue->insert_count - tx_queue->old_read_count);
1651
1652 return fill_level;
1653}
1654
1655/* Get all supported features.
1656 * If a feature is not fixed, it is present in hw_features.
1657 * If a feature is fixed, it does not present in hw_features, but
1658 * always in features.
1659 */
1660static inline netdev_features_t efx_supported_features(const struct efx_nic *efx)
1661{
1662 const struct net_device *net_dev = efx->net_dev;
1663
1664 return net_dev->features | net_dev->hw_features;
1665}
1666
1667/* Get the current TX queue insert index. */
1668static inline unsigned int
1669efx_tx_queue_get_insert_index(const struct efx_tx_queue *tx_queue)
1670{
1671 return tx_queue->insert_count & tx_queue->ptr_mask;
1672}
1673
1674/* Get a TX buffer. */
1675static inline struct efx_tx_buffer *
1676__efx_tx_queue_get_insert_buffer(const struct efx_tx_queue *tx_queue)
1677{
1678 return &tx_queue->buffer[efx_tx_queue_get_insert_index(tx_queue)];
1679}
1680
1681/* Get a TX buffer, checking it's not currently in use. */
1682static inline struct efx_tx_buffer *
1683efx_tx_queue_get_insert_buffer(const struct efx_tx_queue *tx_queue)
1684{
1685 struct efx_tx_buffer *buffer =
1686 __efx_tx_queue_get_insert_buffer(tx_queue);
1687
1688 EFX_WARN_ON_ONCE_PARANOID(buffer->len);
1689 EFX_WARN_ON_ONCE_PARANOID(buffer->flags);
1690 EFX_WARN_ON_ONCE_PARANOID(buffer->unmap_len);
1691
1692 return buffer;
1693}
1694
1695#endif /* EFX_NET_DRIVER_H */