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1/*
2 * Applied Micro X-Gene SoC Ethernet v2 Driver
3 *
4 * Copyright (c) 2017, Applied Micro Circuits Corporation
5 * Author(s): Iyappan Subramanian <isubramanian@apm.com>
6 * Keyur Chudgar <kchudgar@apm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#ifndef __XGENE_ENET_V2_MAC_H__
23#define __XGENE_ENET_V2_MAC_H__
24
25/* Register offsets */
26#define MAC_CONFIG_1 0xa000
27#define MAC_CONFIG_2 0xa004
28#define MII_MGMT_CONFIG 0xa020
29#define MII_MGMT_COMMAND 0xa024
30#define MII_MGMT_ADDRESS 0xa028
31#define MII_MGMT_CONTROL 0xa02c
32#define MII_MGMT_STATUS 0xa030
33#define MII_MGMT_INDICATORS 0xa034
34#define INTERFACE_CONTROL 0xa038
35#define STATION_ADDR0 0xa040
36#define STATION_ADDR1 0xa044
37
38#define RGMII_REG_0 0x27e0
39#define ICM_CONFIG0_REG_0 0x2c00
40#define ICM_CONFIG2_REG_0 0x2c08
41#define ECM_CONFIG0_REG_0 0x2d00
42
43/* Register fields */
44#define SOFT_RESET BIT(31)
45#define TX_EN BIT(0)
46#define RX_EN BIT(2)
47#define PAD_CRC BIT(2)
48#define CRC_EN BIT(1)
49#define FULL_DUPLEX BIT(0)
50
51#define INTF_MODE_POS 8
52#define INTF_MODE_LEN 2
53#define HD_MODE_POS 25
54#define HD_MODE_LEN 2
55#define CFG_MACMODE_POS 18
56#define CFG_MACMODE_LEN 2
57#define CFG_WAITASYNCRD_POS 0
58#define CFG_WAITASYNCRD_LEN 16
59#define CFG_SPEED_125_POS 24
60#define CFG_WFIFOFULLTHR_POS 0
61#define CFG_WFIFOFULLTHR_LEN 7
62#define MGMT_CLOCK_SEL_POS 0
63#define MGMT_CLOCK_SEL_LEN 3
64#define PHY_ADDR_POS 8
65#define PHY_ADDR_LEN 5
66#define REG_ADDR_POS 0
67#define REG_ADDR_LEN 5
68#define MII_MGMT_BUSY BIT(0)
69#define MII_READ_CYCLE BIT(0)
70#define CFG_WAITASYNCRD_EN BIT(16)
71
72static inline void xgene_set_reg_bits(u32 *var, int pos, int len, u32 val)
73{
74 u32 mask = GENMASK(pos + len, pos);
75
76 *var &= ~mask;
77 *var |= ((val << pos) & mask);
78}
79
80static inline u32 xgene_get_reg_bits(u32 var, int pos, int len)
81{
82 u32 mask = GENMASK(pos + len, pos);
83
84 return (var & mask) >> pos;
85}
86
87#define SET_REG_BITS(var, field, val) \
88 xgene_set_reg_bits(var, field ## _POS, field ## _LEN, val)
89
90#define SET_REG_BIT(var, field, val) \
91 xgene_set_reg_bits(var, field ## _POS, 1, val)
92
93#define GET_REG_BITS(var, field) \
94 xgene_get_reg_bits(var, field ## _POS, field ## _LEN)
95
96#define GET_REG_BIT(var, field) ((var) & (field))
97
98struct xge_pdata;
99
100void xge_mac_reset(struct xge_pdata *pdata);
101void xge_mac_set_speed(struct xge_pdata *pdata);
102void xge_mac_enable(struct xge_pdata *pdata);
103void xge_mac_disable(struct xge_pdata *pdata);
104void xge_mac_init(struct xge_pdata *pdata);
105void xge_mac_set_station_addr(struct xge_pdata *pdata);
106
107#endif /* __XGENE_ENET_V2_MAC_H__ */
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Applied Micro X-Gene SoC Ethernet v2 Driver
4 *
5 * Copyright (c) 2017, Applied Micro Circuits Corporation
6 * Author(s): Iyappan Subramanian <isubramanian@apm.com>
7 * Keyur Chudgar <kchudgar@apm.com>
8 */
9
10#ifndef __XGENE_ENET_V2_MAC_H__
11#define __XGENE_ENET_V2_MAC_H__
12
13/* Register offsets */
14#define MAC_CONFIG_1 0xa000
15#define MAC_CONFIG_2 0xa004
16#define MII_MGMT_CONFIG 0xa020
17#define MII_MGMT_COMMAND 0xa024
18#define MII_MGMT_ADDRESS 0xa028
19#define MII_MGMT_CONTROL 0xa02c
20#define MII_MGMT_STATUS 0xa030
21#define MII_MGMT_INDICATORS 0xa034
22#define INTERFACE_CONTROL 0xa038
23#define STATION_ADDR0 0xa040
24#define STATION_ADDR1 0xa044
25
26#define RGMII_REG_0 0x27e0
27#define ICM_CONFIG0_REG_0 0x2c00
28#define ICM_CONFIG2_REG_0 0x2c08
29#define ECM_CONFIG0_REG_0 0x2d00
30
31/* Register fields */
32#define SOFT_RESET BIT(31)
33#define TX_EN BIT(0)
34#define RX_EN BIT(2)
35#define PAD_CRC BIT(2)
36#define CRC_EN BIT(1)
37#define FULL_DUPLEX BIT(0)
38
39#define INTF_MODE_POS 8
40#define INTF_MODE_LEN 2
41#define HD_MODE_POS 25
42#define HD_MODE_LEN 2
43#define CFG_MACMODE_POS 18
44#define CFG_MACMODE_LEN 2
45#define CFG_WAITASYNCRD_POS 0
46#define CFG_WAITASYNCRD_LEN 16
47#define CFG_SPEED_125_POS 24
48#define CFG_WFIFOFULLTHR_POS 0
49#define CFG_WFIFOFULLTHR_LEN 7
50#define MGMT_CLOCK_SEL_POS 0
51#define MGMT_CLOCK_SEL_LEN 3
52#define PHY_ADDR_POS 8
53#define PHY_ADDR_LEN 5
54#define REG_ADDR_POS 0
55#define REG_ADDR_LEN 5
56#define MII_MGMT_BUSY BIT(0)
57#define MII_READ_CYCLE BIT(0)
58#define CFG_WAITASYNCRD_EN BIT(16)
59
60static inline void xgene_set_reg_bits(u32 *var, int pos, int len, u32 val)
61{
62 u32 mask = GENMASK(pos + len, pos);
63
64 *var &= ~mask;
65 *var |= ((val << pos) & mask);
66}
67
68static inline u32 xgene_get_reg_bits(u32 var, int pos, int len)
69{
70 u32 mask = GENMASK(pos + len, pos);
71
72 return (var & mask) >> pos;
73}
74
75#define SET_REG_BITS(var, field, val) \
76 xgene_set_reg_bits(var, field ## _POS, field ## _LEN, val)
77
78#define SET_REG_BIT(var, field, val) \
79 xgene_set_reg_bits(var, field ## _POS, 1, val)
80
81#define GET_REG_BITS(var, field) \
82 xgene_get_reg_bits(var, field ## _POS, field ## _LEN)
83
84#define GET_REG_BIT(var, field) ((var) & (field))
85
86struct xge_pdata;
87
88void xge_mac_reset(struct xge_pdata *pdata);
89void xge_mac_set_speed(struct xge_pdata *pdata);
90void xge_mac_enable(struct xge_pdata *pdata);
91void xge_mac_disable(struct xge_pdata *pdata);
92void xge_mac_init(struct xge_pdata *pdata);
93void xge_mac_set_station_addr(struct xge_pdata *pdata);
94
95#endif /* __XGENE_ENET_V2_MAC_H__ */