Loading...
1/*
2 * Copyright (C) 2008-2010 Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>
3 *
4 * Derived from the ems_pci.c driver:
5 * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com>
6 * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
7 * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the version 2 of the GNU General Public License
11 * as published by the Free Software Foundation
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, see <http://www.gnu.org/licenses/>.
20 */
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/interrupt.h>
25#include <linux/netdevice.h>
26#include <linux/delay.h>
27#include <linux/slab.h>
28#include <linux/pci.h>
29#include <linux/can/dev.h>
30#include <linux/io.h>
31
32#include "sja1000.h"
33
34#define DRV_NAME "sja1000_plx_pci"
35
36MODULE_AUTHOR("Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>");
37MODULE_DESCRIPTION("Socket-CAN driver for PLX90xx PCI-bridge cards with "
38 "the SJA1000 chips");
39MODULE_SUPPORTED_DEVICE("Adlink PCI-7841/cPCI-7841, "
40 "Adlink PCI-7841/cPCI-7841 SE, "
41 "Marathon CAN-bus-PCI, "
42 "Marathon CAN-bus-PCIe, "
43 "TEWS TECHNOLOGIES TPMC810, "
44 "esd CAN-PCI/CPCI/PCI104/200, "
45 "esd CAN-PCI/PMC/266, "
46 "esd CAN-PCIe/2000, "
47 "Connect Tech Inc. CANpro/104-Plus Opto (CRG001), "
48 "IXXAT PC-I 04/PCI, "
49 "ELCUS CAN-200-PCI")
50MODULE_LICENSE("GPL v2");
51
52#define PLX_PCI_MAX_CHAN 2
53
54struct plx_pci_card {
55 int channels; /* detected channels count */
56 struct net_device *net_dev[PLX_PCI_MAX_CHAN];
57 void __iomem *conf_addr;
58
59 /* Pointer to device-dependent reset function */
60 void (*reset_func)(struct pci_dev *pdev);
61};
62
63#define PLX_PCI_CAN_CLOCK (16000000 / 2)
64
65/* PLX9030/9050/9052 registers */
66#define PLX_INTCSR 0x4c /* Interrupt Control/Status */
67#define PLX_CNTRL 0x50 /* User I/O, Direct Slave Response,
68 * Serial EEPROM, and Initialization
69 * Control register
70 */
71
72#define PLX_LINT1_EN 0x1 /* Local interrupt 1 enable */
73#define PLX_LINT2_EN (1 << 3) /* Local interrupt 2 enable */
74#define PLX_PCI_INT_EN (1 << 6) /* PCI Interrupt Enable */
75#define PLX_PCI_RESET (1 << 30) /* PCI Adapter Software Reset */
76
77/* PLX9056 registers */
78#define PLX9056_INTCSR 0x68 /* Interrupt Control/Status */
79#define PLX9056_CNTRL 0x6c /* Control / Software Reset */
80
81#define PLX9056_LINTI (1 << 11)
82#define PLX9056_PCI_INT_EN (1 << 8)
83#define PLX9056_PCI_RCR (1 << 29) /* Read Configuration Registers */
84
85/*
86 * The board configuration is probably following:
87 * RX1 is connected to ground.
88 * TX1 is not connected.
89 * CLKO is not connected.
90 * Setting the OCR register to 0xDA is a good idea.
91 * This means normal output mode, push-pull and the correct polarity.
92 */
93#define PLX_PCI_OCR (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL)
94
95/*
96 * In the CDR register, you should set CBP to 1.
97 * You will probably also want to set the clock divider value to 7
98 * (meaning direct oscillator output) because the second SJA1000 chip
99 * is driven by the first one CLKOUT output.
100 */
101#define PLX_PCI_CDR (CDR_CBP | CDR_CLKOUT_MASK)
102
103/* SJA1000 Control Register in the BasicCAN Mode */
104#define REG_CR 0x00
105
106/* States of some SJA1000 registers after hardware reset in the BasicCAN mode*/
107#define REG_CR_BASICCAN_INITIAL 0x21
108#define REG_CR_BASICCAN_INITIAL_MASK 0xa1
109#define REG_SR_BASICCAN_INITIAL 0x0c
110#define REG_IR_BASICCAN_INITIAL 0xe0
111
112/* States of some SJA1000 registers after hardware reset in the PeliCAN mode*/
113#define REG_MOD_PELICAN_INITIAL 0x01
114#define REG_SR_PELICAN_INITIAL 0x3c
115#define REG_IR_PELICAN_INITIAL 0x00
116
117#define ADLINK_PCI_VENDOR_ID 0x144A
118#define ADLINK_PCI_DEVICE_ID 0x7841
119
120#define ESD_PCI_SUB_SYS_ID_PCI200 0x0004
121#define ESD_PCI_SUB_SYS_ID_PCI266 0x0009
122#define ESD_PCI_SUB_SYS_ID_PMC266 0x000e
123#define ESD_PCI_SUB_SYS_ID_CPCI200 0x010b
124#define ESD_PCI_SUB_SYS_ID_PCIE2000 0x0200
125#define ESD_PCI_SUB_SYS_ID_PCI104200 0x0501
126
127#define CAN200PCI_DEVICE_ID 0x9030
128#define CAN200PCI_VENDOR_ID 0x10b5
129#define CAN200PCI_SUB_DEVICE_ID 0x0301
130#define CAN200PCI_SUB_VENDOR_ID 0xe1c5
131
132#define IXXAT_PCI_VENDOR_ID 0x10b5
133#define IXXAT_PCI_DEVICE_ID 0x9050
134#define IXXAT_PCI_SUB_SYS_ID 0x2540
135
136#define MARATHON_PCI_DEVICE_ID 0x2715
137#define MARATHON_PCIE_DEVICE_ID 0x3432
138
139#define TEWS_PCI_VENDOR_ID 0x1498
140#define TEWS_PCI_DEVICE_ID_TMPC810 0x032A
141
142#define CTI_PCI_VENDOR_ID 0x12c4
143#define CTI_PCI_DEVICE_ID_CRG001 0x0900
144
145#define MOXA_PCI_VENDOR_ID 0x1393
146#define MOXA_PCI_DEVICE_ID 0x0100
147
148static void plx_pci_reset_common(struct pci_dev *pdev);
149static void plx9056_pci_reset_common(struct pci_dev *pdev);
150static void plx_pci_reset_marathon_pci(struct pci_dev *pdev);
151static void plx_pci_reset_marathon_pcie(struct pci_dev *pdev);
152
153struct plx_pci_channel_map {
154 u32 bar;
155 u32 offset;
156 u32 size; /* 0x00 - auto, e.g. length of entire bar */
157};
158
159struct plx_pci_card_info {
160 const char *name;
161 int channel_count;
162 u32 can_clock;
163 u8 ocr; /* output control register */
164 u8 cdr; /* clock divider register */
165
166 /* Parameters for mapping local configuration space */
167 struct plx_pci_channel_map conf_map;
168
169 /* Parameters for mapping the SJA1000 chips */
170 struct plx_pci_channel_map chan_map_tbl[PLX_PCI_MAX_CHAN];
171
172 /* Pointer to device-dependent reset function */
173 void (*reset_func)(struct pci_dev *pdev);
174};
175
176static struct plx_pci_card_info plx_pci_card_info_adlink = {
177 "Adlink PCI-7841/cPCI-7841", 2,
178 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
179 {1, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} },
180 &plx_pci_reset_common
181 /* based on PLX9052 */
182};
183
184static struct plx_pci_card_info plx_pci_card_info_adlink_se = {
185 "Adlink PCI-7841/cPCI-7841 SE", 2,
186 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
187 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} },
188 &plx_pci_reset_common
189 /* based on PLX9052 */
190};
191
192static struct plx_pci_card_info plx_pci_card_info_esd200 = {
193 "esd CAN-PCI/CPCI/PCI104/200", 2,
194 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
195 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} },
196 &plx_pci_reset_common
197 /* based on PLX9030/9050 */
198};
199
200static struct plx_pci_card_info plx_pci_card_info_esd266 = {
201 "esd CAN-PCI/PMC/266", 2,
202 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
203 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} },
204 &plx9056_pci_reset_common
205 /* based on PLX9056 */
206};
207
208static struct plx_pci_card_info plx_pci_card_info_esd2000 = {
209 "esd CAN-PCIe/2000", 2,
210 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
211 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} },
212 &plx9056_pci_reset_common
213 /* based on PEX8311 */
214};
215
216static struct plx_pci_card_info plx_pci_card_info_ixxat = {
217 "IXXAT PC-I 04/PCI", 2,
218 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
219 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x200, 0x80} },
220 &plx_pci_reset_common
221 /* based on PLX9050 */
222};
223
224static struct plx_pci_card_info plx_pci_card_info_marathon_pci = {
225 "Marathon CAN-bus-PCI", 2,
226 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
227 {0, 0x00, 0x00}, { {2, 0x00, 0x00}, {4, 0x00, 0x00} },
228 &plx_pci_reset_marathon_pci
229 /* based on PLX9052 */
230};
231
232static struct plx_pci_card_info plx_pci_card_info_marathon_pcie = {
233 "Marathon CAN-bus-PCIe", 2,
234 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
235 {0, 0x00, 0x00}, { {2, 0x00, 0x00}, {3, 0x80, 0x00} },
236 &plx_pci_reset_marathon_pcie
237 /* based on PEX8311 */
238};
239
240static struct plx_pci_card_info plx_pci_card_info_tews = {
241 "TEWS TECHNOLOGIES TPMC810", 2,
242 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
243 {0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} },
244 &plx_pci_reset_common
245 /* based on PLX9030 */
246};
247
248static struct plx_pci_card_info plx_pci_card_info_cti = {
249 "Connect Tech Inc. CANpro/104-Plus Opto (CRG001)", 2,
250 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
251 {0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} },
252 &plx_pci_reset_common
253 /* based on PLX9030 */
254};
255
256static struct plx_pci_card_info plx_pci_card_info_elcus = {
257 "Eclus CAN-200-PCI", 2,
258 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
259 {1, 0x00, 0x00}, { {2, 0x00, 0x80}, {3, 0x00, 0x80} },
260 &plx_pci_reset_common
261 /* based on PLX9030 */
262};
263
264static struct plx_pci_card_info plx_pci_card_info_moxa = {
265 "MOXA", 2,
266 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
267 {0, 0x00, 0x00}, { {0, 0x00, 0x80}, {1, 0x00, 0x80} },
268 &plx_pci_reset_common
269 /* based on PLX9052 */
270};
271
272static const struct pci_device_id plx_pci_tbl[] = {
273 {
274 /* Adlink PCI-7841/cPCI-7841 */
275 ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID,
276 PCI_ANY_ID, PCI_ANY_ID,
277 PCI_CLASS_NETWORK_OTHER << 8, ~0,
278 (kernel_ulong_t)&plx_pci_card_info_adlink
279 },
280 {
281 /* Adlink PCI-7841/cPCI-7841 SE */
282 ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID,
283 PCI_ANY_ID, PCI_ANY_ID,
284 PCI_CLASS_COMMUNICATION_OTHER << 8, ~0,
285 (kernel_ulong_t)&plx_pci_card_info_adlink_se
286 },
287 {
288 /* esd CAN-PCI/200 */
289 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
290 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI200,
291 0, 0,
292 (kernel_ulong_t)&plx_pci_card_info_esd200
293 },
294 {
295 /* esd CAN-CPCI/200 */
296 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
297 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_CPCI200,
298 0, 0,
299 (kernel_ulong_t)&plx_pci_card_info_esd200
300 },
301 {
302 /* esd CAN-PCI104/200 */
303 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
304 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI104200,
305 0, 0,
306 (kernel_ulong_t)&plx_pci_card_info_esd200
307 },
308 {
309 /* esd CAN-PCI/266 */
310 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056,
311 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI266,
312 0, 0,
313 (kernel_ulong_t)&plx_pci_card_info_esd266
314 },
315 {
316 /* esd CAN-PMC/266 */
317 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056,
318 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PMC266,
319 0, 0,
320 (kernel_ulong_t)&plx_pci_card_info_esd266
321 },
322 {
323 /* esd CAN-PCIE/2000 */
324 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056,
325 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCIE2000,
326 0, 0,
327 (kernel_ulong_t)&plx_pci_card_info_esd2000
328 },
329 {
330 /* IXXAT PC-I 04/PCI card */
331 IXXAT_PCI_VENDOR_ID, IXXAT_PCI_DEVICE_ID,
332 PCI_ANY_ID, IXXAT_PCI_SUB_SYS_ID,
333 0, 0,
334 (kernel_ulong_t)&plx_pci_card_info_ixxat
335 },
336 {
337 /* Marathon CAN-bus-PCI card */
338 PCI_VENDOR_ID_PLX, MARATHON_PCI_DEVICE_ID,
339 PCI_ANY_ID, PCI_ANY_ID,
340 0, 0,
341 (kernel_ulong_t)&plx_pci_card_info_marathon_pci
342 },
343 {
344 /* Marathon CAN-bus-PCIe card */
345 PCI_VENDOR_ID_PLX, MARATHON_PCIE_DEVICE_ID,
346 PCI_ANY_ID, PCI_ANY_ID,
347 0, 0,
348 (kernel_ulong_t)&plx_pci_card_info_marathon_pcie
349 },
350 {
351 /* TEWS TECHNOLOGIES TPMC810 card */
352 TEWS_PCI_VENDOR_ID, TEWS_PCI_DEVICE_ID_TMPC810,
353 PCI_ANY_ID, PCI_ANY_ID,
354 0, 0,
355 (kernel_ulong_t)&plx_pci_card_info_tews
356 },
357 {
358 /* Connect Tech Inc. CANpro/104-Plus Opto (CRG001) card */
359 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
360 CTI_PCI_VENDOR_ID, CTI_PCI_DEVICE_ID_CRG001,
361 0, 0,
362 (kernel_ulong_t)&plx_pci_card_info_cti
363 },
364 {
365 /* Elcus CAN-200-PCI */
366 CAN200PCI_VENDOR_ID, CAN200PCI_DEVICE_ID,
367 CAN200PCI_SUB_VENDOR_ID, CAN200PCI_SUB_DEVICE_ID,
368 0, 0,
369 (kernel_ulong_t)&plx_pci_card_info_elcus
370 },
371 {
372 /* moxa */
373 MOXA_PCI_VENDOR_ID, MOXA_PCI_DEVICE_ID,
374 PCI_ANY_ID, PCI_ANY_ID,
375 0, 0,
376 (kernel_ulong_t)&plx_pci_card_info_moxa
377 },
378 { 0,}
379};
380MODULE_DEVICE_TABLE(pci, plx_pci_tbl);
381
382static u8 plx_pci_read_reg(const struct sja1000_priv *priv, int port)
383{
384 return ioread8(priv->reg_base + port);
385}
386
387static void plx_pci_write_reg(const struct sja1000_priv *priv, int port, u8 val)
388{
389 iowrite8(val, priv->reg_base + port);
390}
391
392/*
393 * Check if a CAN controller is present at the specified location
394 * by trying to switch 'em from the Basic mode into the PeliCAN mode.
395 * Also check states of some registers in reset mode.
396 */
397static inline int plx_pci_check_sja1000(const struct sja1000_priv *priv)
398{
399 int flag = 0;
400
401 /*
402 * Check registers after hardware reset (the Basic mode)
403 * See states on p. 10 of the Datasheet.
404 */
405 if ((priv->read_reg(priv, REG_CR) & REG_CR_BASICCAN_INITIAL_MASK) ==
406 REG_CR_BASICCAN_INITIAL &&
407 (priv->read_reg(priv, SJA1000_SR) == REG_SR_BASICCAN_INITIAL) &&
408 (priv->read_reg(priv, SJA1000_IR) == REG_IR_BASICCAN_INITIAL))
409 flag = 1;
410
411 /* Bring the SJA1000 into the PeliCAN mode*/
412 priv->write_reg(priv, SJA1000_CDR, CDR_PELICAN);
413
414 /*
415 * Check registers after reset in the PeliCAN mode.
416 * See states on p. 23 of the Datasheet.
417 */
418 if (priv->read_reg(priv, SJA1000_MOD) == REG_MOD_PELICAN_INITIAL &&
419 priv->read_reg(priv, SJA1000_SR) == REG_SR_PELICAN_INITIAL &&
420 priv->read_reg(priv, SJA1000_IR) == REG_IR_PELICAN_INITIAL)
421 return flag;
422
423 return 0;
424}
425
426/*
427 * PLX9030/50/52 software reset
428 * Also LRESET# asserts and brings to reset device on the Local Bus (if wired).
429 * For most cards it's enough for reset the SJA1000 chips.
430 */
431static void plx_pci_reset_common(struct pci_dev *pdev)
432{
433 struct plx_pci_card *card = pci_get_drvdata(pdev);
434 u32 cntrl;
435
436 cntrl = ioread32(card->conf_addr + PLX_CNTRL);
437 cntrl |= PLX_PCI_RESET;
438 iowrite32(cntrl, card->conf_addr + PLX_CNTRL);
439 udelay(100);
440 cntrl ^= PLX_PCI_RESET;
441 iowrite32(cntrl, card->conf_addr + PLX_CNTRL);
442};
443
444/*
445 * PLX9056 software reset
446 * Assert LRESET# and reset device(s) on the Local Bus (if wired).
447 */
448static void plx9056_pci_reset_common(struct pci_dev *pdev)
449{
450 struct plx_pci_card *card = pci_get_drvdata(pdev);
451 u32 cntrl;
452
453 /* issue a local bus reset */
454 cntrl = ioread32(card->conf_addr + PLX9056_CNTRL);
455 cntrl |= PLX_PCI_RESET;
456 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL);
457 udelay(100);
458 cntrl ^= PLX_PCI_RESET;
459 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL);
460
461 /* reload local configuration from EEPROM */
462 cntrl |= PLX9056_PCI_RCR;
463 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL);
464
465 /*
466 * There is no safe way to poll for the end
467 * of reconfiguration process. Waiting for 10ms
468 * is safe.
469 */
470 mdelay(10);
471
472 cntrl ^= PLX9056_PCI_RCR;
473 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL);
474};
475
476/* Special reset function for Marathon CAN-bus-PCI card */
477static void plx_pci_reset_marathon_pci(struct pci_dev *pdev)
478{
479 void __iomem *reset_addr;
480 int i;
481 static const int reset_bar[2] = {3, 5};
482
483 plx_pci_reset_common(pdev);
484
485 for (i = 0; i < 2; i++) {
486 reset_addr = pci_iomap(pdev, reset_bar[i], 0);
487 if (!reset_addr) {
488 dev_err(&pdev->dev, "Failed to remap reset "
489 "space %d (BAR%d)\n", i, reset_bar[i]);
490 } else {
491 /* reset the SJA1000 chip */
492 iowrite8(0x1, reset_addr);
493 udelay(100);
494 pci_iounmap(pdev, reset_addr);
495 }
496 }
497}
498
499/* Special reset function for Marathon CAN-bus-PCIe card */
500static void plx_pci_reset_marathon_pcie(struct pci_dev *pdev)
501{
502 void __iomem *addr;
503 void __iomem *reset_addr;
504 int i;
505
506 plx9056_pci_reset_common(pdev);
507
508 for (i = 0; i < 2; i++) {
509 struct plx_pci_channel_map *chan_map =
510 &plx_pci_card_info_marathon_pcie.chan_map_tbl[i];
511 addr = pci_iomap(pdev, chan_map->bar, chan_map->size);
512 if (!addr) {
513 dev_err(&pdev->dev, "Failed to remap reset "
514 "space %d (BAR%d)\n", i, chan_map->bar);
515 } else {
516 /* reset the SJA1000 chip */
517 #define MARATHON_PCIE_RESET_OFFSET 32
518 reset_addr = addr + chan_map->offset +
519 MARATHON_PCIE_RESET_OFFSET;
520 iowrite8(0x1, reset_addr);
521 udelay(100);
522 pci_iounmap(pdev, addr);
523 }
524 }
525}
526
527static void plx_pci_del_card(struct pci_dev *pdev)
528{
529 struct plx_pci_card *card = pci_get_drvdata(pdev);
530 struct net_device *dev;
531 struct sja1000_priv *priv;
532 int i = 0;
533
534 for (i = 0; i < PLX_PCI_MAX_CHAN; i++) {
535 dev = card->net_dev[i];
536 if (!dev)
537 continue;
538
539 dev_info(&pdev->dev, "Removing %s\n", dev->name);
540 unregister_sja1000dev(dev);
541 priv = netdev_priv(dev);
542 if (priv->reg_base)
543 pci_iounmap(pdev, priv->reg_base);
544 free_sja1000dev(dev);
545 }
546
547 card->reset_func(pdev);
548
549 /*
550 * Disable interrupts from PCI-card and disable local
551 * interrupts
552 */
553 if (pdev->device != PCI_DEVICE_ID_PLX_9056 &&
554 pdev->device != MARATHON_PCIE_DEVICE_ID)
555 iowrite32(0x0, card->conf_addr + PLX_INTCSR);
556 else
557 iowrite32(0x0, card->conf_addr + PLX9056_INTCSR);
558
559 if (card->conf_addr)
560 pci_iounmap(pdev, card->conf_addr);
561
562 kfree(card);
563
564 pci_disable_device(pdev);
565}
566
567/*
568 * Probe PLX90xx based device for the SJA1000 chips and register each
569 * available CAN channel to SJA1000 Socket-CAN subsystem.
570 */
571static int plx_pci_add_card(struct pci_dev *pdev,
572 const struct pci_device_id *ent)
573{
574 struct sja1000_priv *priv;
575 struct net_device *dev;
576 struct plx_pci_card *card;
577 struct plx_pci_card_info *ci;
578 int err, i;
579 u32 val;
580 void __iomem *addr;
581
582 ci = (struct plx_pci_card_info *)ent->driver_data;
583
584 if (pci_enable_device(pdev) < 0) {
585 dev_err(&pdev->dev, "Failed to enable PCI device\n");
586 return -ENODEV;
587 }
588
589 dev_info(&pdev->dev, "Detected \"%s\" card at slot #%i\n",
590 ci->name, PCI_SLOT(pdev->devfn));
591
592 /* Allocate card structures to hold addresses, ... */
593 card = kzalloc(sizeof(*card), GFP_KERNEL);
594 if (!card) {
595 pci_disable_device(pdev);
596 return -ENOMEM;
597 }
598
599 pci_set_drvdata(pdev, card);
600
601 card->channels = 0;
602
603 /* Remap PLX90xx configuration space */
604 addr = pci_iomap(pdev, ci->conf_map.bar, ci->conf_map.size);
605 if (!addr) {
606 err = -ENOMEM;
607 dev_err(&pdev->dev, "Failed to remap configuration space "
608 "(BAR%d)\n", ci->conf_map.bar);
609 goto failure_cleanup;
610 }
611 card->conf_addr = addr + ci->conf_map.offset;
612
613 ci->reset_func(pdev);
614 card->reset_func = ci->reset_func;
615
616 /* Detect available channels */
617 for (i = 0; i < ci->channel_count; i++) {
618 struct plx_pci_channel_map *cm = &ci->chan_map_tbl[i];
619
620 dev = alloc_sja1000dev(0);
621 if (!dev) {
622 err = -ENOMEM;
623 goto failure_cleanup;
624 }
625
626 card->net_dev[i] = dev;
627 priv = netdev_priv(dev);
628 priv->priv = card;
629 priv->irq_flags = IRQF_SHARED;
630
631 dev->irq = pdev->irq;
632
633 /*
634 * Remap IO space of the SJA1000 chips
635 * This is device-dependent mapping
636 */
637 addr = pci_iomap(pdev, cm->bar, cm->size);
638 if (!addr) {
639 err = -ENOMEM;
640 dev_err(&pdev->dev, "Failed to remap BAR%d\n", cm->bar);
641 goto failure_cleanup;
642 }
643
644 priv->reg_base = addr + cm->offset;
645 priv->read_reg = plx_pci_read_reg;
646 priv->write_reg = plx_pci_write_reg;
647
648 /* Check if channel is present */
649 if (plx_pci_check_sja1000(priv)) {
650 priv->can.clock.freq = ci->can_clock;
651 priv->ocr = ci->ocr;
652 priv->cdr = ci->cdr;
653
654 SET_NETDEV_DEV(dev, &pdev->dev);
655 dev->dev_id = i;
656
657 /* Register SJA1000 device */
658 err = register_sja1000dev(dev);
659 if (err) {
660 dev_err(&pdev->dev, "Registering device failed "
661 "(err=%d)\n", err);
662 goto failure_cleanup;
663 }
664
665 card->channels++;
666
667 dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d "
668 "registered as %s\n", i + 1, priv->reg_base,
669 dev->irq, dev->name);
670 } else {
671 dev_err(&pdev->dev, "Channel #%d not detected\n",
672 i + 1);
673 free_sja1000dev(dev);
674 card->net_dev[i] = NULL;
675 }
676 }
677
678 if (!card->channels) {
679 err = -ENODEV;
680 goto failure_cleanup;
681 }
682
683 /*
684 * Enable interrupts from PCI-card (PLX90xx) and enable Local_1,
685 * Local_2 interrupts from the SJA1000 chips
686 */
687 if (pdev->device != PCI_DEVICE_ID_PLX_9056 &&
688 pdev->device != MARATHON_PCIE_DEVICE_ID) {
689 val = ioread32(card->conf_addr + PLX_INTCSR);
690 if (pdev->subsystem_vendor == PCI_VENDOR_ID_ESDGMBH)
691 val |= PLX_LINT1_EN | PLX_PCI_INT_EN;
692 else
693 val |= PLX_LINT1_EN | PLX_LINT2_EN | PLX_PCI_INT_EN;
694 iowrite32(val, card->conf_addr + PLX_INTCSR);
695 } else {
696 iowrite32(PLX9056_LINTI | PLX9056_PCI_INT_EN,
697 card->conf_addr + PLX9056_INTCSR);
698 }
699 return 0;
700
701failure_cleanup:
702 dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n", err);
703
704 plx_pci_del_card(pdev);
705
706 return err;
707}
708
709static struct pci_driver plx_pci_driver = {
710 .name = DRV_NAME,
711 .id_table = plx_pci_tbl,
712 .probe = plx_pci_add_card,
713 .remove = plx_pci_del_card,
714};
715
716module_pci_driver(plx_pci_driver);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2008-2010 Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>
4 *
5 * Derived from the ems_pci.c driver:
6 * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com>
7 * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
8 * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
9 */
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/interrupt.h>
14#include <linux/netdevice.h>
15#include <linux/delay.h>
16#include <linux/slab.h>
17#include <linux/pci.h>
18#include <linux/can/dev.h>
19#include <linux/io.h>
20
21#include "sja1000.h"
22
23#define DRV_NAME "sja1000_plx_pci"
24
25MODULE_AUTHOR("Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>");
26MODULE_DESCRIPTION("Socket-CAN driver for PLX90xx PCI-bridge cards with "
27 "the SJA1000 chips");
28MODULE_LICENSE("GPL v2");
29
30#define PLX_PCI_MAX_CHAN 2
31
32struct plx_pci_card {
33 int channels; /* detected channels count */
34 struct net_device *net_dev[PLX_PCI_MAX_CHAN];
35 void __iomem *conf_addr;
36
37 /* Pointer to device-dependent reset function */
38 void (*reset_func)(struct pci_dev *pdev);
39};
40
41#define PLX_PCI_CAN_CLOCK (16000000 / 2)
42
43/* PLX9030/9050/9052 registers */
44#define PLX_INTCSR 0x4c /* Interrupt Control/Status */
45#define PLX_CNTRL 0x50 /* User I/O, Direct Slave Response,
46 * Serial EEPROM, and Initialization
47 * Control register
48 */
49
50#define PLX_LINT1_EN 0x1 /* Local interrupt 1 enable */
51#define PLX_LINT1_POL (1 << 1) /* Local interrupt 1 polarity */
52#define PLX_LINT2_EN (1 << 3) /* Local interrupt 2 enable */
53#define PLX_LINT2_POL (1 << 4) /* Local interrupt 2 polarity */
54#define PLX_PCI_INT_EN (1 << 6) /* PCI Interrupt Enable */
55#define PLX_PCI_RESET (1 << 30) /* PCI Adapter Software Reset */
56
57/* PLX9056 registers */
58#define PLX9056_INTCSR 0x68 /* Interrupt Control/Status */
59#define PLX9056_CNTRL 0x6c /* Control / Software Reset */
60
61#define PLX9056_LINTI (1 << 11)
62#define PLX9056_PCI_INT_EN (1 << 8)
63#define PLX9056_PCI_RCR (1 << 29) /* Read Configuration Registers */
64
65/*
66 * The board configuration is probably following:
67 * RX1 is connected to ground.
68 * TX1 is not connected.
69 * CLKO is not connected.
70 * Setting the OCR register to 0xDA is a good idea.
71 * This means normal output mode, push-pull and the correct polarity.
72 */
73#define PLX_PCI_OCR (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL)
74
75/* OCR setting for ASEM Dual CAN raw */
76#define ASEM_PCI_OCR 0xfe
77
78/*
79 * In the CDR register, you should set CBP to 1.
80 * You will probably also want to set the clock divider value to 7
81 * (meaning direct oscillator output) because the second SJA1000 chip
82 * is driven by the first one CLKOUT output.
83 */
84#define PLX_PCI_CDR (CDR_CBP | CDR_CLKOUT_MASK)
85
86/* SJA1000 Control Register in the BasicCAN Mode */
87#define REG_CR 0x00
88
89/* States of some SJA1000 registers after hardware reset in the BasicCAN mode*/
90#define REG_CR_BASICCAN_INITIAL 0x21
91#define REG_CR_BASICCAN_INITIAL_MASK 0xa1
92#define REG_SR_BASICCAN_INITIAL 0x0c
93#define REG_IR_BASICCAN_INITIAL 0xe0
94
95/* States of some SJA1000 registers after hardware reset in the PeliCAN mode*/
96#define REG_MOD_PELICAN_INITIAL 0x01
97#define REG_SR_PELICAN_INITIAL 0x3c
98#define REG_IR_PELICAN_INITIAL 0x00
99
100#define ADLINK_PCI_VENDOR_ID 0x144A
101#define ADLINK_PCI_DEVICE_ID 0x7841
102
103#define ESD_PCI_SUB_SYS_ID_PCI200 0x0004
104#define ESD_PCI_SUB_SYS_ID_PCI266 0x0009
105#define ESD_PCI_SUB_SYS_ID_PMC266 0x000e
106#define ESD_PCI_SUB_SYS_ID_CPCI200 0x010b
107#define ESD_PCI_SUB_SYS_ID_PCIE2000 0x0200
108#define ESD_PCI_SUB_SYS_ID_PCI104200 0x0501
109
110#define CAN200PCI_DEVICE_ID 0x9030
111#define CAN200PCI_VENDOR_ID 0x10b5
112#define CAN200PCI_SUB_DEVICE_ID 0x0301
113#define CAN200PCI_SUB_VENDOR_ID 0xe1c5
114
115#define IXXAT_PCI_VENDOR_ID 0x10b5
116#define IXXAT_PCI_DEVICE_ID 0x9050
117#define IXXAT_PCI_SUB_SYS_ID 0x2540
118
119#define MARATHON_PCI_DEVICE_ID 0x2715
120#define MARATHON_PCIE_DEVICE_ID 0x3432
121
122#define TEWS_PCI_VENDOR_ID 0x1498
123#define TEWS_PCI_DEVICE_ID_TMPC810 0x032A
124
125#define CTI_PCI_DEVICE_ID_CRG001 0x0900
126
127#define MOXA_PCI_VENDOR_ID 0x1393
128#define MOXA_PCI_DEVICE_ID 0x0100
129
130#define ASEM_RAW_CAN_VENDOR_ID 0x10b5
131#define ASEM_RAW_CAN_DEVICE_ID 0x9030
132#define ASEM_RAW_CAN_SUB_VENDOR_ID 0x3000
133#define ASEM_RAW_CAN_SUB_DEVICE_ID 0x1001
134#define ASEM_RAW_CAN_SUB_DEVICE_ID_BIS 0x1002
135#define ASEM_RAW_CAN_RST_REGISTER 0x54
136#define ASEM_RAW_CAN_RST_MASK_CAN1 0x20
137#define ASEM_RAW_CAN_RST_MASK_CAN2 0x04
138
139static void plx_pci_reset_common(struct pci_dev *pdev);
140static void plx9056_pci_reset_common(struct pci_dev *pdev);
141static void plx_pci_reset_marathon_pci(struct pci_dev *pdev);
142static void plx_pci_reset_marathon_pcie(struct pci_dev *pdev);
143static void plx_pci_reset_asem_dual_can_raw(struct pci_dev *pdev);
144
145struct plx_pci_channel_map {
146 u32 bar;
147 u32 offset;
148 u32 size; /* 0x00 - auto, e.g. length of entire bar */
149};
150
151struct plx_pci_card_info {
152 const char *name;
153 int channel_count;
154 u32 can_clock;
155 u8 ocr; /* output control register */
156 u8 cdr; /* clock divider register */
157
158 /* Parameters for mapping local configuration space */
159 struct plx_pci_channel_map conf_map;
160
161 /* Parameters for mapping the SJA1000 chips */
162 struct plx_pci_channel_map chan_map_tbl[PLX_PCI_MAX_CHAN];
163
164 /* Pointer to device-dependent reset function */
165 void (*reset_func)(struct pci_dev *pdev);
166};
167
168static struct plx_pci_card_info plx_pci_card_info_adlink = {
169 "Adlink PCI-7841/cPCI-7841", 2,
170 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
171 {1, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} },
172 &plx_pci_reset_common
173 /* based on PLX9052 */
174};
175
176static struct plx_pci_card_info plx_pci_card_info_adlink_se = {
177 "Adlink PCI-7841/cPCI-7841 SE", 2,
178 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
179 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} },
180 &plx_pci_reset_common
181 /* based on PLX9052 */
182};
183
184static struct plx_pci_card_info plx_pci_card_info_esd200 = {
185 "esd CAN-PCI/CPCI/PCI104/200", 2,
186 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
187 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} },
188 &plx_pci_reset_common
189 /* based on PLX9030/9050 */
190};
191
192static struct plx_pci_card_info plx_pci_card_info_esd266 = {
193 "esd CAN-PCI/PMC/266", 2,
194 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
195 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} },
196 &plx9056_pci_reset_common
197 /* based on PLX9056 */
198};
199
200static struct plx_pci_card_info plx_pci_card_info_esd2000 = {
201 "esd CAN-PCIe/2000", 2,
202 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
203 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} },
204 &plx9056_pci_reset_common
205 /* based on PEX8311 */
206};
207
208static struct plx_pci_card_info plx_pci_card_info_ixxat = {
209 "IXXAT PC-I 04/PCI", 2,
210 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
211 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x200, 0x80} },
212 &plx_pci_reset_common
213 /* based on PLX9050 */
214};
215
216static struct plx_pci_card_info plx_pci_card_info_marathon_pci = {
217 "Marathon CAN-bus-PCI", 2,
218 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
219 {0, 0x00, 0x00}, { {2, 0x00, 0x00}, {4, 0x00, 0x00} },
220 &plx_pci_reset_marathon_pci
221 /* based on PLX9052 */
222};
223
224static struct plx_pci_card_info plx_pci_card_info_marathon_pcie = {
225 "Marathon CAN-bus-PCIe", 2,
226 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
227 {0, 0x00, 0x00}, { {2, 0x00, 0x00}, {3, 0x80, 0x00} },
228 &plx_pci_reset_marathon_pcie
229 /* based on PEX8311 */
230};
231
232static struct plx_pci_card_info plx_pci_card_info_tews = {
233 "TEWS TECHNOLOGIES TPMC810", 2,
234 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
235 {0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} },
236 &plx_pci_reset_common
237 /* based on PLX9030 */
238};
239
240static struct plx_pci_card_info plx_pci_card_info_cti = {
241 "Connect Tech Inc. CANpro/104-Plus Opto (CRG001)", 2,
242 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
243 {0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} },
244 &plx_pci_reset_common
245 /* based on PLX9030 */
246};
247
248static struct plx_pci_card_info plx_pci_card_info_elcus = {
249 "Eclus CAN-200-PCI", 2,
250 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
251 {1, 0x00, 0x00}, { {2, 0x00, 0x80}, {3, 0x00, 0x80} },
252 &plx_pci_reset_common
253 /* based on PLX9030 */
254};
255
256static struct plx_pci_card_info plx_pci_card_info_moxa = {
257 "MOXA", 2,
258 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
259 {0, 0x00, 0x00}, { {0, 0x00, 0x80}, {1, 0x00, 0x80} },
260 &plx_pci_reset_common
261 /* based on PLX9052 */
262};
263
264static struct plx_pci_card_info plx_pci_card_info_asem_dual_can = {
265 "ASEM Dual CAN raw PCI", 2,
266 PLX_PCI_CAN_CLOCK, ASEM_PCI_OCR, PLX_PCI_CDR,
267 {0, 0x00, 0x00}, { {2, 0x00, 0x00}, {4, 0x00, 0x00} },
268 &plx_pci_reset_asem_dual_can_raw
269 /* based on PLX9030 */
270};
271
272static const struct pci_device_id plx_pci_tbl[] = {
273 {
274 /* Adlink PCI-7841/cPCI-7841 */
275 ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID,
276 PCI_ANY_ID, PCI_ANY_ID,
277 PCI_CLASS_NETWORK_OTHER << 8, ~0,
278 (kernel_ulong_t)&plx_pci_card_info_adlink
279 },
280 {
281 /* Adlink PCI-7841/cPCI-7841 SE */
282 ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID,
283 PCI_ANY_ID, PCI_ANY_ID,
284 PCI_CLASS_COMMUNICATION_OTHER << 8, ~0,
285 (kernel_ulong_t)&plx_pci_card_info_adlink_se
286 },
287 {
288 /* esd CAN-PCI/200 */
289 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
290 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI200,
291 0, 0,
292 (kernel_ulong_t)&plx_pci_card_info_esd200
293 },
294 {
295 /* esd CAN-CPCI/200 */
296 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
297 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_CPCI200,
298 0, 0,
299 (kernel_ulong_t)&plx_pci_card_info_esd200
300 },
301 {
302 /* esd CAN-PCI104/200 */
303 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
304 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI104200,
305 0, 0,
306 (kernel_ulong_t)&plx_pci_card_info_esd200
307 },
308 {
309 /* esd CAN-PCI/266 */
310 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056,
311 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI266,
312 0, 0,
313 (kernel_ulong_t)&plx_pci_card_info_esd266
314 },
315 {
316 /* esd CAN-PMC/266 */
317 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056,
318 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PMC266,
319 0, 0,
320 (kernel_ulong_t)&plx_pci_card_info_esd266
321 },
322 {
323 /* esd CAN-PCIE/2000 */
324 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056,
325 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCIE2000,
326 0, 0,
327 (kernel_ulong_t)&plx_pci_card_info_esd2000
328 },
329 {
330 /* IXXAT PC-I 04/PCI card */
331 IXXAT_PCI_VENDOR_ID, IXXAT_PCI_DEVICE_ID,
332 PCI_ANY_ID, IXXAT_PCI_SUB_SYS_ID,
333 0, 0,
334 (kernel_ulong_t)&plx_pci_card_info_ixxat
335 },
336 {
337 /* Marathon CAN-bus-PCI card */
338 PCI_VENDOR_ID_PLX, MARATHON_PCI_DEVICE_ID,
339 PCI_ANY_ID, PCI_ANY_ID,
340 0, 0,
341 (kernel_ulong_t)&plx_pci_card_info_marathon_pci
342 },
343 {
344 /* Marathon CAN-bus-PCIe card */
345 PCI_VENDOR_ID_PLX, MARATHON_PCIE_DEVICE_ID,
346 PCI_ANY_ID, PCI_ANY_ID,
347 0, 0,
348 (kernel_ulong_t)&plx_pci_card_info_marathon_pcie
349 },
350 {
351 /* TEWS TECHNOLOGIES TPMC810 card */
352 TEWS_PCI_VENDOR_ID, TEWS_PCI_DEVICE_ID_TMPC810,
353 PCI_ANY_ID, PCI_ANY_ID,
354 0, 0,
355 (kernel_ulong_t)&plx_pci_card_info_tews
356 },
357 {
358 /* Connect Tech Inc. CANpro/104-Plus Opto (CRG001) card */
359 PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
360 PCI_SUBVENDOR_ID_CONNECT_TECH, CTI_PCI_DEVICE_ID_CRG001,
361 0, 0,
362 (kernel_ulong_t)&plx_pci_card_info_cti
363 },
364 {
365 /* Elcus CAN-200-PCI */
366 CAN200PCI_VENDOR_ID, CAN200PCI_DEVICE_ID,
367 CAN200PCI_SUB_VENDOR_ID, CAN200PCI_SUB_DEVICE_ID,
368 0, 0,
369 (kernel_ulong_t)&plx_pci_card_info_elcus
370 },
371 {
372 /* moxa */
373 MOXA_PCI_VENDOR_ID, MOXA_PCI_DEVICE_ID,
374 PCI_ANY_ID, PCI_ANY_ID,
375 0, 0,
376 (kernel_ulong_t)&plx_pci_card_info_moxa
377 },
378 {
379 /* ASEM Dual CAN raw */
380 ASEM_RAW_CAN_VENDOR_ID, ASEM_RAW_CAN_DEVICE_ID,
381 ASEM_RAW_CAN_SUB_VENDOR_ID, ASEM_RAW_CAN_SUB_DEVICE_ID,
382 0, 0,
383 (kernel_ulong_t)&plx_pci_card_info_asem_dual_can
384 },
385 {
386 /* ASEM Dual CAN raw -new model */
387 ASEM_RAW_CAN_VENDOR_ID, ASEM_RAW_CAN_DEVICE_ID,
388 ASEM_RAW_CAN_SUB_VENDOR_ID, ASEM_RAW_CAN_SUB_DEVICE_ID_BIS,
389 0, 0,
390 (kernel_ulong_t)&plx_pci_card_info_asem_dual_can
391 },
392 { 0,}
393};
394MODULE_DEVICE_TABLE(pci, plx_pci_tbl);
395
396static u8 plx_pci_read_reg(const struct sja1000_priv *priv, int port)
397{
398 return ioread8(priv->reg_base + port);
399}
400
401static void plx_pci_write_reg(const struct sja1000_priv *priv, int port, u8 val)
402{
403 iowrite8(val, priv->reg_base + port);
404}
405
406/*
407 * Check if a CAN controller is present at the specified location
408 * by trying to switch 'em from the Basic mode into the PeliCAN mode.
409 * Also check states of some registers in reset mode.
410 */
411static inline int plx_pci_check_sja1000(const struct sja1000_priv *priv)
412{
413 int flag = 0;
414
415 /*
416 * Check registers after hardware reset (the Basic mode)
417 * See states on p. 10 of the Datasheet.
418 */
419 if ((priv->read_reg(priv, REG_CR) & REG_CR_BASICCAN_INITIAL_MASK) ==
420 REG_CR_BASICCAN_INITIAL &&
421 (priv->read_reg(priv, SJA1000_SR) == REG_SR_BASICCAN_INITIAL) &&
422 (priv->read_reg(priv, SJA1000_IR) == REG_IR_BASICCAN_INITIAL))
423 flag = 1;
424
425 /* Bring the SJA1000 into the PeliCAN mode*/
426 priv->write_reg(priv, SJA1000_CDR, CDR_PELICAN);
427
428 /*
429 * Check registers after reset in the PeliCAN mode.
430 * See states on p. 23 of the Datasheet.
431 */
432 if (priv->read_reg(priv, SJA1000_MOD) == REG_MOD_PELICAN_INITIAL &&
433 priv->read_reg(priv, SJA1000_SR) == REG_SR_PELICAN_INITIAL &&
434 priv->read_reg(priv, SJA1000_IR) == REG_IR_PELICAN_INITIAL)
435 return flag;
436
437 return 0;
438}
439
440/*
441 * PLX9030/50/52 software reset
442 * Also LRESET# asserts and brings to reset device on the Local Bus (if wired).
443 * For most cards it's enough for reset the SJA1000 chips.
444 */
445static void plx_pci_reset_common(struct pci_dev *pdev)
446{
447 struct plx_pci_card *card = pci_get_drvdata(pdev);
448 u32 cntrl;
449
450 cntrl = ioread32(card->conf_addr + PLX_CNTRL);
451 cntrl |= PLX_PCI_RESET;
452 iowrite32(cntrl, card->conf_addr + PLX_CNTRL);
453 udelay(100);
454 cntrl ^= PLX_PCI_RESET;
455 iowrite32(cntrl, card->conf_addr + PLX_CNTRL);
456};
457
458/*
459 * PLX9056 software reset
460 * Assert LRESET# and reset device(s) on the Local Bus (if wired).
461 */
462static void plx9056_pci_reset_common(struct pci_dev *pdev)
463{
464 struct plx_pci_card *card = pci_get_drvdata(pdev);
465 u32 cntrl;
466
467 /* issue a local bus reset */
468 cntrl = ioread32(card->conf_addr + PLX9056_CNTRL);
469 cntrl |= PLX_PCI_RESET;
470 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL);
471 udelay(100);
472 cntrl ^= PLX_PCI_RESET;
473 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL);
474
475 /* reload local configuration from EEPROM */
476 cntrl |= PLX9056_PCI_RCR;
477 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL);
478
479 /*
480 * There is no safe way to poll for the end
481 * of reconfiguration process. Waiting for 10ms
482 * is safe.
483 */
484 mdelay(10);
485
486 cntrl ^= PLX9056_PCI_RCR;
487 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL);
488};
489
490/* Special reset function for Marathon CAN-bus-PCI card */
491static void plx_pci_reset_marathon_pci(struct pci_dev *pdev)
492{
493 void __iomem *reset_addr;
494 int i;
495 static const int reset_bar[2] = {3, 5};
496
497 plx_pci_reset_common(pdev);
498
499 for (i = 0; i < 2; i++) {
500 reset_addr = pci_iomap(pdev, reset_bar[i], 0);
501 if (!reset_addr) {
502 dev_err(&pdev->dev, "Failed to remap reset "
503 "space %d (BAR%d)\n", i, reset_bar[i]);
504 } else {
505 /* reset the SJA1000 chip */
506 iowrite8(0x1, reset_addr);
507 udelay(100);
508 pci_iounmap(pdev, reset_addr);
509 }
510 }
511}
512
513/* Special reset function for Marathon CAN-bus-PCIe card */
514static void plx_pci_reset_marathon_pcie(struct pci_dev *pdev)
515{
516 void __iomem *addr;
517 void __iomem *reset_addr;
518 int i;
519
520 plx9056_pci_reset_common(pdev);
521
522 for (i = 0; i < 2; i++) {
523 struct plx_pci_channel_map *chan_map =
524 &plx_pci_card_info_marathon_pcie.chan_map_tbl[i];
525 addr = pci_iomap(pdev, chan_map->bar, chan_map->size);
526 if (!addr) {
527 dev_err(&pdev->dev, "Failed to remap reset "
528 "space %d (BAR%d)\n", i, chan_map->bar);
529 } else {
530 /* reset the SJA1000 chip */
531 #define MARATHON_PCIE_RESET_OFFSET 32
532 reset_addr = addr + chan_map->offset +
533 MARATHON_PCIE_RESET_OFFSET;
534 iowrite8(0x1, reset_addr);
535 udelay(100);
536 pci_iounmap(pdev, addr);
537 }
538 }
539}
540
541/* Special reset function for ASEM Dual CAN raw card */
542static void plx_pci_reset_asem_dual_can_raw(struct pci_dev *pdev)
543{
544 void __iomem *bar0_addr;
545 u8 tmpval;
546
547 plx_pci_reset_common(pdev);
548
549 bar0_addr = pci_iomap(pdev, 0, 0);
550 if (!bar0_addr) {
551 dev_err(&pdev->dev, "Failed to remap reset space 0 (BAR0)\n");
552 return;
553 }
554
555 /* reset the two SJA1000 chips */
556 tmpval = ioread8(bar0_addr + ASEM_RAW_CAN_RST_REGISTER);
557 tmpval &= ~(ASEM_RAW_CAN_RST_MASK_CAN1 | ASEM_RAW_CAN_RST_MASK_CAN2);
558 iowrite8(tmpval, bar0_addr + ASEM_RAW_CAN_RST_REGISTER);
559 usleep_range(300, 400);
560 tmpval |= ASEM_RAW_CAN_RST_MASK_CAN1 | ASEM_RAW_CAN_RST_MASK_CAN2;
561 iowrite8(tmpval, bar0_addr + ASEM_RAW_CAN_RST_REGISTER);
562 usleep_range(300, 400);
563 pci_iounmap(pdev, bar0_addr);
564}
565
566static void plx_pci_del_card(struct pci_dev *pdev)
567{
568 struct plx_pci_card *card = pci_get_drvdata(pdev);
569 struct net_device *dev;
570 struct sja1000_priv *priv;
571 int i = 0;
572
573 for (i = 0; i < PLX_PCI_MAX_CHAN; i++) {
574 dev = card->net_dev[i];
575 if (!dev)
576 continue;
577
578 dev_info(&pdev->dev, "Removing %s\n", dev->name);
579 unregister_sja1000dev(dev);
580 priv = netdev_priv(dev);
581 if (priv->reg_base)
582 pci_iounmap(pdev, priv->reg_base);
583 free_sja1000dev(dev);
584 }
585
586 card->reset_func(pdev);
587
588 /*
589 * Disable interrupts from PCI-card and disable local
590 * interrupts
591 */
592 if (pdev->device != PCI_DEVICE_ID_PLX_9056 &&
593 pdev->device != MARATHON_PCIE_DEVICE_ID)
594 iowrite32(0x0, card->conf_addr + PLX_INTCSR);
595 else
596 iowrite32(0x0, card->conf_addr + PLX9056_INTCSR);
597
598 if (card->conf_addr)
599 pci_iounmap(pdev, card->conf_addr);
600
601 kfree(card);
602
603 pci_disable_device(pdev);
604}
605
606/*
607 * Probe PLX90xx based device for the SJA1000 chips and register each
608 * available CAN channel to SJA1000 Socket-CAN subsystem.
609 */
610static int plx_pci_add_card(struct pci_dev *pdev,
611 const struct pci_device_id *ent)
612{
613 struct sja1000_priv *priv;
614 struct net_device *dev;
615 struct plx_pci_card *card;
616 struct plx_pci_card_info *ci;
617 int err, i;
618 u32 val;
619 void __iomem *addr;
620
621 ci = (struct plx_pci_card_info *)ent->driver_data;
622
623 if (pci_enable_device(pdev) < 0) {
624 dev_err(&pdev->dev, "Failed to enable PCI device\n");
625 return -ENODEV;
626 }
627
628 dev_info(&pdev->dev, "Detected \"%s\" card at slot #%i\n",
629 ci->name, PCI_SLOT(pdev->devfn));
630
631 /* Allocate card structures to hold addresses, ... */
632 card = kzalloc(sizeof(*card), GFP_KERNEL);
633 if (!card) {
634 pci_disable_device(pdev);
635 return -ENOMEM;
636 }
637
638 pci_set_drvdata(pdev, card);
639
640 card->channels = 0;
641
642 /* Remap PLX90xx configuration space */
643 addr = pci_iomap(pdev, ci->conf_map.bar, ci->conf_map.size);
644 if (!addr) {
645 err = -ENOMEM;
646 dev_err(&pdev->dev, "Failed to remap configuration space "
647 "(BAR%d)\n", ci->conf_map.bar);
648 goto failure_cleanup;
649 }
650 card->conf_addr = addr + ci->conf_map.offset;
651
652 ci->reset_func(pdev);
653 card->reset_func = ci->reset_func;
654
655 /* Detect available channels */
656 for (i = 0; i < ci->channel_count; i++) {
657 struct plx_pci_channel_map *cm = &ci->chan_map_tbl[i];
658
659 dev = alloc_sja1000dev(0);
660 if (!dev) {
661 err = -ENOMEM;
662 goto failure_cleanup;
663 }
664
665 card->net_dev[i] = dev;
666 priv = netdev_priv(dev);
667 priv->priv = card;
668 priv->irq_flags = IRQF_SHARED;
669
670 dev->irq = pdev->irq;
671
672 /*
673 * Remap IO space of the SJA1000 chips
674 * This is device-dependent mapping
675 */
676 addr = pci_iomap(pdev, cm->bar, cm->size);
677 if (!addr) {
678 err = -ENOMEM;
679 dev_err(&pdev->dev, "Failed to remap BAR%d\n", cm->bar);
680 goto failure_cleanup;
681 }
682
683 priv->reg_base = addr + cm->offset;
684 priv->read_reg = plx_pci_read_reg;
685 priv->write_reg = plx_pci_write_reg;
686
687 /* Check if channel is present */
688 if (plx_pci_check_sja1000(priv)) {
689 priv->can.clock.freq = ci->can_clock;
690 priv->ocr = ci->ocr;
691 priv->cdr = ci->cdr;
692
693 SET_NETDEV_DEV(dev, &pdev->dev);
694 dev->dev_id = i;
695
696 /* Register SJA1000 device */
697 err = register_sja1000dev(dev);
698 if (err) {
699 dev_err(&pdev->dev, "Registering device failed "
700 "(err=%d)\n", err);
701 goto failure_cleanup;
702 }
703
704 card->channels++;
705
706 dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d "
707 "registered as %s\n", i + 1, priv->reg_base,
708 dev->irq, dev->name);
709 } else {
710 dev_err(&pdev->dev, "Channel #%d not detected\n",
711 i + 1);
712 free_sja1000dev(dev);
713 card->net_dev[i] = NULL;
714 }
715 }
716
717 if (!card->channels) {
718 err = -ENODEV;
719 goto failure_cleanup;
720 }
721
722 /*
723 * Enable interrupts from PCI-card (PLX90xx) and enable Local_1,
724 * Local_2 interrupts from the SJA1000 chips
725 */
726 if (pdev->device != PCI_DEVICE_ID_PLX_9056 &&
727 pdev->device != MARATHON_PCIE_DEVICE_ID) {
728 val = ioread32(card->conf_addr + PLX_INTCSR);
729 if (pdev->subsystem_vendor == PCI_VENDOR_ID_ESDGMBH)
730 val |= PLX_LINT1_EN | PLX_PCI_INT_EN;
731 else
732 val |= PLX_LINT1_EN | PLX_LINT2_EN | PLX_PCI_INT_EN;
733 iowrite32(val, card->conf_addr + PLX_INTCSR);
734 } else {
735 iowrite32(PLX9056_LINTI | PLX9056_PCI_INT_EN,
736 card->conf_addr + PLX9056_INTCSR);
737 }
738 return 0;
739
740failure_cleanup:
741 dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n", err);
742
743 plx_pci_del_card(pdev);
744
745 return err;
746}
747
748static struct pci_driver plx_pci_driver = {
749 .name = DRV_NAME,
750 .id_table = plx_pci_tbl,
751 .probe = plx_pci_add_card,
752 .remove = plx_pci_del_card,
753};
754
755module_pci_driver(plx_pci_driver);