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1/*
2 * SMP initialisation and IPI support
3 * Based on arch/arm64/kernel/smp.c
4 *
5 * Copyright (C) 2012 ARM Ltd.
6 * Copyright (C) 2015 Regents of the University of California
7 * Copyright (C) 2017 SiFive
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#include <linux/interrupt.h>
23#include <linux/smp.h>
24#include <linux/sched.h>
25
26#include <asm/sbi.h>
27#include <asm/tlbflush.h>
28#include <asm/cacheflush.h>
29
30/* A collection of single bit ipi messages. */
31static struct {
32 unsigned long bits ____cacheline_aligned;
33} ipi_data[NR_CPUS] __cacheline_aligned;
34
35enum ipi_message_type {
36 IPI_RESCHEDULE,
37 IPI_CALL_FUNC,
38 IPI_MAX
39};
40
41
42/* Unsupported */
43int setup_profiling_timer(unsigned int multiplier)
44{
45 return -EINVAL;
46}
47
48irqreturn_t handle_ipi(void)
49{
50 unsigned long *pending_ipis = &ipi_data[smp_processor_id()].bits;
51
52 /* Clear pending IPI */
53 csr_clear(sip, SIE_SSIE);
54
55 while (true) {
56 unsigned long ops;
57
58 /* Order bit clearing and data access. */
59 mb();
60
61 ops = xchg(pending_ipis, 0);
62 if (ops == 0)
63 return IRQ_HANDLED;
64
65 if (ops & (1 << IPI_RESCHEDULE))
66 scheduler_ipi();
67
68 if (ops & (1 << IPI_CALL_FUNC))
69 generic_smp_call_function_interrupt();
70
71 BUG_ON((ops >> IPI_MAX) != 0);
72
73 /* Order data access and bit testing. */
74 mb();
75 }
76
77 return IRQ_HANDLED;
78}
79
80static void
81send_ipi_message(const struct cpumask *to_whom, enum ipi_message_type operation)
82{
83 int i;
84
85 mb();
86 for_each_cpu(i, to_whom)
87 set_bit(operation, &ipi_data[i].bits);
88
89 mb();
90 sbi_send_ipi(cpumask_bits(to_whom));
91}
92
93void arch_send_call_function_ipi_mask(struct cpumask *mask)
94{
95 send_ipi_message(mask, IPI_CALL_FUNC);
96}
97
98void arch_send_call_function_single_ipi(int cpu)
99{
100 send_ipi_message(cpumask_of(cpu), IPI_CALL_FUNC);
101}
102
103static void ipi_stop(void *unused)
104{
105 while (1)
106 wait_for_interrupt();
107}
108
109void smp_send_stop(void)
110{
111 on_each_cpu(ipi_stop, NULL, 1);
112}
113
114void smp_send_reschedule(int cpu)
115{
116 send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
117}
118
119/*
120 * Performs an icache flush for the given MM context. RISC-V has no direct
121 * mechanism for instruction cache shoot downs, so instead we send an IPI that
122 * informs the remote harts they need to flush their local instruction caches.
123 * To avoid pathologically slow behavior in a common case (a bunch of
124 * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
125 * IPIs for harts that are not currently executing a MM context and instead
126 * schedule a deferred local instruction cache flush to be performed before
127 * execution resumes on each hart.
128 */
129void flush_icache_mm(struct mm_struct *mm, bool local)
130{
131 unsigned int cpu;
132 cpumask_t others, *mask;
133
134 preempt_disable();
135
136 /* Mark every hart's icache as needing a flush for this MM. */
137 mask = &mm->context.icache_stale_mask;
138 cpumask_setall(mask);
139 /* Flush this hart's I$ now, and mark it as flushed. */
140 cpu = smp_processor_id();
141 cpumask_clear_cpu(cpu, mask);
142 local_flush_icache_all();
143
144 /*
145 * Flush the I$ of other harts concurrently executing, and mark them as
146 * flushed.
147 */
148 cpumask_andnot(&others, mm_cpumask(mm), cpumask_of(cpu));
149 local |= cpumask_empty(&others);
150 if (mm != current->active_mm || !local)
151 sbi_remote_fence_i(others.bits);
152 else {
153 /*
154 * It's assumed that at least one strongly ordered operation is
155 * performed on this hart between setting a hart's cpumask bit
156 * and scheduling this MM context on that hart. Sending an SBI
157 * remote message will do this, but in the case where no
158 * messages are sent we still need to order this hart's writes
159 * with flush_icache_deferred().
160 */
161 smp_mb();
162 }
163
164 preempt_enable();
165}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * SMP initialisation and IPI support
4 * Based on arch/arm64/kernel/smp.c
5 *
6 * Copyright (C) 2012 ARM Ltd.
7 * Copyright (C) 2015 Regents of the University of California
8 * Copyright (C) 2017 SiFive
9 */
10
11#include <linux/cpu.h>
12#include <linux/clockchips.h>
13#include <linux/interrupt.h>
14#include <linux/module.h>
15#include <linux/kexec.h>
16#include <linux/kgdb.h>
17#include <linux/percpu.h>
18#include <linux/profile.h>
19#include <linux/smp.h>
20#include <linux/sched.h>
21#include <linux/seq_file.h>
22#include <linux/delay.h>
23#include <linux/irq.h>
24#include <linux/irq_work.h>
25#include <linux/nmi.h>
26
27#include <asm/tlbflush.h>
28#include <asm/cacheflush.h>
29#include <asm/cpu_ops.h>
30
31enum ipi_message_type {
32 IPI_RESCHEDULE,
33 IPI_CALL_FUNC,
34 IPI_CPU_STOP,
35 IPI_CPU_CRASH_STOP,
36 IPI_IRQ_WORK,
37 IPI_TIMER,
38 IPI_CPU_BACKTRACE,
39 IPI_KGDB_ROUNDUP,
40 IPI_MAX
41};
42
43unsigned long __cpuid_to_hartid_map[NR_CPUS] __ro_after_init = {
44 [0 ... NR_CPUS-1] = INVALID_HARTID
45};
46
47void __init smp_setup_processor_id(void)
48{
49 cpuid_to_hartid_map(0) = boot_cpu_hartid;
50}
51
52static DEFINE_PER_CPU_READ_MOSTLY(int, ipi_dummy_dev);
53static int ipi_virq_base __ro_after_init;
54static int nr_ipi __ro_after_init = IPI_MAX;
55static struct irq_desc *ipi_desc[IPI_MAX] __read_mostly;
56
57int riscv_hartid_to_cpuid(unsigned long hartid)
58{
59 int i;
60
61 for (i = 0; i < NR_CPUS; i++)
62 if (cpuid_to_hartid_map(i) == hartid)
63 return i;
64
65 return -ENOENT;
66}
67
68static void ipi_stop(void)
69{
70 set_cpu_online(smp_processor_id(), false);
71 while (1)
72 wait_for_interrupt();
73}
74
75#ifdef CONFIG_KEXEC_CORE
76static atomic_t waiting_for_crash_ipi = ATOMIC_INIT(0);
77
78static inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs)
79{
80 crash_save_cpu(regs, cpu);
81
82 atomic_dec(&waiting_for_crash_ipi);
83
84 local_irq_disable();
85
86#ifdef CONFIG_HOTPLUG_CPU
87 if (cpu_has_hotplug(cpu))
88 cpu_ops->cpu_stop();
89#endif
90
91 for(;;)
92 wait_for_interrupt();
93}
94#else
95static inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs)
96{
97 unreachable();
98}
99#endif
100
101static void send_ipi_mask(const struct cpumask *mask, enum ipi_message_type op)
102{
103 __ipi_send_mask(ipi_desc[op], mask);
104}
105
106static void send_ipi_single(int cpu, enum ipi_message_type op)
107{
108 __ipi_send_mask(ipi_desc[op], cpumask_of(cpu));
109}
110
111#ifdef CONFIG_IRQ_WORK
112void arch_irq_work_raise(void)
113{
114 send_ipi_single(smp_processor_id(), IPI_IRQ_WORK);
115}
116#endif
117
118static irqreturn_t handle_IPI(int irq, void *data)
119{
120 unsigned int cpu = smp_processor_id();
121 int ipi = irq - ipi_virq_base;
122
123 switch (ipi) {
124 case IPI_RESCHEDULE:
125 scheduler_ipi();
126 break;
127 case IPI_CALL_FUNC:
128 generic_smp_call_function_interrupt();
129 break;
130 case IPI_CPU_STOP:
131 ipi_stop();
132 break;
133 case IPI_CPU_CRASH_STOP:
134 ipi_cpu_crash_stop(cpu, get_irq_regs());
135 break;
136 case IPI_IRQ_WORK:
137 irq_work_run();
138 break;
139#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
140 case IPI_TIMER:
141 tick_receive_broadcast();
142 break;
143#endif
144 case IPI_CPU_BACKTRACE:
145 nmi_cpu_backtrace(get_irq_regs());
146 break;
147 case IPI_KGDB_ROUNDUP:
148 kgdb_nmicallback(cpu, get_irq_regs());
149 break;
150 default:
151 pr_warn("CPU%d: unhandled IPI%d\n", cpu, ipi);
152 break;
153 }
154
155 return IRQ_HANDLED;
156}
157
158void riscv_ipi_enable(void)
159{
160 int i;
161
162 if (WARN_ON_ONCE(!ipi_virq_base))
163 return;
164
165 for (i = 0; i < nr_ipi; i++)
166 enable_percpu_irq(ipi_virq_base + i, 0);
167}
168
169void riscv_ipi_disable(void)
170{
171 int i;
172
173 if (WARN_ON_ONCE(!ipi_virq_base))
174 return;
175
176 for (i = 0; i < nr_ipi; i++)
177 disable_percpu_irq(ipi_virq_base + i);
178}
179
180bool riscv_ipi_have_virq_range(void)
181{
182 return (ipi_virq_base) ? true : false;
183}
184
185void riscv_ipi_set_virq_range(int virq, int nr)
186{
187 int i, err;
188
189 if (WARN_ON(ipi_virq_base))
190 return;
191
192 WARN_ON(nr < IPI_MAX);
193 nr_ipi = min(nr, IPI_MAX);
194 ipi_virq_base = virq;
195
196 /* Request IPIs */
197 for (i = 0; i < nr_ipi; i++) {
198 err = request_percpu_irq(ipi_virq_base + i, handle_IPI,
199 "IPI", &ipi_dummy_dev);
200 WARN_ON(err);
201
202 ipi_desc[i] = irq_to_desc(ipi_virq_base + i);
203 irq_set_status_flags(ipi_virq_base + i, IRQ_HIDDEN);
204 }
205
206 /* Enabled IPIs for boot CPU immediately */
207 riscv_ipi_enable();
208}
209
210static const char * const ipi_names[] = {
211 [IPI_RESCHEDULE] = "Rescheduling interrupts",
212 [IPI_CALL_FUNC] = "Function call interrupts",
213 [IPI_CPU_STOP] = "CPU stop interrupts",
214 [IPI_CPU_CRASH_STOP] = "CPU stop (for crash dump) interrupts",
215 [IPI_IRQ_WORK] = "IRQ work interrupts",
216 [IPI_TIMER] = "Timer broadcast interrupts",
217 [IPI_CPU_BACKTRACE] = "CPU backtrace interrupts",
218 [IPI_KGDB_ROUNDUP] = "KGDB roundup interrupts",
219};
220
221void show_ipi_stats(struct seq_file *p, int prec)
222{
223 unsigned int cpu, i;
224
225 for (i = 0; i < IPI_MAX; i++) {
226 seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i,
227 prec >= 4 ? " " : "");
228 for_each_online_cpu(cpu)
229 seq_printf(p, "%10u ", irq_desc_kstat_cpu(ipi_desc[i], cpu));
230 seq_printf(p, " %s\n", ipi_names[i]);
231 }
232}
233
234void arch_send_call_function_ipi_mask(struct cpumask *mask)
235{
236 send_ipi_mask(mask, IPI_CALL_FUNC);
237}
238
239void arch_send_call_function_single_ipi(int cpu)
240{
241 send_ipi_single(cpu, IPI_CALL_FUNC);
242}
243
244#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
245void tick_broadcast(const struct cpumask *mask)
246{
247 send_ipi_mask(mask, IPI_TIMER);
248}
249#endif
250
251void smp_send_stop(void)
252{
253 unsigned long timeout;
254
255 if (num_online_cpus() > 1) {
256 cpumask_t mask;
257
258 cpumask_copy(&mask, cpu_online_mask);
259 cpumask_clear_cpu(smp_processor_id(), &mask);
260
261 if (system_state <= SYSTEM_RUNNING)
262 pr_crit("SMP: stopping secondary CPUs\n");
263 send_ipi_mask(&mask, IPI_CPU_STOP);
264 }
265
266 /* Wait up to one second for other CPUs to stop */
267 timeout = USEC_PER_SEC;
268 while (num_online_cpus() > 1 && timeout--)
269 udelay(1);
270
271 if (num_online_cpus() > 1)
272 pr_warn("SMP: failed to stop secondary CPUs %*pbl\n",
273 cpumask_pr_args(cpu_online_mask));
274}
275
276#ifdef CONFIG_KEXEC_CORE
277/*
278 * The number of CPUs online, not counting this CPU (which may not be
279 * fully online and so not counted in num_online_cpus()).
280 */
281static inline unsigned int num_other_online_cpus(void)
282{
283 unsigned int this_cpu_online = cpu_online(smp_processor_id());
284
285 return num_online_cpus() - this_cpu_online;
286}
287
288void crash_smp_send_stop(void)
289{
290 static int cpus_stopped;
291 cpumask_t mask;
292 unsigned long timeout;
293
294 /*
295 * This function can be called twice in panic path, but obviously
296 * we execute this only once.
297 */
298 if (cpus_stopped)
299 return;
300
301 cpus_stopped = 1;
302
303 /*
304 * If this cpu is the only one alive at this point in time, online or
305 * not, there are no stop messages to be sent around, so just back out.
306 */
307 if (num_other_online_cpus() == 0)
308 return;
309
310 cpumask_copy(&mask, cpu_online_mask);
311 cpumask_clear_cpu(smp_processor_id(), &mask);
312
313 atomic_set(&waiting_for_crash_ipi, num_other_online_cpus());
314
315 pr_crit("SMP: stopping secondary CPUs\n");
316 send_ipi_mask(&mask, IPI_CPU_CRASH_STOP);
317
318 /* Wait up to one second for other CPUs to stop */
319 timeout = USEC_PER_SEC;
320 while ((atomic_read(&waiting_for_crash_ipi) > 0) && timeout--)
321 udelay(1);
322
323 if (atomic_read(&waiting_for_crash_ipi) > 0)
324 pr_warn("SMP: failed to stop secondary CPUs %*pbl\n",
325 cpumask_pr_args(&mask));
326}
327
328bool smp_crash_stop_failed(void)
329{
330 return (atomic_read(&waiting_for_crash_ipi) > 0);
331}
332#endif
333
334void arch_smp_send_reschedule(int cpu)
335{
336 send_ipi_single(cpu, IPI_RESCHEDULE);
337}
338EXPORT_SYMBOL_GPL(arch_smp_send_reschedule);
339
340static void riscv_backtrace_ipi(cpumask_t *mask)
341{
342 send_ipi_mask(mask, IPI_CPU_BACKTRACE);
343}
344
345void arch_trigger_cpumask_backtrace(const cpumask_t *mask, int exclude_cpu)
346{
347 nmi_trigger_cpumask_backtrace(mask, exclude_cpu, riscv_backtrace_ipi);
348}
349
350#ifdef CONFIG_KGDB
351void kgdb_roundup_cpus(void)
352{
353 int this_cpu = raw_smp_processor_id();
354 int cpu;
355
356 for_each_online_cpu(cpu) {
357 /* No need to roundup ourselves */
358 if (cpu == this_cpu)
359 continue;
360
361 send_ipi_single(cpu, IPI_KGDB_ROUNDUP);
362 }
363}
364#endif