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1/*
2 * Copied from arch/arm64/kernel/cpufeature.c
3 *
4 * Copyright (C) 2015 ARM Ltd.
5 * Copyright (C) 2017 SiFive
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include <linux/of.h>
21#include <asm/processor.h>
22#include <asm/hwcap.h>
23
24unsigned long elf_hwcap __read_mostly;
25
26void riscv_fill_hwcap(void)
27{
28 struct device_node *node;
29 const char *isa;
30 size_t i;
31 static unsigned long isa2hwcap[256] = {0};
32
33 isa2hwcap['i'] = isa2hwcap['I'] = COMPAT_HWCAP_ISA_I;
34 isa2hwcap['m'] = isa2hwcap['M'] = COMPAT_HWCAP_ISA_M;
35 isa2hwcap['a'] = isa2hwcap['A'] = COMPAT_HWCAP_ISA_A;
36 isa2hwcap['f'] = isa2hwcap['F'] = COMPAT_HWCAP_ISA_F;
37 isa2hwcap['d'] = isa2hwcap['D'] = COMPAT_HWCAP_ISA_D;
38 isa2hwcap['c'] = isa2hwcap['C'] = COMPAT_HWCAP_ISA_C;
39
40 elf_hwcap = 0;
41
42 /*
43 * We don't support running Linux on hertergenous ISA systems. For
44 * now, we just check the ISA of the first processor.
45 */
46 node = of_find_node_by_type(NULL, "cpu");
47 if (!node) {
48 pr_warning("Unable to find \"cpu\" devicetree entry");
49 return;
50 }
51
52 if (of_property_read_string(node, "riscv,isa", &isa)) {
53 pr_warning("Unable to find \"riscv,isa\" devicetree entry");
54 return;
55 }
56
57 for (i = 0; i < strlen(isa); ++i)
58 elf_hwcap |= isa2hwcap[(unsigned char)(isa[i])];
59
60 pr_info("elf_hwcap is 0x%lx", elf_hwcap);
61}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copied from arch/arm64/kernel/cpufeature.c
4 *
5 * Copyright (C) 2015 ARM Ltd.
6 * Copyright (C) 2017 SiFive
7 */
8
9#include <linux/acpi.h>
10#include <linux/bitmap.h>
11#include <linux/cpu.h>
12#include <linux/cpuhotplug.h>
13#include <linux/ctype.h>
14#include <linux/log2.h>
15#include <linux/memory.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <asm/acpi.h>
19#include <asm/alternative.h>
20#include <asm/cacheflush.h>
21#include <asm/cpufeature.h>
22#include <asm/hwcap.h>
23#include <asm/text-patching.h>
24#include <asm/hwprobe.h>
25#include <asm/processor.h>
26#include <asm/sbi.h>
27#include <asm/vector.h>
28#include <asm/vendor_extensions.h>
29
30#define NUM_ALPHA_EXTS ('z' - 'a' + 1)
31
32static bool any_cpu_has_zicboz;
33
34unsigned long elf_hwcap __read_mostly;
35
36/* Host ISA bitmap */
37static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
38
39/* Per-cpu ISA extensions. */
40struct riscv_isainfo hart_isa[NR_CPUS];
41
42/**
43 * riscv_isa_extension_base() - Get base extension word
44 *
45 * @isa_bitmap: ISA bitmap to use
46 * Return: base extension word as unsigned long value
47 *
48 * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
49 */
50unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap)
51{
52 if (!isa_bitmap)
53 return riscv_isa[0];
54 return isa_bitmap[0];
55}
56EXPORT_SYMBOL_GPL(riscv_isa_extension_base);
57
58/**
59 * __riscv_isa_extension_available() - Check whether given extension
60 * is available or not
61 *
62 * @isa_bitmap: ISA bitmap to use
63 * @bit: bit position of the desired extension
64 * Return: true or false
65 *
66 * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
67 */
68bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, unsigned int bit)
69{
70 const unsigned long *bmap = (isa_bitmap) ? isa_bitmap : riscv_isa;
71
72 if (bit >= RISCV_ISA_EXT_MAX)
73 return false;
74
75 return test_bit(bit, bmap) ? true : false;
76}
77EXPORT_SYMBOL_GPL(__riscv_isa_extension_available);
78
79static int riscv_ext_zicbom_validate(const struct riscv_isa_ext_data *data,
80 const unsigned long *isa_bitmap)
81{
82 if (!riscv_cbom_block_size) {
83 pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n");
84 return -EINVAL;
85 }
86 if (!is_power_of_2(riscv_cbom_block_size)) {
87 pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n");
88 return -EINVAL;
89 }
90 return 0;
91}
92
93static int riscv_ext_zicboz_validate(const struct riscv_isa_ext_data *data,
94 const unsigned long *isa_bitmap)
95{
96 if (!riscv_cboz_block_size) {
97 pr_err("Zicboz detected in ISA string, disabling as no cboz-block-size found\n");
98 return -EINVAL;
99 }
100 if (!is_power_of_2(riscv_cboz_block_size)) {
101 pr_err("Zicboz disabled as cboz-block-size present, but is not a power-of-2\n");
102 return -EINVAL;
103 }
104 any_cpu_has_zicboz = true;
105 return 0;
106}
107
108static int riscv_ext_zca_depends(const struct riscv_isa_ext_data *data,
109 const unsigned long *isa_bitmap)
110{
111 if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA))
112 return 0;
113
114 return -EPROBE_DEFER;
115}
116static int riscv_ext_zcd_validate(const struct riscv_isa_ext_data *data,
117 const unsigned long *isa_bitmap)
118{
119 if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) &&
120 __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d))
121 return 0;
122
123 return -EPROBE_DEFER;
124}
125
126static int riscv_ext_zcf_validate(const struct riscv_isa_ext_data *data,
127 const unsigned long *isa_bitmap)
128{
129 if (IS_ENABLED(CONFIG_64BIT))
130 return -EINVAL;
131
132 if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) &&
133 __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_f))
134 return 0;
135
136 return -EPROBE_DEFER;
137}
138
139static int riscv_ext_svadu_validate(const struct riscv_isa_ext_data *data,
140 const unsigned long *isa_bitmap)
141{
142 /* SVADE has already been detected, use SVADE only */
143 if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_SVADE))
144 return -EOPNOTSUPP;
145
146 return 0;
147}
148
149static const unsigned int riscv_zk_bundled_exts[] = {
150 RISCV_ISA_EXT_ZBKB,
151 RISCV_ISA_EXT_ZBKC,
152 RISCV_ISA_EXT_ZBKX,
153 RISCV_ISA_EXT_ZKND,
154 RISCV_ISA_EXT_ZKNE,
155 RISCV_ISA_EXT_ZKR,
156 RISCV_ISA_EXT_ZKT,
157};
158
159static const unsigned int riscv_zkn_bundled_exts[] = {
160 RISCV_ISA_EXT_ZBKB,
161 RISCV_ISA_EXT_ZBKC,
162 RISCV_ISA_EXT_ZBKX,
163 RISCV_ISA_EXT_ZKND,
164 RISCV_ISA_EXT_ZKNE,
165 RISCV_ISA_EXT_ZKNH,
166};
167
168static const unsigned int riscv_zks_bundled_exts[] = {
169 RISCV_ISA_EXT_ZBKB,
170 RISCV_ISA_EXT_ZBKC,
171 RISCV_ISA_EXT_ZKSED,
172 RISCV_ISA_EXT_ZKSH
173};
174
175#define RISCV_ISA_EXT_ZVKN \
176 RISCV_ISA_EXT_ZVKNED, \
177 RISCV_ISA_EXT_ZVKNHB, \
178 RISCV_ISA_EXT_ZVKB, \
179 RISCV_ISA_EXT_ZVKT
180
181static const unsigned int riscv_zvkn_bundled_exts[] = {
182 RISCV_ISA_EXT_ZVKN
183};
184
185static const unsigned int riscv_zvknc_bundled_exts[] = {
186 RISCV_ISA_EXT_ZVKN,
187 RISCV_ISA_EXT_ZVBC
188};
189
190static const unsigned int riscv_zvkng_bundled_exts[] = {
191 RISCV_ISA_EXT_ZVKN,
192 RISCV_ISA_EXT_ZVKG
193};
194
195#define RISCV_ISA_EXT_ZVKS \
196 RISCV_ISA_EXT_ZVKSED, \
197 RISCV_ISA_EXT_ZVKSH, \
198 RISCV_ISA_EXT_ZVKB, \
199 RISCV_ISA_EXT_ZVKT
200
201static const unsigned int riscv_zvks_bundled_exts[] = {
202 RISCV_ISA_EXT_ZVKS
203};
204
205static const unsigned int riscv_zvksc_bundled_exts[] = {
206 RISCV_ISA_EXT_ZVKS,
207 RISCV_ISA_EXT_ZVBC
208};
209
210static const unsigned int riscv_zvksg_bundled_exts[] = {
211 RISCV_ISA_EXT_ZVKS,
212 RISCV_ISA_EXT_ZVKG
213};
214
215static const unsigned int riscv_zvbb_exts[] = {
216 RISCV_ISA_EXT_ZVKB
217};
218
219#define RISCV_ISA_EXT_ZVE64F_IMPLY_LIST \
220 RISCV_ISA_EXT_ZVE64X, \
221 RISCV_ISA_EXT_ZVE32F, \
222 RISCV_ISA_EXT_ZVE32X
223
224#define RISCV_ISA_EXT_ZVE64D_IMPLY_LIST \
225 RISCV_ISA_EXT_ZVE64F, \
226 RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
227
228#define RISCV_ISA_EXT_V_IMPLY_LIST \
229 RISCV_ISA_EXT_ZVE64D, \
230 RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
231
232static const unsigned int riscv_zve32f_exts[] = {
233 RISCV_ISA_EXT_ZVE32X
234};
235
236static const unsigned int riscv_zve64f_exts[] = {
237 RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
238};
239
240static const unsigned int riscv_zve64d_exts[] = {
241 RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
242};
243
244static const unsigned int riscv_v_exts[] = {
245 RISCV_ISA_EXT_V_IMPLY_LIST
246};
247
248static const unsigned int riscv_zve64x_exts[] = {
249 RISCV_ISA_EXT_ZVE32X,
250 RISCV_ISA_EXT_ZVE64X
251};
252
253/*
254 * While the [ms]envcfg CSRs were not defined until version 1.12 of the RISC-V
255 * privileged ISA, the existence of the CSRs is implied by any extension which
256 * specifies [ms]envcfg bit(s). Hence, we define a custom ISA extension for the
257 * existence of the CSR, and treat it as a subset of those other extensions.
258 */
259static const unsigned int riscv_xlinuxenvcfg_exts[] = {
260 RISCV_ISA_EXT_XLINUXENVCFG
261};
262
263/*
264 * Zc* spec states that:
265 * - C always implies Zca
266 * - C+F implies Zcf (RV32 only)
267 * - C+D implies Zcd
268 *
269 * These extensions will be enabled and then validated depending on the
270 * availability of F/D RV32.
271 */
272static const unsigned int riscv_c_exts[] = {
273 RISCV_ISA_EXT_ZCA,
274 RISCV_ISA_EXT_ZCF,
275 RISCV_ISA_EXT_ZCD,
276};
277
278/*
279 * The canonical order of ISA extension names in the ISA string is defined in
280 * chapter 27 of the unprivileged specification.
281 *
282 * Ordinarily, for in-kernel data structures, this order is unimportant but
283 * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo.
284 *
285 * The specification uses vague wording, such as should, when it comes to
286 * ordering, so for our purposes the following rules apply:
287 *
288 * 1. All multi-letter extensions must be separated from other extensions by an
289 * underscore.
290 *
291 * 2. Additional standard extensions (starting with 'Z') must be sorted after
292 * single-letter extensions and before any higher-privileged extensions.
293 *
294 * 3. The first letter following the 'Z' conventionally indicates the most
295 * closely related alphabetical extension category, IMAFDQLCBKJTPVH.
296 * If multiple 'Z' extensions are named, they must be ordered first by
297 * category, then alphabetically within a category.
298 *
299 * 3. Standard supervisor-level extensions (starting with 'S') must be listed
300 * after standard unprivileged extensions. If multiple supervisor-level
301 * extensions are listed, they must be ordered alphabetically.
302 *
303 * 4. Standard machine-level extensions (starting with 'Zxm') must be listed
304 * after any lower-privileged, standard extensions. If multiple
305 * machine-level extensions are listed, they must be ordered
306 * alphabetically.
307 *
308 * 5. Non-standard extensions (starting with 'X') must be listed after all
309 * standard extensions. If multiple non-standard extensions are listed, they
310 * must be ordered alphabetically.
311 *
312 * An example string following the order is:
313 * rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux
314 *
315 * New entries to this struct should follow the ordering rules described above.
316 */
317const struct riscv_isa_ext_data riscv_isa_ext[] = {
318 __RISCV_ISA_EXT_DATA(i, RISCV_ISA_EXT_i),
319 __RISCV_ISA_EXT_DATA(m, RISCV_ISA_EXT_m),
320 __RISCV_ISA_EXT_DATA(a, RISCV_ISA_EXT_a),
321 __RISCV_ISA_EXT_DATA(f, RISCV_ISA_EXT_f),
322 __RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d),
323 __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q),
324 __RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_c, riscv_c_exts),
325 __RISCV_ISA_EXT_SUPERSET(v, RISCV_ISA_EXT_v, riscv_v_exts),
326 __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),
327 __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts,
328 riscv_ext_zicbom_validate),
329 __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts,
330 riscv_ext_zicboz_validate),
331 __RISCV_ISA_EXT_DATA(ziccrse, RISCV_ISA_EXT_ZICCRSE),
332 __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR),
333 __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND),
334 __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR),
335 __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI),
336 __RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL),
337 __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
338 __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM),
339 __RISCV_ISA_EXT_DATA(zimop, RISCV_ISA_EXT_ZIMOP),
340 __RISCV_ISA_EXT_DATA(zabha, RISCV_ISA_EXT_ZABHA),
341 __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS),
342 __RISCV_ISA_EXT_DATA(zawrs, RISCV_ISA_EXT_ZAWRS),
343 __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA),
344 __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH),
345 __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN),
346 __RISCV_ISA_EXT_DATA(zca, RISCV_ISA_EXT_ZCA),
347 __RISCV_ISA_EXT_DATA_VALIDATE(zcb, RISCV_ISA_EXT_ZCB, riscv_ext_zca_depends),
348 __RISCV_ISA_EXT_DATA_VALIDATE(zcd, RISCV_ISA_EXT_ZCD, riscv_ext_zcd_validate),
349 __RISCV_ISA_EXT_DATA_VALIDATE(zcf, RISCV_ISA_EXT_ZCF, riscv_ext_zcf_validate),
350 __RISCV_ISA_EXT_DATA_VALIDATE(zcmop, RISCV_ISA_EXT_ZCMOP, riscv_ext_zca_depends),
351 __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
352 __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
353 __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC),
354 __RISCV_ISA_EXT_DATA(zbkb, RISCV_ISA_EXT_ZBKB),
355 __RISCV_ISA_EXT_DATA(zbkc, RISCV_ISA_EXT_ZBKC),
356 __RISCV_ISA_EXT_DATA(zbkx, RISCV_ISA_EXT_ZBKX),
357 __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),
358 __RISCV_ISA_EXT_BUNDLE(zk, riscv_zk_bundled_exts),
359 __RISCV_ISA_EXT_BUNDLE(zkn, riscv_zkn_bundled_exts),
360 __RISCV_ISA_EXT_DATA(zknd, RISCV_ISA_EXT_ZKND),
361 __RISCV_ISA_EXT_DATA(zkne, RISCV_ISA_EXT_ZKNE),
362 __RISCV_ISA_EXT_DATA(zknh, RISCV_ISA_EXT_ZKNH),
363 __RISCV_ISA_EXT_DATA(zkr, RISCV_ISA_EXT_ZKR),
364 __RISCV_ISA_EXT_BUNDLE(zks, riscv_zks_bundled_exts),
365 __RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT),
366 __RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED),
367 __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH),
368 __RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO),
369 __RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts),
370 __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),
371 __RISCV_ISA_EXT_SUPERSET(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve32f_exts),
372 __RISCV_ISA_EXT_DATA(zve32x, RISCV_ISA_EXT_ZVE32X),
373 __RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts),
374 __RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts),
375 __RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts),
376 __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH),
377 __RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN),
378 __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),
379 __RISCV_ISA_EXT_DATA(zvkg, RISCV_ISA_EXT_ZVKG),
380 __RISCV_ISA_EXT_BUNDLE(zvkn, riscv_zvkn_bundled_exts),
381 __RISCV_ISA_EXT_BUNDLE(zvknc, riscv_zvknc_bundled_exts),
382 __RISCV_ISA_EXT_DATA(zvkned, RISCV_ISA_EXT_ZVKNED),
383 __RISCV_ISA_EXT_BUNDLE(zvkng, riscv_zvkng_bundled_exts),
384 __RISCV_ISA_EXT_DATA(zvknha, RISCV_ISA_EXT_ZVKNHA),
385 __RISCV_ISA_EXT_DATA(zvknhb, RISCV_ISA_EXT_ZVKNHB),
386 __RISCV_ISA_EXT_BUNDLE(zvks, riscv_zvks_bundled_exts),
387 __RISCV_ISA_EXT_BUNDLE(zvksc, riscv_zvksc_bundled_exts),
388 __RISCV_ISA_EXT_DATA(zvksed, RISCV_ISA_EXT_ZVKSED),
389 __RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH),
390 __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts),
391 __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT),
392 __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
393 __RISCV_ISA_EXT_DATA(smmpm, RISCV_ISA_EXT_SMMPM),
394 __RISCV_ISA_EXT_SUPERSET(smnpm, RISCV_ISA_EXT_SMNPM, riscv_xlinuxenvcfg_exts),
395 __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN),
396 __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
397 __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
398 __RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_xlinuxenvcfg_exts),
399 __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
400 __RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE),
401 __RISCV_ISA_EXT_DATA_VALIDATE(svadu, RISCV_ISA_EXT_SVADU, riscv_ext_svadu_validate),
402 __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
403 __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
404 __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
405 __RISCV_ISA_EXT_DATA(svvptc, RISCV_ISA_EXT_SVVPTC),
406};
407
408const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext);
409
410static void riscv_isa_set_ext(const struct riscv_isa_ext_data *ext, unsigned long *bitmap)
411{
412 if (ext->id != RISCV_ISA_EXT_INVALID)
413 set_bit(ext->id, bitmap);
414
415 for (int i = 0; i < ext->subset_ext_size; i++) {
416 if (ext->subset_ext_ids[i] != RISCV_ISA_EXT_INVALID)
417 set_bit(ext->subset_ext_ids[i], bitmap);
418 }
419}
420
421static const struct riscv_isa_ext_data *riscv_get_isa_ext_data(unsigned int ext_id)
422{
423 for (int i = 0; i < riscv_isa_ext_count; i++) {
424 if (riscv_isa_ext[i].id == ext_id)
425 return &riscv_isa_ext[i];
426 }
427
428 return NULL;
429}
430
431/*
432 * "Resolve" a source ISA bitmap into one that matches kernel configuration as
433 * well as correct extension dependencies. Some extensions depends on specific
434 * kernel configuration to be usable (V needs CONFIG_RISCV_ISA_V for instance)
435 * and this function will actually validate all the extensions provided in
436 * source_isa into the resolved_isa based on extensions validate() callbacks.
437 */
438static void __init riscv_resolve_isa(unsigned long *source_isa,
439 unsigned long *resolved_isa, unsigned long *this_hwcap,
440 unsigned long *isa2hwcap)
441{
442 bool loop;
443 const struct riscv_isa_ext_data *ext;
444 DECLARE_BITMAP(prev_resolved_isa, RISCV_ISA_EXT_MAX);
445 int max_loop_count = riscv_isa_ext_count, ret;
446 unsigned int bit;
447
448 do {
449 loop = false;
450 if (max_loop_count-- < 0) {
451 pr_err("Failed to reach a stable ISA state\n");
452 return;
453 }
454 bitmap_copy(prev_resolved_isa, resolved_isa, RISCV_ISA_EXT_MAX);
455 for_each_set_bit(bit, source_isa, RISCV_ISA_EXT_MAX) {
456 ext = riscv_get_isa_ext_data(bit);
457
458 if (ext && ext->validate) {
459 ret = ext->validate(ext, resolved_isa);
460 if (ret == -EPROBE_DEFER) {
461 loop = true;
462 continue;
463 } else if (ret) {
464 /* Disable the extension entirely */
465 clear_bit(bit, source_isa);
466 continue;
467 }
468 }
469
470 set_bit(bit, resolved_isa);
471 /* No need to keep it in source isa now that it is enabled */
472 clear_bit(bit, source_isa);
473
474 /* Single letter extensions get set in hwcap */
475 if (bit < RISCV_ISA_EXT_BASE)
476 *this_hwcap |= isa2hwcap[bit];
477 }
478 } while (loop && !bitmap_equal(prev_resolved_isa, resolved_isa, RISCV_ISA_EXT_MAX));
479}
480
481static void __init match_isa_ext(const char *name, const char *name_end, unsigned long *bitmap)
482{
483 for (int i = 0; i < riscv_isa_ext_count; i++) {
484 const struct riscv_isa_ext_data *ext = &riscv_isa_ext[i];
485
486 if ((name_end - name == strlen(ext->name)) &&
487 !strncasecmp(name, ext->name, name_end - name)) {
488 riscv_isa_set_ext(ext, bitmap);
489 break;
490 }
491 }
492}
493
494static void __init riscv_parse_isa_string(const char *isa, unsigned long *bitmap)
495{
496 /*
497 * For all possible cpus, we have already validated in
498 * the boot process that they at least contain "rv" and
499 * whichever of "32"/"64" this kernel supports, and so this
500 * section can be skipped.
501 */
502 isa += 4;
503
504 while (*isa) {
505 const char *ext = isa++;
506 const char *ext_end = isa;
507 bool ext_err = false;
508
509 switch (*ext) {
510 case 'x':
511 case 'X':
512 if (acpi_disabled)
513 pr_warn_once("Vendor extensions are ignored in riscv,isa. Use riscv,isa-extensions instead.");
514 /*
515 * To skip an extension, we find its end.
516 * As multi-letter extensions must be split from other multi-letter
517 * extensions with an "_", the end of a multi-letter extension will
518 * either be the null character or the "_" at the start of the next
519 * multi-letter extension.
520 */
521 for (; *isa && *isa != '_'; ++isa)
522 ;
523 ext_err = true;
524 break;
525 case 's':
526 /*
527 * Workaround for invalid single-letter 's' & 'u' (QEMU).
528 * No need to set the bit in riscv_isa as 's' & 'u' are
529 * not valid ISA extensions. It works unless the first
530 * multi-letter extension in the ISA string begins with
531 * "Su" and is not prefixed with an underscore.
532 */
533 if (ext[-1] != '_' && ext[1] == 'u') {
534 ++isa;
535 ext_err = true;
536 break;
537 }
538 fallthrough;
539 case 'S':
540 case 'z':
541 case 'Z':
542 /*
543 * Before attempting to parse the extension itself, we find its end.
544 * As multi-letter extensions must be split from other multi-letter
545 * extensions with an "_", the end of a multi-letter extension will
546 * either be the null character or the "_" at the start of the next
547 * multi-letter extension.
548 *
549 * Next, as the extensions version is currently ignored, we
550 * eliminate that portion. This is done by parsing backwards from
551 * the end of the extension, removing any numbers. This may be a
552 * major or minor number however, so the process is repeated if a
553 * minor number was found.
554 *
555 * ext_end is intended to represent the first character *after* the
556 * name portion of an extension, but will be decremented to the last
557 * character itself while eliminating the extensions version number.
558 * A simple re-increment solves this problem.
559 */
560 for (; *isa && *isa != '_'; ++isa)
561 if (unlikely(!isalnum(*isa)))
562 ext_err = true;
563
564 ext_end = isa;
565 if (unlikely(ext_err))
566 break;
567
568 if (!isdigit(ext_end[-1]))
569 break;
570
571 while (isdigit(*--ext_end))
572 ;
573
574 if (tolower(ext_end[0]) != 'p' || !isdigit(ext_end[-1])) {
575 ++ext_end;
576 break;
577 }
578
579 while (isdigit(*--ext_end))
580 ;
581
582 ++ext_end;
583 break;
584 default:
585 /*
586 * Things are a little easier for single-letter extensions, as they
587 * are parsed forwards.
588 *
589 * After checking that our starting position is valid, we need to
590 * ensure that, when isa was incremented at the start of the loop,
591 * that it arrived at the start of the next extension.
592 *
593 * If we are already on a non-digit, there is nothing to do. Either
594 * we have a multi-letter extension's _, or the start of an
595 * extension.
596 *
597 * Otherwise we have found the current extension's major version
598 * number. Parse past it, and a subsequent p/minor version number
599 * if present. The `p` extension must not appear immediately after
600 * a number, so there is no fear of missing it.
601 *
602 */
603 if (unlikely(!isalpha(*ext))) {
604 ext_err = true;
605 break;
606 }
607
608 if (!isdigit(*isa))
609 break;
610
611 while (isdigit(*++isa))
612 ;
613
614 if (tolower(*isa) != 'p')
615 break;
616
617 if (!isdigit(*++isa)) {
618 --isa;
619 break;
620 }
621
622 while (isdigit(*++isa))
623 ;
624
625 break;
626 }
627
628 /*
629 * The parser expects that at the start of an iteration isa points to the
630 * first character of the next extension. As we stop parsing an extension
631 * on meeting a non-alphanumeric character, an extra increment is needed
632 * where the succeeding extension is a multi-letter prefixed with an "_".
633 */
634 if (*isa == '_')
635 ++isa;
636
637 if (unlikely(ext_err))
638 continue;
639
640 match_isa_ext(ext, ext_end, bitmap);
641 }
642}
643
644static void __init riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwcap)
645{
646 struct device_node *node;
647 const char *isa;
648 int rc;
649 struct acpi_table_header *rhct;
650 acpi_status status;
651 unsigned int cpu;
652 u64 boot_vendorid;
653 u64 boot_archid;
654
655 if (!acpi_disabled) {
656 status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct);
657 if (ACPI_FAILURE(status))
658 return;
659 }
660
661 boot_vendorid = riscv_get_mvendorid();
662 boot_archid = riscv_get_marchid();
663
664 for_each_possible_cpu(cpu) {
665 struct riscv_isainfo *isainfo = &hart_isa[cpu];
666 unsigned long this_hwcap = 0;
667 DECLARE_BITMAP(source_isa, RISCV_ISA_EXT_MAX) = { 0 };
668
669 if (acpi_disabled) {
670 node = of_cpu_device_node_get(cpu);
671 if (!node) {
672 pr_warn("Unable to find cpu node\n");
673 continue;
674 }
675
676 rc = of_property_read_string(node, "riscv,isa", &isa);
677 of_node_put(node);
678 if (rc) {
679 pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
680 continue;
681 }
682 } else {
683 rc = acpi_get_riscv_isa(rhct, cpu, &isa);
684 if (rc < 0) {
685 pr_warn("Unable to get ISA for the hart - %d\n", cpu);
686 continue;
687 }
688 }
689
690 riscv_parse_isa_string(isa, source_isa);
691
692 /*
693 * These ones were as they were part of the base ISA when the
694 * port & dt-bindings were upstreamed, and so can be set
695 * unconditionally where `i` is in riscv,isa on DT systems.
696 */
697 if (acpi_disabled) {
698 set_bit(RISCV_ISA_EXT_ZICSR, source_isa);
699 set_bit(RISCV_ISA_EXT_ZIFENCEI, source_isa);
700 set_bit(RISCV_ISA_EXT_ZICNTR, source_isa);
701 set_bit(RISCV_ISA_EXT_ZIHPM, source_isa);
702 }
703
704 /*
705 * "V" in ISA strings is ambiguous in practice: it should mean
706 * just the standard V-1.0 but vendors aren't well behaved.
707 * Many vendors with T-Head CPU cores which implement the 0.7.1
708 * version of the vector specification put "v" into their DTs.
709 * CPU cores with the ratified spec will contain non-zero
710 * marchid.
711 */
712 if (acpi_disabled && boot_vendorid == THEAD_VENDOR_ID && boot_archid == 0x0) {
713 this_hwcap &= ~isa2hwcap[RISCV_ISA_EXT_v];
714 clear_bit(RISCV_ISA_EXT_v, source_isa);
715 }
716
717 riscv_resolve_isa(source_isa, isainfo->isa, &this_hwcap, isa2hwcap);
718
719 /*
720 * All "okay" hart should have same isa. Set HWCAP based on
721 * common capabilities of every "okay" hart, in case they don't
722 * have.
723 */
724 if (elf_hwcap)
725 elf_hwcap &= this_hwcap;
726 else
727 elf_hwcap = this_hwcap;
728
729 if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
730 bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
731 else
732 bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
733 }
734
735 if (!acpi_disabled && rhct)
736 acpi_put_table((struct acpi_table_header *)rhct);
737}
738
739static void __init riscv_fill_cpu_vendor_ext(struct device_node *cpu_node, int cpu)
740{
741 if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT))
742 return;
743
744 for (int i = 0; i < riscv_isa_vendor_ext_list_size; i++) {
745 struct riscv_isa_vendor_ext_data_list *ext_list = riscv_isa_vendor_ext_list[i];
746
747 for (int j = 0; j < ext_list->ext_data_count; j++) {
748 const struct riscv_isa_ext_data ext = ext_list->ext_data[j];
749 struct riscv_isavendorinfo *isavendorinfo = &ext_list->per_hart_isa_bitmap[cpu];
750
751 if (of_property_match_string(cpu_node, "riscv,isa-extensions",
752 ext.property) < 0)
753 continue;
754
755 /*
756 * Assume that subset extensions are all members of the
757 * same vendor.
758 */
759 if (ext.subset_ext_size)
760 for (int k = 0; k < ext.subset_ext_size; k++)
761 set_bit(ext.subset_ext_ids[k], isavendorinfo->isa);
762
763 set_bit(ext.id, isavendorinfo->isa);
764 }
765 }
766}
767
768/*
769 * Populate all_harts_isa_bitmap for each vendor with all of the extensions that
770 * are shared across CPUs for that vendor.
771 */
772static void __init riscv_fill_vendor_ext_list(int cpu)
773{
774 if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT))
775 return;
776
777 for (int i = 0; i < riscv_isa_vendor_ext_list_size; i++) {
778 struct riscv_isa_vendor_ext_data_list *ext_list = riscv_isa_vendor_ext_list[i];
779
780 if (!ext_list->is_initialized) {
781 bitmap_copy(ext_list->all_harts_isa_bitmap.isa,
782 ext_list->per_hart_isa_bitmap[cpu].isa,
783 RISCV_ISA_VENDOR_EXT_MAX);
784 ext_list->is_initialized = true;
785 } else {
786 bitmap_and(ext_list->all_harts_isa_bitmap.isa,
787 ext_list->all_harts_isa_bitmap.isa,
788 ext_list->per_hart_isa_bitmap[cpu].isa,
789 RISCV_ISA_VENDOR_EXT_MAX);
790 }
791 }
792}
793
794static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap)
795{
796 unsigned int cpu;
797
798 for_each_possible_cpu(cpu) {
799 unsigned long this_hwcap = 0;
800 struct device_node *cpu_node;
801 struct riscv_isainfo *isainfo = &hart_isa[cpu];
802 DECLARE_BITMAP(source_isa, RISCV_ISA_EXT_MAX) = { 0 };
803
804 cpu_node = of_cpu_device_node_get(cpu);
805 if (!cpu_node) {
806 pr_warn("Unable to find cpu node\n");
807 continue;
808 }
809
810 if (!of_property_present(cpu_node, "riscv,isa-extensions")) {
811 of_node_put(cpu_node);
812 continue;
813 }
814
815 for (int i = 0; i < riscv_isa_ext_count; i++) {
816 const struct riscv_isa_ext_data *ext = &riscv_isa_ext[i];
817
818 if (of_property_match_string(cpu_node, "riscv,isa-extensions",
819 ext->property) < 0)
820 continue;
821
822 riscv_isa_set_ext(ext, source_isa);
823 }
824
825 riscv_resolve_isa(source_isa, isainfo->isa, &this_hwcap, isa2hwcap);
826 riscv_fill_cpu_vendor_ext(cpu_node, cpu);
827
828 of_node_put(cpu_node);
829
830 /*
831 * All "okay" harts should have same isa. Set HWCAP based on
832 * common capabilities of every "okay" hart, in case they don't.
833 */
834 if (elf_hwcap)
835 elf_hwcap &= this_hwcap;
836 else
837 elf_hwcap = this_hwcap;
838
839 if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
840 bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
841 else
842 bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
843
844 riscv_fill_vendor_ext_list(cpu);
845 }
846
847 if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
848 return -ENOENT;
849
850 return 0;
851}
852
853#ifdef CONFIG_RISCV_ISA_FALLBACK
854bool __initdata riscv_isa_fallback = true;
855#else
856bool __initdata riscv_isa_fallback;
857static int __init riscv_isa_fallback_setup(char *__unused)
858{
859 riscv_isa_fallback = true;
860 return 1;
861}
862early_param("riscv_isa_fallback", riscv_isa_fallback_setup);
863#endif
864
865void __init riscv_fill_hwcap(void)
866{
867 char print_str[NUM_ALPHA_EXTS + 1];
868 unsigned long isa2hwcap[26] = {0};
869 int i, j;
870
871 isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I;
872 isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M;
873 isa2hwcap['a' - 'a'] = COMPAT_HWCAP_ISA_A;
874 isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F;
875 isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D;
876 isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C;
877 isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V;
878
879 if (!acpi_disabled) {
880 riscv_fill_hwcap_from_isa_string(isa2hwcap);
881 } else {
882 int ret = riscv_fill_hwcap_from_ext_list(isa2hwcap);
883
884 if (ret && riscv_isa_fallback) {
885 pr_info("Falling back to deprecated \"riscv,isa\"\n");
886 riscv_fill_hwcap_from_isa_string(isa2hwcap);
887 }
888 }
889
890 /*
891 * We don't support systems with F but without D, so mask those out
892 * here.
893 */
894 if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) {
895 pr_info("This kernel does not support systems with F but not D\n");
896 elf_hwcap &= ~COMPAT_HWCAP_ISA_F;
897 }
898
899 if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_ZVE32X)) {
900 /*
901 * This cannot fail when called on the boot hart
902 */
903 riscv_v_setup_vsize();
904 }
905
906 if (elf_hwcap & COMPAT_HWCAP_ISA_V) {
907 /*
908 * ISA string in device tree might have 'v' flag, but
909 * CONFIG_RISCV_ISA_V is disabled in kernel.
910 * Clear V flag in elf_hwcap if CONFIG_RISCV_ISA_V is disabled.
911 */
912 if (!IS_ENABLED(CONFIG_RISCV_ISA_V))
913 elf_hwcap &= ~COMPAT_HWCAP_ISA_V;
914 }
915
916 memset(print_str, 0, sizeof(print_str));
917 for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
918 if (riscv_isa[0] & BIT_MASK(i))
919 print_str[j++] = (char)('a' + i);
920 pr_info("riscv: base ISA extensions %s\n", print_str);
921
922 memset(print_str, 0, sizeof(print_str));
923 for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
924 if (elf_hwcap & BIT_MASK(i))
925 print_str[j++] = (char)('a' + i);
926 pr_info("riscv: ELF capabilities %s\n", print_str);
927}
928
929unsigned long riscv_get_elf_hwcap(void)
930{
931 unsigned long hwcap;
932
933 hwcap = (elf_hwcap & ((1UL << RISCV_ISA_EXT_BASE) - 1));
934
935 if (!riscv_v_vstate_ctrl_user_allowed())
936 hwcap &= ~COMPAT_HWCAP_ISA_V;
937
938 return hwcap;
939}
940
941void __init riscv_user_isa_enable(void)
942{
943 if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICBOZ))
944 current->thread.envcfg |= ENVCFG_CBZE;
945 else if (any_cpu_has_zicboz)
946 pr_warn("Zicboz disabled as it is unavailable on some harts\n");
947}
948
949#ifdef CONFIG_RISCV_ALTERNATIVE
950/*
951 * Alternative patch sites consider 48 bits when determining when to patch
952 * the old instruction sequence with the new. These bits are broken into a
953 * 16-bit vendor ID and a 32-bit patch ID. A non-zero vendor ID means the
954 * patch site is for an erratum, identified by the 32-bit patch ID. When
955 * the vendor ID is zero, the patch site is for a cpufeature. cpufeatures
956 * further break down patch ID into two 16-bit numbers. The lower 16 bits
957 * are the cpufeature ID and the upper 16 bits are used for a value specific
958 * to the cpufeature and patch site. If the upper 16 bits are zero, then it
959 * implies no specific value is specified. cpufeatures that want to control
960 * patching on a per-site basis will provide non-zero values and implement
961 * checks here. The checks return true when patching should be done, and
962 * false otherwise.
963 */
964static bool riscv_cpufeature_patch_check(u16 id, u16 value)
965{
966 if (!value)
967 return true;
968
969 switch (id) {
970 case RISCV_ISA_EXT_ZICBOZ:
971 /*
972 * Zicboz alternative applications provide the maximum
973 * supported block size order, or zero when it doesn't
974 * matter. If the current block size exceeds the maximum,
975 * then the alternative cannot be applied.
976 */
977 return riscv_cboz_block_size <= (1U << value);
978 }
979
980 return false;
981}
982
983void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin,
984 struct alt_entry *end,
985 unsigned int stage)
986{
987 struct alt_entry *alt;
988 void *oldptr, *altptr;
989 u16 id, value, vendor;
990
991 if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
992 return;
993
994 for (alt = begin; alt < end; alt++) {
995 id = PATCH_ID_CPUFEATURE_ID(alt->patch_id);
996 vendor = PATCH_ID_CPUFEATURE_ID(alt->vendor_id);
997
998 /*
999 * Any alternative with a patch_id that is less than
1000 * RISCV_ISA_EXT_MAX is interpreted as a standard extension.
1001 *
1002 * Any alternative with patch_id that is greater than or equal
1003 * to RISCV_VENDOR_EXT_ALTERNATIVES_BASE is interpreted as a
1004 * vendor extension.
1005 */
1006 if (id < RISCV_ISA_EXT_MAX) {
1007 /*
1008 * This patch should be treated as errata so skip
1009 * processing here.
1010 */
1011 if (alt->vendor_id != 0)
1012 continue;
1013
1014 if (!__riscv_isa_extension_available(NULL, id))
1015 continue;
1016
1017 value = PATCH_ID_CPUFEATURE_VALUE(alt->patch_id);
1018 if (!riscv_cpufeature_patch_check(id, value))
1019 continue;
1020 } else if (id >= RISCV_VENDOR_EXT_ALTERNATIVES_BASE) {
1021 if (!__riscv_isa_vendor_extension_available(VENDOR_EXT_ALL_CPUS, vendor,
1022 id - RISCV_VENDOR_EXT_ALTERNATIVES_BASE))
1023 continue;
1024 } else {
1025 WARN(1, "This extension id:%d is not in ISA extension list", id);
1026 continue;
1027 }
1028
1029 oldptr = ALT_OLD_PTR(alt);
1030 altptr = ALT_ALT_PTR(alt);
1031
1032 mutex_lock(&text_mutex);
1033 patch_text_nosync(oldptr, altptr, alt->alt_len);
1034 riscv_alternative_fix_offsets(oldptr, alt->alt_len, oldptr - altptr);
1035 mutex_unlock(&text_mutex);
1036 }
1037}
1038#endif