Loading...
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * General MIPS MT support routines, usable in AP/SP and SMVP.
4 * Copyright (C) 2005 Mips Technologies, Inc
5 */
6
7#include <linux/device.h>
8#include <linux/kernel.h>
9#include <linux/sched.h>
10#include <linux/export.h>
11#include <linux/interrupt.h>
12#include <linux/security.h>
13
14#include <asm/cpu.h>
15#include <asm/processor.h>
16#include <linux/atomic.h>
17#include <asm/hardirq.h>
18#include <asm/mmu_context.h>
19#include <asm/mipsmtregs.h>
20#include <asm/r4kcache.h>
21#include <asm/cacheflush.h>
22
23int vpelimit;
24
25static int __init maxvpes(char *str)
26{
27 get_option(&str, &vpelimit);
28
29 return 1;
30}
31
32__setup("maxvpes=", maxvpes);
33
34int tclimit;
35
36static int __init maxtcs(char *str)
37{
38 get_option(&str, &tclimit);
39
40 return 1;
41}
42
43__setup("maxtcs=", maxtcs);
44
45/*
46 * Dump new MIPS MT state for the core. Does not leave TCs halted.
47 * Takes an argument which taken to be a pre-call MVPControl value.
48 */
49
50void mips_mt_regdump(unsigned long mvpctl)
51{
52 unsigned long flags;
53 unsigned long vpflags;
54 unsigned long mvpconf0;
55 int nvpe;
56 int ntc;
57 int i;
58 int tc;
59 unsigned long haltval;
60 unsigned long tcstatval;
61
62 local_irq_save(flags);
63 vpflags = dvpe();
64 printk("=== MIPS MT State Dump ===\n");
65 printk("-- Global State --\n");
66 printk(" MVPControl Passed: %08lx\n", mvpctl);
67 printk(" MVPControl Read: %08lx\n", vpflags);
68 printk(" MVPConf0 : %08lx\n", (mvpconf0 = read_c0_mvpconf0()));
69 nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
70 ntc = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
71 printk("-- per-VPE State --\n");
72 for (i = 0; i < nvpe; i++) {
73 for (tc = 0; tc < ntc; tc++) {
74 settc(tc);
75 if ((read_tc_c0_tcbind() & TCBIND_CURVPE) == i) {
76 printk(" VPE %d\n", i);
77 printk(" VPEControl : %08lx\n",
78 read_vpe_c0_vpecontrol());
79 printk(" VPEConf0 : %08lx\n",
80 read_vpe_c0_vpeconf0());
81 printk(" VPE%d.Status : %08lx\n",
82 i, read_vpe_c0_status());
83 printk(" VPE%d.EPC : %08lx %pS\n",
84 i, read_vpe_c0_epc(),
85 (void *) read_vpe_c0_epc());
86 printk(" VPE%d.Cause : %08lx\n",
87 i, read_vpe_c0_cause());
88 printk(" VPE%d.Config7 : %08lx\n",
89 i, read_vpe_c0_config7());
90 break; /* Next VPE */
91 }
92 }
93 }
94 printk("-- per-TC State --\n");
95 for (tc = 0; tc < ntc; tc++) {
96 settc(tc);
97 if (read_tc_c0_tcbind() == read_c0_tcbind()) {
98 /* Are we dumping ourself? */
99 haltval = 0; /* Then we're not halted, and mustn't be */
100 tcstatval = flags; /* And pre-dump TCStatus is flags */
101 printk(" TC %d (current TC with VPE EPC above)\n", tc);
102 } else {
103 haltval = read_tc_c0_tchalt();
104 write_tc_c0_tchalt(1);
105 tcstatval = read_tc_c0_tcstatus();
106 printk(" TC %d\n", tc);
107 }
108 printk(" TCStatus : %08lx\n", tcstatval);
109 printk(" TCBind : %08lx\n", read_tc_c0_tcbind());
110 printk(" TCRestart : %08lx %pS\n",
111 read_tc_c0_tcrestart(), (void *) read_tc_c0_tcrestart());
112 printk(" TCHalt : %08lx\n", haltval);
113 printk(" TCContext : %08lx\n", read_tc_c0_tccontext());
114 if (!haltval)
115 write_tc_c0_tchalt(0);
116 }
117 printk("===========================\n");
118 evpe(vpflags);
119 local_irq_restore(flags);
120}
121
122static int mt_opt_norps;
123static int mt_opt_rpsctl = -1;
124static int mt_opt_nblsu = -1;
125static int mt_opt_forceconfig7;
126static int mt_opt_config7 = -1;
127
128static int __init rps_disable(char *s)
129{
130 mt_opt_norps = 1;
131 return 1;
132}
133__setup("norps", rps_disable);
134
135static int __init rpsctl_set(char *str)
136{
137 get_option(&str, &mt_opt_rpsctl);
138 return 1;
139}
140__setup("rpsctl=", rpsctl_set);
141
142static int __init nblsu_set(char *str)
143{
144 get_option(&str, &mt_opt_nblsu);
145 return 1;
146}
147__setup("nblsu=", nblsu_set);
148
149static int __init config7_set(char *str)
150{
151 get_option(&str, &mt_opt_config7);
152 mt_opt_forceconfig7 = 1;
153 return 1;
154}
155__setup("config7=", config7_set);
156
157/* Experimental cache flush control parameters that should go away some day */
158int mt_protiflush;
159int mt_protdflush;
160int mt_n_iflushes = 1;
161int mt_n_dflushes = 1;
162
163static int __init set_protiflush(char *s)
164{
165 mt_protiflush = 1;
166 return 1;
167}
168__setup("protiflush", set_protiflush);
169
170static int __init set_protdflush(char *s)
171{
172 mt_protdflush = 1;
173 return 1;
174}
175__setup("protdflush", set_protdflush);
176
177static int __init niflush(char *s)
178{
179 get_option(&s, &mt_n_iflushes);
180 return 1;
181}
182__setup("niflush=", niflush);
183
184static int __init ndflush(char *s)
185{
186 get_option(&s, &mt_n_dflushes);
187 return 1;
188}
189__setup("ndflush=", ndflush);
190
191static unsigned int itc_base;
192
193static int __init set_itc_base(char *str)
194{
195 get_option(&str, &itc_base);
196 return 1;
197}
198
199__setup("itcbase=", set_itc_base);
200
201void mips_mt_set_cpuoptions(void)
202{
203 unsigned int oconfig7 = read_c0_config7();
204 unsigned int nconfig7 = oconfig7;
205
206 if (mt_opt_norps) {
207 printk("\"norps\" option deprecated: use \"rpsctl=\"\n");
208 }
209 if (mt_opt_rpsctl >= 0) {
210 printk("34K return prediction stack override set to %d.\n",
211 mt_opt_rpsctl);
212 if (mt_opt_rpsctl)
213 nconfig7 |= (1 << 2);
214 else
215 nconfig7 &= ~(1 << 2);
216 }
217 if (mt_opt_nblsu >= 0) {
218 printk("34K ALU/LSU sync override set to %d.\n", mt_opt_nblsu);
219 if (mt_opt_nblsu)
220 nconfig7 |= (1 << 5);
221 else
222 nconfig7 &= ~(1 << 5);
223 }
224 if (mt_opt_forceconfig7) {
225 printk("CP0.Config7 forced to 0x%08x.\n", mt_opt_config7);
226 nconfig7 = mt_opt_config7;
227 }
228 if (oconfig7 != nconfig7) {
229 __asm__ __volatile("sync");
230 write_c0_config7(nconfig7);
231 ehb();
232 printk("Config7: 0x%08x\n", read_c0_config7());
233 }
234
235 /* Report Cache management debug options */
236 if (mt_protiflush)
237 printk("I-cache flushes single-threaded\n");
238 if (mt_protdflush)
239 printk("D-cache flushes single-threaded\n");
240 if (mt_n_iflushes != 1)
241 printk("I-Cache Flushes Repeated %d times\n", mt_n_iflushes);
242 if (mt_n_dflushes != 1)
243 printk("D-Cache Flushes Repeated %d times\n", mt_n_dflushes);
244
245 if (itc_base != 0) {
246 /*
247 * Configure ITC mapping. This code is very
248 * specific to the 34K core family, which uses
249 * a special mode bit ("ITC") in the ErrCtl
250 * register to enable access to ITC control
251 * registers via cache "tag" operations.
252 */
253 unsigned long ectlval;
254 unsigned long itcblkgrn;
255
256 /* ErrCtl register is known as "ecc" to Linux */
257 ectlval = read_c0_ecc();
258 write_c0_ecc(ectlval | (0x1 << 26));
259 ehb();
260#define INDEX_0 (0x80000000)
261#define INDEX_8 (0x80000008)
262 /* Read "cache tag" for Dcache pseudo-index 8 */
263 cache_op(Index_Load_Tag_D, INDEX_8);
264 ehb();
265 itcblkgrn = read_c0_dtaglo();
266 itcblkgrn &= 0xfffe0000;
267 /* Set for 128 byte pitch of ITC cells */
268 itcblkgrn |= 0x00000c00;
269 /* Stage in Tag register */
270 write_c0_dtaglo(itcblkgrn);
271 ehb();
272 /* Write out to ITU with CACHE op */
273 cache_op(Index_Store_Tag_D, INDEX_8);
274 /* Now set base address, and turn ITC on with 0x1 bit */
275 write_c0_dtaglo((itc_base & 0xfffffc00) | 0x1 );
276 ehb();
277 /* Write out to ITU with CACHE op */
278 cache_op(Index_Store_Tag_D, INDEX_0);
279 write_c0_ecc(ectlval);
280 ehb();
281 printk("Mapped %ld ITC cells starting at 0x%08x\n",
282 ((itcblkgrn & 0x7fe00000) >> 20), itc_base);
283 }
284}
285
286/*
287 * Function to protect cache flushes from concurrent execution
288 * depends on MP software model chosen.
289 */
290
291void mt_cflush_lockdown(void)
292{
293 /* FILL IN VSMP and AP/SP VERSIONS HERE */
294}
295
296void mt_cflush_release(void)
297{
298 /* FILL IN VSMP and AP/SP VERSIONS HERE */
299}
300
301struct class *mt_class;
302
303static int __init mt_init(void)
304{
305 struct class *mtc;
306
307 mtc = class_create(THIS_MODULE, "mt");
308 if (IS_ERR(mtc))
309 return PTR_ERR(mtc);
310
311 mt_class = mtc;
312
313 return 0;
314}
315
316subsys_initcall(mt_init);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * General MIPS MT support routines, usable in AP/SP and SMVP.
4 * Copyright (C) 2005 Mips Technologies, Inc
5 */
6
7#include <linux/device.h>
8#include <linux/kernel.h>
9#include <linux/sched.h>
10#include <linux/export.h>
11#include <linux/interrupt.h>
12#include <linux/security.h>
13
14#include <asm/cpu.h>
15#include <asm/processor.h>
16#include <linux/atomic.h>
17#include <asm/hardirq.h>
18#include <asm/mmu_context.h>
19#include <asm/mipsmtregs.h>
20#include <asm/r4kcache.h>
21#include <asm/cacheflush.h>
22#include <asm/mips_mt.h>
23
24int vpelimit;
25
26static int __init maxvpes(char *str)
27{
28 get_option(&str, &vpelimit);
29
30 return 1;
31}
32
33__setup("maxvpes=", maxvpes);
34
35int tclimit;
36
37static int __init maxtcs(char *str)
38{
39 get_option(&str, &tclimit);
40
41 return 1;
42}
43
44__setup("maxtcs=", maxtcs);
45
46static int mt_opt_rpsctl = -1;
47static int mt_opt_nblsu = -1;
48static int mt_opt_forceconfig7;
49static int mt_opt_config7 = -1;
50
51static int __init rpsctl_set(char *str)
52{
53 get_option(&str, &mt_opt_rpsctl);
54 return 1;
55}
56__setup("rpsctl=", rpsctl_set);
57
58static int __init nblsu_set(char *str)
59{
60 get_option(&str, &mt_opt_nblsu);
61 return 1;
62}
63__setup("nblsu=", nblsu_set);
64
65static int __init config7_set(char *str)
66{
67 get_option(&str, &mt_opt_config7);
68 mt_opt_forceconfig7 = 1;
69 return 1;
70}
71__setup("config7=", config7_set);
72
73static unsigned int itc_base;
74
75static int __init set_itc_base(char *str)
76{
77 get_option(&str, &itc_base);
78 return 1;
79}
80
81__setup("itcbase=", set_itc_base);
82
83void mips_mt_set_cpuoptions(void)
84{
85 unsigned int oconfig7 = read_c0_config7();
86 unsigned int nconfig7 = oconfig7;
87
88 if (mt_opt_rpsctl >= 0) {
89 printk("34K return prediction stack override set to %d.\n",
90 mt_opt_rpsctl);
91 if (mt_opt_rpsctl)
92 nconfig7 |= (1 << 2);
93 else
94 nconfig7 &= ~(1 << 2);
95 }
96 if (mt_opt_nblsu >= 0) {
97 printk("34K ALU/LSU sync override set to %d.\n", mt_opt_nblsu);
98 if (mt_opt_nblsu)
99 nconfig7 |= (1 << 5);
100 else
101 nconfig7 &= ~(1 << 5);
102 }
103 if (mt_opt_forceconfig7) {
104 printk("CP0.Config7 forced to 0x%08x.\n", mt_opt_config7);
105 nconfig7 = mt_opt_config7;
106 }
107 if (oconfig7 != nconfig7) {
108 __asm__ __volatile("sync");
109 write_c0_config7(nconfig7);
110 ehb();
111 printk("Config7: 0x%08x\n", read_c0_config7());
112 }
113
114 if (itc_base != 0) {
115 /*
116 * Configure ITC mapping. This code is very
117 * specific to the 34K core family, which uses
118 * a special mode bit ("ITC") in the ErrCtl
119 * register to enable access to ITC control
120 * registers via cache "tag" operations.
121 */
122 unsigned long ectlval;
123 unsigned long itcblkgrn;
124
125 /* ErrCtl register is known as "ecc" to Linux */
126 ectlval = read_c0_ecc();
127 write_c0_ecc(ectlval | (0x1 << 26));
128 ehb();
129#define INDEX_0 (0x80000000)
130#define INDEX_8 (0x80000008)
131 /* Read "cache tag" for Dcache pseudo-index 8 */
132 cache_op(Index_Load_Tag_D, INDEX_8);
133 ehb();
134 itcblkgrn = read_c0_dtaglo();
135 itcblkgrn &= 0xfffe0000;
136 /* Set for 128 byte pitch of ITC cells */
137 itcblkgrn |= 0x00000c00;
138 /* Stage in Tag register */
139 write_c0_dtaglo(itcblkgrn);
140 ehb();
141 /* Write out to ITU with CACHE op */
142 cache_op(Index_Store_Tag_D, INDEX_8);
143 /* Now set base address, and turn ITC on with 0x1 bit */
144 write_c0_dtaglo((itc_base & 0xfffffc00) | 0x1 );
145 ehb();
146 /* Write out to ITU with CACHE op */
147 cache_op(Index_Store_Tag_D, INDEX_0);
148 write_c0_ecc(ectlval);
149 ehb();
150 printk("Mapped %ld ITC cells starting at 0x%08x\n",
151 ((itcblkgrn & 0x7fe00000) >> 20), itc_base);
152 }
153}
154
155const struct class mt_class = {
156 .name = "mt",
157};
158
159static int __init mips_mt_init(void)
160{
161 return class_register(&mt_class);
162}
163
164subsys_initcall(mips_mt_init);