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1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2021 NXP
4 */
5
6/dts-v1/;
7
8#include "imx8ulp.dtsi"
9
10/ {
11 model = "NXP i.MX8ULP EVK";
12 compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";
13
14 bt_sco_codec: bt-sco-codec {
15 #sound-dai-cells = <1>;
16 compatible = "linux,bt-sco";
17 };
18
19 chosen {
20 stdout-path = &lpuart5;
21 };
22
23 memory@80000000 {
24 device_type = "memory";
25 reg = <0x0 0x80000000 0 0x80000000>;
26 };
27
28 reserved-memory {
29 #address-cells = <2>;
30 #size-cells = <2>;
31 ranges;
32
33 linux,cma {
34 compatible = "shared-dma-pool";
35 reusable;
36 size = <0 0x28000000>;
37 linux,cma-default;
38 };
39
40 m33_reserved: noncacheable-section@a8600000 {
41 reg = <0 0xa8600000 0 0x1000000>;
42 no-map;
43 };
44
45 rsc_table: rsc-table@1fff8000 {
46 reg = <0 0x1fff8000 0 0x1000>;
47 no-map;
48 };
49
50 vdev0vring0: vdev0vring0@aff00000 {
51 reg = <0 0xaff00000 0 0x8000>;
52 no-map;
53 };
54
55 vdev0vring1: vdev0vring1@aff08000 {
56 reg = <0 0xaff08000 0 0x8000>;
57 no-map;
58 };
59
60 vdev1vring0: vdev1vring0@aff10000 {
61 reg = <0 0xaff10000 0 0x8000>;
62 no-map;
63 };
64
65 vdev1vring1: vdev1vring1@aff18000 {
66 reg = <0 0xaff18000 0 0x8000>;
67 no-map;
68 };
69
70 vdevbuffer: vdevbuffer@a8400000 {
71 compatible = "shared-dma-pool";
72 reg = <0 0xa8400000 0 0x100000>;
73 no-map;
74 };
75 };
76
77 clock_ext_rmii: clock-ext-rmii {
78 compatible = "fixed-clock";
79 clock-frequency = <50000000>;
80 clock-output-names = "ext_rmii_clk";
81 #clock-cells = <0>;
82 };
83
84 clock_ext_ts: clock-ext-ts {
85 compatible = "fixed-clock";
86 /* External ts clock is 50MHZ from PHY on EVK board. */
87 clock-frequency = <50000000>;
88 clock-output-names = "ext_ts_clk";
89 #clock-cells = <0>;
90 };
91
92 sound-bt-sco {
93 compatible = "simple-audio-card";
94 simple-audio-card,name = "bt-sco-audio";
95 simple-audio-card,format = "dsp_a";
96 simple-audio-card,bitclock-inversion;
97 simple-audio-card,frame-master = <&btcpu>;
98 simple-audio-card,bitclock-master = <&btcpu>;
99
100 btcpu: simple-audio-card,cpu {
101 sound-dai = <&sai5>;
102 dai-tdm-slot-num = <2>;
103 dai-tdm-slot-width = <16>;
104 };
105
106 simple-audio-card,codec {
107 sound-dai = <&bt_sco_codec 1>;
108 };
109 };
110
111 sound-spdif {
112 compatible = "fsl,imx-audio-spdif";
113 model = "imx-spdif";
114 audio-cpu = <&spdif>;
115 audio-codec = <&spdif_out>;
116 };
117
118 spdif_out: spdif-out {
119 compatible = "linux,spdif-dit";
120 #sound-dai-cells = <0>;
121 };
122};
123
124&cm33 {
125 mbox-names = "tx", "rx", "rxdb";
126 mboxes = <&mu 0 1>,
127 <&mu 1 1>,
128 <&mu 3 1>;
129 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
130 <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
131 status = "okay";
132};
133
134&flexspi2 {
135 pinctrl-names = "default", "sleep";
136 pinctrl-0 = <&pinctrl_flexspi2_ptd>;
137 pinctrl-1 = <&pinctrl_flexspi2_ptd>;
138 status = "okay";
139
140 mx25uw51345gxdi00: flash@0 {
141 compatible = "jedec,spi-nor";
142 reg = <0>;
143 spi-max-frequency = <200000000>;
144 spi-tx-bus-width = <8>;
145 spi-rx-bus-width = <8>;
146 };
147};
148
149&lpuart5 {
150 /* console */
151 pinctrl-names = "default", "sleep";
152 pinctrl-0 = <&pinctrl_lpuart5>;
153 pinctrl-1 = <&pinctrl_lpuart5>;
154 status = "okay";
155};
156
157&lpi2c7 {
158 #address-cells = <1>;
159 #size-cells = <0>;
160 clock-frequency = <400000>;
161 pinctrl-names = "default", "sleep";
162 pinctrl-0 = <&pinctrl_lpi2c7>;
163 pinctrl-1 = <&pinctrl_lpi2c7>;
164 status = "okay";
165
166 ptn5150_1: typec@1d {
167 compatible = "nxp,ptn5150";
168 reg = <0x1d>;
169 int-gpios = <&gpiof 3 IRQ_TYPE_EDGE_FALLING>;
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_typec1>;
172 status = "disabled";
173 };
174
175 pcal6408: gpio@21 {
176 compatible = "nxp,pcal9554b";
177 reg = <0x21>;
178 gpio-controller;
179 #gpio-cells = <2>;
180 };
181
182 ptn5150_2: typec@3d {
183 compatible = "nxp,ptn5150";
184 reg = <0x3d>;
185 int-gpios = <&gpiof 5 IRQ_TYPE_EDGE_FALLING>;
186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_typec2>;
188 status = "disabled";
189 };
190};
191
192&sai5 {
193 pinctrl-names = "default", "sleep";
194 pinctrl-0 = <&pinctrl_sai5>;
195 pinctrl-1 = <&pinctrl_sai5>;
196 assigned-clocks = <&cgc1 IMX8ULP_CLK_SAI5_SEL>;
197 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>;
198 fsl,dataline = <1 0x08 0x01>;
199 status = "okay";
200};
201
202&spdif {
203 pinctrl-names = "default", "sleep";
204 pinctrl-0 = <&pinctrl_spdif>;
205 pinctrl-1 = <&pinctrl_spdif>;
206 assigned-clocks = <&cgc2 IMX8ULP_CLK_SPDIF_SEL>;
207 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>;
208 status = "okay";
209};
210
211&usbotg1 {
212 pinctrl-names = "default";
213 pinctrl-0 = <&pinctrl_usb1>;
214 dr_mode = "otg";
215 hnp-disable;
216 srp-disable;
217 adp-disable;
218 over-current-active-low;
219 status = "okay";
220};
221
222&usbphy1 {
223 fsl,tx-d-cal = <110>;
224 status = "okay";
225};
226
227&usbmisc1 {
228 status = "okay";
229};
230
231&usbotg2 {
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_usb2>;
234 dr_mode = "otg";
235 hnp-disable;
236 srp-disable;
237 adp-disable;
238 over-current-active-low;
239 status = "okay";
240};
241
242&usbphy2 {
243 fsl,tx-d-cal = <110>;
244 status = "okay";
245};
246
247&usbmisc2 {
248 status = "okay";
249};
250
251&usdhc0 {
252 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
253 pinctrl-0 = <&pinctrl_usdhc0>;
254 pinctrl-1 = <&pinctrl_usdhc0>;
255 pinctrl-2 = <&pinctrl_usdhc0>;
256 pinctrl-3 = <&pinctrl_usdhc0>;
257 non-removable;
258 bus-width = <8>;
259 status = "okay";
260};
261
262&fec {
263 pinctrl-names = "default", "sleep";
264 pinctrl-0 = <&pinctrl_enet>;
265 pinctrl-1 = <&pinctrl_enet>;
266 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
267 <&pcc4 IMX8ULP_CLK_ENET>,
268 <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>,
269 <&clock_ext_rmii>;
270 clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
271 assigned-clocks = <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>;
272 assigned-clock-parents = <&clock_ext_ts>;
273 phy-mode = "rmii";
274 phy-handle = <ðphy>;
275 status = "okay";
276
277 mdio {
278 #address-cells = <1>;
279 #size-cells = <0>;
280
281 ethphy: ethernet-phy@1 {
282 reg = <1>;
283 micrel,led-mode = <1>;
284 };
285 };
286};
287
288&mu {
289 status = "okay";
290};
291
292&iomuxc1 {
293 pinctrl_enet: enetgrp {
294 fsl,pins = <
295 MX8ULP_PAD_PTE15__ENET0_MDC 0x43
296 MX8ULP_PAD_PTE14__ENET0_MDIO 0x43
297 MX8ULP_PAD_PTE17__ENET0_RXER 0x43
298 MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43
299 MX8ULP_PAD_PTF1__ENET0_RXD0 0x43
300 MX8ULP_PAD_PTE20__ENET0_RXD1 0x43
301 MX8ULP_PAD_PTE16__ENET0_TXEN 0x43
302 MX8ULP_PAD_PTE23__ENET0_TXD0 0x43
303 MX8ULP_PAD_PTE22__ENET0_TXD1 0x43
304 MX8ULP_PAD_PTE19__ENET0_REFCLK 0x43
305 MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
306 >;
307 };
308
309 pinctrl_flexspi2_ptd: flexspi2ptdgrp {
310 fsl,pins = <
311
312 MX8ULP_PAD_PTD12__FLEXSPI2_A_SS0_B 0x42
313 MX8ULP_PAD_PTD13__FLEXSPI2_A_SCLK 0x42
314 MX8ULP_PAD_PTD14__FLEXSPI2_A_DATA3 0x42
315 MX8ULP_PAD_PTD15__FLEXSPI2_A_DATA2 0x42
316 MX8ULP_PAD_PTD16__FLEXSPI2_A_DATA1 0x42
317 MX8ULP_PAD_PTD17__FLEXSPI2_A_DATA0 0x42
318 MX8ULP_PAD_PTD18__FLEXSPI2_A_DQS 0x42
319 MX8ULP_PAD_PTD19__FLEXSPI2_A_DATA7 0x42
320 MX8ULP_PAD_PTD20__FLEXSPI2_A_DATA6 0x42
321 MX8ULP_PAD_PTD21__FLEXSPI2_A_DATA5 0x42
322 MX8ULP_PAD_PTD22__FLEXSPI2_A_DATA4 0x42
323 >;
324 };
325
326 pinctrl_lpuart5: lpuart5grp {
327 fsl,pins = <
328 MX8ULP_PAD_PTF14__LPUART5_TX 0x3
329 MX8ULP_PAD_PTF15__LPUART5_RX 0x3
330 >;
331 };
332
333 pinctrl_lpi2c7: lpi2c7grp {
334 fsl,pins = <
335 MX8ULP_PAD_PTE12__LPI2C7_SCL 0x20
336 MX8ULP_PAD_PTE13__LPI2C7_SDA 0x20
337 >;
338 };
339
340 pinctrl_sai5: sai5grp {
341 fsl,pins = <
342 MX8ULP_PAD_PTF26__I2S5_TX_BCLK 0x43
343 MX8ULP_PAD_PTF27__I2S5_TX_FS 0x43
344 MX8ULP_PAD_PTF28__I2S5_TXD0 0x43
345 MX8ULP_PAD_PTF24__I2S5_RXD3 0x43
346 >;
347 };
348
349 pinctrl_spdif: spdifgrp {
350 fsl,pins = <
351 MX8ULP_PAD_PTF25__SPDIF_OUT1 0x43
352 >;
353 };
354
355 pinctrl_typec1: typec1grp {
356 fsl,pins = <
357 MX8ULP_PAD_PTF3__PTF3 0x3
358 >;
359 };
360
361 pinctrl_typec2: typec2grp {
362 fsl,pins = <
363 MX8ULP_PAD_PTF5__PTF5 0x3
364 >;
365 };
366
367 pinctrl_usb1: usb1grp {
368 fsl,pins = <
369 MX8ULP_PAD_PTF2__USB0_ID 0x10003
370 MX8ULP_PAD_PTF4__USB0_OC 0x10003
371 >;
372 };
373
374 pinctrl_usb2: usb2grp {
375 fsl,pins = <
376 MX8ULP_PAD_PTD23__USB1_ID 0x10003
377 MX8ULP_PAD_PTF6__USB1_OC 0x10003
378 >;
379 };
380
381 pinctrl_usdhc0: usdhc0grp {
382 fsl,pins = <
383 MX8ULP_PAD_PTD1__SDHC0_CMD 0x3
384 MX8ULP_PAD_PTD2__SDHC0_CLK 0x10002
385 MX8ULP_PAD_PTD10__SDHC0_D0 0x3
386 MX8ULP_PAD_PTD9__SDHC0_D1 0x3
387 MX8ULP_PAD_PTD8__SDHC0_D2 0x3
388 MX8ULP_PAD_PTD7__SDHC0_D3 0x3
389 MX8ULP_PAD_PTD6__SDHC0_D4 0x3
390 MX8ULP_PAD_PTD5__SDHC0_D5 0x3
391 MX8ULP_PAD_PTD4__SDHC0_D6 0x3
392 MX8ULP_PAD_PTD3__SDHC0_D7 0x3
393 MX8ULP_PAD_PTD11__SDHC0_DQS 0x10002
394 >;
395 };
396};