1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 2/*
 3 * Copyright (C) 2021 PHYTEC Messtechnik GmbH
 4 * Author: Jens Lang <j.lang@phytec.de>
 5 *
 6 * Tauri-L 2 x RS232:
 7 *  - GPIO3_20 uart4_rs485_en needs to be driven low (inactive)
 8 */
 9
10#include <dt-bindings/clock/imx8mm-clock.h>
11#include <dt-bindings/gpio/gpio.h>
12#include "imx8mm-pinfunc.h"
13
14/dts-v1/;
15/plugin/;
16
17&gpio3 {
18	pinctrl-names = "default";
19	pinctrl-0 = <&pinctrl_gpio3_hog>;
20
21	uart4-rs485-en-hog {
22		gpio-hog;
23		gpios = <20 GPIO_ACTIVE_HIGH>;
24		output-low;
25		line-name = "uart4_rs485_en";
26	};
27};
28
29/* UART2 - RS232  */
30&uart2 {
31	pinctrl-names = "default";
32	pinctrl-0 = <&pinctrl_uart2>;
33	assigned-clocks = <&clk IMX8MM_CLK_UART2>;
34	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
35	status = "okay";
36};
37
38/* UART4 - RS232  */
39&uart4 {
40	pinctrl-names = "default";
41	pinctrl-0 = <&pinctrl_uart4>;
42	assigned-clocks = <&clk IMX8MM_CLK_UART4>;
43	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
44	status = "okay";
45};
46
47&iomuxc {
48	pinctrl_gpio3_hog: gpio3hoggrp {
49		fsl,pins = <
50			MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20	0x49
51		>;
52	};
53
54	pinctrl_uart2: uart2grp {
55		fsl,pins = <
56			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x00
57			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x00
58		>;
59	};
60
61	pinctrl_uart4: uart4grp {
62		fsl,pins = <
63			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX	0x49
64			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX	0x49
65		>;
66	};
67};