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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019~2020, 2022 NXP
4 */
5
6/dts-v1/;
7
8#include "imx8dxl.dtsi"
9
10/ {
11 model = "Freescale i.MX8DXL EVK";
12 compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl";
13
14 aliases {
15 i2c2 = &i2c2;
16 mmc0 = &usdhc1;
17 mmc1 = &usdhc2;
18 serial0 = &lpuart0;
19 serial1 = &lpuart1;
20 serial6 = &cm40_lpuart;
21 };
22
23 chosen {
24 stdout-path = &lpuart0;
25 };
26
27 imx8dxl-cm4 {
28 compatible = "fsl,imx8qxp-cm4";
29 clocks = <&clk_dummy>;
30 mbox-names = "tx", "rx", "rxdb";
31 mboxes = <&lsio_mu5 0 1 &lsio_mu5 1 1 &lsio_mu5 3 1>;
32 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
33 <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
34 power-domains = <&pd IMX_SC_R_M4_0_PID0>, <&pd IMX_SC_R_M4_0_MU_1A>;
35 fsl,resource-id = <IMX_SC_R_M4_0_PID0>;
36 fsl,entry-address = <0x34fe0000>;
37 };
38
39
40 memory@80000000 {
41 device_type = "memory";
42 reg = <0x00000000 0x80000000 0 0x40000000>;
43 };
44
45 reserved-memory {
46 #address-cells = <2>;
47 #size-cells = <2>;
48 ranges;
49
50 /*
51 * Memory reserved for optee usage. Please do not use.
52 * This will be automatically added to dtb if OP-TEE is installed.
53 * optee@96000000 {
54 * reg = <0 0x96000000 0 0x2000000>;
55 * no-map;
56 * };
57 */
58
59 /* global autoconfigured region for contiguous allocations */
60 linux,cma {
61 compatible = "shared-dma-pool";
62 reusable;
63 size = <0 0x14000000>;
64 alloc-ranges = <0 0x98000000 0 0x14000000>;
65 linux,cma-default;
66 };
67
68 vdev0vring0: memory0@90000000 {
69 reg = <0 0x90000000 0 0x8000>;
70 no-map;
71 };
72
73 vdev0vring1: memory@90008000 {
74 reg = <0 0x90008000 0 0x8000>;
75 no-map;
76 };
77
78 vdev1vring0: memory@90010000 {
79 reg = <0 0x90010000 0 0x8000>;
80 no-map;
81 };
82
83 vdev1vring1: memory@90018000 {
84 reg = <0 0x90018000 0 0x8000>;
85 no-map;
86 };
87
88 rsc_table: memory-rsc-table@900ff000 {
89 reg = <0 0x900ff000 0 0x1000>;
90 no-map;
91 };
92
93 vdevbuffer: memory-vdevbuffer@90400000 {
94 compatible = "shared-dma-pool";
95 reg = <0 0x90400000 0 0x100000>;
96 no-map;
97 };
98 };
99
100 m2_uart1_sel: regulator-m2uart1sel {
101 compatible = "regulator-fixed";
102 regulator-min-microvolt = <3300000>;
103 regulator-max-microvolt = <3300000>;
104 regulator-name = "m2_uart1_sel";
105 gpio = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
106 enable-active-high;
107 regulator-always-on;
108 };
109
110 mux3_en: regulator-0 {
111 compatible = "regulator-fixed";
112 regulator-min-microvolt = <3300000>;
113 regulator-max-microvolt = <3300000>;
114 regulator-name = "mux3_en";
115 gpio = <&pca6416_2 8 GPIO_ACTIVE_LOW>;
116 regulator-always-on;
117 };
118
119 reg_fec1_sel: regulator-1 {
120 compatible = "regulator-fixed";
121 regulator-name = "fec1_supply";
122 regulator-min-microvolt = <3300000>;
123 regulator-max-microvolt = <3300000>;
124 gpio = <&pca6416_1 11 GPIO_ACTIVE_LOW>;
125 regulator-always-on;
126 status = "disabled";
127 };
128
129 reg_fec1_io: regulator-2 {
130 compatible = "regulator-fixed";
131 regulator-name = "fec1_io_supply";
132 regulator-min-microvolt = <1800000>;
133 regulator-max-microvolt = <1800000>;
134 gpio = <&max7322 0 GPIO_ACTIVE_HIGH>;
135 enable-active-high;
136 regulator-always-on;
137 status = "disabled";
138 };
139
140 reg_can0_stby: regulator-4 {
141 compatible = "regulator-fixed";
142 regulator-name = "can0-stby";
143 regulator-min-microvolt = <3300000>;
144 regulator-max-microvolt = <3300000>;
145 gpio = <&pca6416_3 0 GPIO_ACTIVE_HIGH>;
146 enable-active-high;
147 };
148
149 reg_can1_stby: regulator-5 {
150 compatible = "regulator-fixed";
151 regulator-name = "can1-stby";
152 regulator-min-microvolt = <3300000>;
153 regulator-max-microvolt = <3300000>;
154 gpio = <&pca6416_3 1 GPIO_ACTIVE_HIGH>;
155 enable-active-high;
156 };
157
158 reg_usdhc2_vmmc: regulator-3 {
159 compatible = "regulator-fixed";
160 regulator-name = "SD1_SPWR";
161 regulator-min-microvolt = <3000000>;
162 regulator-max-microvolt = <3000000>;
163 gpio = <&lsio_gpio4 30 GPIO_ACTIVE_HIGH>;
164 enable-active-high;
165 off-on-delay-us = <3480>;
166 };
167
168 reg_vref_1v8: regulator-adc-vref {
169 compatible = "regulator-fixed";
170 regulator-name = "vref_1v8";
171 regulator-min-microvolt = <1800000>;
172 regulator-max-microvolt = <1800000>;
173 };
174
175 mii_select: regulator-4 {
176 compatible = "regulator-fixed";
177 regulator-name = "mii-select";
178 regulator-min-microvolt = <3300000>;
179 regulator-max-microvolt = <3300000>;
180 gpio = <&scu_gpio 6 GPIO_ACTIVE_HIGH>;
181 enable-active-high;
182 regulator-always-on;
183 };
184
185 reg_pcieb: regulator-pcieb {
186 compatible = "regulator-fixed";
187 regulator-max-microvolt = <3300000>;
188 regulator-min-microvolt = <3300000>;
189 regulator-name = "reg_pcieb";
190 gpio = <&pca6416_1 13 GPIO_ACTIVE_HIGH>;
191 enable-active-high;
192 };
193
194 bt_sco_codec: audio-codec-bt {
195 compatible = "linux,bt-sco";
196 #sound-dai-cells = <1>;
197 };
198
199 sound-bt-sco {
200 compatible = "simple-audio-card";
201 simple-audio-card,name = "bt-sco-audio";
202 simple-audio-card,format = "dsp_a";
203 simple-audio-card,bitclock-inversion;
204 simple-audio-card,frame-master = <&btcpu>;
205 simple-audio-card,bitclock-master = <&btcpu>;
206
207 btcpu: simple-audio-card,cpu {
208 sound-dai = <&sai0>;
209 dai-tdm-slot-num = <2>;
210 dai-tdm-slot-width = <16>;
211 };
212
213 simple-audio-card,codec {
214 sound-dai = <&bt_sco_codec 1>;
215 };
216 };
217
218 sound-wm8960-1 {
219 compatible = "fsl,imx-audio-wm8960";
220 model = "wm8960-audio";
221 audio-cpu = <&sai1>;
222 audio-codec = <&wm8960_1>;
223 audio-asrc = <&asrc0>;
224 audio-routing = "Headphone Jack", "HP_L",
225 "Headphone Jack", "HP_R",
226 "Ext Spk", "SPK_LP",
227 "Ext Spk", "SPK_LN",
228 "Ext Spk", "SPK_RP",
229 "Ext Spk", "SPK_RN",
230 "LINPUT1", "Mic Jack",
231 "Mic Jack", "MICB";
232 };
233
234 sound-wm8960-2 {
235 compatible = "fsl,imx-audio-wm8960";
236 model = "wm8960-audio-2";
237 audio-cpu = <&sai2>;
238 audio-codec = <&wm8960_2>;
239 audio-routing = "Headphone Jack", "HP_L",
240 "Headphone Jack", "HP_R",
241 "Ext Spk", "SPK_LP",
242 "Ext Spk", "SPK_LN",
243 "Ext Spk", "SPK_RP",
244 "Ext Spk", "SPK_RN",
245 "LINPUT1", "Mic Jack",
246 "Mic Jack", "MICB";
247 };
248
249 sound-wm8960-3 {
250 compatible = "fsl,imx-audio-wm8960";
251 model = "wm8960-audio-3";
252 audio-cpu = <&sai3>;
253 audio-codec = <&wm8960_3>;
254 audio-routing = "Headphone Jack", "HP_L",
255 "Headphone Jack", "HP_R",
256 "Ext Spk", "SPK_LP",
257 "Ext Spk", "SPK_LN",
258 "Ext Spk", "SPK_RP",
259 "Ext Spk", "SPK_RN",
260 "LINPUT1", "Mic Jack",
261 "Mic Jack", "MICB";
262 };
263};
264
265&adc0 {
266 vref-supply = <®_vref_1v8>;
267 status = "okay";
268};
269
270&asrc0 {
271 fsl,asrc-rate = <48000>;
272 status = "okay";
273};
274
275&eqos {
276 pinctrl-names = "default";
277 pinctrl-0 = <&pinctrl_eqos>;
278 phy-mode = "rgmii-id";
279 phy-handle = <ðphy0>;
280 nvmem-cells = <&fec_mac1>;
281 nvmem-cell-names = "mac-address";
282 status = "okay";
283
284 mdio {
285 compatible = "snps,dwmac-mdio";
286 #address-cells = <1>;
287 #size-cells = <0>;
288
289 ethphy0: ethernet-phy@0 {
290 compatible = "ethernet-phy-ieee802.3-c22";
291 reg = <0>;
292 eee-broken-1000t;
293 qca,disable-smarteee;
294 qca,disable-hibernation-mode;
295 reset-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>;
296 reset-assert-us = <20>;
297 reset-deassert-us = <200000>;
298 vddio-supply = <&vddio0>;
299
300 vddio0: vddio-regulator {
301 regulator-min-microvolt = <1800000>;
302 regulator-max-microvolt = <1800000>;
303 };
304 };
305 };
306};
307
308/*
309 * fec1 shares the some PINs with usdhc2.
310 * by default usdhc2 is enabled in this dts.
311 * Please disable usdhc2 to enable fec1
312 */
313&fec1 {
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_fec1>;
316 phy-mode = "rgmii-txid";
317 phy-handle = <ðphy1>;
318 fsl,magic-packet;
319 rx-internal-delay-ps = <2000>;
320 nvmem-cells = <&fec_mac0>;
321 nvmem-cell-names = "mac-address";
322 status = "disabled";
323
324 mdio {
325 #address-cells = <1>;
326 #size-cells = <0>;
327
328 ethphy1: ethernet-phy@1 {
329 compatible = "ethernet-phy-ieee802.3-c22";
330 reg = <1>;
331 reset-gpios = <&pca6416_1 0 GPIO_ACTIVE_LOW>;
332 reset-assert-us = <10000>;
333 qca,disable-smarteee;
334 vddio-supply = <&vddio1>;
335
336 vddio1: vddio-regulator {
337 regulator-min-microvolt = <1800000>;
338 regulator-max-microvolt = <1800000>;
339 };
340 };
341 };
342};
343
344&flexspi0 {
345 pinctrl-names = "default";
346 pinctrl-0 = <&pinctrl_flexspi0>;
347 status = "okay";
348
349 mt35xu512aba0: flash@0 {
350 reg = <0>;
351 #address-cells = <1>;
352 #size-cells = <1>;
353 compatible = "jedec,spi-nor";
354 spi-max-frequency = <133000000>;
355 spi-tx-bus-width = <8>;
356 spi-rx-bus-width = <8>;
357 };
358};
359
360&i2c2 {
361 #address-cells = <1>;
362 #size-cells = <0>;
363 clock-frequency = <100000>;
364 pinctrl-names = "default";
365 pinctrl-0 = <&pinctrl_i2c2>;
366 status = "okay";
367
368 pca6416_1: gpio@20 {
369 compatible = "ti,tca6416";
370 reg = <0x20>;
371 gpio-controller;
372 #gpio-cells = <2>;
373 };
374
375 pca6416_2: gpio@21 {
376 compatible = "ti,tca6416";
377 reg = <0x21>;
378 gpio-controller;
379 #gpio-cells = <2>;
380 };
381
382 pca9548_1: i2c-mux@70 {
383 compatible = "nxp,pca9548";
384 #address-cells = <1>;
385 #size-cells = <0>;
386 reg = <0x70>;
387
388 i2c@0 {
389 #address-cells = <1>;
390 #size-cells = <0>;
391 reg = <0x0>;
392
393 max7322: gpio@68 {
394 compatible = "maxim,max7322";
395 reg = <0x68>;
396 gpio-controller;
397 #gpio-cells = <2>;
398 status = "disabled";
399 };
400 };
401
402 i2c@1 {
403 #address-cells = <1>;
404 #size-cells = <0>;
405 reg = <0x1>;
406
407 wm8960_1: audio-codec@1a {
408 compatible = "wlf,wm8960";
409 reg = <0x1a>;
410 clocks = <&mclkout1_lpcg IMX_LPCG_CLK_0>;
411 clock-names = "mclk";
412 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
413 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
414 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
415 <&mclkout1_lpcg IMX_LPCG_CLK_0>;
416 assigned-clock-rates = <786432000>,
417 <49152000>,
418 <12288000>,
419 <12288000>;
420 wlf,shared-lrclk;
421 wlf,hp-cfg = <2 2 3>;
422 wlf,gpio-cfg = <1 3>;
423 };
424 };
425
426 i2c@2 {
427 #address-cells = <1>;
428 #size-cells = <0>;
429 reg = <0x2>;
430
431 wm8960_2: audio-codec@1a {
432 compatible = "wlf,wm8960";
433 reg = <0x1a>;
434 clocks = <&mclkout1_lpcg IMX_LPCG_CLK_0>;
435 clock-names = "mclk";
436 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
437 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
438 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
439 <&mclkout1_lpcg IMX_LPCG_CLK_0>;
440 assigned-clock-rates = <786432000>,
441 <49152000>,
442 <12288000>,
443 <12288000>;
444 wlf,shared-lrclk;
445 wlf,hp-cfg = <2 2 3>;
446 wlf,gpio-cfg = <1 3>;
447 };
448 };
449
450 i2c@3 {
451 #address-cells = <1>;
452 #size-cells = <0>;
453 reg = <0x3>;
454
455 wm8960_3: audio-codec@1a {
456 compatible = "wlf,wm8960";
457 reg = <0x1a>;
458 clocks = <&mclkout1_lpcg IMX_LPCG_CLK_0>;
459 clock-names = "mclk";
460 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
461 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
462 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
463 <&mclkout1_lpcg IMX_LPCG_CLK_0>;
464 assigned-clock-rates = <786432000>,
465 <49152000>,
466 <12288000>,
467 <12288000>;
468 wlf,shared-lrclk;
469 wlf,hp-cfg = <2 2 3>;
470 wlf,gpio-cfg = <1 3>;
471 };
472 };
473
474 i2c@4 {
475 #address-cells = <1>;
476 #size-cells = <0>;
477 reg = <0x4>;
478 };
479
480 i2c@5 {
481 #address-cells = <1>;
482 #size-cells = <0>;
483 reg = <0x5>;
484 };
485
486 i2c@6 {
487 #address-cells = <1>;
488 #size-cells = <0>;
489 reg = <0x6>;
490 };
491 };
492};
493
494&i2c3 {
495 #address-cells = <1>;
496 #size-cells = <0>;
497 clock-frequency = <100000>;
498 pinctrl-names = "default";
499 pinctrl-0 = <&pinctrl_i2c3>;
500 status = "okay";
501
502 pca6416_3: gpio@20 {
503 compatible = "ti,tca6416";
504 reg = <0x20>;
505 gpio-controller;
506 #gpio-cells = <2>;
507 interrupt-parent = <&lsio_gpio2>;
508 interrupts = <5 IRQ_TYPE_EDGE_RISING>;
509 };
510
511 pca9548_2: i2c-mux@70 {
512 compatible = "nxp,pca9548";
513 reg = <0x70>;
514 #address-cells = <1>;
515 #size-cells = <0>;
516
517 i2c@0 {
518 #address-cells = <1>;
519 #size-cells = <0>;
520 reg = <0x0>;
521 };
522
523 i2c@1 {
524 #address-cells = <1>;
525 #size-cells = <0>;
526 reg = <0x1>;
527 };
528
529 i2c@2 {
530 #address-cells = <1>;
531 #size-cells = <0>;
532 reg = <0x2>;
533 };
534
535 i2c@3 {
536 #address-cells = <1>;
537 #size-cells = <0>;
538 reg = <0x3>;
539 };
540
541 i2c@4 {
542 #address-cells = <1>;
543 #size-cells = <0>;
544 reg = <0x4>;
545 };
546 };
547};
548
549&lpuart0 {
550 pinctrl-names = "default";
551 pinctrl-0 = <&pinctrl_lpuart0>;
552 status = "okay";
553};
554
555&lpuart1 {
556 pinctrl-names = "default";
557 pinctrl-0 = <&pinctrl_lpuart1>;
558 status = "okay";
559};
560
561&lsio_mu5 {
562 status = "okay";
563};
564
565&flexcan2 {
566 pinctrl-names = "default";
567 pinctrl-0 = <&pinctrl_flexcan2>;
568 xceiver-supply = <®_can0_stby>;
569 status = "okay";
570};
571
572&flexcan3 {
573 pinctrl-names = "default";
574 pinctrl-0 = <&pinctrl_flexcan3>;
575 xceiver-supply = <®_can1_stby>;
576 status = "okay";
577};
578
579&hsio_phy {
580 fsl,hsio-cfg = "pciea-x2-pcieb";
581 fsl,refclk-pad-mode = "output";
582 status = "okay";
583};
584
585&cm40_intmux {
586 status = "disabled";
587};
588
589&cm40_lpuart {
590 pinctrl-names = "default";
591 pinctrl-0 = <&pinctrl_cm40_lpuart>;
592 status = "disabled";
593};
594
595&lsio_gpio4 {
596 status = "okay";
597};
598
599&lsio_gpio5 {
600 status = "okay";
601};
602
603&pcieb {
604 phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>;
605 phy-names = "pcie-phy";
606 pinctrl-0 = <&pinctrl_pcieb>;
607 pinctrl-names = "default";
608 reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
609 vpcie-supply = <®_pcieb>;
610 status = "okay";
611};
612
613&sai0 {
614 pinctrl-names = "default";
615 pinctrl-0 = <&pinctrl_sai0>;
616 #sound-dai-cells = <0>;
617 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
618 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
619 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
620 <&sai0_lpcg IMX_LPCG_CLK_0>;
621 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
622 status = "okay";
623};
624
625&sai1 {
626 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
627 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
628 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
629 <&sai1_lpcg IMX_LPCG_CLK_0>;
630 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
631 pinctrl-names = "default";
632 pinctrl-0 = <&pinctrl_sai1>;
633 status = "okay";
634};
635
636&sai2 {
637 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
638 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
639 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
640 <&sai2_lpcg IMX_LPCG_CLK_0>;
641 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
642 pinctrl-names = "default";
643 pinctrl-0 = <&pinctrl_sai2>;
644 fsl,sai-asynchronous;
645 status = "okay";
646};
647
648&sai3 {
649 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
650 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
651 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
652 <&sai3_lpcg IMX_LPCG_CLK_0>;
653 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
654 pinctrl-names = "default";
655 pinctrl-0 = <&pinctrl_sai3>;
656 fsl,sai-asynchronous;
657 status = "okay";
658};
659
660&thermal_zones {
661 pmic-thermal {
662 polling-delay-passive = <250>;
663 polling-delay = <2000>;
664 thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
665
666 trips {
667 pmic_alert0: trip0 {
668 temperature = <110000>;
669 hysteresis = <2000>;
670 type = "passive";
671 };
672
673 pmic_crit0: trip1 {
674 temperature = <125000>;
675 hysteresis = <2000>;
676 type = "critical";
677 };
678 };
679
680 cooling-maps {
681 map0 {
682 trip = <&pmic_alert0>;
683 cooling-device =
684 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
685 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
686 };
687 };
688 };
689};
690
691&usbphy1 {
692 /* USB eye diagram tests result */
693 fsl,tx-d-cal = <114>;
694 status = "okay";
695};
696
697&usbotg1 {
698 pinctrl-names = "default";
699 pinctrl-0 = <&pinctrl_usbotg1>;
700 srp-disable;
701 hnp-disable;
702 adp-disable;
703 power-active-high;
704 disable-over-current;
705 status = "okay";
706};
707
708&usbphy2 {
709 /* USB eye diagram tests result */
710 fsl,tx-d-cal = <111>;
711 status = "okay";
712};
713
714&usbotg2 {
715 pinctrl-names = "default";
716 pinctrl-0 = <&pinctrl_usbotg2>;
717 srp-disable;
718 hnp-disable;
719 adp-disable;
720 power-active-high;
721 disable-over-current;
722 status = "okay";
723};
724
725&usdhc1 {
726 pinctrl-names = "default";
727 pinctrl-0 = <&pinctrl_usdhc1>;
728 bus-width = <8>;
729 no-sd;
730 no-sdio;
731 non-removable;
732 status = "okay";
733};
734
735&usdhc2 {
736 pinctrl-names = "default";
737 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
738 bus-width = <4>;
739 vmmc-supply = <®_usdhc2_vmmc>;
740 cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>;
741 wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>;
742 status = "okay";
743};
744
745&lpspi3 {
746 fsl,spi-only-use-cs1-sel;
747 pinctrl-names = "default";
748 pinctrl-0 = <&pinctrl_lpspi3>;
749 status = "okay";
750};
751
752&iomuxc {
753 pinctrl-names = "default";
754 pinctrl-0 = <&pinctrl_hog>;
755
756 pinctrl_hog: hoggrp {
757 fsl,pins = <
758 IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0
759 IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD 0x000014a0
760 IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1 0x0600004c
761 IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN 0x0600004c
762 >;
763 };
764
765 pinctrl_usbotg1: usbotg1grp {
766 fsl,pins = <
767 IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021
768 >;
769 };
770
771 pinctrl_usbotg2: usbotg2grp {
772 fsl,pins = <
773 IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR 0x00000021
774 >;
775 };
776
777 pinctrl_eqos: eqosgrp {
778 fsl,pins = <
779 IMX8DXL_ENET0_MDC_CONN_EQOS_MDC 0x06000020
780 IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO 0x06000020
781 IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC 0x06000020
782 IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 0x06000020
783 IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 0x06000020
784 IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 0x06000020
785 IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 0x06000020
786 IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL 0x06000020
787 IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC 0x06000020
788 IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 0x06000020
789 IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 0x06000020
790 IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 0x06000020
791 IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 0x06000020
792 IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL 0x06000020
793 >;
794 };
795
796 pinctrl_flexspi0: flexspi0grp {
797 fsl,pins = <
798 IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021
799 IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021
800 IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021
801 IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021
802 IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021
803 IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021
804 IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021
805 IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021
806 IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021
807 IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021
808 IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021
809 IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021
810 IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021
811 IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021
812 >;
813 };
814
815 pinctrl_flexcan2: flexcan2grp {
816 fsl,pins = <
817 IMX8DXL_UART2_TX_ADMA_FLEXCAN1_TX 0x00000021
818 IMX8DXL_UART2_RX_ADMA_FLEXCAN1_RX 0x00000021
819 >;
820 };
821
822 pinctrl_flexcan3: flexcan3grp {
823 fsl,pins = <
824 IMX8DXL_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x00000021
825 IMX8DXL_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x00000021
826 >;
827 };
828
829 pinctrl_fec1: fec1grp {
830 fsl,pins = <
831 IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0
832 IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0
833 IMX8DXL_ENET0_MDC_CONN_ENET0_MDC 0x06000020
834 IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
835 IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060
836 IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060
837 IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060
838 IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060
839 IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060
840 IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060
841 IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060
842 IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060
843 IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060
844 IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060
845 IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060
846 IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060
847 >;
848 };
849
850 pinctrl_lpspi3: lpspi3grp {
851 fsl,pins = <
852 IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK 0x6000040
853 IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO 0x6000040
854 IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI 0x6000040
855 IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 0x6000040
856 >;
857 };
858
859 pinctrl_i2c2: i2c2grp {
860 fsl,pins = <
861 IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA 0x06000021
862 IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL 0x06000021
863 >;
864 };
865
866 pinctrl_cm40_lpuart: cm40lpuartgrp {
867 fsl,pins = <
868 IMX8DXL_ADC_IN2_M40_UART0_RX 0x06000020
869 IMX8DXL_ADC_IN3_M40_UART0_TX 0x06000020
870 >;
871 };
872
873 pinctrl_i2c3: i2c3grp {
874 fsl,pins = <
875 IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA 0x06000021
876 IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL 0x06000021
877 >;
878 };
879
880 pinctrl_lpuart0: lpuart0grp {
881 fsl,pins = <
882 IMX8DXL_UART0_RX_ADMA_UART0_RX 0x06000020
883 IMX8DXL_UART0_TX_ADMA_UART0_TX 0x06000020
884 >;
885 };
886
887 pinctrl_lpuart1: lpuart1grp {
888 fsl,pins = <
889 IMX8DXL_UART1_TX_ADMA_UART1_TX 0x06000020
890 IMX8DXL_UART1_RX_ADMA_UART1_RX 0x06000020
891 IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020
892 IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020
893 >;
894 };
895
896 pinctrl_pcieb: pcieagrp {
897 fsl,pins = <
898 IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021
899 IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021
900 IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021
901 >;
902 };
903
904 pinctrl_sai0: sai0grp {
905 fsl,pins = <
906 IMX8DXL_SPI0_CS0_ADMA_SAI0_RXD 0x06000060
907 IMX8DXL_SPI0_CS1_ADMA_SAI0_RXC 0x06000040
908 IMX8DXL_SPI0_SCK_ADMA_SAI0_TXC 0x06000060
909 IMX8DXL_SPI0_SDI_ADMA_SAI0_TXD 0x06000060
910 IMX8DXL_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040
911 >;
912 };
913
914 pinctrl_sai1: sai1grp {
915 fsl,pins = <
916 IMX8DXL_FLEXCAN0_RX_ADMA_SAI1_TXC 0x06000040
917 IMX8DXL_FLEXCAN0_TX_ADMA_SAI1_TXFS 0x06000040
918 IMX8DXL_FLEXCAN1_RX_ADMA_SAI1_TXD 0x06000060
919 IMX8DXL_FLEXCAN1_TX_ADMA_SAI1_RXD 0x06000060
920 >;
921 };
922
923 pinctrl_sai2: sai2grp {
924 fsl,pins = <
925 IMX8DXL_SNVS_TAMPER_OUT3_ADMA_SAI2_RXC 0x06000040
926 IMX8DXL_SNVS_TAMPER_IN0_ADMA_SAI2_RXFS 0x06000040
927 IMX8DXL_SNVS_TAMPER_OUT4_ADMA_SAI2_RXD 0x06000060
928 >;
929 };
930
931 pinctrl_sai3: sai3grp {
932 fsl,pins = <
933 IMX8DXL_SNVS_TAMPER_IN1_ADMA_SAI3_RXC 0x06000040
934 IMX8DXL_SNVS_TAMPER_IN3_ADMA_SAI3_RXFS 0x06000040
935 IMX8DXL_SNVS_TAMPER_IN2_ADMA_SAI3_RXD 0x06000060
936 >;
937 };
938
939 pinctrl_usdhc1: usdhc1grp {
940 fsl,pins = <
941 IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
942 IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
943 IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
944 IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
945 IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
946 IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
947 IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
948 IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
949 IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
950 IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
951 IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
952 >;
953 };
954
955 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
956 fsl,pins = <
957 IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x00000040 /* RESET_B */
958 IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x00000021 /* WP */
959 IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x00000021 /* CD */
960 >;
961 };
962
963 pinctrl_usdhc2: usdhc2grp {
964 fsl,pins = <
965 IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041
966 IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021
967 IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021
968 IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021
969 IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021
970 IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021
971 IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021
972 >;
973 };
974};