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1/*
2 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3 *
4 * Copyright 2016 Freescale Semiconductor, Inc.
5 *
6 * Mingkai Hu <mingkai.hu@nxp.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPLv2 or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively,
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
45 */
46
47/dts-v1/;
48
49#include "fsl-ls1046a.dtsi"
50
51/ {
52 model = "LS1046A RDB Board";
53 compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
54
55 aliases {
56 serial0 = &duart0;
57 serial1 = &duart1;
58 serial2 = &duart2;
59 serial3 = &duart3;
60 };
61
62 chosen {
63 stdout-path = "serial0:115200n8";
64 };
65};
66
67&duart0 {
68 status = "okay";
69};
70
71&duart1 {
72 status = "okay";
73};
74
75&esdhc {
76 mmc-hs200-1_8v;
77 sd-uhs-sdr104;
78 sd-uhs-sdr50;
79 sd-uhs-sdr25;
80 sd-uhs-sdr12;
81};
82
83&i2c0 {
84 status = "okay";
85
86 ina220@40 {
87 compatible = "ti,ina220";
88 reg = <0x40>;
89 shunt-resistor = <1000>;
90 };
91
92 temp-sensor@4c {
93 compatible = "adi,adt7461";
94 reg = <0x4c>;
95 };
96
97 eeprom@56 {
98 compatible = "atmel,24c512";
99 reg = <0x52>;
100 };
101
102 eeprom@57 {
103 compatible = "atmel,24c512";
104 reg = <0x53>;
105 };
106};
107
108&i2c3 {
109 status = "okay";
110
111 rtc@51 {
112 compatible = "nxp,pcf2129";
113 reg = <0x51>;
114 };
115};
116
117&ifc {
118 #address-cells = <2>;
119 #size-cells = <1>;
120 /* NAND Flashe and CPLD on board */
121 ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
122 0x2 0x0 0x0 0x7fb00000 0x00000100>;
123 status = "okay";
124
125 nand@0,0 {
126 compatible = "fsl,ifc-nand";
127 #address-cells = <1>;
128 #size-cells = <1>;
129 reg = <0x0 0x0 0x10000>;
130 };
131
132 cpld: board-control@2,0 {
133 compatible = "fsl,ls1046ardb-cpld";
134 reg = <0x2 0x0 0x0000100>;
135 };
136};
137
138&qspi {
139 num-cs = <2>;
140 bus-num = <0>;
141 status = "okay";
142
143 qflash0: s25fs512s@0 {
144 compatible = "spansion,m25p80";
145 #address-cells = <1>;
146 #size-cells = <1>;
147 spi-max-frequency = <20000000>;
148 reg = <0>;
149 };
150
151 qflash1: s25fs512s@1 {
152 compatible = "spansion,m25p80";
153 #address-cells = <1>;
154 #size-cells = <1>;
155 spi-max-frequency = <20000000>;
156 reg = <1>;
157 };
158};
159
160#include "fsl-ls1046-post.dtsi"
161
162&fman0 {
163 ethernet@e4000 {
164 phy-handle = <&rgmii_phy1>;
165 phy-connection-type = "rgmii";
166 };
167
168 ethernet@e6000 {
169 phy-handle = <&rgmii_phy2>;
170 phy-connection-type = "rgmii";
171 };
172
173 ethernet@e8000 {
174 phy-handle = <&sgmii_phy1>;
175 phy-connection-type = "sgmii";
176 };
177
178 ethernet@ea000 {
179 phy-handle = <&sgmii_phy2>;
180 phy-connection-type = "sgmii";
181 };
182
183 ethernet@f0000 { /* 10GEC1 */
184 phy-handle = <&aqr106_phy>;
185 phy-connection-type = "xgmii";
186 };
187
188 ethernet@f2000 { /* 10GEC2 */
189 fixed-link = <0 1 1000 0 0>;
190 phy-connection-type = "xgmii";
191 };
192
193 mdio@fc000 {
194 rgmii_phy1: ethernet-phy@1 {
195 reg = <0x1>;
196 };
197
198 rgmii_phy2: ethernet-phy@2 {
199 reg = <0x2>;
200 };
201
202 sgmii_phy1: ethernet-phy@3 {
203 reg = <0x3>;
204 };
205
206 sgmii_phy2: ethernet-phy@4 {
207 reg = <0x4>;
208 };
209 };
210
211 mdio@fd000 {
212 aqr106_phy: ethernet-phy@0 {
213 compatible = "ethernet-phy-ieee802.3-c45";
214 interrupts = <0 131 4>;
215 reg = <0x0>;
216 };
217 };
218};
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
4 *
5 * Copyright 2016 Freescale Semiconductor, Inc.
6 * Copyright 2019-2020 NXP
7 *
8 * Mingkai Hu <mingkai.hu@nxp.com>
9 */
10
11/dts-v1/;
12
13#include "fsl-ls1046a.dtsi"
14
15/ {
16 model = "LS1046A RDB Board";
17 compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
18
19 aliases {
20 serial0 = &duart0;
21 serial1 = &duart1;
22 serial2 = &duart2;
23 serial3 = &duart3;
24 };
25
26 chosen {
27 stdout-path = "serial0:115200n8";
28 };
29};
30
31&duart0 {
32 status = "okay";
33};
34
35&duart1 {
36 status = "okay";
37};
38
39&esdhc {
40 mmc-hs200-1_8v;
41 sd-uhs-sdr104;
42 sd-uhs-sdr50;
43 sd-uhs-sdr25;
44 sd-uhs-sdr12;
45};
46
47&i2c0 {
48 status = "okay";
49
50 ina220@40 {
51 compatible = "ti,ina220";
52 reg = <0x40>;
53 shunt-resistor = <1000>;
54 };
55
56 temp-sensor@4c {
57 compatible = "adi,adt7461";
58 reg = <0x4c>;
59 };
60
61 eeprom@52 {
62 compatible = "onnn,cat24c05", "atmel,24c04";
63 reg = <0x52>;
64 };
65};
66
67&i2c3 {
68 status = "okay";
69
70 rtc@51 {
71 compatible = "nxp,pcf2129";
72 reg = <0x51>;
73 /* IRQ_RTC_B -> IRQ05, active low */
74 interrupts-extended = <&extirq 5 IRQ_TYPE_LEVEL_LOW>;
75 };
76};
77
78&ifc {
79 #address-cells = <2>;
80 #size-cells = <1>;
81 /* NAND Flashe and CPLD on board */
82 ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
83 0x2 0x0 0x0 0x7fb00000 0x00000100>;
84 status = "okay";
85
86 nand@0,0 {
87 compatible = "fsl,ifc-nand";
88 #address-cells = <1>;
89 #size-cells = <1>;
90 reg = <0x0 0x0 0x10000>;
91 };
92
93 cpld: board-control@2,0 {
94 compatible = "fsl,ls1046ardb-cpld";
95 reg = <0x2 0x0 0x0000100>;
96 };
97};
98
99&qspi {
100 status = "okay";
101
102 s25fs512s0: flash@0 {
103 compatible = "jedec,spi-nor";
104 #address-cells = <1>;
105 #size-cells = <1>;
106 spi-max-frequency = <50000000>;
107 spi-rx-bus-width = <4>;
108 spi-tx-bus-width = <1>;
109 reg = <0>;
110 };
111
112 s25fs512s1: flash@1 {
113 compatible = "jedec,spi-nor";
114 #address-cells = <1>;
115 #size-cells = <1>;
116 spi-max-frequency = <50000000>;
117 spi-rx-bus-width = <4>;
118 spi-tx-bus-width = <1>;
119 reg = <1>;
120 };
121};
122
123&usb1 {
124 dr_mode = "otg";
125};
126
127#include "fsl-ls1046-post.dtsi"
128
129&fman0 {
130 ethernet@e4000 {
131 phy-handle = <&rgmii_phy1>;
132 phy-connection-type = "rgmii-id";
133 };
134
135 ethernet@e6000 {
136 phy-handle = <&rgmii_phy2>;
137 phy-connection-type = "rgmii-id";
138 };
139
140 ethernet@e8000 {
141 phy-handle = <&sgmii_phy1>;
142 phy-connection-type = "sgmii";
143 };
144
145 ethernet@ea000 {
146 phy-handle = <&sgmii_phy2>;
147 phy-connection-type = "sgmii";
148 };
149
150 ethernet@f0000 { /* 10GEC1 */
151 phy-handle = <&aqr106_phy>;
152 phy-connection-type = "xgmii";
153 };
154
155 ethernet@f2000 { /* 10GEC2 */
156 phy-connection-type = "10gbase-r";
157 managed = "in-band-status";
158 };
159
160 mdio@fc000 {
161 rgmii_phy1: ethernet-phy@1 {
162 reg = <0x1>;
163 };
164
165 rgmii_phy2: ethernet-phy@2 {
166 reg = <0x2>;
167 };
168
169 sgmii_phy1: ethernet-phy@3 {
170 reg = <0x3>;
171 };
172
173 sgmii_phy2: ethernet-phy@4 {
174 reg = <0x4>;
175 };
176 };
177
178 mdio@fd000 {
179 aqr106_phy: ethernet-phy@0 {
180 compatible = "ethernet-phy-ieee802.3-c45";
181 interrupts = <0 131 4>;
182 reg = <0x0>;
183 };
184 };
185};